1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ; Copyright(c) 2011-2016 Intel Corporation All rights reserved.
4 ; Redistribution and use in source and binary forms, with or without
5 ; modification, are permitted provided that the following conditions
7 ; * Redistributions of source code must retain the above copyright
8 ; notice, this list of conditions and the following disclaimer.
9 ; * Redistributions in binary form must reproduce the above copyright
10 ; notice, this list of conditions and the following disclaimer in
11 ; the documentation and/or other materials provided with the
13 ; * Neither the name of Intel Corporation nor the names of its
14 ; contributors may be used to endorse or promote products derived
15 ; from this software without specific prior written permission.
17 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
30 %include "sha256_job.asm"
32 %include "sha256_mb_mgr_datastruct.asm"
34 %include "reg_sizes.asm"
36 extern sha256_mb_x8_avx2
42 %ifidn __OUTPUT_FORMAT__, elf64
43 ; Linux register definitions
44 %define arg1 rdi ; rcx
45 %define arg2 rsi ; rdx
47 %define size_offset rcx ; rdi
48 %define tmp2 rcx ; rdi
51 ; WINDOWS register definitions
55 %define size_offset rdi
69 %define start_offset r11
71 %define unused_lanes rbx
84 ; STACK_SPACE needs to be an odd multiple of 8
85 %define STACK_SPACE 8*8 + 16*10 + 8
87 ; SHA256_JOB* sha256_mb_mgr_submit_avx2(SHA256_MB_JOB_MGR *state, SHA256_JOB *job)
90 mk_global sha256_mb_mgr_submit_avx2, function
91 sha256_mb_mgr_submit_avx2:
101 %ifidn __OUTPUT_FORMAT__, win64
104 vmovdqa [rsp + 8*8 + 16*0], xmm6
105 vmovdqa [rsp + 8*8 + 16*1], xmm7
106 vmovdqa [rsp + 8*8 + 16*2], xmm8
107 vmovdqa [rsp + 8*8 + 16*3], xmm9
108 vmovdqa [rsp + 8*8 + 16*4], xmm10
109 vmovdqa [rsp + 8*8 + 16*5], xmm11
110 vmovdqa [rsp + 8*8 + 16*6], xmm12
111 vmovdqa [rsp + 8*8 + 16*7], xmm13
112 vmovdqa [rsp + 8*8 + 16*8], xmm14
113 vmovdqa [rsp + 8*8 + 16*9], xmm15
115 mov unused_lanes, [state + _unused_lanes]
116 mov lane, unused_lanes
119 imul lane_data, lane, _LANE_DATA_size
120 mov dword [job + _status], STS_BEING_PROCESSED
121 lea lane_data, [state + _ldata + lane_data]
122 mov [state + _unused_lanes], unused_lanes
123 mov DWORD(len), [job + _len]
127 mov [state + _lens + 4*lane], DWORD(len)
129 mov [lane_data + _job_in_lane], job
131 ; Load digest words from result_digest
132 vmovdqu xmm0, [job + _result_digest + 0*16]
133 vmovdqu xmm1, [job + _result_digest + 1*16]
134 vmovd [state + _args_digest + 4*lane + 0*4*8], xmm0
135 vpextrd [state + _args_digest + 4*lane + 1*4*8], xmm0, 1
136 vpextrd [state + _args_digest + 4*lane + 2*4*8], xmm0, 2
137 vpextrd [state + _args_digest + 4*lane + 3*4*8], xmm0, 3
138 vmovd [state + _args_digest + 4*lane + 4*4*8], xmm1
139 vpextrd [state + _args_digest + 4*lane + 5*4*8], xmm1, 1
140 vpextrd [state + _args_digest + 4*lane + 6*4*8], xmm1, 2
141 vpextrd [state + _args_digest + 4*lane + 7*4*8], xmm1, 3
144 mov p, [job + _buffer]
145 mov [state + _args_data_ptr + 8*lane], p
147 add dword [state + _num_lanes_inuse], 1
148 cmp unused_lanes, 0xf
153 vmovdqa xmm0, [state + _lens + 0*16]
154 vmovdqa xmm1, [state + _lens + 1*16]
156 vpminud xmm2, xmm0, xmm1 ; xmm2 has {D,C,B,A}
157 vpalignr xmm3, xmm3, xmm2, 8 ; xmm3 has {x,x,D,C}
158 vpminud xmm2, xmm2, xmm3 ; xmm2 has {x,x,E,F}
159 vpalignr xmm3, xmm3, xmm2, 4 ; xmm3 has {x,x,x,E}
160 vpminud xmm2, xmm2, xmm3 ; xmm2 has min value in low dword
162 vmovd DWORD(idx), xmm2
168 vpand xmm2, xmm2, [rel clear_low_nibble]
169 vpshufd xmm2, xmm2, 0
171 vpsubd xmm0, xmm0, xmm2
172 vpsubd xmm1, xmm1, xmm2
174 vmovdqa [state + _lens + 0*16], xmm0
175 vmovdqa [state + _lens + 1*16], xmm1
178 ; "state" and "args" are the same address, arg1
180 call sha256_mb_x8_avx2
182 ; state and idx are intact
185 ; process completed job "idx"
186 imul lane_data, idx, _LANE_DATA_size
187 lea lane_data, [state + _ldata + lane_data]
189 mov job_rax, [lane_data + _job_in_lane]
190 mov unused_lanes, [state + _unused_lanes]
191 mov qword [lane_data + _job_in_lane], 0
192 mov dword [job_rax + _status], STS_COMPLETED
195 mov [state + _unused_lanes], unused_lanes
197 sub dword [state + _num_lanes_inuse], 1
199 vmovd xmm0, [state + _args_digest + 4*idx + 0*4*8]
200 vpinsrd xmm0, [state + _args_digest + 4*idx + 1*4*8], 1
201 vpinsrd xmm0, [state + _args_digest + 4*idx + 2*4*8], 2
202 vpinsrd xmm0, [state + _args_digest + 4*idx + 3*4*8], 3
203 vmovd xmm1, [state + _args_digest + 4*idx + 4*4*8]
204 vpinsrd xmm1, [state + _args_digest + 4*idx + 5*4*8], 1
205 vpinsrd xmm1, [state + _args_digest + 4*idx + 6*4*8], 2
206 vpinsrd xmm1, [state + _args_digest + 4*idx + 7*4*8], 3
208 vmovdqa [job_rax + _result_digest + 0*16], xmm0
209 vmovdqa [job_rax + _result_digest + 1*16], xmm1
213 %ifidn __OUTPUT_FORMAT__, win64
214 vmovdqa xmm6, [rsp + 8*8 + 16*0]
215 vmovdqa xmm7, [rsp + 8*8 + 16*1]
216 vmovdqa xmm8, [rsp + 8*8 + 16*2]
217 vmovdqa xmm9, [rsp + 8*8 + 16*3]
218 vmovdqa xmm10, [rsp + 8*8 + 16*4]
219 vmovdqa xmm11, [rsp + 8*8 + 16*5]
220 vmovdqa xmm12, [rsp + 8*8 + 16*6]
221 vmovdqa xmm13, [rsp + 8*8 + 16*7]
222 vmovdqa xmm14, [rsp + 8*8 + 16*8]
223 vmovdqa xmm15, [rsp + 8*8 + 16*9]
241 section .data align=16
245 dq 0x00000000FFFFFFF0, 0x0000000000000000