ceph/src/crypto/isa-l/isa-l_crypto/sha256_mb/sha256_mb_x4_sse.asm

   1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
   2 ;  Copyright(c) 2011-2016 Intel Corporation All rights reserved.
   3 ;
   4 ;  Redistribution and use in source and binary forms, with or without
   5 ;  modification, are permitted provided that the following conditions
   6 ;  are met:
   7 ;    * Redistributions of source code must retain the above copyright
   8 ;      notice, this list of conditions and the following disclaimer.
   9 ;    * Redistributions in binary form must reproduce the above copyright
  10 ;      notice, this list of conditions and the following disclaimer in
  11 ;      the documentation and/or other materials provided with the
  12 ;      distribution.
  13 ;    * Neither the name of Intel Corporation nor the names of its
  14 ;      contributors may be used to endorse or promote products derived
  15 ;      from this software without specific prior written permission.
  16 ;
  17 ;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 ;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 ;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 ;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 ;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 ;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 ;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 ;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 ;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 ;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 ;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  29
  30 %include "sha256_mb_mgr_datastruct.asm"
  31 %include "reg_sizes.asm"
  32
  33 default rel
  34
  35 ;; code to compute quad SHA256 using SSE
  36 ;; Logic designed/laid out by JDG
  37
  38 ; transpose r0, r1, r2, r3, t0, t1
  39 ; "transpose" data in {r0..r3} using temps {t0..t3}
  40 ; Input looks like: {r0 r1 r2 r3}
  41 ; r0 = {a3 a2 a1 a0}
  42 ; r1 = {b3 b2 b1 b0}
  43 ; r2 = {c3 c2 c1 c0}
  44 ; r3 = {d3 d2 d1 d0}
  45 ;
  46 ; output looks like: {t0 r1 r0 r3}
  47 ; t0 = {d0 c0 b0 a0}
  48 ; r1 = {d1 c1 b1 a1}
  49 ; r0 = {d2 c2 b2 a2}
  50 ; r3 = {d3 c3 b3 a3}
  51 ;
  52 %macro TRANSPOSE 6
  53 %define %%r0 %1
  54 %define %%r1 %2
  55 %define %%r2 %3
  56 %define %%r3 %4
  57 %define %%t0 %5
  58 %define %%t1 %6
  59         movaps  %%t0, %%r0              ; t0 = {a3 a2 a1 a0}
  60         shufps  %%t0, %%r1, 0x44        ; t0 = {b1 b0 a1 a0}
  61         shufps  %%r0, %%r1, 0xEE        ; r0 = {b3 b2 a3 a2}
  62
  63         movaps  %%t1, %%r2              ; t1 = {c3 c2 c1 c0}
  64         shufps  %%t1, %%r3, 0x44        ; t1 = {d1 d0 c1 c0}
  65         shufps  %%r2, %%r3, 0xEE        ; r2 = {d3 d2 c3 c2}
  66
  67         movaps  %%r1, %%t0              ; r1 = {b1 b0 a1 a0}
  68         shufps  %%r1, %%t1, 0xDD        ; r1 = {d1 c1 b1 a1}
  69
  70         movaps  %%r3, %%r0              ; r3 = {b3 b2 a3 a2}
  71         shufps  %%r3, %%r2, 0xDD        ; r3 = {d3 c3 b3 a3}
  72
  73         shufps  %%r0, %%r2, 0x88        ; r0 = {d2 c2 b2 a2}
  74         shufps  %%t0, %%t1, 0x88        ; t0 = {d0 c0 b0 a0}
  75 %endmacro
  76
  77
  78 %define TABLE   K256_4_MB
  79 %define SZ      4
  80 %define SZ4     4*SZ
  81 %define ROUNDS 64*SZ4
  82
  83 %define a xmm0
  84 %define b xmm1
  85 %define c xmm2
  86 %define d xmm3
  87 %define e xmm4
  88 %define f xmm5
  89 %define g xmm6
  90 %define h xmm7
  91
  92 %define a0 xmm8
  93 %define a1 xmm9
  94 %define a2 xmm10
  95
  96 %define TT0 xmm14
  97 %define TT1 xmm13
  98 %define TT2 xmm12
  99 %define TT3 xmm11
 100 %define TT4 xmm10
 101 %define TT5 xmm9
 102
 103 %define T1  xmm14
 104 %define TMP xmm15
 105
 106
 107 %macro ROTATE_ARGS 0
 108 %xdefine TMP_ h
 109 %xdefine h g
 110 %xdefine g f
 111 %xdefine f e
 112 %xdefine e d
 113 %xdefine d c
 114 %xdefine c b
 115 %xdefine b a
 116 %xdefine a TMP_
 117 %endm
 118
 119 ; PRORD reg, imm, tmp
 120 %macro PRORD 3
 121 %define %%reg %1
 122 %define %%imm %2
 123 %define %%tmp %3
 124         movdqa  %%tmp, %%reg
 125         psrld   %%reg, %%imm
 126         pslld   %%tmp, (32-(%%imm))
 127         por     %%reg, %%tmp
 128 %endmacro
 129
 130 %macro PRORD 2
 131         PRORD   %1, %2, TMP
 132 %endmacro
 133
 134 ;; arguments passed implicitly in preprocessor symbols i, a...h
 135 %macro ROUND_00_15 2
 136 %define %%T1 %1
 137 %define %%i  %2
 138
 139
 140         movdqa  a0, e           ; sig1: a0 = e
 141         movdqa  a1, e           ; sig1: s1 = e
 142         PRORD   a0, (11-6)      ; sig1: a0 = (e >> 5)
 143
 144         movdqa  a2, f           ; ch: a2 = f
 145         pxor    a2, g           ; ch: a2 = f^g
 146         pand    a2, e           ; ch: a2 = (f^g)&e
 147         pxor    a2, g           ; a2 = ch
 148
 149         PRORD   a1, 25          ; sig1: a1 = (e >> 25)
 150         movdqa  [SZ4*(%%i&0xf) + rsp],%%T1
 151         paddd   %%T1,[TBL + ROUND]      ; T1 = W + K
 152         pxor    a0, e           ; sig1: a0 = e ^ (e >> 5)
 153         PRORD   a0, 6           ; sig1: a0 = (e >> 6) ^ (e >> 11)
 154         paddd   h, a2           ; h = h + ch
 155         movdqa  a2, a           ; sig0: a2 = a
 156         PRORD   a2, (13-2)      ; sig0: a2 = (a >> 11)
 157         paddd   h, %%T1         ; h = h + ch + W + K
 158         pxor    a0, a1          ; a0 = sigma1
 159         movdqa  a1, a           ; sig0: a1 = a
 160         movdqa  %%T1, a         ; maj: T1 = a
 161         PRORD   a1, 22          ; sig0: a1 = (a >> 22)
 162         pxor    %%T1, c         ; maj: T1 = a^c
 163         add     ROUND, SZ4      ; ROUND++
 164         pand    %%T1, b         ; maj: T1 = (a^c)&b
 165         paddd   h, a0
 166
 167         paddd   d, h
 168
 169         pxor    a2, a           ; sig0: a2 = a ^ (a >> 11)
 170         PRORD   a2, 2           ; sig0: a2 = (a >> 2) ^ (a >> 13)
 171         pxor    a2, a1          ; a2 = sig0
 172         movdqa  a1, a           ; maj: a1 = a
 173         pand    a1, c           ; maj: a1 = a&c
 174         por     a1, %%T1        ; a1 = maj
 175         paddd   h, a1           ; h = h + ch + W + K + maj
 176         paddd   h, a2           ; h = h + ch + W + K + maj + sigma0
 177
 178         ROTATE_ARGS
 179 %endm
 180
 181
 182 ;; arguments passed implicitly in preprocessor symbols i, a...h
 183 %macro ROUND_16_XX 2
 184 %define %%T1 %1
 185 %define %%i  %2
 186
 187         movdqa  %%T1, [SZ4*((%%i-15)&0xf) + rsp]
 188         movdqa  a1, [SZ4*((%%i-2)&0xf) + rsp]
 189         movdqa  a0, %%T1
 190         PRORD   %%T1, 18-7
 191         movdqa  a2, a1
 192         PRORD   a1, 19-17
 193         pxor    %%T1, a0
 194         PRORD   %%T1, 7
 195         pxor    a1, a2
 196         PRORD   a1, 17
 197         psrld   a0, 3
 198         pxor    %%T1, a0
 199         psrld   a2, 10
 200         pxor    a1, a2
 201         paddd   %%T1, [SZ4*((%%i-16)&0xf) + rsp]
 202         paddd   a1, [SZ4*((%%i-7)&0xf) + rsp]
 203         paddd   %%T1, a1
 204
 205         ROUND_00_15 %%T1, %%i
 206 %endm
 207
 208 %define DIGEST_SIZE     8*SZ4
 209 %define DATA           16*SZ4
 210 %define ALIGNMENT       1*8
 211 ; ALIGNMENT makes FRAMESZ + pushes an odd multiple of 8
 212 %define FRAMESZ (DATA + DIGEST_SIZE + ALIGNMENT)
 213 %define _DIGEST (DATA)
 214
 215 %define MOVPS   movups
 216
 217 %define inp0 r8
 218 %define inp1 r9
 219 %define inp2 r10
 220 %define inp3 r11
 221
 222 %ifidn __OUTPUT_FORMAT__, elf64
 223  ; Linux definitions
 224  %define arg1   rdi
 225  %define arg2   rsi
 226 %else
 227  ; Windows definitions
 228  %define arg1   rcx
 229  %define arg2   rdx
 230 %endif
 231
 232 ; Common definitions
 233 %define IDX     rax
 234 %define ROUND   rbx
 235 %define TBL     r12
 236
 237 ;; void sha256_mb_x4_sse(SHA256_MB_ARGS_X8 *args, uint64_t len);
 238 ;; arg 1 :  pointer args (only 4 of the 8 lanes used)
 239 ;; arg 2 :  size of data in blocks (assumed >= 1)
 240 ;;
 241 ;; Clobbers registers: arg2, rax, rbx, r8-r12, xmm0-xmm15
 242 ;;
 243
 244 global sha256_mb_x4_sse:function internal
 245 align 32
 246 sha256_mb_x4_sse:
 247         sub     rsp, FRAMESZ
 248
 249         ;; Initialize digests
 250         movdqa  a,[arg1+0*SZ4]
 251         movdqa  b,[arg1+1*SZ4]
 252         movdqa  c,[arg1+2*SZ4]
 253         movdqa  d,[arg1+3*SZ4]
 254         movdqa  e,[arg1+4*SZ4]
 255         movdqa  f,[arg1+5*SZ4]
 256         movdqa  g,[arg1+6*SZ4]
 257         movdqa  h,[arg1+7*SZ4]
 258
 259         lea     TBL,[TABLE]
 260
 261         ;; transpose input onto stack
 262         mov     inp0,[arg1 + _data_ptr + 0*8]
 263         mov     inp1,[arg1 + _data_ptr + 1*8]
 264         mov     inp2,[arg1 + _data_ptr + 2*8]
 265         mov     inp3,[arg1 + _data_ptr + 3*8]
 266
 267         xor     IDX, IDX
 268 lloop:
 269         xor     ROUND, ROUND
 270
 271         ;; save old digest
 272         movdqa  [rsp + _DIGEST + 0*SZ4], a
 273         movdqa  [rsp + _DIGEST + 1*SZ4], b
 274         movdqa  [rsp + _DIGEST + 2*SZ4], c
 275         movdqa  [rsp + _DIGEST + 3*SZ4], d
 276         movdqa  [rsp + _DIGEST + 4*SZ4], e
 277         movdqa  [rsp + _DIGEST + 5*SZ4], f
 278         movdqa  [rsp + _DIGEST + 6*SZ4], g
 279         movdqa  [rsp + _DIGEST + 7*SZ4], h
 280
 281 %assign i 0
 282 %rep 4
 283         movdqa  TMP, [PSHUFFLE_BYTE_FLIP_MASK]
 284         MOVPS   TT2,[inp0+IDX+i*16]
 285         MOVPS   TT1,[inp1+IDX+i*16]
 286         MOVPS   TT4,[inp2+IDX+i*16]
 287         MOVPS   TT3,[inp3+IDX+i*16]
 288         TRANSPOSE       TT2, TT1, TT4, TT3, TT0, TT5
 289         pshufb  TT0, TMP
 290         pshufb  TT1, TMP
 291         pshufb  TT2, TMP
 292         pshufb  TT3, TMP
 293         ROUND_00_15     TT0,(i*4+0)
 294         ROUND_00_15     TT1,(i*4+1)
 295         ROUND_00_15     TT2,(i*4+2)
 296         ROUND_00_15     TT3,(i*4+3)
 297 %assign i (i+1)
 298 %endrep
 299         add     IDX, 4*4*4
 300
 301
 302 %assign i (i*4)
 303
 304         jmp     Lrounds_16_xx
 305 align 16
 306 Lrounds_16_xx:
 307 %rep 16
 308         ROUND_16_XX     T1, i
 309 %assign i (i+1)
 310 %endrep
 311
 312         cmp     ROUND,ROUNDS
 313         jb      Lrounds_16_xx
 314
 315         ;; add old digest
 316         paddd   a, [rsp + _DIGEST + 0*SZ4]
 317         paddd   b, [rsp + _DIGEST + 1*SZ4]
 318         paddd   c, [rsp + _DIGEST + 2*SZ4]
 319         paddd   d, [rsp + _DIGEST + 3*SZ4]
 320         paddd   e, [rsp + _DIGEST + 4*SZ4]
 321         paddd   f, [rsp + _DIGEST + 5*SZ4]
 322         paddd   g, [rsp + _DIGEST + 6*SZ4]
 323         paddd   h, [rsp + _DIGEST + 7*SZ4]
 324
 325
 326         sub     arg2, 1
 327         jne     lloop
 328
 329         ; write digests out
 330         movdqa  [arg1+0*SZ4],a
 331         movdqa  [arg1+1*SZ4],b
 332         movdqa  [arg1+2*SZ4],c
 333         movdqa  [arg1+3*SZ4],d
 334         movdqa  [arg1+4*SZ4],e
 335         movdqa  [arg1+5*SZ4],f
 336         movdqa  [arg1+6*SZ4],g
 337         movdqa  [arg1+7*SZ4],h
 338
 339         ; update input pointers
 340         add     inp0, IDX
 341         mov     [arg1 + _data_ptr + 0*8], inp0
 342         add     inp1, IDX
 343         mov     [arg1 + _data_ptr + 1*8], inp1
 344         add     inp2, IDX
 345         mov     [arg1 + _data_ptr + 2*8], inp2
 346         add     inp3, IDX
 347         mov     [arg1 + _data_ptr + 3*8], inp3
 348
 349         ;;;;;;;;;;;;;;;;
 350         ;; Postamble
 351
 352         add     rsp, FRAMESZ
 353         ret
 354
 355 section .data align=64
 356
 357 align 64
 358 TABLE:
 359         dq      0x428a2f98428a2f98, 0x428a2f98428a2f98
 360         dq      0x7137449171374491, 0x7137449171374491
 361         dq      0xb5c0fbcfb5c0fbcf, 0xb5c0fbcfb5c0fbcf
 362         dq      0xe9b5dba5e9b5dba5, 0xe9b5dba5e9b5dba5
 363         dq      0x3956c25b3956c25b, 0x3956c25b3956c25b
 364         dq      0x59f111f159f111f1, 0x59f111f159f111f1
 365         dq      0x923f82a4923f82a4, 0x923f82a4923f82a4
 366         dq      0xab1c5ed5ab1c5ed5, 0xab1c5ed5ab1c5ed5
 367         dq      0xd807aa98d807aa98, 0xd807aa98d807aa98
 368         dq      0x12835b0112835b01, 0x12835b0112835b01
 369         dq      0x243185be243185be, 0x243185be243185be
 370         dq      0x550c7dc3550c7dc3, 0x550c7dc3550c7dc3
 371         dq      0x72be5d7472be5d74, 0x72be5d7472be5d74
 372         dq      0x80deb1fe80deb1fe, 0x80deb1fe80deb1fe
 373         dq      0x9bdc06a79bdc06a7, 0x9bdc06a79bdc06a7
 374         dq      0xc19bf174c19bf174, 0xc19bf174c19bf174
 375         dq      0xe49b69c1e49b69c1, 0xe49b69c1e49b69c1
 376         dq      0xefbe4786efbe4786, 0xefbe4786efbe4786
 377         dq      0x0fc19dc60fc19dc6, 0x0fc19dc60fc19dc6
 378         dq      0x240ca1cc240ca1cc, 0x240ca1cc240ca1cc
 379         dq      0x2de92c6f2de92c6f, 0x2de92c6f2de92c6f
 380         dq      0x4a7484aa4a7484aa, 0x4a7484aa4a7484aa
 381         dq      0x5cb0a9dc5cb0a9dc, 0x5cb0a9dc5cb0a9dc
 382         dq      0x76f988da76f988da, 0x76f988da76f988da
 383         dq      0x983e5152983e5152, 0x983e5152983e5152
 384         dq      0xa831c66da831c66d, 0xa831c66da831c66d
 385         dq      0xb00327c8b00327c8, 0xb00327c8b00327c8
 386         dq      0xbf597fc7bf597fc7, 0xbf597fc7bf597fc7
 387         dq      0xc6e00bf3c6e00bf3, 0xc6e00bf3c6e00bf3
 388         dq      0xd5a79147d5a79147, 0xd5a79147d5a79147
 389         dq      0x06ca635106ca6351, 0x06ca635106ca6351
 390         dq      0x1429296714292967, 0x1429296714292967
 391         dq      0x27b70a8527b70a85, 0x27b70a8527b70a85
 392         dq      0x2e1b21382e1b2138, 0x2e1b21382e1b2138
 393         dq      0x4d2c6dfc4d2c6dfc, 0x4d2c6dfc4d2c6dfc
 394         dq      0x53380d1353380d13, 0x53380d1353380d13
 395         dq      0x650a7354650a7354, 0x650a7354650a7354
 396         dq      0x766a0abb766a0abb, 0x766a0abb766a0abb
 397         dq      0x81c2c92e81c2c92e, 0x81c2c92e81c2c92e
 398         dq      0x92722c8592722c85, 0x92722c8592722c85
 399         dq      0xa2bfe8a1a2bfe8a1, 0xa2bfe8a1a2bfe8a1
 400         dq      0xa81a664ba81a664b, 0xa81a664ba81a664b
 401         dq      0xc24b8b70c24b8b70, 0xc24b8b70c24b8b70
 402         dq      0xc76c51a3c76c51a3, 0xc76c51a3c76c51a3
 403         dq      0xd192e819d192e819, 0xd192e819d192e819
 404         dq      0xd6990624d6990624, 0xd6990624d6990624
 405         dq      0xf40e3585f40e3585, 0xf40e3585f40e3585
 406         dq      0x106aa070106aa070, 0x106aa070106aa070
 407         dq      0x19a4c11619a4c116, 0x19a4c11619a4c116
 408         dq      0x1e376c081e376c08, 0x1e376c081e376c08
 409         dq      0x2748774c2748774c, 0x2748774c2748774c
 410         dq      0x34b0bcb534b0bcb5, 0x34b0bcb534b0bcb5
 411         dq      0x391c0cb3391c0cb3, 0x391c0cb3391c0cb3
 412         dq      0x4ed8aa4a4ed8aa4a, 0x4ed8aa4a4ed8aa4a
 413         dq      0x5b9cca4f5b9cca4f, 0x5b9cca4f5b9cca4f
 414         dq      0x682e6ff3682e6ff3, 0x682e6ff3682e6ff3
 415         dq      0x748f82ee748f82ee, 0x748f82ee748f82ee
 416         dq      0x78a5636f78a5636f, 0x78a5636f78a5636f
 417         dq      0x84c8781484c87814, 0x84c8781484c87814
 418         dq      0x8cc702088cc70208, 0x8cc702088cc70208
 419         dq      0x90befffa90befffa, 0x90befffa90befffa
 420         dq      0xa4506ceba4506ceb, 0xa4506ceba4506ceb
 421         dq      0xbef9a3f7bef9a3f7, 0xbef9a3f7bef9a3f7
 422         dq      0xc67178f2c67178f2, 0xc67178f2c67178f2
 423 PSHUFFLE_BYTE_FLIP_MASK: dq 0x0405060700010203, 0x0c0d0e0f08090a0b