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28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
30 %include "sha512_job.asm"
31 %include "sha512_mb_mgr_datastruct.asm"
33 %include "reg_sizes.asm"
35 extern sha512_mb_x2_sse
38 %ifidn __OUTPUT_FORMAT__, elf64
39 ; LINUX register definitions
40 %define arg1 rdi ; rcx
41 %define arg2 rsi ; rdx
43 ; idx needs to be other than arg1, arg2, rbx, r12
46 ; WINDOWS register definitions
50 ; idx needs to be other than arg1, arg2, rbx, r12
59 %define unused_lanes rbx
65 %define size_offset rax
67 %define start_offset rax
71 %define extra_blocks arg2
81 ; STACK_SPACE needs to be an odd multiple of 8
82 _XMM_SAVE_SIZE equ 10*16
83 _GPR_SAVE_SIZE equ 8*3
87 _GPR_SAVE equ _XMM_SAVE + _XMM_SAVE_SIZE
88 STACK_SPACE equ _GPR_SAVE + _GPR_SAVE_SIZE + _ALIGN_SIZE
90 %define APPEND(a,b) a %+ b
92 ; SHA512_JOB* sha512_mb_mgr_flush_sse(SHA512_MB_JOB_MGR *state)
94 global sha512_mb_mgr_flush_sse:function
95 sha512_mb_mgr_flush_sse:
98 mov [rsp + _GPR_SAVE + 8*0], rbx
99 mov [rsp + _GPR_SAVE + 8*1], r12
100 %ifidn __OUTPUT_FORMAT__, win64
101 mov [rsp + _GPR_SAVE + 8*2], rsi
102 movdqa [rsp + _XMM_SAVE + 16*0], xmm6
103 movdqa [rsp + _XMM_SAVE + 16*1], xmm7
104 movdqa [rsp + _XMM_SAVE + 16*2], xmm8
105 movdqa [rsp + _XMM_SAVE + 16*3], xmm9
106 movdqa [rsp + _XMM_SAVE + 16*4], xmm10
107 movdqa [rsp + _XMM_SAVE + 16*5], xmm11
108 movdqa [rsp + _XMM_SAVE + 16*6], xmm12
109 movdqa [rsp + _XMM_SAVE + 16*7], xmm13
110 movdqa [rsp + _XMM_SAVE + 16*8], xmm14
111 movdqa [rsp + _XMM_SAVE + 16*9], xmm15
115 mov unused_lanes, [state + _unused_lanes]
116 bt unused_lanes, 16+7
119 ; find a lane with a non-null job
121 cmp qword [state + _ldata + 1 * _LANE_DATA_size + _job_in_lane], 0
124 ; copy idx to empty lanes
126 mov tmp, [state + _args + _data_ptr + 8*idx]
130 cmp qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0
132 mov [state + _args + _data_ptr + 8*I], tmp
133 mov dword [state + _lens + 4 + 8*I], 0xFFFFFFFF
139 mov lens0, [state + _lens + 0*8]
141 mov lens1, [state + _lens + 1*8]
153 mov [state + _lens + 0*8], lens0
154 mov [state + _lens + 1*8], lens1
156 ; "state" and "args" are the same address, arg1
158 call sha512_mb_x2_sse
159 ; state and idx are intact
163 ; process completed job "idx"
164 imul lane_data, idx, _LANE_DATA_size
165 lea lane_data, [state + _ldata + lane_data]
167 mov job_rax, [lane_data + _job_in_lane]
168 mov qword [lane_data + _job_in_lane], 0
169 mov dword [job_rax + _status], STS_COMPLETED
170 mov unused_lanes, [state + _unused_lanes]
173 mov [state + _unused_lanes], unused_lanes
175 movq xmm0, [state + _args_digest + 8*idx + 0*32]
176 pinsrq xmm0, [state + _args_digest + 8*idx + 1*32], 1
177 movq xmm1, [state + _args_digest + 8*idx + 2*32]
178 pinsrq xmm1, [state + _args_digest + 8*idx + 3*32], 1
179 movq xmm2, [state + _args_digest + 8*idx + 4*32]
180 pinsrq xmm2, [state + _args_digest + 8*idx + 5*32], 1
181 movq xmm3, [state + _args_digest + 8*idx + 6*32]
182 pinsrq xmm3, [state + _args_digest + 8*idx + 7*32], 1
185 movdqa [job_rax + _result_digest + 0*16], xmm0
186 movdqa [job_rax + _result_digest + 1*16], xmm1
187 movdqa [job_rax + _result_digest + 2*16], xmm2
188 movdqa [job_rax + _result_digest + 3*16], xmm3
192 %ifidn __OUTPUT_FORMAT__, win64
193 movdqa xmm6, [rsp + _XMM_SAVE + 16*0]
194 movdqa xmm7, [rsp + _XMM_SAVE + 16*1]
195 movdqa xmm8, [rsp + _XMM_SAVE + 16*2]
196 movdqa xmm9, [rsp + _XMM_SAVE + 16*3]
197 movdqa xmm10, [rsp + _XMM_SAVE + 16*4]
198 movdqa xmm11, [rsp + _XMM_SAVE + 16*5]
199 movdqa xmm12, [rsp + _XMM_SAVE + 16*6]
200 movdqa xmm13, [rsp + _XMM_SAVE + 16*7]
201 movdqa xmm14, [rsp + _XMM_SAVE + 16*8]
202 movdqa xmm15, [rsp + _XMM_SAVE + 16*9]
203 mov rsi, [rsp + _GPR_SAVE + 8*2]
205 mov rbx, [rsp + _GPR_SAVE + 8*0]
206 mov r12, [rsp + _GPR_SAVE + 8*1]
215 section .data align=16