]> git.proxmox.com Git - ceph.git/blob - ceph/src/crypto/isa-l/isa-l_crypto/sha512_mb/sha512_mb_mgr_flush_sse.asm
add subtree-ish sources for 12.0.3
[ceph.git] / ceph / src / crypto / isa-l / isa-l_crypto / sha512_mb / sha512_mb_mgr_flush_sse.asm
1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ; Copyright(c) 2011-2016 Intel Corporation All rights reserved.
3 ;
4 ; Redistribution and use in source and binary forms, with or without
5 ; modification, are permitted provided that the following conditions
6 ; are met:
7 ; * Redistributions of source code must retain the above copyright
8 ; notice, this list of conditions and the following disclaimer.
9 ; * Redistributions in binary form must reproduce the above copyright
10 ; notice, this list of conditions and the following disclaimer in
11 ; the documentation and/or other materials provided with the
12 ; distribution.
13 ; * Neither the name of Intel Corporation nor the names of its
14 ; contributors may be used to endorse or promote products derived
15 ; from this software without specific prior written permission.
16 ;
17 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
29
30 %include "sha512_job.asm"
31 %include "sha512_mb_mgr_datastruct.asm"
32
33 %include "reg_sizes.asm"
34
35 extern sha512_mb_x2_sse
36 default rel
37
38 %ifidn __OUTPUT_FORMAT__, elf64
39 ; LINUX register definitions
40 %define arg1 rdi ; rcx
41 %define arg2 rsi ; rdx
42
43 ; idx needs to be other than arg1, arg2, rbx, r12
44 %define idx rdx ; rsi
45 %else
46 ; WINDOWS register definitions
47 %define arg1 rcx
48 %define arg2 rdx
49
50 ; idx needs to be other than arg1, arg2, rbx, r12
51 %define idx rsi
52 %endif
53
54 ; Common definitions
55 %define state arg1
56 %define job arg2
57 %define len2 arg2
58
59 %define unused_lanes rbx
60 %define lane_data rbx
61 %define tmp2 rbx
62
63 %define job_rax rax
64 %define tmp1 rax
65 %define size_offset rax
66 %define tmp rax
67 %define start_offset rax
68
69 %define tmp3 arg1
70
71 %define extra_blocks arg2
72 %define p arg2
73
74 %define tmp4 r8
75 %define lens0 r8
76
77 %define lens1 r9
78 %define lens2 r10
79 %define lens3 r11
80
81 ; STACK_SPACE needs to be an odd multiple of 8
82 _XMM_SAVE_SIZE equ 10*16
83 _GPR_SAVE_SIZE equ 8*3
84 _ALIGN_SIZE equ 0
85
86 _XMM_SAVE equ 0
87 _GPR_SAVE equ _XMM_SAVE + _XMM_SAVE_SIZE
88 STACK_SPACE equ _GPR_SAVE + _GPR_SAVE_SIZE + _ALIGN_SIZE
89
90 %define APPEND(a,b) a %+ b
91
92 ; SHA512_JOB* sha512_mb_mgr_flush_sse(SHA512_MB_JOB_MGR *state)
93 ; arg 1 : rcx : state
94 global sha512_mb_mgr_flush_sse:function
95 sha512_mb_mgr_flush_sse:
96
97 sub rsp, STACK_SPACE
98 mov [rsp + _GPR_SAVE + 8*0], rbx
99 mov [rsp + _GPR_SAVE + 8*1], r12
100 %ifidn __OUTPUT_FORMAT__, win64
101 mov [rsp + _GPR_SAVE + 8*2], rsi
102 movdqa [rsp + _XMM_SAVE + 16*0], xmm6
103 movdqa [rsp + _XMM_SAVE + 16*1], xmm7
104 movdqa [rsp + _XMM_SAVE + 16*2], xmm8
105 movdqa [rsp + _XMM_SAVE + 16*3], xmm9
106 movdqa [rsp + _XMM_SAVE + 16*4], xmm10
107 movdqa [rsp + _XMM_SAVE + 16*5], xmm11
108 movdqa [rsp + _XMM_SAVE + 16*6], xmm12
109 movdqa [rsp + _XMM_SAVE + 16*7], xmm13
110 movdqa [rsp + _XMM_SAVE + 16*8], xmm14
111 movdqa [rsp + _XMM_SAVE + 16*9], xmm15
112 %endif
113
114
115 mov unused_lanes, [state + _unused_lanes]
116 bt unused_lanes, 16+7
117 jc return_null
118
119 ; find a lane with a non-null job
120 xor idx, idx
121 cmp qword [state + _ldata + 1 * _LANE_DATA_size + _job_in_lane], 0
122 cmovne idx, [one]
123
124 ; copy idx to empty lanes
125 copy_lane_data:
126 mov tmp, [state + _args + _data_ptr + 8*idx]
127
128 %assign I 0
129 %rep 2
130 cmp qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0
131 jne APPEND(skip_,I)
132 mov [state + _args + _data_ptr + 8*I], tmp
133 mov dword [state + _lens + 4 + 8*I], 0xFFFFFFFF
134 APPEND(skip_,I):
135 %assign I (I+1)
136 %endrep
137
138 ; Find min length
139 mov lens0, [state + _lens + 0*8]
140 mov idx, lens0
141 mov lens1, [state + _lens + 1*8]
142 cmp lens1, idx
143 cmovb idx, lens1
144
145 mov len2, idx
146 and idx, 0xF
147 and len2, ~0xFF
148 jz len_is_0
149
150 sub lens0, len2
151 sub lens1, len2
152 shr len2, 32
153 mov [state + _lens + 0*8], lens0
154 mov [state + _lens + 1*8], lens1
155
156 ; "state" and "args" are the same address, arg1
157 ; len is arg2
158 call sha512_mb_x2_sse
159 ; state and idx are intact
160
161
162 len_is_0:
163 ; process completed job "idx"
164 imul lane_data, idx, _LANE_DATA_size
165 lea lane_data, [state + _ldata + lane_data]
166
167 mov job_rax, [lane_data + _job_in_lane]
168 mov qword [lane_data + _job_in_lane], 0
169 mov dword [job_rax + _status], STS_COMPLETED
170 mov unused_lanes, [state + _unused_lanes]
171 shl unused_lanes, 8
172 or unused_lanes, idx
173 mov [state + _unused_lanes], unused_lanes
174
175 movq xmm0, [state + _args_digest + 8*idx + 0*32]
176 pinsrq xmm0, [state + _args_digest + 8*idx + 1*32], 1
177 movq xmm1, [state + _args_digest + 8*idx + 2*32]
178 pinsrq xmm1, [state + _args_digest + 8*idx + 3*32], 1
179 movq xmm2, [state + _args_digest + 8*idx + 4*32]
180 pinsrq xmm2, [state + _args_digest + 8*idx + 5*32], 1
181 movq xmm3, [state + _args_digest + 8*idx + 6*32]
182 pinsrq xmm3, [state + _args_digest + 8*idx + 7*32], 1
183
184
185 movdqa [job_rax + _result_digest + 0*16], xmm0
186 movdqa [job_rax + _result_digest + 1*16], xmm1
187 movdqa [job_rax + _result_digest + 2*16], xmm2
188 movdqa [job_rax + _result_digest + 3*16], xmm3
189
190 return:
191
192 %ifidn __OUTPUT_FORMAT__, win64
193 movdqa xmm6, [rsp + _XMM_SAVE + 16*0]
194 movdqa xmm7, [rsp + _XMM_SAVE + 16*1]
195 movdqa xmm8, [rsp + _XMM_SAVE + 16*2]
196 movdqa xmm9, [rsp + _XMM_SAVE + 16*3]
197 movdqa xmm10, [rsp + _XMM_SAVE + 16*4]
198 movdqa xmm11, [rsp + _XMM_SAVE + 16*5]
199 movdqa xmm12, [rsp + _XMM_SAVE + 16*6]
200 movdqa xmm13, [rsp + _XMM_SAVE + 16*7]
201 movdqa xmm14, [rsp + _XMM_SAVE + 16*8]
202 movdqa xmm15, [rsp + _XMM_SAVE + 16*9]
203 mov rsi, [rsp + _GPR_SAVE + 8*2]
204 %endif
205 mov rbx, [rsp + _GPR_SAVE + 8*0]
206 mov r12, [rsp + _GPR_SAVE + 8*1]
207 add rsp, STACK_SPACE
208
209 ret
210
211 return_null:
212 xor job_rax, job_rax
213 jmp return
214
215 section .data align=16
216
217 align 16
218 one: dq 1
219 two: dq 2
220 three: dq 3
221