ceph/src/dpdk/app/test-pipeline/pipeline_acl.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <stdint.h>
  37
  38 #include <rte_log.h>
  39 #include <rte_ethdev.h>
  40 #include <rte_ether.h>
  41 #include <rte_ip.h>
  42 #include <rte_byteorder.h>
  43
  44 #include <rte_port_ring.h>
  45 #include <rte_table_acl.h>
  46 #include <rte_pipeline.h>
  47
  48 #include "main.h"
  49
  50 enum {
  51         PROTO_FIELD_IPV4,
  52         SRC_FIELD_IPV4,
  53         DST_FIELD_IPV4,
  54         SRCP_FIELD_IPV4,
  55         DSTP_FIELD_IPV4,
  56         NUM_FIELDS_IPV4
  57 };
  58
  59 /*
  60  * Here we define the 'shape' of the data we're searching for,
  61  * by defining the meta-data of the ACL rules.
  62  * in this case, we're defining 5 tuples. IP addresses, ports,
  63  * and protocol.
  64  */
  65 struct rte_acl_field_def ipv4_field_formats[NUM_FIELDS_IPV4] = {
  66         {
  67                 .type = RTE_ACL_FIELD_TYPE_BITMASK,
  68                 .size = sizeof(uint8_t),
  69                 .field_index = PROTO_FIELD_IPV4,
  70                 .input_index = PROTO_FIELD_IPV4,
  71                 .offset = sizeof(struct ether_hdr) +
  72                         offsetof(struct ipv4_hdr, next_proto_id),
  73         },
  74         {
  75                 .type = RTE_ACL_FIELD_TYPE_MASK,
  76                 .size = sizeof(uint32_t),
  77                 .field_index = SRC_FIELD_IPV4,
  78                 .input_index = SRC_FIELD_IPV4,
  79                 .offset = sizeof(struct ether_hdr) +
  80                         offsetof(struct ipv4_hdr, src_addr),
  81         },
  82         {
  83                 .type = RTE_ACL_FIELD_TYPE_MASK,
  84                 .size = sizeof(uint32_t),
  85                 .field_index = DST_FIELD_IPV4,
  86                 .input_index = DST_FIELD_IPV4,
  87                 .offset = sizeof(struct ether_hdr) +
  88                         offsetof(struct ipv4_hdr, dst_addr),
  89         },
  90         {
  91                 .type = RTE_ACL_FIELD_TYPE_RANGE,
  92                 .size = sizeof(uint16_t),
  93                 .field_index = SRCP_FIELD_IPV4,
  94                 .input_index = SRCP_FIELD_IPV4,
  95                 .offset = sizeof(struct ether_hdr) + sizeof(struct ipv4_hdr),
  96         },
  97         {
  98                 .type = RTE_ACL_FIELD_TYPE_RANGE,
  99                 .size = sizeof(uint16_t),
 100                 .field_index = DSTP_FIELD_IPV4,
 101                 .input_index = SRCP_FIELD_IPV4,
 102                 .offset = sizeof(struct ether_hdr) + sizeof(struct ipv4_hdr) +
 103                         sizeof(uint16_t),
 104         },
 105 };
 106
 107
 108
 109 void
 110 app_main_loop_worker_pipeline_acl(void) {
 111         struct rte_pipeline_params pipeline_params = {
 112                 .name = "pipeline",
 113                 .socket_id = rte_socket_id(),
 114         };
 115
 116         struct rte_pipeline *p;
 117         uint32_t port_in_id[APP_MAX_PORTS];
 118         uint32_t port_out_id[APP_MAX_PORTS];
 119         uint32_t table_id;
 120         uint32_t i;
 121
 122         RTE_LOG(INFO, USER1,
 123                 "Core %u is doing work (pipeline with ACL table)\n",
 124                 rte_lcore_id());
 125
 126         /* Pipeline configuration */
 127         p = rte_pipeline_create(&pipeline_params);
 128         if (p == NULL)
 129                 rte_panic("Unable to configure the pipeline\n");
 130
 131         /* Input port configuration */
 132         for (i = 0; i < app.n_ports; i++) {
 133                 struct rte_port_ring_reader_params port_ring_params = {
 134                         .ring = app.rings_rx[i],
 135                 };
 136
 137                 struct rte_pipeline_port_in_params port_params = {
 138                         .ops = &rte_port_ring_reader_ops,
 139                         .arg_create = (void *) &port_ring_params,
 140                         .f_action = NULL,
 141                         .arg_ah = NULL,
 142                         .burst_size = app.burst_size_worker_read,
 143                 };
 144
 145                 if (rte_pipeline_port_in_create(p, &port_params,
 146                         &port_in_id[i]))
 147                         rte_panic("Unable to configure input port for "
 148                                 "ring %d\n", i);
 149         }
 150
 151         /* Output port configuration */
 152         for (i = 0; i < app.n_ports; i++) {
 153                 struct rte_port_ring_writer_params port_ring_params = {
 154                         .ring = app.rings_tx[i],
 155                         .tx_burst_sz = app.burst_size_worker_write,
 156                 };
 157
 158                 struct rte_pipeline_port_out_params port_params = {
 159                         .ops = &rte_port_ring_writer_ops,
 160                         .arg_create = (void *) &port_ring_params,
 161                         .f_action = NULL,
 162                         .arg_ah = NULL,
 163                 };
 164
 165                 if (rte_pipeline_port_out_create(p, &port_params,
 166                         &port_out_id[i]))
 167                         rte_panic("Unable to configure output port for "
 168                                 "ring %d\n", i);
 169         }
 170
 171         /* Table configuration */
 172         {
 173                 struct rte_table_acl_params table_acl_params = {
 174                         .name = "test", /* unique identifier for acl contexts */
 175                         .n_rules = 1 << 5,
 176                         .n_rule_fields = DIM(ipv4_field_formats),
 177                 };
 178
 179                 /* Copy in the rule meta-data defined above into the params */
 180                 memcpy(table_acl_params.field_format, ipv4_field_formats,
 181                         sizeof(ipv4_field_formats));
 182
 183                 struct rte_pipeline_table_params table_params = {
 184                         .ops = &rte_table_acl_ops,
 185                         .arg_create = &table_acl_params,
 186                         .f_action_hit = NULL,
 187                         .f_action_miss = NULL,
 188                         .arg_ah = NULL,
 189                         .action_data_size = 0,
 190                 };
 191
 192                 if (rte_pipeline_table_create(p, &table_params, &table_id))
 193                         rte_panic("Unable to configure the ACL table\n");
 194         }
 195
 196         /* Interconnecting ports and tables */
 197         for (i = 0; i < app.n_ports; i++)
 198                 if (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],
 199                         table_id))
 200                         rte_panic("Unable to connect input port %u to "
 201                                 "table %u\n", port_in_id[i],  table_id);
 202
 203         /* Add entries to tables */
 204         for (i = 0; i < app.n_ports; i++) {
 205                 struct rte_pipeline_table_entry table_entry = {
 206                         .action = RTE_PIPELINE_ACTION_PORT,
 207                         {.port_id = port_out_id[i & (app.n_ports - 1)]},
 208                 };
 209                 struct rte_table_acl_rule_add_params rule_params;
 210                 struct rte_pipeline_table_entry *entry_ptr;
 211                 int key_found, ret;
 212
 213                 memset(&rule_params, 0, sizeof(rule_params));
 214
 215                 /* Set the rule values */
 216                 rule_params.field_value[SRC_FIELD_IPV4].value.u32 = 0;
 217                 rule_params.field_value[SRC_FIELD_IPV4].mask_range.u32 = 0;
 218                 rule_params.field_value[DST_FIELD_IPV4].value.u32 =
 219                         i << (24 - __builtin_popcount(app.n_ports - 1));
 220                 rule_params.field_value[DST_FIELD_IPV4].mask_range.u32 =
 221                         8 + __builtin_popcount(app.n_ports - 1);
 222                 rule_params.field_value[SRCP_FIELD_IPV4].value.u16 = 0;
 223                 rule_params.field_value[SRCP_FIELD_IPV4].mask_range.u16 =
 224                         UINT16_MAX;
 225                 rule_params.field_value[DSTP_FIELD_IPV4].value.u16 = 0;
 226                 rule_params.field_value[DSTP_FIELD_IPV4].mask_range.u16 =
 227                         UINT16_MAX;
 228                 rule_params.field_value[PROTO_FIELD_IPV4].value.u8 = 0;
 229                 rule_params.field_value[PROTO_FIELD_IPV4].mask_range.u8 = 0;
 230
 231                 rule_params.priority = 0;
 232
 233                 uint32_t dst_addr = rule_params.field_value[DST_FIELD_IPV4].
 234                         value.u32;
 235                 uint32_t dst_mask =
 236                         rule_params.field_value[DST_FIELD_IPV4].mask_range.u32;
 237
 238                 printf("Adding rule to ACL table (IPv4 destination = "
 239                         "%u.%u.%u.%u/%u => port out = %u)\n",
 240                         (dst_addr & 0xFF000000) >> 24,
 241                         (dst_addr & 0x00FF0000) >> 16,
 242                         (dst_addr & 0x0000FF00) >> 8,
 243                         dst_addr & 0x000000FF,
 244                         dst_mask,
 245                         table_entry.port_id);
 246
 247                 /* For ACL, add needs an rte_table_acl_rule_add_params struct */
 248                 ret = rte_pipeline_table_entry_add(p, table_id, &rule_params,
 249                         &table_entry, &key_found, &entry_ptr);
 250                 if (ret < 0)
 251                         rte_panic("Unable to add entry to table %u (%d)\n",
 252                                 table_id, ret);
 253         }
 254
 255         /* Enable input ports */
 256         for (i = 0; i < app.n_ports; i++)
 257                 if (rte_pipeline_port_in_enable(p, port_in_id[i]))
 258                         rte_panic("Unable to enable input port %u\n",
 259                                 port_in_id[i]);
 260
 261         /* Check pipeline consistency */
 262         if (rte_pipeline_check(p) < 0)
 263                 rte_panic("Pipeline consistency check failed\n");
 264
 265         /* Run-time */
 266 #if APP_FLUSH == 0
 267         for ( ; ; )
 268                 rte_pipeline_run(p);
 269 #else
 270         for (i = 0; ; i++) {
 271                 rte_pipeline_run(p);
 272
 273                 if ((i & APP_FLUSH) == 0)
 274                         rte_pipeline_flush(p);
 275         }
 276 #endif
 277 }