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[ceph.git] / ceph / src / dpdk / drivers / net / bnx2x / bnx2x.h
1 /*-
2 * Copyright (c) 2007-2013 Broadcom Corporation.
3 *
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
7 *
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015 QLogic Corporation.
10 * All rights reserved.
11 * www.qlogic.com
12 *
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
14 */
15
16 #ifndef __BNX2X_H__
17 #define __BNX2X_H__
18
19 #include <rte_byteorder.h>
20 #include <rte_spinlock.h>
21
22 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
23 #ifndef __LITTLE_ENDIAN
24 #define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN
25 #endif
26 #undef __BIG_ENDIAN
27 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
28 #ifndef __BIG_ENDIAN
29 #define __BIG_ENDIAN RTE_BIG_ENDIAN
30 #endif
31 #undef __LITTLE_ENDIAN
32 #endif
33
34 #include "bnx2x_ethdev.h"
35 #include "ecore_mfw_req.h"
36 #include "ecore_fw_defs.h"
37 #include "ecore_hsi.h"
38 #include "ecore_reg.h"
39 #include "bnx2x_stats.h"
40 #include "bnx2x_vfpf.h"
41
42 #include "elink.h"
43
44 #ifndef __FreeBSD__
45 #include <linux/pci_regs.h>
46
47 #define PCIY_PMG PCI_CAP_ID_PM
48 #define PCIY_MSI PCI_CAP_ID_MSI
49 #define PCIY_EXPRESS PCI_CAP_ID_EXP
50 #define PCIY_MSIX PCI_CAP_ID_MSIX
51 #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC
52 #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND
53 #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA
54 #define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW
55 #define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS
56 #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL
57 #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD
58 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ
59 #define PCIR_POWER_STATUS PCI_PM_CTRL
60 #define PCIM_PSTAT_DMASK PCI_PM_CTRL_STATE_MASK
61 #define PCIM_PSTAT_PME PCI_PM_CTRL_PME_STATUS
62 #define PCIM_PSTAT_D3 0x3
63 #define PCIM_PSTAT_PMEENABLE PCI_PM_CTRL_PME_ENABLE
64 #define PCIR_MSIX_CTRL PCI_MSIX_FLAGS
65 #define PCIM_MSIXCTRL_TABLE_SIZE PCI_MSIX_FLAGS_QSIZE
66 #else
67 #include <dev/pci/pcireg.h>
68 #endif
69
70 #define IFM_10G_CX4 20 /* 10GBase CX4 copper */
71 #define IFM_10G_TWINAX 22 /* 10GBase Twinax copper */
72 #define IFM_10G_T 26 /* 10GBase-T - RJ45 */
73
74 #ifndef __FreeBSD__
75 #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC
76 #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND
77 #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA
78 #define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW
79 #define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS
80 #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL
81 #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD
82 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ
83 #else
84 #define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA
85 #define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND
86 #define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA
87 #define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH
88 #define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED
89 #define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL
90 #define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
91 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST
92 #endif
93
94 #ifndef ARRAY_SIZE
95 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
96 #endif
97 #ifndef ARRSIZE
98 #define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
99 #endif
100 #ifndef DIV_ROUND_UP
101 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
102 #endif
103 #ifndef roundup
104 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
105 #endif
106 #ifndef ilog2
107 static inline
108 int bnx2x_ilog2(int x)
109 {
110 int log = 0;
111 x >>= 1;
112
113 while(x) {
114 log++;
115 x >>= 1;
116 }
117 return log;
118 }
119 #define ilog2(x) bnx2x_ilog2(x)
120 #endif
121
122 #include "ecore_sp.h"
123
124 struct bnx2x_device_type {
125 uint16_t bnx2x_vid;
126 uint16_t bnx2x_did;
127 uint16_t bnx2x_svid;
128 uint16_t bnx2x_sdid;
129 char *bnx2x_name;
130 };
131
132 #define BNX2X_PAGE_SHIFT 12
133 #define BNX2X_PAGE_SIZE (1 << BNX2X_PAGE_SHIFT)
134 #define BNX2X_PAGE_MASK (~(BNX2X_PAGE_SIZE - 1))
135 #define BNX2X_PAGE_ALIGN(addr) ((addr + BNX2X_PAGE_SIZE - 1) & BNX2X_PAGE_MASK)
136
137 #if BNX2X_PAGE_SIZE != 4096
138 #error Page sizes other than 4KB are unsupported!
139 #endif
140
141 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF))
142 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32))
143 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo))
144
145 /* dropless fc FW/HW related params */
146 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512)
147 #define MAX_AGG_QS(sc) ETH_MAX_AGGREGATION_QUEUES_E1H_E2
148 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc))
149 #define FW_PREFETCH_CNT 16U
150 #define DROPLESS_FC_HEADROOM 100
151
152 /*
153 * Transmit Buffer Descriptor (tx_bd) definitions*
154 */
155 /* NUM_TX_PAGES must be a power of 2. */
156 #define TOTAL_TX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_tx_bd_types)) /* 256 */
157 #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) /* 255 */
158
159 #define TOTAL_TX_BD(q) (TOTAL_TX_BD_PER_PAGE * q->nb_tx_pages) /* 512 */
160 #define USABLE_TX_BD(q) (USABLE_TX_BD_PER_PAGE * q->nb_tx_pages) /* 510 */
161 #define MAX_TX_BD(q) (TOTAL_TX_BD(q) - 1) /* 511 */
162
163 #define NEXT_TX_BD(x) \
164 ((((x) & USABLE_TX_BD_PER_PAGE) == \
165 (USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
166
167 #define TX_BD(x, q) ((x) & MAX_TX_BD(q))
168 #define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8)
169 #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
170
171 #define BDS_PER_TX_PKT (3)
172
173 /*
174 * Trigger pending transmits when the number of available BDs is greater
175 * than 1/8 of the total number of usable BDs.
176 */
177 #define BNX2X_TX_CLEANUP_THRESHOLD(q) (USABLE_TX_BD(q) / 8)
178 #define BNX2X_TX_TIMEOUT 5
179
180 /*
181 * Receive Buffer Descriptor (rx_bd) definitions*
182 */
183 //#define NUM_RX_PAGES 1
184 #define TOTAL_RX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(struct eth_rx_bd)) /* 512 */
185 #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 2) /* 510 */
186 #define RX_BD_PER_PAGE_MASK (TOTAL_RX_BD_PER_PAGE - 1) /* 511 */
187 #define TOTAL_RX_BD(q) (TOTAL_RX_BD_PER_PAGE * q->nb_rx_pages) /* 512 */
188 #define USABLE_RX_BD(q) (USABLE_RX_BD_PER_PAGE * q->nb_rx_pages) /* 510 */
189 #define MAX_RX_BD(q) (TOTAL_RX_BD(q) - 1) /* 511 */
190 #define RX_BD_NEXT_PAGE_DESC_CNT 2
191
192 #define NEXT_RX_BD(x) \
193 ((((x) & RX_BD_PER_PAGE_MASK) == \
194 (USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 3 : (x) + 1)
195
196 /* x & 0x3ff */
197 #define RX_BD(x, q) ((x) & MAX_RX_BD(q))
198 #define RX_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9)
199 #define RX_IDX(x) ((x) & RX_BD_PER_PAGE_MASK)
200
201 /*
202 * Receive Completion Queue definitions*
203 */
204 //#define NUM_RCQ_PAGES (NUM_RX_PAGES * 4)
205 #define TOTAL_RCQ_ENTRIES_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_rx_cqe)) /* 128 */
206 #define USABLE_RCQ_ENTRIES_PER_PAGE (TOTAL_RCQ_ENTRIES_PER_PAGE - 1) /* 127 */
207 #define TOTAL_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 512 */
208 #define USABLE_RCQ_ENTRIES(q) (USABLE_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 508 */
209 #define MAX_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES(q) - 1) /* 511 */
210 #define RCQ_NEXT_PAGE_DESC_CNT 1
211
212 #define NEXT_RCQ_IDX(x) \
213 ((((x) & USABLE_RCQ_ENTRIES_PER_PAGE) == \
214 (USABLE_RCQ_ENTRIES_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
215
216 #define CQE_BD_REL \
217 (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
218
219 #define RCQ_BD_PAGES(q) \
220 (q->nb_rx_pages * CQE_BD_REL)
221
222 #define RCQ_ENTRY(x, q) ((x) & MAX_RCQ_ENTRIES(q))
223 #define RCQ_PAGE(x) (((x) & ~USABLE_RCQ_ENTRIES_PER_PAGE) >> 7)
224 #define RCQ_IDX(x) ((x) & USABLE_RCQ_ENTRIES_PER_PAGE)
225
226 /*
227 * dropless fc calculations for BDs
228 * Number of BDs should be as number of buffers in BRB:
229 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT
230 * "next" elements on each page
231 */
232 #define NUM_BD_REQ(sc) \
233 BRB_SIZE(sc)
234 #define NUM_BD_PG_REQ(sc) \
235 ((NUM_BD_REQ(sc) + USABLE_RX_BD_PER_PAGE - 1) / USABLE_RX_BD_PER_PAGE)
236 #define BD_TH_LO(sc) \
237 (NUM_BD_REQ(sc) + \
238 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \
239 FW_DROP_LEVEL(sc))
240 #define BD_TH_HI(sc) \
241 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM)
242 #define MIN_RX_AVAIL(sc) \
243 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128)
244
245 /*
246 * dropless fc calculations for RCQs
247 * Number of RCQs should be as number of buffers in BRB:
248 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT
249 * "next" elements on each page
250 */
251 #define NUM_RCQ_REQ(sc) \
252 BRB_SIZE(sc)
253 #define NUM_RCQ_PG_REQ(sc) \
254 ((NUM_RCQ_REQ(sc) + USABLE_RCQ_ENTRIES_PER_PAGE - 1) / USABLE_RCQ_ENTRIES_PER_PAGE)
255 #define RCQ_TH_LO(sc) \
256 (NUM_RCQ_REQ(sc) + \
257 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \
258 FW_DROP_LEVEL(sc))
259 #define RCQ_TH_HI(sc) \
260 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM)
261
262 /* Load / Unload modes */
263 #define LOAD_NORMAL 0
264 #define LOAD_OPEN 1
265 #define LOAD_DIAG 2
266 #define LOAD_LOOPBACK_EXT 3
267 #define UNLOAD_NORMAL 0
268 #define UNLOAD_CLOSE 1
269 #define UNLOAD_RECOVERY 2
270
271 /* Some constants... */
272 //#define MAX_PATH_NUM 2
273 //#define E2_MAX_NUM_OF_VFS 64
274 //#define E1H_FUNC_MAX 8
275 //#define E2_FUNC_MAX 4 /* per path */
276 #define MAX_VNIC_NUM 4
277 #define MAX_FUNC_NUM 8 /* common to all chips */
278 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */
279 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */
280 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */
281
282 #define ILT_NUM_PAGE_ENTRIES 3072
283 /*
284 * 57711 we use whole table since we have 8 functions.
285 * 57712 we have only 4 functions, but use same size per func, so only half
286 * of the table is used.
287 */
288 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8)
289 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
290 /*
291 * the phys address is shifted right 12 bits and has an added
292 * 1=valid bit added to the 53rd bit
293 * then since this is a wide register(TM)
294 * we split it into two 32 bit writes
295 */
296 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
297 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
298
299 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
300 #define ETH_HLEN 14
301 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
302 #define ETH_MIN_PACKET_SIZE 60
303 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */
304 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
305 /* TCP with Timestamp Option (32) + IPv6 (40) */
306
307 /* max supported alignment is 256 (8 shift) */
308 #define BNX2X_RX_ALIGN_SHIFT RTE_MAX(6, min(8, RTE_CACHE_LINE_SIZE_LOG2))
309
310 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
311
312 struct bnx2x_bar {
313 void *base_addr;
314 };
315
316 /* Used to manage DMA allocations. */
317 struct bnx2x_dma {
318 struct bnx2x_softc *sc;
319 phys_addr_t paddr;
320 void *vaddr;
321 int nseg;
322 char msg[RTE_MEMZONE_NAMESIZE - 6];
323 };
324
325 /* attn group wiring */
326 #define MAX_DYNAMIC_ATTN_GRPS 8
327
328 struct attn_route {
329 uint32_t sig[5];
330 };
331
332 struct iro {
333 uint32_t base;
334 uint16_t m1;
335 uint16_t m2;
336 uint16_t m3;
337 uint16_t size;
338 };
339
340 union bnx2x_host_hc_status_block {
341 /* pointer to fp status block e2 */
342 struct host_hc_status_block_e2 *e2_sb;
343 /* pointer to fp status block e1x */
344 struct host_hc_status_block_e1x *e1x_sb;
345 };
346
347 union bnx2x_db_prod {
348 struct doorbell_set_prod data;
349 uint32_t raw;
350 };
351
352 struct bnx2x_sw_tx_bd {
353 struct mbuf *m;
354 uint16_t first_bd;
355 uint8_t flags;
356 /* set on the first BD descriptor when there is a split BD */
357 #define BNX2X_TSO_SPLIT_BD (1 << 0)
358 };
359
360 /*
361 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN
362 * instances of the fastpath structure when using multiple queues.
363 */
364 struct bnx2x_fastpath {
365 /* pointer back to parent structure */
366 struct bnx2x_softc *sc;
367
368 /* status block */
369 struct bnx2x_dma sb_dma;
370 union bnx2x_host_hc_status_block status_block;
371
372 phys_addr_t tx_desc_mapping;
373
374 phys_addr_t rx_desc_mapping;
375 phys_addr_t rx_comp_mapping;
376
377 uint16_t *sb_index_values;
378 uint16_t *sb_running_index;
379 uint32_t ustorm_rx_prods_offset;
380
381 uint8_t igu_sb_id; /* status block number in HW */
382 uint8_t fw_sb_id; /* status block number in FW */
383
384 uint32_t rx_buf_size;
385
386 int state;
387 #define BNX2X_FP_STATE_CLOSED 0x01
388 #define BNX2X_FP_STATE_IRQ 0x02
389 #define BNX2X_FP_STATE_OPENING 0x04
390 #define BNX2X_FP_STATE_OPEN 0x08
391 #define BNX2X_FP_STATE_HALTING 0x10
392 #define BNX2X_FP_STATE_HALTED 0x20
393
394 /* reference back to this fastpath queue number */
395 uint8_t index; /* this is also the 'cid' */
396 #define FP_IDX(fp) (fp->index)
397
398 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */
399 uint8_t cl_id;
400 #define FP_CL_ID(fp) (fp->cl_id)
401 uint8_t cl_qzone_id;
402
403 uint16_t fp_hc_idx;
404
405 union bnx2x_db_prod tx_db;
406
407 struct tstorm_per_queue_stats old_tclient;
408 struct ustorm_per_queue_stats old_uclient;
409 struct xstorm_per_queue_stats old_xclient;
410 struct bnx2x_eth_q_stats eth_q_stats;
411 struct bnx2x_eth_q_stats_old eth_q_stats_old;
412
413 /* Pointer to the receive consumer in the status block */
414 uint16_t *rx_cq_cons_sb;
415
416 /* Pointer to the transmit consumer in the status block */
417 uint16_t *tx_cons_sb;
418
419 /* transmit timeout until chip reset */
420 int watchdog_timer;
421
422 }; /* struct bnx2x_fastpath */
423
424 #define BNX2X_MAX_NUM_OF_VFS 64
425 #define BNX2X_VF_ID_INVALID 0xFF
426
427 /* maximum number of fast-path interrupt contexts */
428 #define FP_SB_MAX_E1x 16
429 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
430
431 union cdu_context {
432 struct eth_context eth;
433 char pad[1024];
434 };
435
436 /* CDU host DB constants */
437 #define CDU_ILT_PAGE_SZ_HW 2
438 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
439 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
440
441 #define CNIC_ISCSI_CID_MAX 256
442 #define CNIC_FCOE_CID_MAX 2048
443 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
444 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
445
446 #define QM_ILT_PAGE_SZ_HW 0
447 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
448 #define QM_CID_ROUND 1024
449
450 /* TM (timers) host DB constants */
451 #define TM_ILT_PAGE_SZ_HW 0
452 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
453 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
454 #define TM_CONN_NUM 1024
455 #define TM_ILT_SZ (8 * TM_CONN_NUM)
456 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
457
458 /* SRC (Searcher) host DB constants */
459 #define SRC_ILT_PAGE_SZ_HW 0
460 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
461 #define SRC_HASH_BITS 10
462 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
463 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
464 #define SRC_T2_SZ SRC_ILT_SZ
465 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
466
467 struct hw_context {
468 struct bnx2x_dma vcxt_dma;
469 union cdu_context *vcxt;
470 //phys_addr_t cxt_mapping;
471 size_t size;
472 };
473
474 #define SM_RX_ID 0
475 #define SM_TX_ID 1
476
477 /* defines for multiple tx priority indices */
478 #define FIRST_TX_ONLY_COS_INDEX 1
479 #define FIRST_TX_COS_INDEX 0
480
481 #define CID_TO_FP(cid, sc) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(sc))
482
483 #define HC_INDEX_ETH_RX_CQ_CONS 1
484 #define HC_INDEX_OOO_TX_CQ_CONS 4
485 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
486 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
487 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
488 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
489
490 /* congestion management fairness mode */
491 #define CMNG_FNS_NONE 0
492 #define CMNG_FNS_MINMAX 1
493
494 /* CMNG constants, as derived from system spec calculations */
495 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
496 #define DEF_MIN_RATE 100
497 /* resolution of the rate shaping timer - 400 usec */
498 #define RS_PERIODIC_TIMEOUT_USEC 400
499 /* number of bytes in single QM arbitration cycle -
500 * coefficient for calculating the fairness timer */
501 #define QM_ARB_BYTES 160000
502 /* resolution of Min algorithm 1:100 */
503 #define MIN_RES 100
504 /* how many bytes above threshold for the minimal credit of Min algorithm*/
505 #define MIN_ABOVE_THRESH 32768
506 /* fairness algorithm integration time coefficient -
507 * for calculating the actual Tfair */
508 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
509 /* memory of fairness algorithm - 2 cycles */
510 #define FAIR_MEM 2
511
512 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */
513 #define HC_SEG_ACCESS_ATTN 4
514 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */
515
516 /*
517 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
518 * control by the number of fast-path status blocks supported by the
519 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
520 * status block represents an independent interrupts context that can
521 * serve a regular L2 networking queue. However special L2 queues such
522 * as the FCoE queue do not require a FP-SB and other components like
523 * the CNIC may consume FP-SB reducing the number of possible L2 queues
524 *
525 * If the maximum number of FP-SB available is X then:
526 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
527 * regular L2 queues is Y=X-1
528 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
529 * c. If the FCoE L2 queue is supported the actual number of L2 queues
530 * is Y+1
531 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
532 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
533 * FP interrupt context for the CNIC).
534 * e. The number of HW context (CID count) is always X or X+1 if FCoE
535 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
536 *
537 * So this is quite simple for now as no ULPs are supported yet. :-)
538 */
539 #define BNX2X_NUM_QUEUES(sc) ((sc)->num_queues)
540 #define BNX2X_NUM_ETH_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
541 #define BNX2X_NUM_NON_CNIC_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
542 #define BNX2X_NUM_RX_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
543
544 #define FOR_EACH_QUEUE(sc, var) \
545 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(sc); (var)++)
546
547 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \
548 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(sc); (var)++)
549
550 #define FOR_EACH_ETH_QUEUE(sc, var) \
551 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++)
552
553 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \
554 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++)
555
556 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \
557 for ((var) = 0; (var) < (sc)->max_cos; (var)++)
558
559 #define FOR_EACH_CNIC_QUEUE(sc, var) \
560 for ((var) = BNX2X_NUM_ETH_QUEUES(sc); \
561 (var) < BNX2X_NUM_QUEUES(sc); \
562 (var)++)
563
564 enum {
565 OOO_IDX_OFFSET,
566 FCOE_IDX_OFFSET,
567 FWD_IDX_OFFSET,
568 };
569
570 #define FCOE_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET)
571 #define bnx2x_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)])
572 #define bnx2x_fcoe(sc, var) (bnx2x_fcoe_fp(sc)->var)
573 #define bnx2x_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)])
574 #define bnx2x_fcoe_sp_obj(sc, var) (bnx2x_fcoe_inner_sp_obj(sc)->var)
575 #define bnx2x_fcoe_tx(sc, var) (bnx2x_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var)
576
577 #define OOO_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET)
578 #define bnx2x_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)])
579 #define bnx2x_ooo(sc, var) (bnx2x_ooo_fp(sc)->var)
580 #define bnx2x_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)])
581 #define bnx2x_ooo_sp_obj(sc, var) (bnx2x_ooo_inner_sp_obj(sc)->var)
582
583 #define FWD_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET)
584 #define bnx2x_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)])
585 #define bnx2x_fwd(sc, var) (bnx2x_fwd_fp(sc)->var)
586 #define bnx2x_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)])
587 #define bnx2x_fwd_sp_obj(sc, var) (bnx2x_fwd_inner_sp_obj(sc)->var)
588 #define bnx2x_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX])
589
590 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->sc))
591 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc))
592 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc))
593 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc))
594 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc))
595 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc))
596 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc))
597
598 enum {
599 BNX2X_PORT_QUERY_IDX,
600 BNX2X_PF_QUERY_IDX,
601 BNX2X_FCOE_QUERY_IDX,
602 BNX2X_FIRST_QUEUE_QUERY_IDX,
603 };
604
605 struct bnx2x_fw_stats_req {
606 struct stats_query_header hdr;
607 struct stats_query_entry query[FP_SB_MAX_E1x +
608 BNX2X_FIRST_QUEUE_QUERY_IDX];
609 };
610
611 struct bnx2x_fw_stats_data {
612 struct stats_counter storm_counters;
613 struct per_port_stats port;
614 struct per_pf_stats pf;
615 struct per_queue_stats queue_stats[1];
616 };
617
618 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
619 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
620 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
621
622 #define MAX_DMAE_C 8
623
624 /*
625 * This is the slowpath data structure. It is mapped into non-paged memory
626 * so that the hardware can access it's contents directly and must be page
627 * aligned.
628 */
629 struct bnx2x_slowpath {
630
631 /* used by the DMAE command executer */
632 struct dmae_command dmae[MAX_DMAE_C];
633
634 /* statistics completion */
635 uint32_t stats_comp;
636
637 /* firmware defined statistics blocks */
638 union mac_stats mac_stats;
639 struct nig_stats nig_stats;
640 struct host_port_stats port_stats;
641 struct host_func_stats func_stats;
642
643 /* DMAE completion value and data source/sink */
644 uint32_t wb_comp;
645 uint32_t wb_data[4];
646
647 union {
648 struct mac_configuration_cmd e1x;
649 struct eth_classify_rules_ramrod_data e2;
650 } mac_rdata;
651
652 union {
653 struct tstorm_eth_mac_filter_config e1x;
654 struct eth_filter_rules_ramrod_data e2;
655 } rx_mode_rdata;
656
657 struct eth_rss_update_ramrod_data rss_rdata;
658
659 union {
660 struct mac_configuration_cmd e1;
661 struct eth_multicast_rules_ramrod_data e2;
662 } mcast_rdata;
663
664 union {
665 struct function_start_data func_start;
666 struct flow_control_configuration pfc_config; /* for DCBX ramrod */
667 } func_rdata;
668
669 /* Queue State related ramrods */
670 union {
671 struct client_init_ramrod_data init_data;
672 struct client_update_ramrod_data update_data;
673 } q_rdata;
674
675 /*
676 * AFEX ramrod can not be a part of func_rdata union because these
677 * events might arrive in parallel to other events from func_rdata.
678 * If they were defined in the same union the data can get corrupted.
679 */
680 struct afex_vif_list_ramrod_data func_afex_rdata;
681
682 union drv_info_to_mcp drv_info_to_mcp;
683 }; /* struct bnx2x_slowpath */
684
685 /*
686 * Port specifc data structure.
687 */
688 struct bnx2x_port {
689 /*
690 * Port Management Function (for 57711E only).
691 * When this field is set the driver instance is
692 * responsible for managing port specifc
693 * configurations such as handling link attentions.
694 */
695 uint32_t pmf;
696
697 /* Ethernet maximum transmission unit. */
698 uint16_t ether_mtu;
699
700 uint32_t link_config[ELINK_LINK_CONFIG_SIZE];
701
702 uint32_t ext_phy_config;
703
704 /* Port feature config.*/
705 uint32_t config;
706
707 /* Defines the features supported by the PHY. */
708 uint32_t supported[ELINK_LINK_CONFIG_SIZE];
709
710 /* Defines the features advertised by the PHY. */
711 uint32_t advertising[ELINK_LINK_CONFIG_SIZE];
712 #define ADVERTISED_10baseT_Half (1 << 1)
713 #define ADVERTISED_10baseT_Full (1 << 2)
714 #define ADVERTISED_100baseT_Half (1 << 3)
715 #define ADVERTISED_100baseT_Full (1 << 4)
716 #define ADVERTISED_1000baseT_Half (1 << 5)
717 #define ADVERTISED_1000baseT_Full (1 << 6)
718 #define ADVERTISED_TP (1 << 7)
719 #define ADVERTISED_FIBRE (1 << 8)
720 #define ADVERTISED_Autoneg (1 << 9)
721 #define ADVERTISED_Asym_Pause (1 << 10)
722 #define ADVERTISED_Pause (1 << 11)
723 #define ADVERTISED_2500baseX_Full (1 << 15)
724 #define ADVERTISED_10000baseT_Full (1 << 16)
725
726 uint32_t phy_addr;
727
728 /*
729 * MCP scratchpad address for port specific statistics.
730 * The device is responsible for writing statistcss
731 * back to the MCP for use with management firmware such
732 * as UMP/NC-SI.
733 */
734 uint32_t port_stx;
735
736 struct nig_stats old_nig_stats;
737 }; /* struct bnx2x_port */
738
739 struct bnx2x_mf_info {
740 uint32_t mf_config[E1HVN_MAX];
741
742 uint32_t vnics_per_port; /* 1, 2 or 4 */
743 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */
744 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */
745
746 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode)
747 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port)
748 #define VNICS_PER_PATH(sc) \
749 ((sc)->devinfo.mf_info.vnics_per_port * \
750 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 ))
751
752 uint8_t min_bw[MAX_VNIC_NUM];
753 uint8_t max_bw[MAX_VNIC_NUM];
754
755 uint16_t ext_id; /* vnic outer vlan or VIF ID */
756 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096)
757 #define INVALID_VIF_ID 0xFFFF
758 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id)
759 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id)
760
761 uint16_t default_vlan;
762 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan)
763
764 uint8_t niv_allowed_priorities;
765 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities)
766
767 uint8_t niv_default_cos;
768 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos)
769
770 uint8_t niv_mba_enabled;
771
772 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
773 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode)
774 int afex_def_vlan_tag;
775 uint32_t pending_max;
776
777 uint16_t flags;
778 #define MF_INFO_VALID_MAC 0x0001
779
780 uint16_t mf_ov;
781 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */
782 #define IS_MF(sc) \
783 (IS_MULTI_VNIC(sc) && \
784 ((sc)->devinfo.mf_info.mf_mode != 0))
785 #define IS_MF_SD(sc) \
786 (IS_MULTI_VNIC(sc) && \
787 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD))
788 #define IS_MF_SI(sc) \
789 (IS_MULTI_VNIC(sc) && \
790 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI))
791 #define IS_MF_AFEX(sc) \
792 (IS_MULTI_VNIC(sc) && \
793 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX))
794 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc)
795 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc)
796 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc)
797
798 uint32_t mf_protos_supported;
799 #define MF_PROTO_SUPPORT_ETHERNET 0x1
800 #define MF_PROTO_SUPPORT_ISCSI 0x2
801 #define MF_PROTO_SUPPORT_FCOE 0x4
802 }; /* struct bnx2x_mf_info */
803
804 /* Device information data structure. */
805 struct bnx2x_devinfo {
806 /* PCIe info */
807 uint16_t vendor_id;
808 uint16_t device_id;
809 uint16_t subvendor_id;
810 uint16_t subdevice_id;
811
812 /*
813 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB'
814 * C = Chip Number (bits 16-31)
815 * R = Chip Revision (bits 12-15)
816 * M = Chip Metal (bits 4-11)
817 * B = Chip Bond ID (bits 0-3)
818 */
819 uint32_t chip_id;
820 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
821 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
822 /* device ids */
823 #define CHIP_NUM_57711 0x164f
824 #define CHIP_NUM_57711E 0x1650
825 #define CHIP_NUM_57712 0x1662
826 #define CHIP_NUM_57712_MF 0x1663
827 #define CHIP_NUM_57712_VF 0x166f
828 #define CHIP_NUM_57800 0x168a
829 #define CHIP_NUM_57800_MF 0x16a5
830 #define CHIP_NUM_57800_VF 0x16a9
831 #define CHIP_NUM_57810 0x168e
832 #define CHIP_NUM_57810_MF 0x16ae
833 #define CHIP_NUM_57810_VF 0x16af
834 #define CHIP_NUM_57811 0x163d
835 #define CHIP_NUM_57811_MF 0x163e
836 #define CHIP_NUM_57811_VF 0x163f
837 #define CHIP_NUM_57840_OBS 0x168d
838 #define CHIP_NUM_57840_OBS_MF 0x16ab
839 #define CHIP_NUM_57840_4_10 0x16a1
840 #define CHIP_NUM_57840_2_20 0x16a2
841 #define CHIP_NUM_57840_MF 0x16a4
842 #define CHIP_NUM_57840_VF 0x16ad
843
844 #define CHIP_REV_SHIFT 12
845 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
846 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK)
847
848 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
849 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
850 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT)
851
852 #define CHIP_REV_IS_SLOW(sc) \
853 (CHIP_REV(sc) > 0x00005000)
854 #define CHIP_REV_IS_FPGA(sc) \
855 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000))
856 #define CHIP_REV_IS_EMUL(sc) \
857 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000))
858 #define CHIP_REV_IS_ASIC(sc) \
859 (!CHIP_REV_IS_SLOW(sc))
860
861 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
862 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
863
864 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
865 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
866 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
867 (CHIP_IS_57711E(sc)))
868 #define CHIP_IS_E1x(sc) CHIP_IS_E1H(sc)
869
870 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712)
871 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF)
872 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF)
873 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \
874 CHIP_IS_57712_MF(sc))
875
876 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800)
877 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF)
878 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF)
879 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810)
880 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF)
881 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF)
882 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811)
883 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF)
884 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF)
885 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \
886 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \
887 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20))
888 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \
889 (CHIP_NUM(sc) == CHIP_NUM_57840_MF))
890 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF)
891
892 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \
893 CHIP_IS_57800_MF(sc) || \
894 CHIP_IS_57800_VF(sc) || \
895 CHIP_IS_57810(sc) || \
896 CHIP_IS_57810_MF(sc) || \
897 CHIP_IS_57810_VF(sc) || \
898 CHIP_IS_57811(sc) || \
899 CHIP_IS_57811_MF(sc) || \
900 CHIP_IS_57811_VF(sc) || \
901 CHIP_IS_57840(sc) || \
902 CHIP_IS_57840_MF(sc) || \
903 CHIP_IS_57840_VF(sc))
904 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \
905 (CHIP_REV(sc) == CHIP_REV_Ax))
906 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \
907 (CHIP_REV(sc) == CHIP_REV_Bx))
908
909 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc))
910 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \
911 CHIP_IS_E3(sc))
912
913 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \
914 CHIP_IS_57712_MF(sc) || \
915 CHIP_IS_E3(sc))
916
917 #define IS_VF(sc) ((sc)->flags & BNX2X_IS_VF_FLAG)
918 #define IS_PF(sc) (!IS_VF(sc))
919
920 /*
921 * This define is used in two main places:
922 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher
923 * to nic-only mode or to offload mode. Offload mode is configured if either
924 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic
925 * already registered for this port (which means that the user wants storage
926 * services).
927 * 2. During cnic-related load, to know if offload mode is already configured
928 * in the HW or needs to be configrued. Since the transition from nic-mode to
929 * offload-mode in HW causes traffic coruption, nic-mode is configured only
930 * in ports on which storage services where never requested.
931 */
932 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc))
933
934 uint8_t chip_port_mode;
935 #define CHIP_4_PORT_MODE 0x0
936 #define CHIP_2_PORT_MODE 0x1
937 #define CHIP_PORT_MODE_NONE 0x2
938 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode)
939 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE)
940
941 uint8_t int_block;
942 #define INT_BLOCK_HC 0
943 #define INT_BLOCK_IGU 1
944 #define INT_BLOCK_MODE_NORMAL 0
945 #define INT_BLOCK_MODE_BW_COMP 2
946 #define CHIP_INT_MODE_IS_NBC(sc) \
947 (!CHIP_IS_E1x(sc) && \
948 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP))
949 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc))
950
951 uint32_t shmem_base;
952 uint32_t shmem2_base;
953 uint32_t bc_ver;
954 char bc_ver_str[32];
955 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */
956 struct bnx2x_mf_info mf_info;
957
958 uint32_t flash_size;
959 #define NVRAM_1MB_SIZE 0x20000
960 #define NVRAM_TIMEOUT_COUNT 30000
961 #define NVRAM_PAGE_SIZE 256
962
963 /* PCIe capability information */
964 uint32_t pcie_cap_flags;
965 #define BNX2X_PM_CAPABLE_FLAG 0x00000001
966 #define BNX2X_PCIE_CAPABLE_FLAG 0x00000002
967 #define BNX2X_MSI_CAPABLE_FLAG 0x00000004
968 #define BNX2X_MSIX_CAPABLE_FLAG 0x00000008
969 uint16_t pcie_pm_cap_reg;
970 uint16_t pcie_link_width;
971 uint16_t pcie_link_speed;
972 uint16_t pcie_msi_cap_reg;
973 uint16_t pcie_msix_cap_reg;
974
975 /* device configuration read from bootcode shared memory */
976 uint32_t hw_config;
977 uint32_t hw_config2;
978 }; /* struct bnx2x_devinfo */
979
980 struct bnx2x_sp_objs {
981 struct ecore_vlan_mac_obj mac_obj; /* MACs object */
982 struct ecore_queue_sp_obj q_obj; /* Queue State object */
983 }; /* struct bnx2x_sp_objs */
984
985 /*
986 * Data that will be used to create a link report message. We will keep the
987 * data used for the last link report in order to prevent reporting the same
988 * link parameters twice.
989 */
990 struct bnx2x_link_report_data {
991 uint16_t line_speed; /* Effective line speed */
992 unsigned long link_report_flags; /* BNX2X_LINK_REPORT_XXX flags */
993 };
994
995 enum {
996 BNX2X_LINK_REPORT_FULL_DUPLEX,
997 BNX2X_LINK_REPORT_LINK_DOWN,
998 BNX2X_LINK_REPORT_RX_FC_ON,
999 BNX2X_LINK_REPORT_TX_FC_ON
1000 };
1001
1002 #define BNX2X_RX_CHAIN_PAGE_SZ BNX2X_PAGE_SIZE
1003
1004 struct bnx2x_pci_cap {
1005 struct bnx2x_pci_cap *next;
1006 uint16_t id;
1007 uint16_t type;
1008 uint16_t addr;
1009 };
1010
1011 struct bnx2x_vfdb;
1012
1013 /* Top level device private data structure. */
1014 struct bnx2x_softc {
1015
1016 void **rx_queues;
1017 void **tx_queues;
1018 uint32_t max_tx_queues;
1019 uint32_t max_rx_queues;
1020 const struct rte_pci_device *pci_dev;
1021 uint32_t pci_val;
1022 struct bnx2x_pci_cap *pci_caps;
1023 #define BNX2X_INTRS_POLL_PERIOD 1
1024
1025 void *firmware;
1026 uint64_t fw_len;
1027
1028 /* MAC address operations */
1029 struct bnx2x_mac_ops mac_ops;
1030
1031 /* structures for VF mbox/response/bulletin */
1032 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1033 struct bnx2x_dma vf2pf_mbox_mapping;
1034 struct vf_acquire_resp_tlv acquire_resp;
1035 struct bnx2x_vf_bulletin *pf2vf_bulletin;
1036 struct bnx2x_dma pf2vf_bulletin_mapping;
1037 struct bnx2x_vf_bulletin old_bulletin;
1038 rte_spinlock_t vf2pf_lock;
1039
1040 int media;
1041
1042 int state; /* device state */
1043 #define BNX2X_STATE_CLOSED 0x0000
1044 #define BNX2X_STATE_OPENING_WAITING_LOAD 0x1000
1045 #define BNX2X_STATE_OPENING_WAITING_PORT 0x2000
1046 #define BNX2X_STATE_OPEN 0x3000
1047 #define BNX2X_STATE_CLOSING_WAITING_HALT 0x4000
1048 #define BNX2X_STATE_CLOSING_WAITING_DELETE 0x5000
1049 #define BNX2X_STATE_CLOSING_WAITING_UNLOAD 0x6000
1050 #define BNX2X_STATE_DISABLED 0xD000
1051 #define BNX2X_STATE_DIAG 0xE000
1052 #define BNX2X_STATE_ERROR 0xF000
1053
1054 int flags;
1055 #define BNX2X_ONE_PORT_FLAG 0x1
1056 #define BNX2X_NO_FCOE_FLAG 0x2
1057 #define BNX2X_NO_WOL_FLAG 0x4
1058 #define BNX2X_NO_MCP_FLAG 0x8
1059 #define BNX2X_NO_ISCSI_OOO_FLAG 0x10
1060 #define BNX2X_NO_ISCSI_FLAG 0x20
1061 #define BNX2X_MF_FUNC_DIS 0x40
1062 #define BNX2X_TX_SWITCHING 0x80
1063 #define BNX2X_IS_VF_FLAG 0x100
1064
1065 #define BNX2X_ONE_PORT(sc) (sc->flags & BNX2X_ONE_PORT_FLAG)
1066 #define BNX2X_NOFCOE(sc) (sc->flags & BNX2X_NO_FCOE_FLAG)
1067 #define BNX2X_NOMCP(sc) (sc->flags & BNX2X_NO_MCP_FLAG)
1068
1069 #define MAX_BARS 5
1070 struct bnx2x_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */
1071
1072 uint16_t doorbell_size;
1073
1074 /* periodic timer callout */
1075 #define PERIODIC_STOP 0
1076 #define PERIODIC_GO 1
1077 volatile unsigned long periodic_flags;
1078
1079 struct bnx2x_fastpath fp[MAX_RSS_CHAINS];
1080 struct bnx2x_sp_objs sp_objs[MAX_RSS_CHAINS];
1081
1082 uint8_t unit; /* driver instance number */
1083
1084 int pcie_bus; /* PCIe bus number */
1085 int pcie_device; /* PCIe device/slot number */
1086 int pcie_func; /* PCIe function number */
1087
1088 uint8_t pfunc_rel; /* function relative */
1089 uint8_t pfunc_abs; /* function absolute */
1090 uint8_t path_id; /* function absolute */
1091 #define SC_PATH(sc) (sc->path_id)
1092 #define SC_PORT(sc) (sc->pfunc_rel & 1)
1093 #define SC_FUNC(sc) (sc->pfunc_rel)
1094 #define SC_ABS_FUNC(sc) (sc->pfunc_abs)
1095 #define SC_VN(sc) (sc->pfunc_rel >> 1)
1096 #define SC_L_ID(sc) (SC_VN(sc) << 2)
1097 #define PORT_ID(sc) SC_PORT(sc)
1098 #define PATH_ID(sc) SC_PATH(sc)
1099 #define VNIC_ID(sc) SC_VN(sc)
1100 #define FUNC_ID(sc) SC_FUNC(sc)
1101 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc)
1102 #define SC_FW_MB_IDX_VN(sc, vn) \
1103 (SC_PORT(sc) + (vn) * \
1104 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1))
1105 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc))
1106
1107 int if_capen; /* enabled interface capabilities */
1108
1109 struct bnx2x_devinfo devinfo;
1110 char fw_ver_str[32];
1111 char mf_mode_str[32];
1112 char pci_link_str[32];
1113
1114 struct iro *iro_array;
1115
1116 int dmae_ready;
1117 #define DMAE_READY(sc) (sc->dmae_ready)
1118
1119 struct ecore_credit_pool_obj vlans_pool;
1120 struct ecore_credit_pool_obj macs_pool;
1121 struct ecore_rx_mode_obj rx_mode_obj;
1122 struct ecore_mcast_obj mcast_obj;
1123 struct ecore_rss_config_obj rss_conf_obj;
1124 struct ecore_func_sp_obj func_obj;
1125
1126 uint16_t fw_seq;
1127 uint16_t fw_drv_pulse_wr_seq;
1128 uint32_t func_stx;
1129
1130 struct elink_params link_params;
1131 struct elink_vars link_vars;
1132 uint32_t link_cnt;
1133 struct bnx2x_link_report_data last_reported_link;
1134 char mac_addr_str[32];
1135
1136 uint32_t tx_ring_size;
1137 uint32_t rx_ring_size;
1138 int wol;
1139
1140 int is_leader;
1141 int recovery_state;
1142 #define BNX2X_RECOVERY_DONE 1
1143 #define BNX2X_RECOVERY_INIT 2
1144 #define BNX2X_RECOVERY_WAIT 3
1145 #define BNX2X_RECOVERY_FAILED 4
1146 #define BNX2X_RECOVERY_NIC_LOADING 5
1147
1148 uint32_t rx_mode;
1149 #define BNX2X_RX_MODE_NONE 0
1150 #define BNX2X_RX_MODE_NORMAL 1
1151 #define BNX2X_RX_MODE_ALLMULTI 2
1152 #define BNX2X_RX_MODE_PROMISC 3
1153 #define BNX2X_MAX_MULTICAST 64
1154
1155 struct bnx2x_port port;
1156
1157 struct cmng_init cmng;
1158
1159 /* user configs */
1160 uint8_t num_queues;
1161 int hc_rx_ticks;
1162 int hc_tx_ticks;
1163 uint32_t rx_budget;
1164 int interrupt_mode;
1165 #define INTR_MODE_INTX 0
1166 #define INTR_MODE_MSI 1
1167 #define INTR_MODE_MSIX 2
1168 #define INTR_MODE_SINGLE_MSIX 3
1169 int udp_rss;
1170
1171 uint8_t igu_dsb_id;
1172 uint8_t igu_base_sb;
1173 uint8_t igu_sb_cnt;
1174 uint32_t igu_base_addr;
1175 uint8_t base_fw_ndsb;
1176 #define DEF_SB_IGU_ID 16
1177 #define DEF_SB_ID HC_SP_SB_ID
1178
1179 /* default status block */
1180 struct bnx2x_dma def_sb_dma;
1181 struct host_sp_status_block *def_sb;
1182 uint16_t def_idx;
1183 uint16_t def_att_idx;
1184 uint32_t attn_state;
1185 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1186
1187 /* general SP events - stats query, cfc delete, etc */
1188 #define HC_SP_INDEX_ETH_DEF_CONS 3
1189 /* EQ completions */
1190 #define HC_SP_INDEX_EQ_CONS 7
1191 /* FCoE L2 connection completions */
1192 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
1193 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
1194 /* iSCSI L2 */
1195 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
1196 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
1197
1198 /* event queue */
1199 struct bnx2x_dma eq_dma;
1200 union event_ring_elem *eq;
1201 uint16_t eq_prod;
1202 uint16_t eq_cons;
1203 uint16_t *eq_cons_sb;
1204 #define NUM_EQ_PAGES 1 /* must be a power of 2 */
1205 #define EQ_DESC_CNT_PAGE (BNX2X_PAGE_SIZE / sizeof(union event_ring_elem))
1206 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1207 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1208 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1209 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1210 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1211 #define NEXT_EQ_IDX(x) \
1212 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \
1213 ((x) + 2) : ((x) + 1))
1214 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1215 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1216
1217 /* slow path */
1218 struct bnx2x_dma sp_dma;
1219 struct bnx2x_slowpath *sp;
1220 unsigned long sp_state;
1221
1222 /* slow path queue */
1223 struct bnx2x_dma spq_dma;
1224 struct eth_spe *spq;
1225 #define SP_DESC_CNT (BNX2X_PAGE_SIZE / sizeof(struct eth_spe))
1226 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1227 #define MAX_SPQ_PENDING 8
1228
1229 uint16_t spq_prod_idx;
1230 struct eth_spe *spq_prod_bd;
1231 struct eth_spe *spq_last_bd;
1232 uint16_t *dsb_sp_prod;
1233
1234 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */
1235 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */
1236
1237 /* fw decompression buffer */
1238 struct bnx2x_dma gz_buf_dma;
1239 void *gz_buf;
1240 uint32_t gz_outlen;
1241 #define GUNZIP_BUF(sc) (sc->gz_buf)
1242 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
1243 #define GUNZIP_PHYS(sc) (phys_addr_t)(sc->gz_buf_dma.paddr)
1244 #define FW_BUF_SIZE 0x40000
1245
1246 struct raw_op *init_ops;
1247 uint16_t *init_ops_offsets; /* init block offsets inside init_ops */
1248 uint32_t *init_data; /* data blob, 32 bit granularity */
1249 uint32_t init_mode_flags;
1250 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags)
1251 /* PRAM blobs - raw data */
1252 const uint8_t *tsem_int_table_data;
1253 const uint8_t *tsem_pram_data;
1254 const uint8_t *usem_int_table_data;
1255 const uint8_t *usem_pram_data;
1256 const uint8_t *xsem_int_table_data;
1257 const uint8_t *xsem_pram_data;
1258 const uint8_t *csem_int_table_data;
1259 const uint8_t *csem_pram_data;
1260 #define INIT_OPS(sc) (sc->init_ops)
1261 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets)
1262 #define INIT_DATA(sc) (sc->init_data)
1263 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data)
1264 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data)
1265 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data)
1266 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data)
1267 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data)
1268 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data)
1269 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data)
1270 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data)
1271
1272 #define PHY_FW_VER_LEN 20
1273 char fw_ver[32];
1274
1275 /* ILT
1276 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1277 * context size we need 8 ILT entries.
1278 */
1279 #define ILT_MAX_L2_LINES 8
1280 struct hw_context context[ILT_MAX_L2_LINES];
1281 struct ecore_ilt *ilt;
1282 #define ILT_MAX_LINES 256
1283
1284 /* max supported number of RSS queues: IGU SBs minus one for CNIC */
1285 #define BNX2X_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc))
1286 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */
1287 #define BNX2X_L2_MAX_CID(sc) \
1288 (BNX2X_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1289 #define BNX2X_L2_CID_COUNT(sc) \
1290 (BNX2X_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1291 #define L2_ILT_LINES(sc) \
1292 (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(sc), ILT_PAGE_CIDS))
1293
1294 int qm_cid_count;
1295
1296 uint8_t dropless_fc;
1297
1298 /* total number of FW statistics requests */
1299 uint8_t fw_stats_num;
1300 /*
1301 * This is a memory buffer that will contain both statistics ramrod
1302 * request and data.
1303 */
1304 struct bnx2x_dma fw_stats_dma;
1305 /*
1306 * FW statistics request shortcut (points at the beginning of fw_stats
1307 * buffer).
1308 */
1309 int fw_stats_req_size;
1310 struct bnx2x_fw_stats_req *fw_stats_req;
1311 phys_addr_t fw_stats_req_mapping;
1312 /*
1313 * FW statistics data shortcut (points at the beginning of fw_stats
1314 * buffer + fw_stats_req_size).
1315 */
1316 int fw_stats_data_size;
1317 struct bnx2x_fw_stats_data *fw_stats_data;
1318 phys_addr_t fw_stats_data_mapping;
1319
1320 /* tracking a pending STAT_QUERY ramrod */
1321 uint16_t stats_pending;
1322 /* number of completed statistics ramrods */
1323 uint16_t stats_comp;
1324 uint16_t stats_counter;
1325 uint8_t stats_init;
1326 int stats_state;
1327
1328 struct bnx2x_eth_stats eth_stats;
1329 struct host_func_stats func_stats;
1330 struct bnx2x_eth_stats_old eth_stats_old;
1331 struct bnx2x_net_stats_old net_stats_old;
1332 struct bnx2x_fw_port_stats_old fw_stats_old;
1333
1334 struct dmae_command stats_dmae; /* used by dmae command loader */
1335 int executer_idx;
1336
1337 int mtu;
1338
1339 /* DCB support on/off */
1340 int dcb_state;
1341 #define BNX2X_DCB_STATE_OFF 0
1342 #define BNX2X_DCB_STATE_ON 1
1343 /* DCBX engine mode */
1344 int dcbx_enabled;
1345 #define BNX2X_DCBX_ENABLED_OFF 0
1346 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1347 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1348 #define BNX2X_DCBX_ENABLED_INVALID -1
1349
1350 uint8_t cnic_support;
1351 uint8_t cnic_enabled;
1352 uint8_t cnic_loaded;
1353 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */
1354 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */
1355 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */
1356
1357 /* multiple tx classes of service */
1358 uint8_t max_cos;
1359 #define BNX2X_MAX_PRIORITY 8
1360 /* priority to cos mapping */
1361 uint8_t prio_to_cos[BNX2X_MAX_PRIORITY];
1362
1363 int panic;
1364 }; /* struct bnx2x_softc */
1365
1366 /* IOCTL sub-commands for edebug and firmware upgrade */
1367 #define BNX2X_IOC_RD_NVRAM 1
1368 #define BNX2X_IOC_WR_NVRAM 2
1369 #define BNX2X_IOC_STATS_SHOW_NUM 3
1370 #define BNX2X_IOC_STATS_SHOW_STR 4
1371 #define BNX2X_IOC_STATS_SHOW_CNT 5
1372
1373 struct bnx2x_nvram_data {
1374 uint32_t op; /* ioctl sub-command */
1375 uint32_t offset;
1376 uint32_t len;
1377 uint32_t value[1]; /* variable */
1378 };
1379
1380 union bnx2x_stats_show_data {
1381 uint32_t op; /* ioctl sub-command */
1382
1383 struct {
1384 uint32_t num; /* return number of stats */
1385 uint32_t len; /* length of each string item */
1386 } desc;
1387
1388 /* variable length... */
1389 char str[1]; /* holds names of desc.num stats, each desc.len in length */
1390
1391 /* variable length... */
1392 uint64_t stats[1]; /* holds all stats */
1393 };
1394
1395 /* function init flags */
1396 #define FUNC_FLG_RSS 0x0001
1397 #define FUNC_FLG_STATS 0x0002
1398 /* FUNC_FLG_UNMATCHED 0x0004 */
1399 #define FUNC_FLG_SPQ 0x0010
1400 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1401
1402 struct bnx2x_func_init_params {
1403 phys_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
1404 phys_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
1405 uint16_t func_flgs;
1406 uint16_t func_id; /* abs function id */
1407 uint16_t pf_id;
1408 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */
1409 };
1410
1411 /* memory resources reside at BARs 0, 2, 4 */
1412 /* Run `pciconf -lb` to see mappings */
1413 #define BAR0 0
1414 #define BAR1 2
1415 #define BAR2 4
1416
1417 static inline void
1418 bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)
1419 {
1420 PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x",
1421 (unsigned long)offset, val);
1422 *((volatile uint8_t*)
1423 ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
1424 }
1425
1426 static inline void
1427 bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val)
1428 {
1429 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1430 if ((offset % 2) != 0)
1431 PMD_DRV_LOG(NOTICE, "Unaligned 16-bit write to 0x%08lx",
1432 (unsigned long)offset);
1433 #endif
1434 PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%04x",
1435 (unsigned long)offset, val);
1436 *((volatile uint16_t*)
1437 ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
1438 }
1439
1440 static inline void
1441 bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val)
1442 {
1443 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1444 if ((offset % 4) != 0)
1445 PMD_DRV_LOG(NOTICE, "Unaligned 32-bit write to 0x%08lx",
1446 (unsigned long)offset);
1447 #endif
1448
1449 PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
1450 (unsigned long)offset, val);
1451 *((volatile uint32_t*)
1452 ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
1453 }
1454
1455 static inline uint8_t
1456 bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset)
1457 {
1458 uint8_t val;
1459
1460 val = (uint8_t)(*((volatile uint8_t*)
1461 ((uintptr_t)sc->bar[BAR0].base_addr + offset)));
1462 PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x",
1463 (unsigned long)offset, val);
1464
1465 return val;
1466 }
1467
1468 static inline uint16_t
1469 bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset)
1470 {
1471 uint16_t val;
1472
1473 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1474 if ((offset % 2) != 0)
1475 PMD_DRV_LOG(NOTICE, "Unaligned 16-bit read from 0x%08lx",
1476 (unsigned long)offset);
1477 #endif
1478
1479 val = (uint16_t)(*((volatile uint16_t*)
1480 ((uintptr_t)sc->bar[BAR0].base_addr + offset)));
1481 PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
1482 (unsigned long)offset, val);
1483
1484 return val;
1485 }
1486
1487 static inline uint32_t
1488 bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)
1489 {
1490 uint32_t val;
1491
1492 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1493 if ((offset % 4) != 0)
1494 PMD_DRV_LOG(NOTICE, "Unaligned 32-bit read from 0x%08lx",
1495 (unsigned long)offset);
1496 #endif
1497
1498 val = (uint32_t)(*((volatile uint32_t*)
1499 ((uintptr_t)sc->bar[BAR0].base_addr + offset)));
1500 PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
1501 (unsigned long)offset, val);
1502
1503 return val;
1504 }
1505
1506 #define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset))
1507
1508 #define REG_RD8(sc, offset) bnx2x_reg_read8(sc, (offset))
1509 #define REG_RD16(sc, offset) bnx2x_reg_read16(sc, (offset))
1510 #define REG_RD32(sc, offset) bnx2x_reg_read32(sc, (offset))
1511
1512 #define REG_WR8(sc, offset, val) bnx2x_reg_write8(sc, (offset), val)
1513 #define REG_WR16(sc, offset, val) bnx2x_reg_write16(sc, (offset), val)
1514 #define REG_WR32(sc, offset, val) bnx2x_reg_write32(sc, (offset), val)
1515
1516 #define REG_RD(sc, offset) REG_RD32(sc, offset)
1517 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val)
1518
1519 #define BNX2X_SP(sc, var) (&(sc)->sp->var)
1520 #define BNX2X_SP_MAPPING(sc, var) \
1521 (sc->sp_dma.paddr + offsetof(struct bnx2x_slowpath, var))
1522
1523 #define BNX2X_FP(sc, nr, var) ((sc)->fp[(nr)].var)
1524 #define BNX2X_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])
1525
1526 #define bnx2x_fp(sc, nr, var) ((sc)->fp[nr].var)
1527
1528 #define REG_RD_DMAE(sc, offset, valp, len32) \
1529 do { \
1530 (void)bnx2x_read_dmae(sc, offset, len32); \
1531 (void)rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \
1532 } while (0)
1533
1534 #define REG_WR_DMAE(sc, offset, valp, len32) \
1535 do { \
1536 (void)rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \
1537 (void)bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data), offset, len32); \
1538 } while (0)
1539
1540 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \
1541 REG_WR_DMAE(sc, offset, valp, len32)
1542
1543 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \
1544 REG_RD_DMAE(sc, offset, valp, len32)
1545
1546 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \
1547 do { \
1548 /* if (le32_swap) { */ \
1549 /* PMD_PWARN_LOG(sc, "VIRT_WR_DMAE_LEN with le32_swap=1"); */ \
1550 /* } */ \
1551 rte_memcpy(GUNZIP_BUF(sc), data, len32 * 4); \
1552 ecore_write_big_buf_wb(sc, addr, len32); \
1553 } while (0)
1554
1555 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
1556 #define BNX2X_DB_SHIFT 7 /* 128 bytes */
1557 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
1558 #error "Minimum DB doorbell stride is 8"
1559 #endif
1560 #define DPM_TRIGGER_TYPE 0x40
1561
1562 /* Doorbell macro */
1563 #define BNX2X_DB_WRITE(db_bar, val) \
1564 *((volatile uint32_t *)(db_bar)) = (val)
1565
1566 #define BNX2X_DB_READ(db_bar) \
1567 *((volatile uint32_t *)(db_bar))
1568
1569 #define DOORBELL_ADDR(sc, offset) \
1570 (volatile uint32_t *)(((char *)(sc)->bar[BAR1].base_addr + (offset)))
1571
1572 #define DOORBELL(sc, cid, val) \
1573 if (IS_PF(sc)) \
1574 BNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid) + DPM_TRIGGER_TYPE)), (val)); \
1575 else \
1576 BNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid))), (val)) \
1577
1578 #define SHMEM_ADDR(sc, field) \
1579 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field))
1580 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))
1581 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field))
1582 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)
1583
1584 #define SHMEM2_ADDR(sc, field) \
1585 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field))
1586 #define SHMEM2_HAS(sc, field) \
1587 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \
1588 offsetof(struct shmem2_region, field)))
1589 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
1590 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
1591
1592 #define MFCFG_ADDR(sc, field) \
1593 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field))
1594 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))
1595 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field))
1596 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)
1597
1598 /* DMAE command defines */
1599
1600 #define DMAE_TIMEOUT -1
1601 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1602 #define DMAE_NOT_RDY -3
1603 #define DMAE_PCI_ERR_FLAG 0x80000000
1604
1605 #define DMAE_SRC_PCI 0
1606 #define DMAE_SRC_GRC 1
1607
1608 #define DMAE_DST_NONE 0
1609 #define DMAE_DST_PCI 1
1610 #define DMAE_DST_GRC 2
1611
1612 #define DMAE_COMP_PCI 0
1613 #define DMAE_COMP_GRC 1
1614
1615 #define DMAE_COMP_REGULAR 0
1616 #define DMAE_COM_SET_ERR 1
1617
1618 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_COMMAND_SRC_SHIFT)
1619 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_COMMAND_SRC_SHIFT)
1620 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_COMMAND_DST_SHIFT)
1621 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_COMMAND_DST_SHIFT)
1622
1623 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_COMMAND_C_DST_SHIFT)
1624 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_COMMAND_C_DST_SHIFT)
1625
1626 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1627 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1628 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1629 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1630
1631 #define DMAE_CMD_PORT_0 0
1632 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1633
1634 #define DMAE_SRC_PF 0
1635 #define DMAE_SRC_VF 1
1636
1637 #define DMAE_DST_PF 0
1638 #define DMAE_DST_VF 1
1639
1640 #define DMAE_C_SRC 0
1641 #define DMAE_C_DST 1
1642
1643 #define DMAE_LEN32_RD_MAX 0x80
1644 #define DMAE_LEN32_WR_MAX(sc) 0x2000
1645
1646 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */
1647
1648 #define MAX_DMAE_C_PER_PORT 8
1649 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc))
1650 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX)
1651
1652 static const uint32_t dmae_reg_go_c[] = {
1653 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
1654 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
1655 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
1656 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
1657 };
1658
1659 #define ATTN_NIG_FOR_FUNC (1L << 8)
1660 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1661 #define GPIO_2_FUNC (1L << 10)
1662 #define GPIO_3_FUNC (1L << 11)
1663 #define GPIO_4_FUNC (1L << 12)
1664 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1665 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1666 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1667 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1668 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1669 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1670 #define ATTN_HARD_WIRED_MASK 0xff00
1671 #define ATTENTION_ID 4
1672
1673 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
1674 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
1675
1676 #define MAX_IGU_ATTN_ACK_TO 100
1677
1678 #define STORM_ASSERT_ARRAY_SIZE 50
1679
1680 #define BNX2X_PMF_LINK_ASSERT(sc) \
1681 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc))
1682
1683 #define BNX2X_MC_ASSERT_BITS \
1684 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1685 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1686 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1687 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1688
1689 #define BNX2X_MCP_ASSERT \
1690 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1691
1692 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1693 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1694 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1695 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1696 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1697 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1698 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1699
1700 #define MULTI_MASK 0x7f
1701
1702 #define PFS_PER_PORT(sc) \
1703 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4)
1704 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc)
1705
1706 #define FIRST_ABS_FUNC_IN_PORT(sc) \
1707 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \
1708 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc))))
1709
1710 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \
1711 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \
1712 (i) < MAX_FUNC_NUM; \
1713 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc)))
1714
1715 #define BNX2X_SWCID_SHIFT 17
1716 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
1717
1718 #define SW_CID(x) (le32toh(x) & BNX2X_SWCID_MASK)
1719 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
1720
1721 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
1722 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
1723 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
1724 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
1725 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
1726
1727 /* must be used on a CID before placing it on a HW ring */
1728 #define HW_CID(sc, x) \
1729 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BNX2X_SWCID_SHIFT) | (x))
1730
1731 #define SPEED_10 10
1732 #define SPEED_100 100
1733 #define SPEED_1000 1000
1734 #define SPEED_2500 2500
1735 #define SPEED_10000 10000
1736
1737 #define PCI_PM_D0 1
1738 #define PCI_PM_D3hot 2
1739
1740 int bnx2x_test_bit(int nr, volatile unsigned long * addr);
1741 void bnx2x_set_bit(unsigned int nr, volatile unsigned long * addr);
1742 void bnx2x_clear_bit(int nr, volatile unsigned long * addr);
1743 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long * addr);
1744 int bnx2x_cmpxchg(volatile int *addr, int old, int new);
1745
1746 int bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size,
1747 struct bnx2x_dma *dma, const char *msg, uint32_t align);
1748
1749 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);
1750 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode);
1751 uint32_t bnx2x_dmae_opcode(struct bnx2x_softc *sc, uint8_t src_type,
1752 uint8_t dst_type, uint8_t with_comp,
1753 uint8_t comp_type);
1754 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx);
1755 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32);
1756 void bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr,
1757 uint32_t dst_addr, uint32_t len32);
1758 void bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
1759 uint32_t cid);
1760 void bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
1761 uint8_t sb_index, uint8_t disable,
1762 uint16_t usec);
1763
1764 int bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid,
1765 uint32_t data_hi, uint32_t data_lo, int cmd_type);
1766
1767 void ecore_init_e1h_firmware(struct bnx2x_softc *sc);
1768 void ecore_init_e2_firmware(struct bnx2x_softc *sc);
1769
1770 void ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr,
1771 size_t size, uint32_t *data);
1772
1773 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));
1774 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe)
1775
1776 #define BNX2X_MAC_FMT "%pM"
1777 #define BNX2X_MAC_PRN_LIST(mac) (mac)
1778
1779 /***********/
1780 /* INLINES */
1781 /***********/
1782
1783 static inline uint32_t
1784 reg_poll(struct bnx2x_softc *sc, uint32_t reg, uint32_t expected, int ms, int wait)
1785 {
1786 uint32_t val;
1787 do {
1788 val = REG_RD(sc, reg);
1789 if (val == expected) {
1790 break;
1791 }
1792 ms -= wait;
1793 DELAY(wait * 1000);
1794 } while (ms > 0);
1795
1796 return val;
1797 }
1798
1799 static inline void
1800 bnx2x_update_fp_sb_idx(struct bnx2x_fastpath *fp)
1801 {
1802 mb(); /* status block is written to by the chip */
1803 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
1804 }
1805
1806 static inline void
1807 bnx2x_igu_ack_sb_gen(struct bnx2x_softc *sc, uint8_t segment,
1808 uint16_t index, uint8_t op, uint8_t update, uint32_t igu_addr)
1809 {
1810 struct igu_regular cmd_data = {0};
1811
1812 cmd_data.sb_id_and_flags =
1813 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
1814 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
1815 (update << IGU_REGULAR_BUPDATE_SHIFT) |
1816 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
1817
1818 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags);
1819
1820 /* Make sure that ACK is written */
1821 mb();
1822 }
1823
1824 static inline void
1825 bnx2x_hc_ack_sb(struct bnx2x_softc *sc, uint8_t sb_id, uint8_t storm,
1826 uint16_t index, uint8_t op, uint8_t update)
1827 {
1828 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
1829 COMMAND_REG_INT_ACK);
1830 union igu_ack_register igu_ack;
1831
1832 igu_ack.sb.status_block_index = index;
1833 igu_ack.sb.sb_id_and_flags =
1834 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
1835 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
1836 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
1837 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
1838
1839 REG_WR(sc, hc_addr, igu_ack.raw_data);
1840
1841 /* Make sure that ACK is written */
1842 mb();
1843 }
1844
1845 static inline uint32_t
1846 bnx2x_hc_ack_int(struct bnx2x_softc *sc)
1847 {
1848 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
1849 COMMAND_REG_SIMD_MASK);
1850 uint32_t result = REG_RD(sc, hc_addr);
1851
1852 mb();
1853 return result;
1854 }
1855
1856 static inline uint32_t
1857 bnx2x_igu_ack_int(struct bnx2x_softc *sc)
1858 {
1859 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER * 8);
1860 uint32_t result = REG_RD(sc, igu_addr);
1861
1862 /* PMD_PDEBUG_LOG(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x",
1863 result, igu_addr); */
1864
1865 mb();
1866 return result;
1867 }
1868
1869 static inline uint32_t
1870 bnx2x_ack_int(struct bnx2x_softc *sc)
1871 {
1872 mb();
1873 if (sc->devinfo.int_block == INT_BLOCK_HC) {
1874 return bnx2x_hc_ack_int(sc);
1875 } else {
1876 return bnx2x_igu_ack_int(sc);
1877 }
1878 }
1879
1880 static inline int
1881 func_by_vn(struct bnx2x_softc *sc, int vn)
1882 {
1883 return 2 * vn + SC_PORT(sc);
1884 }
1885
1886 /*
1887 * send notification to other functions.
1888 */
1889 static inline void
1890 bnx2x_link_sync_notify(struct bnx2x_softc *sc)
1891 {
1892 int func, vn;
1893
1894 /* Set the attention towards other drivers on the same port */
1895 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
1896 if (vn == SC_VN(sc))
1897 continue;
1898
1899 func = func_by_vn(sc, vn);
1900 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_0 +
1901 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func) * 4, 1);
1902 }
1903 }
1904
1905 /*
1906 * Statistics ID are global per chip/path, while Client IDs for E1x
1907 * are per port.
1908 */
1909 static inline uint8_t
1910 bnx2x_stats_id(struct bnx2x_fastpath *fp)
1911 {
1912 struct bnx2x_softc *sc = fp->sc;
1913
1914 if (!CHIP_IS_E1x(sc)) {
1915 return fp->cl_id;
1916 }
1917
1918 return fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x;
1919 }
1920
1921 int bnx2x_init(struct bnx2x_softc *sc);
1922 void bnx2x_load_firmware(struct bnx2x_softc *sc);
1923 int bnx2x_attach(struct bnx2x_softc *sc);
1924 int bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link);
1925 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc);
1926 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc);
1927 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc);
1928 void bnx2x_dump_tx_chain(struct bnx2x_fastpath * fp, int bd_prod, int count);
1929 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0);
1930 uint8_t bnx2x_txeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp);
1931 void bnx2x_print_adapter_info(struct bnx2x_softc *sc);
1932 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp);
1933 void bnx2x_link_status_update(struct bnx2x_softc *sc);
1934 int bnx2x_complete_sp(struct bnx2x_softc *sc);
1935 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc);
1936 void bnx2x_periodic_callout(struct bnx2x_softc *sc);
1937
1938 int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_count);
1939 void bnx2x_vf_close(struct bnx2x_softc *sc);
1940 int bnx2x_vf_init(struct bnx2x_softc *sc);
1941 void bnx2x_vf_unload(struct bnx2x_softc *sc);
1942 int bnx2x_vf_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1943 int leading);
1944 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc);
1945 int bnx2x_vf_set_rx_mode(struct bnx2x_softc *sc);
1946 int bnx2x_check_bull(struct bnx2x_softc *sc);
1947
1948 //#define BNX2X_PULSE
1949
1950 #define BNX2X_PCI_CAP 1
1951 #define BNX2X_PCI_ECAP 2
1952
1953 static inline struct bnx2x_pci_cap*
1954 pci_find_cap(struct bnx2x_softc *sc, uint8_t id, uint8_t type)
1955 {
1956 struct bnx2x_pci_cap *cap = sc->pci_caps;
1957
1958 while (cap) {
1959 if (cap->id == id && cap->type == type)
1960 return cap;
1961 cap = cap->next;
1962 }
1963
1964 return NULL;
1965 }
1966
1967 static inline void
1968 bnx2x_set_rx_mode(struct bnx2x_softc *sc)
1969 {
1970 if (sc->state == BNX2X_STATE_OPEN) {
1971 if (IS_PF(sc)) {
1972 bnx2x_set_storm_rx_mode(sc);
1973 } else {
1974 sc->rx_mode = BNX2X_RX_MODE_PROMISC;
1975 bnx2x_vf_set_rx_mode(sc);
1976 }
1977 } else {
1978 PMD_DRV_LOG(NOTICE, "Card is not ready to change mode");
1979 }
1980 }
1981
1982 static inline int pci_read(struct bnx2x_softc *sc, size_t addr,
1983 void *val, uint8_t size)
1984 {
1985 if (rte_eal_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
1986 PMD_DRV_LOG(ERR, "Can't read from PCI config space");
1987 return ENXIO;
1988 }
1989
1990 return 0;
1991 }
1992
1993 static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val)
1994 {
1995 uint16_t val16 = val;
1996
1997 if (rte_eal_pci_write_config(sc->pci_dev, &val16,
1998 sizeof(val16), addr) <= 0) {
1999 PMD_DRV_LOG(ERR, "Can't write to PCI config space");
2000 return ENXIO;
2001 }
2002
2003 return 0;
2004 }
2005
2006 static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val)
2007 {
2008 uint32_t val32 = val;
2009 if (rte_eal_pci_write_config(sc->pci_dev, &val32,
2010 sizeof(val32), addr) <= 0) {
2011 PMD_DRV_LOG(ERR, "Can't write to PCI config space");
2012 return ENXIO;
2013 }
2014
2015 return 0;
2016 }
2017
2018 #endif /* __BNX2X_H__ */
Ceph