ceph/src/dpdk/drivers/net/cxgbe/base/t4_hw.h

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2014-2016 Chelsio Communications.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Chelsio Communications nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #ifndef __T4_HW_H
  35 #define __T4_HW_H
  36
  37 enum {
  38         NCHAN           = 4,     /* # of HW channels */
  39         EEPROMSIZE      = 17408, /* Serial EEPROM physical size */
  40         EEPROMVSIZE     = 32768, /* Serial EEPROM virtual address space size */
  41         EEPROMPFSIZE    = 1024,  /* EEPROM writable area size for PFn, n>0 */
  42         NMTUS           = 16,    /* size of MTU table */
  43         NCCTRL_WIN      = 32,    /* # of congestion control windows */
  44         MBOX_LEN        = 64,    /* mailbox size in bytes */
  45         UDBS_SEG_SIZE   = 128,   /* segment size for BAR2 user doorbells */
  46 };
  47
  48 enum {
  49         CIMLA_SIZE     = 2048,  /* # of 32-bit words in CIM LA */
  50 };
  51
  52 enum {
  53         SF_SEC_SIZE = 64 * 1024,      /* serial flash sector size */
  54 };
  55
  56 enum {
  57         SGE_NTIMERS = 6,          /* # of interrupt holdoff timer values */
  58         SGE_NCOUNTERS = 4,        /* # of interrupt packet counter values */
  59 };
  60
  61 /* PCI-e memory window access */
  62 enum pcie_memwin {
  63         MEMWIN_NIC      = 0,
  64 };
  65
  66 enum {
  67         SGE_MAX_WR_LEN = 512,     /* max WR size in bytes */
  68         SGE_EQ_IDXSIZE = 64,      /* egress queue pidx/cidx unit size */
  69         /* max no. of desc allowed in WR */
  70         SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / SGE_EQ_IDXSIZE,
  71 };
  72
  73 struct sge_qstat {                /* data written to SGE queue status entries */
  74         __be32 qid;
  75         __be16 cidx;
  76         __be16 pidx;
  77 };
  78
  79 /*
  80  * Structure for last 128 bits of response descriptors
  81  */
  82 struct rsp_ctrl {
  83         __be32 hdrbuflen_pidx;
  84         __be32 pldbuflen_qid;
  85         union {
  86                 u8 type_gen;
  87                 __be64 last_flit;
  88         } u;
  89 };
  90
  91 #define S_RSPD_NEWBUF    31
  92 #define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
  93 #define F_RSPD_NEWBUF    V_RSPD_NEWBUF(1U)
  94
  95 #define S_RSPD_LEN    0
  96 #define M_RSPD_LEN    0x7fffffff
  97 #define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
  98 #define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
  99
 100 #define S_RSPD_GEN    7
 101 #define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
 102 #define F_RSPD_GEN    V_RSPD_GEN(1U)
 103
 104 #define S_RSPD_TYPE    4
 105 #define M_RSPD_TYPE    0x3
 106 #define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
 107 #define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)
 108
 109 /* Rx queue interrupt deferral field: timer index */
 110 #define S_QINTR_CNT_EN    0
 111 #define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
 112 #define F_QINTR_CNT_EN    V_QINTR_CNT_EN(1U)
 113
 114 #define S_QINTR_TIMER_IDX    1
 115 #define M_QINTR_TIMER_IDX    0x7
 116 #define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
 117 #define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
 118
 119 /*
 120  * Flash layout.
 121  */
 122 #define FLASH_START(start)      ((start) * SF_SEC_SIZE)
 123 #define FLASH_MAX_SIZE(nsecs)   ((nsecs) * SF_SEC_SIZE)
 124
 125 enum {
 126         /*
 127          * Location of firmware image in FLASH.
 128          */
 129         FLASH_FW_START_SEC = 8,
 130         FLASH_FW_NSECS = 16,
 131         FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
 132         FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
 133
 134         /*
 135          * Location of Firmware Configuration File in FLASH.
 136          */
 137         FLASH_CFG_START_SEC = 31,
 138         FLASH_CFG_NSECS = 1,
 139         FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
 140         FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
 141
 142         /*
 143          * We don't support FLASH devices which can't support the full
 144          * standard set of sections which we need for normal operations.
 145          */
 146         FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
 147 };
 148
 149 #undef FLASH_START
 150 #undef FLASH_MAX_SIZE
 151
 152 #endif /* __T4_HW_H */