ceph/src/dpdk/drivers/net/e1000/base/e1000_82575.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _E1000_82575_H_
  35 #define _E1000_82575_H_
  36
  37 #define ID_LED_DEFAULT_82575_SERDES     ((ID_LED_DEF1_DEF2 << 12) | \
  38                                          (ID_LED_DEF1_DEF2 <<  8) | \
  39                                          (ID_LED_DEF1_DEF2 <<  4) | \
  40                                          (ID_LED_OFF1_ON2))
  41 /*
  42  * Receive Address Register Count
  43  * Number of high/low register pairs in the RAR.  The RAR (Receive Address
  44  * Registers) holds the directed and multicast addresses that we monitor.
  45  * These entries are also used for MAC-based filtering.
  46  */
  47 /*
  48  * For 82576, there are an additional set of RARs that begin at an offset
  49  * separate from the first set of RARs.
  50  */
  51 #define E1000_RAR_ENTRIES_82575 16
  52 #define E1000_RAR_ENTRIES_82576 24
  53 #define E1000_RAR_ENTRIES_82580 24
  54 #define E1000_RAR_ENTRIES_I350  32
  55 #define E1000_SW_SYNCH_MB       0x00000100
  56 #define E1000_STAT_DEV_RST_SET  0x00100000
  57 #define E1000_CTRL_DEV_RST      0x20000000
  58
  59 #ifdef E1000_BIT_FIELDS
  60 struct e1000_adv_data_desc {
  61         __le64 buffer_addr;    /* Address of the descriptor's data buffer */
  62         union {
  63                 u32 data;
  64                 struct {
  65                         u32 datalen:16; /* Data buffer length */
  66                         u32 rsvd:4;
  67                         u32 dtyp:4;  /* Descriptor type */
  68                         u32 dcmd:8;  /* Descriptor command */
  69                 } config;
  70         } lower;
  71         union {
  72                 u32 data;
  73                 struct {
  74                         u32 status:4;  /* Descriptor status */
  75                         u32 idx:4;
  76                         u32 popts:6;  /* Packet Options */
  77                         u32 paylen:18; /* Payload length */
  78                 } options;
  79         } upper;
  80 };
  81
  82 #define E1000_TXD_DTYP_ADV_C    0x2  /* Advanced Context Descriptor */
  83 #define E1000_TXD_DTYP_ADV_D    0x3  /* Advanced Data Descriptor */
  84 #define E1000_ADV_TXD_CMD_DEXT  0x20 /* Descriptor extension (0 = legacy) */
  85 #define E1000_ADV_TUCMD_IPV4    0x2  /* IP Packet Type: 1=IPv4 */
  86 #define E1000_ADV_TUCMD_IPV6    0x0  /* IP Packet Type: 0=IPv6 */
  87 #define E1000_ADV_TUCMD_L4T_UDP 0x0  /* L4 Packet TYPE of UDP */
  88 #define E1000_ADV_TUCMD_L4T_TCP 0x4  /* L4 Packet TYPE of TCP */
  89 #define E1000_ADV_TUCMD_MKRREQ  0x10 /* Indicates markers are required */
  90 #define E1000_ADV_DCMD_EOP      0x1  /* End of Packet */
  91 #define E1000_ADV_DCMD_IFCS     0x2  /* Insert FCS (Ethernet CRC) */
  92 #define E1000_ADV_DCMD_RS       0x8  /* Report Status */
  93 #define E1000_ADV_DCMD_VLE      0x40 /* Add VLAN tag */
  94 #define E1000_ADV_DCMD_TSE      0x80 /* TCP Seg enable */
  95 /* Extended Device Control */
  96 #define E1000_CTRL_EXT_NSICR    0x00000001 /* Disable Intr Clear all on read */
  97
  98 struct e1000_adv_context_desc {
  99         union {
 100                 u32 ip_config;
 101                 struct {
 102                         u32 iplen:9;
 103                         u32 maclen:7;
 104                         u32 vlan_tag:16;
 105                 } fields;
 106         } ip_setup;
 107         u32 seq_num;
 108         union {
 109                 u64 l4_config;
 110                 struct {
 111                         u32 mkrloc:9;
 112                         u32 tucmd:11;
 113                         u32 dtyp:4;
 114                         u32 adv:8;
 115                         u32 rsvd:4;
 116                         u32 idx:4;
 117                         u32 l4len:8;
 118                         u32 mss:16;
 119                 } fields;
 120         } l4_setup;
 121 };
 122 #endif
 123
 124 /* SRRCTL bit definitions */
 125 #define E1000_SRRCTL_BSIZEPKT_SHIFT             10 /* Shift _right_ */
 126 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK          0x00000F00
 127 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT         2  /* Shift _left_ */
 128 #define E1000_SRRCTL_DESCTYPE_LEGACY            0x00000000
 129 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF        0x02000000
 130 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT         0x04000000
 131 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS  0x0A000000
 132 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION   0x06000000
 133 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
 134 #define E1000_SRRCTL_DESCTYPE_MASK              0x0E000000
 135 #define E1000_SRRCTL_TIMESTAMP                  0x40000000
 136 #define E1000_SRRCTL_DROP_EN                    0x80000000
 137
 138 #define E1000_SRRCTL_BSIZEPKT_MASK              0x0000007F
 139 #define E1000_SRRCTL_BSIZEHDR_MASK              0x00003F00
 140
 141 #define E1000_TX_HEAD_WB_ENABLE         0x1
 142 #define E1000_TX_SEQNUM_WB_ENABLE       0x2
 143
 144 #define E1000_MRQC_ENABLE_RSS_4Q                0x00000002
 145 #define E1000_MRQC_ENABLE_VMDQ                  0x00000003
 146 #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q           0x00000005
 147 #define E1000_MRQC_RSS_FIELD_IPV4_UDP           0x00400000
 148 #define E1000_MRQC_RSS_FIELD_IPV6_UDP           0x00800000
 149 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX        0x01000000
 150 #define E1000_MRQC_ENABLE_RSS_8Q                0x00000002
 151
 152 #define E1000_VMRCTL_MIRROR_PORT_SHIFT          8
 153 #define E1000_VMRCTL_MIRROR_DSTPORT_MASK        (7 << \
 154                                                  E1000_VMRCTL_MIRROR_PORT_SHIFT)
 155 #define E1000_VMRCTL_POOL_MIRROR_ENABLE         (1 << 0)
 156 #define E1000_VMRCTL_UPLINK_MIRROR_ENABLE       (1 << 1)
 157 #define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE     (1 << 2)
 158
 159 #define E1000_EICR_TX_QUEUE ( \
 160         E1000_EICR_TX_QUEUE0 |    \
 161         E1000_EICR_TX_QUEUE1 |    \
 162         E1000_EICR_TX_QUEUE2 |    \
 163         E1000_EICR_TX_QUEUE3)
 164
 165 #define E1000_EICR_RX_QUEUE ( \
 166         E1000_EICR_RX_QUEUE0 |    \
 167         E1000_EICR_RX_QUEUE1 |    \
 168         E1000_EICR_RX_QUEUE2 |    \
 169         E1000_EICR_RX_QUEUE3)
 170
 171 #define E1000_EIMS_RX_QUEUE     E1000_EICR_RX_QUEUE
 172 #define E1000_EIMS_TX_QUEUE     E1000_EICR_TX_QUEUE
 173
 174 #define EIMS_ENABLE_MASK ( \
 175         E1000_EIMS_RX_QUEUE  | \
 176         E1000_EIMS_TX_QUEUE  | \
 177         E1000_EIMS_TCP_TIMER | \
 178         E1000_EIMS_OTHER)
 179
 180 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
 181 #define E1000_IMIR_PORT_IM_EN   0x00010000  /* TCP port enable */
 182 #define E1000_IMIR_PORT_BP      0x00020000  /* TCP port check bypass */
 183 #define E1000_IMIREXT_SIZE_BP   0x00001000  /* Packet size bypass */
 184 #define E1000_IMIREXT_CTRL_URG  0x00002000  /* Check URG bit in header */
 185 #define E1000_IMIREXT_CTRL_ACK  0x00004000  /* Check ACK bit in header */
 186 #define E1000_IMIREXT_CTRL_PSH  0x00008000  /* Check PSH bit in header */
 187 #define E1000_IMIREXT_CTRL_RST  0x00010000  /* Check RST bit in header */
 188 #define E1000_IMIREXT_CTRL_SYN  0x00020000  /* Check SYN bit in header */
 189 #define E1000_IMIREXT_CTRL_FIN  0x00040000  /* Check FIN bit in header */
 190 #define E1000_IMIREXT_CTRL_BP   0x00080000  /* Bypass check of ctrl bits */
 191
 192 /* Receive Descriptor - Advanced */
 193 union e1000_adv_rx_desc {
 194         struct {
 195                 __le64 pkt_addr; /* Packet buffer address */
 196                 __le64 hdr_addr; /* Header buffer address */
 197         } read;
 198         struct {
 199                 struct {
 200                         union {
 201                                 __le32 data;
 202                                 struct {
 203                                         __le16 pkt_info; /*RSS type, Pkt type*/
 204                                         /* Split Header, header buffer len */
 205                                         __le16 hdr_info;
 206                                 } hs_rss;
 207                         } lo_dword;
 208                         union {
 209                                 __le32 rss; /* RSS Hash */
 210                                 struct {
 211                                         __le16 ip_id; /* IP id */
 212                                         __le16 csum; /* Packet Checksum */
 213                                 } csum_ip;
 214                         } hi_dword;
 215                 } lower;
 216                 struct {
 217                         __le32 status_error; /* ext status/error */
 218                         __le16 length; /* Packet length */
 219                         __le16 vlan; /* VLAN tag */
 220                 } upper;
 221         } wb;  /* writeback */
 222 };
 223
 224 #define E1000_RXDADV_RSSTYPE_MASK       0x0000000F
 225 #define E1000_RXDADV_RSSTYPE_SHIFT      12
 226 #define E1000_RXDADV_HDRBUFLEN_MASK     0x7FE0
 227 #define E1000_RXDADV_HDRBUFLEN_SHIFT    5
 228 #define E1000_RXDADV_SPLITHEADER_EN     0x00001000
 229 #define E1000_RXDADV_SPH                0x8000
 230 #define E1000_RXDADV_STAT_TS            0x10000 /* Pkt was time stamped */
 231 #define E1000_RXDADV_STAT_TSIP          0x08000 /* timestamp in packet */
 232 #define E1000_RXDADV_ERR_HBO            0x00800000
 233
 234 /* RSS Hash results */
 235 #define E1000_RXDADV_RSSTYPE_NONE       0x00000000
 236 #define E1000_RXDADV_RSSTYPE_IPV4_TCP   0x00000001
 237 #define E1000_RXDADV_RSSTYPE_IPV4       0x00000002
 238 #define E1000_RXDADV_RSSTYPE_IPV6_TCP   0x00000003
 239 #define E1000_RXDADV_RSSTYPE_IPV6_EX    0x00000004
 240 #define E1000_RXDADV_RSSTYPE_IPV6       0x00000005
 241 #define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
 242 #define E1000_RXDADV_RSSTYPE_IPV4_UDP   0x00000007
 243 #define E1000_RXDADV_RSSTYPE_IPV6_UDP   0x00000008
 244 #define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
 245
 246 /* RSS Packet Types as indicated in the receive descriptor */
 247 #define E1000_RXDADV_PKTTYPE_ILMASK     0x000000F0
 248 #define E1000_RXDADV_PKTTYPE_TLMASK     0x00000F00
 249 #define E1000_RXDADV_PKTTYPE_NONE       0x00000000
 250 #define E1000_RXDADV_PKTTYPE_IPV4       0x00000010 /* IPV4 hdr present */
 251 #define E1000_RXDADV_PKTTYPE_IPV4_EX    0x00000020 /* IPV4 hdr + extensions */
 252 #define E1000_RXDADV_PKTTYPE_IPV6       0x00000040 /* IPV6 hdr present */
 253 #define E1000_RXDADV_PKTTYPE_IPV6_EX    0x00000080 /* IPV6 hdr + extensions */
 254 #define E1000_RXDADV_PKTTYPE_TCP        0x00000100 /* TCP hdr present */
 255 #define E1000_RXDADV_PKTTYPE_UDP        0x00000200 /* UDP hdr present */
 256 #define E1000_RXDADV_PKTTYPE_SCTP       0x00000400 /* SCTP hdr present */
 257 #define E1000_RXDADV_PKTTYPE_NFS        0x00000800 /* NFS hdr present */
 258
 259 #define E1000_RXDADV_PKTTYPE_IPSEC_ESP  0x00001000 /* IPSec ESP */
 260 #define E1000_RXDADV_PKTTYPE_IPSEC_AH   0x00002000 /* IPSec AH */
 261 #define E1000_RXDADV_PKTTYPE_LINKSEC    0x00004000 /* LinkSec Encap */
 262 #define E1000_RXDADV_PKTTYPE_ETQF       0x00008000 /* PKTTYPE is ETQF index */
 263 #define E1000_RXDADV_PKTTYPE_ETQF_MASK  0x00000070 /* ETQF has 8 indices */
 264 #define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
 265
 266 /* LinkSec results */
 267 /* Security Processing bit Indication */
 268 #define E1000_RXDADV_LNKSEC_STATUS_SECP         0x00020000
 269 #define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
 270 #define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
 271 #define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
 272 #define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
 273
 274 #define E1000_RXDADV_IPSEC_STATUS_SECP                  0x00020000
 275 #define E1000_RXDADV_IPSEC_ERROR_BIT_MASK               0x18000000
 276 #define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL       0x08000000
 277 #define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH         0x10000000
 278 #define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED  0x18000000
 279
 280 /* Transmit Descriptor - Advanced */
 281 union e1000_adv_tx_desc {
 282         struct {
 283                 __le64 buffer_addr;    /* Address of descriptor's data buf */
 284                 __le32 cmd_type_len;
 285                 __le32 olinfo_status;
 286         } read;
 287         struct {
 288                 __le64 rsvd;       /* Reserved */
 289                 __le32 nxtseq_seed;
 290                 __le32 status;
 291         } wb;
 292 };
 293
 294 /* Adv Transmit Descriptor Config Masks */
 295 #define E1000_ADVTXD_DTYP_CTXT  0x00200000 /* Advanced Context Descriptor */
 296 #define E1000_ADVTXD_DTYP_DATA  0x00300000 /* Advanced Data Descriptor */
 297 #define E1000_ADVTXD_DCMD_EOP   0x01000000 /* End of Packet */
 298 #define E1000_ADVTXD_DCMD_IFCS  0x02000000 /* Insert FCS (Ethernet CRC) */
 299 #define E1000_ADVTXD_DCMD_RS    0x08000000 /* Report Status */
 300 #define E1000_ADVTXD_DCMD_DDTYP_ISCSI   0x10000000 /* DDP hdr type or iSCSI */
 301 #define E1000_ADVTXD_DCMD_DEXT  0x20000000 /* Descriptor extension (1=Adv) */
 302 #define E1000_ADVTXD_DCMD_VLE   0x40000000 /* VLAN pkt enable */
 303 #define E1000_ADVTXD_DCMD_TSE   0x80000000 /* TCP Seg enable */
 304 #define E1000_ADVTXD_MAC_LINKSEC        0x00040000 /* Apply LinkSec on pkt */
 305 #define E1000_ADVTXD_MAC_TSTAMP         0x00080000 /* IEEE1588 Timestamp pkt */
 306 #define E1000_ADVTXD_STAT_SN_CRC        0x00000002 /* NXTSEQ/SEED prsnt in WB */
 307 #define E1000_ADVTXD_IDX_SHIFT          4  /* Adv desc Index shift */
 308 #define E1000_ADVTXD_POPTS_ISCO_1ST     0x00000000 /* 1st TSO of iSCSI PDU */
 309 #define E1000_ADVTXD_POPTS_ISCO_MDL     0x00000800 /* Middle TSO of iSCSI PDU */
 310 #define E1000_ADVTXD_POPTS_ISCO_LAST    0x00001000 /* Last TSO of iSCSI PDU */
 311 /* 1st & Last TSO-full iSCSI PDU*/
 312 #define E1000_ADVTXD_POPTS_ISCO_FULL    0x00001800
 313 #define E1000_ADVTXD_POPTS_IPSEC        0x00000400 /* IPSec offload request */
 314 #define E1000_ADVTXD_PAYLEN_SHIFT       14 /* Adv desc PAYLEN shift */
 315
 316 /* Context descriptors */
 317 struct e1000_adv_tx_context_desc {
 318         __le32 vlan_macip_lens;
 319         __le32 seqnum_seed;
 320         __le32 type_tucmd_mlhl;
 321         __le32 mss_l4len_idx;
 322 };
 323
 324 #define E1000_ADVTXD_MACLEN_SHIFT       9  /* Adv ctxt desc mac len shift */
 325 #define E1000_ADVTXD_VLAN_SHIFT         16  /* Adv ctxt vlan tag shift */
 326 #define E1000_ADVTXD_TUCMD_IPV4         0x00000400  /* IP Packet Type: 1=IPv4 */
 327 #define E1000_ADVTXD_TUCMD_IPV6         0x00000000  /* IP Packet Type: 0=IPv6 */
 328 #define E1000_ADVTXD_TUCMD_L4T_UDP      0x00000000  /* L4 Packet TYPE of UDP */
 329 #define E1000_ADVTXD_TUCMD_L4T_TCP      0x00000800  /* L4 Packet TYPE of TCP */
 330 #define E1000_ADVTXD_TUCMD_L4T_SCTP     0x00001000  /* L4 Packet TYPE of SCTP */
 331 #define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP       0x00002000 /* IPSec Type ESP */
 332 /* IPSec Encrypt Enable for ESP */
 333 #define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN     0x00004000
 334 /* Req requires Markers and CRC */
 335 #define E1000_ADVTXD_TUCMD_MKRREQ       0x00002000
 336 #define E1000_ADVTXD_L4LEN_SHIFT        8  /* Adv ctxt L4LEN shift */
 337 #define E1000_ADVTXD_MSS_SHIFT          16  /* Adv ctxt MSS shift */
 338 /* Adv ctxt IPSec SA IDX mask */
 339 #define E1000_ADVTXD_IPSEC_SA_INDEX_MASK        0x000000FF
 340 /* Adv ctxt IPSec ESP len mask */
 341 #define E1000_ADVTXD_IPSEC_ESP_LEN_MASK         0x000000FF
 342
 343 /* Additional Transmit Descriptor Control definitions */
 344 #define E1000_TXDCTL_QUEUE_ENABLE       0x02000000 /* Ena specific Tx Queue */
 345 #define E1000_TXDCTL_SWFLSH             0x04000000 /* Tx Desc. wbk flushing */
 346 /* Tx Queue Arbitration Priority 0=low, 1=high */
 347 #define E1000_TXDCTL_PRIORITY           0x08000000
 348
 349 /* Additional Receive Descriptor Control definitions */
 350 #define E1000_RXDCTL_QUEUE_ENABLE       0x02000000 /* Ena specific Rx Queue */
 351 #define E1000_RXDCTL_SWFLSH             0x04000000 /* Rx Desc. wbk flushing */
 352
 353 /* Direct Cache Access (DCA) definitions */
 354 #define E1000_DCA_CTRL_DCA_ENABLE       0x00000000 /* DCA Enable */
 355 #define E1000_DCA_CTRL_DCA_DISABLE      0x00000001 /* DCA Disable */
 356
 357 #define E1000_DCA_CTRL_DCA_MODE_CB1     0x00 /* DCA Mode CB1 */
 358 #define E1000_DCA_CTRL_DCA_MODE_CB2     0x02 /* DCA Mode CB2 */
 359
 360 #define E1000_DCA_RXCTRL_CPUID_MASK     0x0000001F /* Rx CPUID Mask */
 361 #define E1000_DCA_RXCTRL_DESC_DCA_EN    (1 << 5) /* DCA Rx Desc enable */
 362 #define E1000_DCA_RXCTRL_HEAD_DCA_EN    (1 << 6) /* DCA Rx Desc header ena */
 363 #define E1000_DCA_RXCTRL_DATA_DCA_EN    (1 << 7) /* DCA Rx Desc payload ena */
 364 #define E1000_DCA_RXCTRL_DESC_RRO_EN    (1 << 9) /* DCA Rx Desc Relax Order */
 365
 366 #define E1000_DCA_TXCTRL_CPUID_MASK     0x0000001F /* Tx CPUID Mask */
 367 #define E1000_DCA_TXCTRL_DESC_DCA_EN    (1 << 5) /* DCA Tx Desc enable */
 368 #define E1000_DCA_TXCTRL_DESC_RRO_EN    (1 << 9) /* Tx rd Desc Relax Order */
 369 #define E1000_DCA_TXCTRL_TX_WB_RO_EN    (1 << 11) /* Tx Desc writeback RO bit */
 370 #define E1000_DCA_TXCTRL_DATA_RRO_EN    (1 << 13) /* Tx rd data Relax Order */
 371
 372 #define E1000_DCA_TXCTRL_CPUID_MASK_82576       0xFF000000 /* Tx CPUID Mask */
 373 #define E1000_DCA_RXCTRL_CPUID_MASK_82576       0xFF000000 /* Rx CPUID Mask */
 374 #define E1000_DCA_TXCTRL_CPUID_SHIFT_82576      24 /* Tx CPUID */
 375 #define E1000_DCA_RXCTRL_CPUID_SHIFT_82576      24 /* Rx CPUID */
 376
 377 /* Additional interrupt register bit definitions */
 378 #define E1000_ICR_LSECPNS       0x00000020 /* PN threshold - server */
 379 #define E1000_IMS_LSECPNS       E1000_ICR_LSECPNS /* PN threshold - server */
 380 #define E1000_ICS_LSECPNS       E1000_ICR_LSECPNS /* PN threshold - server */
 381
 382 /* ETQF register bit definitions */
 383 #define E1000_ETQF_FILTER_ENABLE        (1 << 26)
 384 #define E1000_ETQF_IMM_INT              (1 << 29)
 385 #define E1000_ETQF_1588                 (1 << 30)
 386 #define E1000_ETQF_QUEUE_ENABLE         (1 << 31)
 387 /*
 388  * ETQF filter list: one static filter per filter consumer. This is
 389  *                   to avoid filter collisions later. Add new filters
 390  *                   here!!
 391  *
 392  * Current filters:
 393  *    EAPOL 802.1x (0x888e): Filter 0
 394  */
 395 #define E1000_ETQF_FILTER_EAPOL         0
 396
 397 #define E1000_FTQF_VF_BP                0x00008000
 398 #define E1000_FTQF_1588_TIME_STAMP      0x08000000
 399 #define E1000_FTQF_MASK                 0xF0000000
 400 #define E1000_FTQF_MASK_PROTO_BP        0x10000000
 401 #define E1000_FTQF_MASK_SOURCE_ADDR_BP  0x20000000
 402 #define E1000_FTQF_MASK_DEST_ADDR_BP    0x40000000
 403 #define E1000_FTQF_MASK_SOURCE_PORT_BP  0x80000000
 404
 405 #define E1000_NVM_APME_82575            0x0400
 406 #define MAX_NUM_VFS                     7
 407
 408 #define E1000_DTXSWC_MAC_SPOOF_MASK     0x000000FF /* Per VF MAC spoof cntrl */
 409 #define E1000_DTXSWC_VLAN_SPOOF_MASK    0x0000FF00 /* Per VF VLAN spoof cntrl */
 410 #define E1000_DTXSWC_LLE_MASK           0x00FF0000 /* Per VF Local LB enables */
 411 #define E1000_DTXSWC_VLAN_SPOOF_SHIFT   8
 412 #define E1000_DTXSWC_LLE_SHIFT          16
 413 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN   (1 << 31)  /* global VF LB enable */
 414
 415 /* Easy defines for setting default pool, would normally be left a zero */
 416 #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
 417 #define E1000_VT_CTL_DEFAULT_POOL_MASK  (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
 418
 419 /* Other useful VMD_CTL register defines */
 420 #define E1000_VT_CTL_IGNORE_MAC         (1 << 28)
 421 #define E1000_VT_CTL_DISABLE_DEF_POOL   (1 << 29)
 422 #define E1000_VT_CTL_VM_REPL_EN         (1 << 30)
 423
 424 /* Per VM Offload register setup */
 425 #define E1000_VMOLR_RLPML_MASK  0x00003FFF /* Long Packet Maximum Length mask */
 426 #define E1000_VMOLR_LPE         0x00010000 /* Accept Long packet */
 427 #define E1000_VMOLR_RSSE        0x00020000 /* Enable RSS */
 428 #define E1000_VMOLR_AUPE        0x01000000 /* Accept untagged packets */
 429 #define E1000_VMOLR_ROMPE       0x02000000 /* Accept overflow multicast */
 430 #define E1000_VMOLR_ROPE        0x04000000 /* Accept overflow unicast */
 431 #define E1000_VMOLR_BAM         0x08000000 /* Accept Broadcast packets */
 432 #define E1000_VMOLR_MPME        0x10000000 /* Multicast promiscuous mode */
 433 #define E1000_VMOLR_STRVLAN     0x40000000 /* Vlan stripping enable */
 434 #define E1000_VMOLR_STRCRC      0x80000000 /* CRC stripping enable */
 435
 436 #define E1000_VMOLR_VPE         0x00800000 /* VLAN promiscuous enable */
 437 #define E1000_VMOLR_UPE         0x20000000 /* Unicast promisuous enable */
 438 #define E1000_DVMOLR_HIDVLAN    0x20000000 /* Vlan hiding enable */
 439 #define E1000_DVMOLR_STRVLAN    0x40000000 /* Vlan stripping enable */
 440 #define E1000_DVMOLR_STRCRC     0x80000000 /* CRC stripping enable */
 441
 442 #define E1000_PBRWAC_WALPB      0x00000007 /* Wrap around event on LAN Rx PB */
 443 #define E1000_PBRWAC_PBE        0x00000008 /* Rx packet buffer empty */
 444
 445 #define E1000_VLVF_ARRAY_SIZE           32
 446 #define E1000_VLVF_VLANID_MASK          0x00000FFF
 447 #define E1000_VLVF_POOLSEL_SHIFT        12
 448 #define E1000_VLVF_POOLSEL_MASK         (0xFF << E1000_VLVF_POOLSEL_SHIFT)
 449 #define E1000_VLVF_LVLAN                0x00100000
 450 #define E1000_VLVF_VLANID_ENABLE        0x80000000
 451
 452 #define E1000_VMVIR_VLANA_DEFAULT       0x40000000 /* Always use default VLAN */
 453 #define E1000_VMVIR_VLANA_NEVER         0x80000000 /* Never insert VLAN tag */
 454
 455 #define E1000_VF_INIT_TIMEOUT   200 /* Number of retries to clear RSTI */
 456
 457 #define E1000_IOVCTL            0x05BBC
 458 #define E1000_IOVCTL_REUSE_VFQ  0x00000001
 459
 460 #define E1000_RPLOLR_STRVLAN    0x40000000
 461 #define E1000_RPLOLR_STRCRC     0x80000000
 462
 463 #define E1000_TCTL_EXT_COLD     0x000FFC00
 464 #define E1000_TCTL_EXT_COLD_SHIFT       10
 465
 466 #define E1000_DTXCTL_8023LL     0x0004
 467 #define E1000_DTXCTL_VLAN_ADDED 0x0008
 468 #define E1000_DTXCTL_OOS_ENABLE 0x0010
 469 #define E1000_DTXCTL_MDP_EN     0x0020
 470 #define E1000_DTXCTL_SPOOF_INT  0x0040
 471
 472 #define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT    (1 << 14)
 473
 474 #define ALL_QUEUES              0xFFFF
 475
 476 /* Rx packet buffer size defines */
 477 #define E1000_RXPBS_SIZE_MASK_82576     0x0000007F
 478 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
 479 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf);
 480 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
 481 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw);
 482 s32  e1000_init_hw_82575(struct e1000_hw *hw);
 483
 484 enum e1000_promisc_type {
 485         e1000_promisc_disabled = 0,   /* all promisc modes disabled */
 486         e1000_promisc_unicast = 1,    /* unicast promiscuous enabled */
 487         e1000_promisc_multicast = 2,  /* multicast promiscuous enabled */
 488         e1000_promisc_enabled = 3,    /* both uni and multicast promisc */
 489         e1000_num_promisc_types
 490 };
 491
 492 void e1000_vfta_set_vf(struct e1000_hw *, u16, bool);
 493 void e1000_rlpml_set_vf(struct e1000_hw *, u16);
 494 s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type type);
 495 u16 e1000_rxpbs_adjust_82580(u32 data);
 496 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data);
 497 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M);
 498 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M);
 499 s32 e1000_get_eee_status_i354(struct e1000_hw *, bool *);
 500 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw);
 501 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw);
 502
 503 /* I2C SDA and SCL timing parameters for standard mode */
 504 #define E1000_I2C_T_HD_STA      4
 505 #define E1000_I2C_T_LOW         5
 506 #define E1000_I2C_T_HIGH        4
 507 #define E1000_I2C_T_SU_STA      5
 508 #define E1000_I2C_T_HD_DATA     5
 509 #define E1000_I2C_T_SU_DATA     1
 510 #define E1000_I2C_T_RISE        1
 511 #define E1000_I2C_T_FALL        1
 512 #define E1000_I2C_T_SU_STO      4
 513 #define E1000_I2C_T_BUF         5
 514
 515 s32 e1000_set_i2c_bb(struct e1000_hw *hw);
 516 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
 517                                 u8 dev_addr, u8 *data);
 518 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
 519                                  u8 dev_addr, u8 data);
 520 void e1000_i2c_bus_clear(struct e1000_hw *hw);
 521 #endif /* _E1000_82575_H_ */