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[ceph.git] / ceph / src / dpdk / drivers / net / e1000 / em_ethdev.c
1 /*-
2 * BSD LICENSE
3 *
4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/queue.h>
35 #include <stdio.h>
36 #include <errno.h>
37 #include <stdint.h>
38 #include <stdarg.h>
39
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
43 #include <rte_log.h>
44 #include <rte_debug.h>
45 #include <rte_pci.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_eal.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
53 #include <rte_dev.h>
54
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
58
59 #define EM_EIAC 0x000DC
60
61 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
62
63
64 static int eth_em_configure(struct rte_eth_dev *dev);
65 static int eth_em_start(struct rte_eth_dev *dev);
66 static void eth_em_stop(struct rte_eth_dev *dev);
67 static void eth_em_close(struct rte_eth_dev *dev);
68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
72 static int eth_em_link_update(struct rte_eth_dev *dev,
73 int wait_to_complete);
74 static void eth_em_stats_get(struct rte_eth_dev *dev,
75 struct rte_eth_stats *rte_stats);
76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
77 static void eth_em_infos_get(struct rte_eth_dev *dev,
78 struct rte_eth_dev_info *dev_info);
79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
80 struct rte_eth_fc_conf *fc_conf);
81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
82 struct rte_eth_fc_conf *fc_conf);
83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
86 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
87 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
88 void *param);
89
90 static int em_hw_init(struct e1000_hw *hw);
91 static int em_hardware_init(struct e1000_hw *hw);
92 static void em_hw_control_acquire(struct e1000_hw *hw);
93 static void em_hw_control_release(struct e1000_hw *hw);
94 static void em_init_manageability(struct e1000_hw *hw);
95 static void em_release_manageability(struct e1000_hw *hw);
96
97 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
98
99 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
100 uint16_t vlan_id, int on);
101 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
102 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
103 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
105 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
106
107 /*
108 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
109 uint16_t vlan_id, int on);
110 */
111
112 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
113 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
114 static void em_lsc_intr_disable(struct e1000_hw *hw);
115 static void em_rxq_intr_enable(struct e1000_hw *hw);
116 static void em_rxq_intr_disable(struct e1000_hw *hw);
117
118 static int eth_em_led_on(struct rte_eth_dev *dev);
119 static int eth_em_led_off(struct rte_eth_dev *dev);
120
121 static int em_get_rx_buffer_size(struct e1000_hw *hw);
122 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
123 uint32_t index, uint32_t pool);
124 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
125
126 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
127 struct ether_addr *mc_addr_set,
128 uint32_t nb_mc_addr);
129
130 #define EM_FC_PAUSE_TIME 0x0680
131 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
132 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
133
134 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
135
136 /*
137 * The set of PCI devices this driver supports
138 */
139 static const struct rte_pci_id pci_id_em_map[] = {
140 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
141 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
142 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
143 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
144 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
145 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
146 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
147 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
148 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
149 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
150 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
151 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
152 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
153 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
154 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
155 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
156 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
157 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
158 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
159 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
160 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
161 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
162 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
163 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
164 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
165 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
166 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
167 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
168 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
169 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
170 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
171 { .vendor_id = 0, /* sentinel */ },
172 };
173
174 static const struct eth_dev_ops eth_em_ops = {
175 .dev_configure = eth_em_configure,
176 .dev_start = eth_em_start,
177 .dev_stop = eth_em_stop,
178 .dev_close = eth_em_close,
179 .promiscuous_enable = eth_em_promiscuous_enable,
180 .promiscuous_disable = eth_em_promiscuous_disable,
181 .allmulticast_enable = eth_em_allmulticast_enable,
182 .allmulticast_disable = eth_em_allmulticast_disable,
183 .link_update = eth_em_link_update,
184 .stats_get = eth_em_stats_get,
185 .stats_reset = eth_em_stats_reset,
186 .dev_infos_get = eth_em_infos_get,
187 .mtu_set = eth_em_mtu_set,
188 .vlan_filter_set = eth_em_vlan_filter_set,
189 .vlan_offload_set = eth_em_vlan_offload_set,
190 .rx_queue_setup = eth_em_rx_queue_setup,
191 .rx_queue_release = eth_em_rx_queue_release,
192 .rx_queue_count = eth_em_rx_queue_count,
193 .rx_descriptor_done = eth_em_rx_descriptor_done,
194 .tx_queue_setup = eth_em_tx_queue_setup,
195 .tx_queue_release = eth_em_tx_queue_release,
196 .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
197 .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
198 .dev_led_on = eth_em_led_on,
199 .dev_led_off = eth_em_led_off,
200 .flow_ctrl_get = eth_em_flow_ctrl_get,
201 .flow_ctrl_set = eth_em_flow_ctrl_set,
202 .mac_addr_add = eth_em_rar_set,
203 .mac_addr_remove = eth_em_rar_clear,
204 .set_mc_addr_list = eth_em_set_mc_addr_list,
205 .rxq_info_get = em_rxq_info_get,
206 .txq_info_get = em_txq_info_get,
207 };
208
209 /**
210 * Atomically reads the link status information from global
211 * structure rte_eth_dev.
212 *
213 * @param dev
214 * - Pointer to the structure rte_eth_dev to read from.
215 * - Pointer to the buffer to be saved with the link status.
216 *
217 * @return
218 * - On success, zero.
219 * - On failure, negative value.
220 */
221 static inline int
222 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
223 struct rte_eth_link *link)
224 {
225 struct rte_eth_link *dst = link;
226 struct rte_eth_link *src = &(dev->data->dev_link);
227
228 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
229 *(uint64_t *)src) == 0)
230 return -1;
231
232 return 0;
233 }
234
235 /**
236 * Atomically writes the link status information into global
237 * structure rte_eth_dev.
238 *
239 * @param dev
240 * - Pointer to the structure rte_eth_dev to read from.
241 * - Pointer to the buffer to be saved with the link status.
242 *
243 * @return
244 * - On success, zero.
245 * - On failure, negative value.
246 */
247 static inline int
248 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
249 struct rte_eth_link *link)
250 {
251 struct rte_eth_link *dst = &(dev->data->dev_link);
252 struct rte_eth_link *src = link;
253
254 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
255 *(uint64_t *)src) == 0)
256 return -1;
257
258 return 0;
259 }
260
261 /**
262 * eth_em_dev_is_ich8 - Check for ICH8 device
263 * @hw: pointer to the HW structure
264 *
265 * return TRUE for ICH8, otherwise FALSE
266 **/
267 static bool
268 eth_em_dev_is_ich8(struct e1000_hw *hw)
269 {
270 DEBUGFUNC("eth_em_dev_is_ich8");
271
272 switch (hw->device_id) {
273 case E1000_DEV_ID_PCH_LPT_I217_LM:
274 case E1000_DEV_ID_PCH_LPT_I217_V:
275 case E1000_DEV_ID_PCH_LPTLP_I218_LM:
276 case E1000_DEV_ID_PCH_LPTLP_I218_V:
277 case E1000_DEV_ID_PCH_I218_V2:
278 case E1000_DEV_ID_PCH_I218_LM2:
279 case E1000_DEV_ID_PCH_I218_V3:
280 case E1000_DEV_ID_PCH_I218_LM3:
281 return 1;
282 default:
283 return 0;
284 }
285 }
286
287 static int
288 eth_em_dev_init(struct rte_eth_dev *eth_dev)
289 {
290 struct rte_pci_device *pci_dev;
291 struct e1000_adapter *adapter =
292 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
293 struct e1000_hw *hw =
294 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
295 struct e1000_vfta * shadow_vfta =
296 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
297
298 pci_dev = eth_dev->pci_dev;
299
300 eth_dev->dev_ops = &eth_em_ops;
301 eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
302 eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
303
304 /* for secondary processes, we don't initialise any further as primary
305 * has already done this work. Only check we don't need a different
306 * RX function */
307 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
308 if (eth_dev->data->scattered_rx)
309 eth_dev->rx_pkt_burst =
310 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
311 return 0;
312 }
313
314 rte_eth_copy_pci_info(eth_dev, pci_dev);
315
316 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
317 hw->device_id = pci_dev->id.device_id;
318 adapter->stopped = 0;
319
320 /* For ICH8 support we'll need to map the flash memory BAR */
321 if (eth_em_dev_is_ich8(hw))
322 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
323
324 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
325 em_hw_init(hw) != 0) {
326 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
327 "failed to init HW",
328 eth_dev->data->port_id, pci_dev->id.vendor_id,
329 pci_dev->id.device_id);
330 return -ENODEV;
331 }
332
333 /* Allocate memory for storing MAC addresses */
334 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
335 hw->mac.rar_entry_count, 0);
336 if (eth_dev->data->mac_addrs == NULL) {
337 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
338 "store MAC addresses",
339 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
340 return -ENOMEM;
341 }
342
343 /* Copy the permanent MAC address */
344 ether_addr_copy((struct ether_addr *) hw->mac.addr,
345 eth_dev->data->mac_addrs);
346
347 /* initialize the vfta */
348 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
349
350 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
351 eth_dev->data->port_id, pci_dev->id.vendor_id,
352 pci_dev->id.device_id);
353
354 rte_intr_callback_register(&(pci_dev->intr_handle),
355 eth_em_interrupt_handler, (void *)eth_dev);
356
357 return 0;
358 }
359
360 static int
361 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
362 {
363 struct rte_pci_device *pci_dev;
364 struct e1000_adapter *adapter =
365 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
366
367 PMD_INIT_FUNC_TRACE();
368
369 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
370 return -EPERM;
371
372 pci_dev = eth_dev->pci_dev;
373
374 if (adapter->stopped == 0)
375 eth_em_close(eth_dev);
376
377 eth_dev->dev_ops = NULL;
378 eth_dev->rx_pkt_burst = NULL;
379 eth_dev->tx_pkt_burst = NULL;
380
381 rte_free(eth_dev->data->mac_addrs);
382 eth_dev->data->mac_addrs = NULL;
383
384 /* disable uio intr before callback unregister */
385 rte_intr_disable(&(pci_dev->intr_handle));
386 rte_intr_callback_unregister(&(pci_dev->intr_handle),
387 eth_em_interrupt_handler, (void *)eth_dev);
388
389 return 0;
390 }
391
392 static struct eth_driver rte_em_pmd = {
393 .pci_drv = {
394 .id_table = pci_id_em_map,
395 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
396 RTE_PCI_DRV_DETACHABLE,
397 .probe = rte_eth_dev_pci_probe,
398 .remove = rte_eth_dev_pci_remove,
399 },
400 .eth_dev_init = eth_em_dev_init,
401 .eth_dev_uninit = eth_em_dev_uninit,
402 .dev_private_size = sizeof(struct e1000_adapter),
403 };
404
405 static int
406 em_hw_init(struct e1000_hw *hw)
407 {
408 int diag;
409
410 diag = hw->mac.ops.init_params(hw);
411 if (diag != 0) {
412 PMD_INIT_LOG(ERR, "MAC Initialization Error");
413 return diag;
414 }
415 diag = hw->nvm.ops.init_params(hw);
416 if (diag != 0) {
417 PMD_INIT_LOG(ERR, "NVM Initialization Error");
418 return diag;
419 }
420 diag = hw->phy.ops.init_params(hw);
421 if (diag != 0) {
422 PMD_INIT_LOG(ERR, "PHY Initialization Error");
423 return diag;
424 }
425 (void) e1000_get_bus_info(hw);
426
427 hw->mac.autoneg = 1;
428 hw->phy.autoneg_wait_to_complete = 0;
429 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
430
431 e1000_init_script_state_82541(hw, TRUE);
432 e1000_set_tbi_compatibility_82543(hw, TRUE);
433
434 /* Copper options */
435 if (hw->phy.media_type == e1000_media_type_copper) {
436 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
437 hw->phy.disable_polarity_correction = 0;
438 hw->phy.ms_type = e1000_ms_hw_default;
439 }
440
441 /*
442 * Start from a known state, this is important in reading the nvm
443 * and mac from that.
444 */
445 e1000_reset_hw(hw);
446
447 /* Make sure we have a good EEPROM before we read from it */
448 if (e1000_validate_nvm_checksum(hw) < 0) {
449 /*
450 * Some PCI-E parts fail the first check due to
451 * the link being in sleep state, call it again,
452 * if it fails a second time its a real issue.
453 */
454 diag = e1000_validate_nvm_checksum(hw);
455 if (diag < 0) {
456 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
457 goto error;
458 }
459 }
460
461 /* Read the permanent MAC address out of the EEPROM */
462 diag = e1000_read_mac_addr(hw);
463 if (diag != 0) {
464 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
465 goto error;
466 }
467
468 /* Now initialize the hardware */
469 diag = em_hardware_init(hw);
470 if (diag != 0) {
471 PMD_INIT_LOG(ERR, "Hardware initialization failed");
472 goto error;
473 }
474
475 hw->mac.get_link_status = 1;
476
477 /* Indicate SOL/IDER usage */
478 diag = e1000_check_reset_block(hw);
479 if (diag < 0) {
480 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
481 "SOL/IDER session");
482 }
483 return 0;
484
485 error:
486 em_hw_control_release(hw);
487 return diag;
488 }
489
490 static int
491 eth_em_configure(struct rte_eth_dev *dev)
492 {
493 struct e1000_interrupt *intr =
494 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
495
496 PMD_INIT_FUNC_TRACE();
497 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
498 PMD_INIT_FUNC_TRACE();
499
500 return 0;
501 }
502
503 static void
504 em_set_pba(struct e1000_hw *hw)
505 {
506 uint32_t pba;
507
508 /*
509 * Packet Buffer Allocation (PBA)
510 * Writing PBA sets the receive portion of the buffer
511 * the remainder is used for the transmit buffer.
512 * Devices before the 82547 had a Packet Buffer of 64K.
513 * After the 82547 the buffer was reduced to 40K.
514 */
515 switch (hw->mac.type) {
516 case e1000_82547:
517 case e1000_82547_rev_2:
518 /* 82547: Total Packet Buffer is 40K */
519 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
520 break;
521 case e1000_82571:
522 case e1000_82572:
523 case e1000_80003es2lan:
524 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
525 break;
526 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
527 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
528 break;
529 case e1000_82574:
530 case e1000_82583:
531 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
532 break;
533 case e1000_ich8lan:
534 pba = E1000_PBA_8K;
535 break;
536 case e1000_ich9lan:
537 case e1000_ich10lan:
538 pba = E1000_PBA_10K;
539 break;
540 case e1000_pchlan:
541 case e1000_pch2lan:
542 case e1000_pch_lpt:
543 pba = E1000_PBA_26K;
544 break;
545 default:
546 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
547 }
548
549 E1000_WRITE_REG(hw, E1000_PBA, pba);
550 }
551
552 static int
553 eth_em_start(struct rte_eth_dev *dev)
554 {
555 struct e1000_adapter *adapter =
556 E1000_DEV_PRIVATE(dev->data->dev_private);
557 struct e1000_hw *hw =
558 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
559 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
560 int ret, mask;
561 uint32_t intr_vector = 0;
562 uint32_t *speeds;
563 int num_speeds;
564 bool autoneg;
565
566 PMD_INIT_FUNC_TRACE();
567
568 eth_em_stop(dev);
569
570 e1000_power_up_phy(hw);
571
572 /* Set default PBA value */
573 em_set_pba(hw);
574
575 /* Put the address into the Receive Address Array */
576 e1000_rar_set(hw, hw->mac.addr, 0);
577
578 /*
579 * With the 82571 adapter, RAR[0] may be overwritten
580 * when the other port is reset, we make a duplicate
581 * in RAR[14] for that eventuality, this assures
582 * the interface continues to function.
583 */
584 if (hw->mac.type == e1000_82571) {
585 e1000_set_laa_state_82571(hw, TRUE);
586 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
587 }
588
589 /* Initialize the hardware */
590 if (em_hardware_init(hw)) {
591 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
592 return -EIO;
593 }
594
595 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
596
597 /* Configure for OS presence */
598 em_init_manageability(hw);
599
600 if (dev->data->dev_conf.intr_conf.rxq != 0) {
601 intr_vector = dev->data->nb_rx_queues;
602 if (rte_intr_efd_enable(intr_handle, intr_vector))
603 return -1;
604 }
605
606 if (rte_intr_dp_is_en(intr_handle)) {
607 intr_handle->intr_vec =
608 rte_zmalloc("intr_vec",
609 dev->data->nb_rx_queues * sizeof(int), 0);
610 if (intr_handle->intr_vec == NULL) {
611 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
612 " intr_vec\n", dev->data->nb_rx_queues);
613 return -ENOMEM;
614 }
615
616 /* enable rx interrupt */
617 em_rxq_intr_enable(hw);
618 }
619
620 eth_em_tx_init(dev);
621
622 ret = eth_em_rx_init(dev);
623 if (ret) {
624 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
625 em_dev_clear_queues(dev);
626 return ret;
627 }
628
629 e1000_clear_hw_cntrs_base_generic(hw);
630
631 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
632 ETH_VLAN_EXTEND_MASK;
633 eth_em_vlan_offload_set(dev, mask);
634
635 /* Set Interrupt Throttling Rate to maximum allowed value. */
636 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
637
638 /* Setup link speed and duplex */
639 speeds = &dev->data->dev_conf.link_speeds;
640 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
641 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
642 hw->mac.autoneg = 1;
643 } else {
644 num_speeds = 0;
645 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
646
647 /* Reset */
648 hw->phy.autoneg_advertised = 0;
649
650 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
651 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
652 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
653 num_speeds = -1;
654 goto error_invalid_config;
655 }
656 if (*speeds & ETH_LINK_SPEED_10M_HD) {
657 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
658 num_speeds++;
659 }
660 if (*speeds & ETH_LINK_SPEED_10M) {
661 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
662 num_speeds++;
663 }
664 if (*speeds & ETH_LINK_SPEED_100M_HD) {
665 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
666 num_speeds++;
667 }
668 if (*speeds & ETH_LINK_SPEED_100M) {
669 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
670 num_speeds++;
671 }
672 if (*speeds & ETH_LINK_SPEED_1G) {
673 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
674 num_speeds++;
675 }
676 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
677 goto error_invalid_config;
678
679 /* Set/reset the mac.autoneg based on the link speed,
680 * fixed or not
681 */
682 if (!autoneg) {
683 hw->mac.autoneg = 0;
684 hw->mac.forced_speed_duplex =
685 hw->phy.autoneg_advertised;
686 } else {
687 hw->mac.autoneg = 1;
688 }
689 }
690
691 e1000_setup_link(hw);
692
693 if (rte_intr_allow_others(intr_handle)) {
694 /* check if lsc interrupt is enabled */
695 if (dev->data->dev_conf.intr_conf.lsc != 0) {
696 ret = eth_em_interrupt_setup(dev);
697 if (ret) {
698 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
699 em_dev_clear_queues(dev);
700 return ret;
701 }
702 }
703 } else {
704 rte_intr_callback_unregister(intr_handle,
705 eth_em_interrupt_handler,
706 (void *)dev);
707 if (dev->data->dev_conf.intr_conf.lsc != 0)
708 PMD_INIT_LOG(INFO, "lsc won't enable because of"
709 " no intr multiplex\n");
710 }
711 /* check if rxq interrupt is enabled */
712 if (dev->data->dev_conf.intr_conf.rxq != 0)
713 eth_em_rxq_interrupt_setup(dev);
714
715 rte_intr_enable(intr_handle);
716
717 adapter->stopped = 0;
718
719 PMD_INIT_LOG(DEBUG, "<<");
720
721 return 0;
722
723 error_invalid_config:
724 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
725 dev->data->dev_conf.link_speeds, dev->data->port_id);
726 em_dev_clear_queues(dev);
727 return -EINVAL;
728 }
729
730 /*********************************************************************
731 *
732 * This routine disables all traffic on the adapter by issuing a
733 * global reset on the MAC.
734 *
735 **********************************************************************/
736 static void
737 eth_em_stop(struct rte_eth_dev *dev)
738 {
739 struct rte_eth_link link;
740 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
741 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
742
743 em_rxq_intr_disable(hw);
744 em_lsc_intr_disable(hw);
745
746 e1000_reset_hw(hw);
747 if (hw->mac.type >= e1000_82544)
748 E1000_WRITE_REG(hw, E1000_WUC, 0);
749
750 /* Power down the phy. Needed to make the link go down */
751 e1000_power_down_phy(hw);
752
753 em_dev_clear_queues(dev);
754
755 /* clear the recorded link status */
756 memset(&link, 0, sizeof(link));
757 rte_em_dev_atomic_write_link_status(dev, &link);
758
759 if (!rte_intr_allow_others(intr_handle))
760 /* resume to the default handler */
761 rte_intr_callback_register(intr_handle,
762 eth_em_interrupt_handler,
763 (void *)dev);
764
765 /* Clean datapath event and queue/vec mapping */
766 rte_intr_efd_disable(intr_handle);
767 if (intr_handle->intr_vec != NULL) {
768 rte_free(intr_handle->intr_vec);
769 intr_handle->intr_vec = NULL;
770 }
771 }
772
773 static void
774 eth_em_close(struct rte_eth_dev *dev)
775 {
776 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
777 struct e1000_adapter *adapter =
778 E1000_DEV_PRIVATE(dev->data->dev_private);
779
780 eth_em_stop(dev);
781 adapter->stopped = 1;
782 em_dev_free_queues(dev);
783 e1000_phy_hw_reset(hw);
784 em_release_manageability(hw);
785 em_hw_control_release(hw);
786 }
787
788 static int
789 em_get_rx_buffer_size(struct e1000_hw *hw)
790 {
791 uint32_t rx_buf_size;
792
793 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
794 return rx_buf_size;
795 }
796
797 /*********************************************************************
798 *
799 * Initialize the hardware
800 *
801 **********************************************************************/
802 static int
803 em_hardware_init(struct e1000_hw *hw)
804 {
805 uint32_t rx_buf_size;
806 int diag;
807
808 /* Issue a global reset */
809 e1000_reset_hw(hw);
810
811 /* Let the firmware know the OS is in control */
812 em_hw_control_acquire(hw);
813
814 /*
815 * These parameters control the automatic generation (Tx) and
816 * response (Rx) to Ethernet PAUSE frames.
817 * - High water mark should allow for at least two standard size (1518)
818 * frames to be received after sending an XOFF.
819 * - Low water mark works best when it is very near the high water mark.
820 * This allows the receiver to restart by sending XON when it has
821 * drained a bit. Here we use an arbitrary value of 1500 which will
822 * restart after one full frame is pulled from the buffer. There
823 * could be several smaller frames in the buffer and if so they will
824 * not trigger the XON until their total number reduces the buffer
825 * by 1500.
826 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
827 */
828 rx_buf_size = em_get_rx_buffer_size(hw);
829
830 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
831 hw->fc.low_water = hw->fc.high_water - 1500;
832
833 if (hw->mac.type == e1000_80003es2lan)
834 hw->fc.pause_time = UINT16_MAX;
835 else
836 hw->fc.pause_time = EM_FC_PAUSE_TIME;
837
838 hw->fc.send_xon = 1;
839
840 /* Set Flow control, use the tunable location if sane */
841 if (em_fc_setting <= e1000_fc_full)
842 hw->fc.requested_mode = em_fc_setting;
843 else
844 hw->fc.requested_mode = e1000_fc_none;
845
846 /* Workaround: no TX flow ctrl for PCH */
847 if (hw->mac.type == e1000_pchlan)
848 hw->fc.requested_mode = e1000_fc_rx_pause;
849
850 /* Override - settings for PCH2LAN, ya its magic :) */
851 if (hw->mac.type == e1000_pch2lan) {
852 hw->fc.high_water = 0x5C20;
853 hw->fc.low_water = 0x5048;
854 hw->fc.pause_time = 0x0650;
855 hw->fc.refresh_time = 0x0400;
856 } else if (hw->mac.type == e1000_pch_lpt) {
857 hw->fc.requested_mode = e1000_fc_full;
858 }
859
860 diag = e1000_init_hw(hw);
861 if (diag < 0)
862 return diag;
863 e1000_check_for_link(hw);
864 return 0;
865 }
866
867 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
868 static void
869 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
870 {
871 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
872 struct e1000_hw_stats *stats =
873 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
874 int pause_frames;
875
876 if(hw->phy.media_type == e1000_media_type_copper ||
877 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
878 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
879 stats->sec += E1000_READ_REG(hw, E1000_SEC);
880 }
881
882 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
883 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
884 stats->scc += E1000_READ_REG(hw, E1000_SCC);
885 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
886
887 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
888 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
889 stats->colc += E1000_READ_REG(hw, E1000_COLC);
890 stats->dc += E1000_READ_REG(hw, E1000_DC);
891 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
892 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
893 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
894
895 /*
896 * For watchdog management we need to know if we have been
897 * paused during the last interval, so capture that here.
898 */
899 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
900 stats->xoffrxc += pause_frames;
901 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
902 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
903 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
904 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
905 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
906 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
907 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
908 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
909 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
910 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
911 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
912 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
913
914 /*
915 * For the 64-bit byte counters the low dword must be read first.
916 * Both registers clear on the read of the high dword.
917 */
918
919 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
920 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
921 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
922 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
923
924 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
925 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
926 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
927 stats->roc += E1000_READ_REG(hw, E1000_ROC);
928 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
929
930 stats->tor += E1000_READ_REG(hw, E1000_TORH);
931 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
932
933 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
934 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
935 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
936 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
937 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
938 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
939 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
940 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
941 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
942 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
943
944 /* Interrupt Counts */
945
946 if (hw->mac.type >= e1000_82571) {
947 stats->iac += E1000_READ_REG(hw, E1000_IAC);
948 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
949 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
950 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
951 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
952 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
953 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
954 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
955 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
956 }
957
958 if (hw->mac.type >= e1000_82543) {
959 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
960 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
961 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
962 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
963 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
964 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
965 }
966
967 if (rte_stats == NULL)
968 return;
969
970 /* Rx Errors */
971 rte_stats->imissed = stats->mpc;
972 rte_stats->ierrors = stats->crcerrs +
973 stats->rlec + stats->ruc + stats->roc +
974 stats->rxerrc + stats->algnerrc + stats->cexterr;
975
976 /* Tx Errors */
977 rte_stats->oerrors = stats->ecol + stats->latecol;
978
979 rte_stats->ipackets = stats->gprc;
980 rte_stats->opackets = stats->gptc;
981 rte_stats->ibytes = stats->gorc;
982 rte_stats->obytes = stats->gotc;
983 }
984
985 static void
986 eth_em_stats_reset(struct rte_eth_dev *dev)
987 {
988 struct e1000_hw_stats *hw_stats =
989 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
990
991 /* HW registers are cleared on read */
992 eth_em_stats_get(dev, NULL);
993
994 /* Reset software totals */
995 memset(hw_stats, 0, sizeof(*hw_stats));
996 }
997
998 static int
999 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1000 {
1001 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1002
1003 em_rxq_intr_enable(hw);
1004 rte_intr_enable(&dev->pci_dev->intr_handle);
1005
1006 return 0;
1007 }
1008
1009 static int
1010 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1011 {
1012 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1013
1014 em_rxq_intr_disable(hw);
1015
1016 return 0;
1017 }
1018
1019 static uint32_t
1020 em_get_max_pktlen(const struct e1000_hw *hw)
1021 {
1022 switch (hw->mac.type) {
1023 case e1000_82571:
1024 case e1000_82572:
1025 case e1000_ich9lan:
1026 case e1000_ich10lan:
1027 case e1000_pch2lan:
1028 case e1000_pch_lpt:
1029 case e1000_82574:
1030 case e1000_80003es2lan: /* 9K Jumbo Frame size */
1031 case e1000_82583:
1032 return 0x2412;
1033 case e1000_pchlan:
1034 return 0x1000;
1035 /* Adapters that do not support jumbo frames */
1036 case e1000_ich8lan:
1037 return ETHER_MAX_LEN;
1038 default:
1039 return MAX_JUMBO_FRAME_SIZE;
1040 }
1041 }
1042
1043 static void
1044 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1045 {
1046 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1047
1048 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1049 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1050 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1051
1052 /*
1053 * Starting with 631xESB hw supports 2 TX/RX queues per port.
1054 * Unfortunatelly, all these nics have just one TX context.
1055 * So we have few choises for TX:
1056 * - Use just one TX queue.
1057 * - Allow cksum offload only for one TX queue.
1058 * - Don't allow TX cksum offload at all.
1059 * For now, option #1 was chosen.
1060 * To use second RX queue we have to use extended RX descriptor
1061 * (Multiple Receive Queues are mutually exclusive with UDP
1062 * fragmentation and are not supported when a legacy receive
1063 * descriptor format is used).
1064 * Which means separate RX routinies - as legacy nics (82540, 82545)
1065 * don't support extended RXD.
1066 * To avoid it we support just one RX queue for now (no RSS).
1067 */
1068
1069 dev_info->max_rx_queues = 1;
1070 dev_info->max_tx_queues = 1;
1071
1072 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1073 .nb_max = E1000_MAX_RING_DESC,
1074 .nb_min = E1000_MIN_RING_DESC,
1075 .nb_align = EM_RXD_ALIGN,
1076 };
1077
1078 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1079 .nb_max = E1000_MAX_RING_DESC,
1080 .nb_min = E1000_MIN_RING_DESC,
1081 .nb_align = EM_TXD_ALIGN,
1082 };
1083
1084 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1085 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1086 ETH_LINK_SPEED_1G;
1087 }
1088
1089 /* return 0 means link status changed, -1 means not changed */
1090 static int
1091 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1092 {
1093 struct e1000_hw *hw =
1094 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1095 struct rte_eth_link link, old;
1096 int link_check, count;
1097
1098 link_check = 0;
1099 hw->mac.get_link_status = 1;
1100
1101 /* possible wait-to-complete in up to 9 seconds */
1102 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1103 /* Read the real link status */
1104 switch (hw->phy.media_type) {
1105 case e1000_media_type_copper:
1106 /* Do the work to read phy */
1107 e1000_check_for_link(hw);
1108 link_check = !hw->mac.get_link_status;
1109 break;
1110
1111 case e1000_media_type_fiber:
1112 e1000_check_for_link(hw);
1113 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1114 E1000_STATUS_LU);
1115 break;
1116
1117 case e1000_media_type_internal_serdes:
1118 e1000_check_for_link(hw);
1119 link_check = hw->mac.serdes_has_link;
1120 break;
1121
1122 default:
1123 break;
1124 }
1125 if (link_check || wait_to_complete == 0)
1126 break;
1127 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1128 }
1129 memset(&link, 0, sizeof(link));
1130 rte_em_dev_atomic_read_link_status(dev, &link);
1131 old = link;
1132
1133 /* Now we check if a transition has happened */
1134 if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1135 uint16_t duplex, speed;
1136 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1137 link.link_duplex = (duplex == FULL_DUPLEX) ?
1138 ETH_LINK_FULL_DUPLEX :
1139 ETH_LINK_HALF_DUPLEX;
1140 link.link_speed = speed;
1141 link.link_status = ETH_LINK_UP;
1142 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1143 ETH_LINK_SPEED_FIXED);
1144 } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1145 link.link_speed = 0;
1146 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1147 link.link_status = ETH_LINK_DOWN;
1148 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1149 }
1150 rte_em_dev_atomic_write_link_status(dev, &link);
1151
1152 /* not changed */
1153 if (old.link_status == link.link_status)
1154 return -1;
1155
1156 /* changed */
1157 return 0;
1158 }
1159
1160 /*
1161 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1162 * For ASF and Pass Through versions of f/w this means
1163 * that the driver is loaded. For AMT version type f/w
1164 * this means that the network i/f is open.
1165 */
1166 static void
1167 em_hw_control_acquire(struct e1000_hw *hw)
1168 {
1169 uint32_t ctrl_ext, swsm;
1170
1171 /* Let firmware know the driver has taken over */
1172 if (hw->mac.type == e1000_82573) {
1173 swsm = E1000_READ_REG(hw, E1000_SWSM);
1174 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1175
1176 } else {
1177 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1178 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1179 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1180 }
1181 }
1182
1183 /*
1184 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1185 * For ASF and Pass Through versions of f/w this means that the
1186 * driver is no longer loaded. For AMT versions of the
1187 * f/w this means that the network i/f is closed.
1188 */
1189 static void
1190 em_hw_control_release(struct e1000_hw *hw)
1191 {
1192 uint32_t ctrl_ext, swsm;
1193
1194 /* Let firmware taken over control of h/w */
1195 if (hw->mac.type == e1000_82573) {
1196 swsm = E1000_READ_REG(hw, E1000_SWSM);
1197 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1198 } else {
1199 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1200 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1201 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1202 }
1203 }
1204
1205 /*
1206 * Bit of a misnomer, what this really means is
1207 * to enable OS management of the system... aka
1208 * to disable special hardware management features.
1209 */
1210 static void
1211 em_init_manageability(struct e1000_hw *hw)
1212 {
1213 if (e1000_enable_mng_pass_thru(hw)) {
1214 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1215 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1216
1217 /* disable hardware interception of ARP */
1218 manc &= ~(E1000_MANC_ARP_EN);
1219
1220 /* enable receiving management packets to the host */
1221 manc |= E1000_MANC_EN_MNG2HOST;
1222 manc2h |= 1 << 5; /* Mng Port 623 */
1223 manc2h |= 1 << 6; /* Mng Port 664 */
1224 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1225 E1000_WRITE_REG(hw, E1000_MANC, manc);
1226 }
1227 }
1228
1229 /*
1230 * Give control back to hardware management
1231 * controller if there is one.
1232 */
1233 static void
1234 em_release_manageability(struct e1000_hw *hw)
1235 {
1236 uint32_t manc;
1237
1238 if (e1000_enable_mng_pass_thru(hw)) {
1239 manc = E1000_READ_REG(hw, E1000_MANC);
1240
1241 /* re-enable hardware interception of ARP */
1242 manc |= E1000_MANC_ARP_EN;
1243 manc &= ~E1000_MANC_EN_MNG2HOST;
1244
1245 E1000_WRITE_REG(hw, E1000_MANC, manc);
1246 }
1247 }
1248
1249 static void
1250 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1251 {
1252 struct e1000_hw *hw =
1253 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1254 uint32_t rctl;
1255
1256 rctl = E1000_READ_REG(hw, E1000_RCTL);
1257 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1258 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1259 }
1260
1261 static void
1262 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1263 {
1264 struct e1000_hw *hw =
1265 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1266 uint32_t rctl;
1267
1268 rctl = E1000_READ_REG(hw, E1000_RCTL);
1269 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1270 if (dev->data->all_multicast == 1)
1271 rctl |= E1000_RCTL_MPE;
1272 else
1273 rctl &= (~E1000_RCTL_MPE);
1274 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1275 }
1276
1277 static void
1278 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1279 {
1280 struct e1000_hw *hw =
1281 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1282 uint32_t rctl;
1283
1284 rctl = E1000_READ_REG(hw, E1000_RCTL);
1285 rctl |= E1000_RCTL_MPE;
1286 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1287 }
1288
1289 static void
1290 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1291 {
1292 struct e1000_hw *hw =
1293 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1294 uint32_t rctl;
1295
1296 if (dev->data->promiscuous == 1)
1297 return; /* must remain in all_multicast mode */
1298 rctl = E1000_READ_REG(hw, E1000_RCTL);
1299 rctl &= (~E1000_RCTL_MPE);
1300 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1301 }
1302
1303 static int
1304 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1305 {
1306 struct e1000_hw *hw =
1307 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1308 struct e1000_vfta * shadow_vfta =
1309 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1310 uint32_t vfta;
1311 uint32_t vid_idx;
1312 uint32_t vid_bit;
1313
1314 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1315 E1000_VFTA_ENTRY_MASK);
1316 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1317 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1318 if (on)
1319 vfta |= vid_bit;
1320 else
1321 vfta &= ~vid_bit;
1322 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1323
1324 /* update local VFTA copy */
1325 shadow_vfta->vfta[vid_idx] = vfta;
1326
1327 return 0;
1328 }
1329
1330 static void
1331 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1332 {
1333 struct e1000_hw *hw =
1334 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1335 uint32_t reg;
1336
1337 /* Filter Table Disable */
1338 reg = E1000_READ_REG(hw, E1000_RCTL);
1339 reg &= ~E1000_RCTL_CFIEN;
1340 reg &= ~E1000_RCTL_VFE;
1341 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1342 }
1343
1344 static void
1345 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1346 {
1347 struct e1000_hw *hw =
1348 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349 struct e1000_vfta * shadow_vfta =
1350 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1351 uint32_t reg;
1352 int i;
1353
1354 /* Filter Table Enable, CFI not used for packet acceptance */
1355 reg = E1000_READ_REG(hw, E1000_RCTL);
1356 reg &= ~E1000_RCTL_CFIEN;
1357 reg |= E1000_RCTL_VFE;
1358 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1359
1360 /* restore vfta from local copy */
1361 for (i = 0; i < IGB_VFTA_SIZE; i++)
1362 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1363 }
1364
1365 static void
1366 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1367 {
1368 struct e1000_hw *hw =
1369 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1370 uint32_t reg;
1371
1372 /* VLAN Mode Disable */
1373 reg = E1000_READ_REG(hw, E1000_CTRL);
1374 reg &= ~E1000_CTRL_VME;
1375 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1376
1377 }
1378
1379 static void
1380 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1381 {
1382 struct e1000_hw *hw =
1383 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1384 uint32_t reg;
1385
1386 /* VLAN Mode Enable */
1387 reg = E1000_READ_REG(hw, E1000_CTRL);
1388 reg |= E1000_CTRL_VME;
1389 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1390 }
1391
1392 static void
1393 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1394 {
1395 if(mask & ETH_VLAN_STRIP_MASK){
1396 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1397 em_vlan_hw_strip_enable(dev);
1398 else
1399 em_vlan_hw_strip_disable(dev);
1400 }
1401
1402 if(mask & ETH_VLAN_FILTER_MASK){
1403 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1404 em_vlan_hw_filter_enable(dev);
1405 else
1406 em_vlan_hw_filter_disable(dev);
1407 }
1408 }
1409
1410 /*
1411 * It enables the interrupt mask and then enable the interrupt.
1412 *
1413 * @param dev
1414 * Pointer to struct rte_eth_dev.
1415 *
1416 * @return
1417 * - On success, zero.
1418 * - On failure, a negative value.
1419 */
1420 static int
1421 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1422 {
1423 uint32_t regval;
1424 struct e1000_hw *hw =
1425 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426
1427 /* clear interrupt */
1428 E1000_READ_REG(hw, E1000_ICR);
1429 regval = E1000_READ_REG(hw, E1000_IMS);
1430 E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1431 return 0;
1432 }
1433
1434 /*
1435 * It clears the interrupt causes and enables the interrupt.
1436 * It will be called once only during nic initialized.
1437 *
1438 * @param dev
1439 * Pointer to struct rte_eth_dev.
1440 *
1441 * @return
1442 * - On success, zero.
1443 * - On failure, a negative value.
1444 */
1445 static int
1446 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1447 {
1448 struct e1000_hw *hw =
1449 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1450
1451 E1000_READ_REG(hw, E1000_ICR);
1452 em_rxq_intr_enable(hw);
1453 return 0;
1454 }
1455
1456 /*
1457 * It enable receive packet interrupt.
1458 * @param hw
1459 * Pointer to struct e1000_hw
1460 *
1461 * @return
1462 */
1463 static void
1464 em_rxq_intr_enable(struct e1000_hw *hw)
1465 {
1466 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1467 E1000_WRITE_FLUSH(hw);
1468 }
1469
1470 /*
1471 * It disabled lsc interrupt.
1472 * @param hw
1473 * Pointer to struct e1000_hw
1474 *
1475 * @return
1476 */
1477 static void
1478 em_lsc_intr_disable(struct e1000_hw *hw)
1479 {
1480 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1481 E1000_WRITE_FLUSH(hw);
1482 }
1483
1484 /*
1485 * It disabled receive packet interrupt.
1486 * @param hw
1487 * Pointer to struct e1000_hw
1488 *
1489 * @return
1490 */
1491 static void
1492 em_rxq_intr_disable(struct e1000_hw *hw)
1493 {
1494 E1000_READ_REG(hw, E1000_ICR);
1495 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1496 E1000_WRITE_FLUSH(hw);
1497 }
1498
1499 /*
1500 * It reads ICR and gets interrupt causes, check it and set a bit flag
1501 * to update link status.
1502 *
1503 * @param dev
1504 * Pointer to struct rte_eth_dev.
1505 *
1506 * @return
1507 * - On success, zero.
1508 * - On failure, a negative value.
1509 */
1510 static int
1511 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1512 {
1513 uint32_t icr;
1514 struct e1000_hw *hw =
1515 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1516 struct e1000_interrupt *intr =
1517 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1518
1519 /* read-on-clear nic registers here */
1520 icr = E1000_READ_REG(hw, E1000_ICR);
1521 if (icr & E1000_ICR_LSC) {
1522 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1523 }
1524
1525 return 0;
1526 }
1527
1528 /*
1529 * It executes link_update after knowing an interrupt is prsent.
1530 *
1531 * @param dev
1532 * Pointer to struct rte_eth_dev.
1533 *
1534 * @return
1535 * - On success, zero.
1536 * - On failure, a negative value.
1537 */
1538 static int
1539 eth_em_interrupt_action(struct rte_eth_dev *dev)
1540 {
1541 struct e1000_hw *hw =
1542 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1543 struct e1000_interrupt *intr =
1544 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1545 uint32_t tctl, rctl;
1546 struct rte_eth_link link;
1547 int ret;
1548
1549 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1550 return -1;
1551
1552 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1553 rte_intr_enable(&(dev->pci_dev->intr_handle));
1554
1555 /* set get_link_status to check register later */
1556 hw->mac.get_link_status = 1;
1557 ret = eth_em_link_update(dev, 0);
1558
1559 /* check if link has changed */
1560 if (ret < 0)
1561 return 0;
1562
1563 memset(&link, 0, sizeof(link));
1564 rte_em_dev_atomic_read_link_status(dev, &link);
1565 if (link.link_status) {
1566 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1567 dev->data->port_id, (unsigned)link.link_speed,
1568 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1569 "full-duplex" : "half-duplex");
1570 } else {
1571 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1572 }
1573 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1574 dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1575 dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1576
1577 tctl = E1000_READ_REG(hw, E1000_TCTL);
1578 rctl = E1000_READ_REG(hw, E1000_RCTL);
1579 if (link.link_status) {
1580 /* enable Tx/Rx */
1581 tctl |= E1000_TCTL_EN;
1582 rctl |= E1000_RCTL_EN;
1583 } else {
1584 /* disable Tx/Rx */
1585 tctl &= ~E1000_TCTL_EN;
1586 rctl &= ~E1000_RCTL_EN;
1587 }
1588 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1589 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1590 E1000_WRITE_FLUSH(hw);
1591
1592 return 0;
1593 }
1594
1595 /**
1596 * Interrupt handler which shall be registered at first.
1597 *
1598 * @param handle
1599 * Pointer to interrupt handle.
1600 * @param param
1601 * The address of parameter (struct rte_eth_dev *) regsitered before.
1602 *
1603 * @return
1604 * void
1605 */
1606 static void
1607 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1608 void *param)
1609 {
1610 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1611
1612 eth_em_interrupt_get_status(dev);
1613 eth_em_interrupt_action(dev);
1614 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1615 }
1616
1617 static int
1618 eth_em_led_on(struct rte_eth_dev *dev)
1619 {
1620 struct e1000_hw *hw;
1621
1622 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1623 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1624 }
1625
1626 static int
1627 eth_em_led_off(struct rte_eth_dev *dev)
1628 {
1629 struct e1000_hw *hw;
1630
1631 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1632 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1633 }
1634
1635 static int
1636 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1637 {
1638 struct e1000_hw *hw;
1639 uint32_t ctrl;
1640 int tx_pause;
1641 int rx_pause;
1642
1643 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1644 fc_conf->pause_time = hw->fc.pause_time;
1645 fc_conf->high_water = hw->fc.high_water;
1646 fc_conf->low_water = hw->fc.low_water;
1647 fc_conf->send_xon = hw->fc.send_xon;
1648 fc_conf->autoneg = hw->mac.autoneg;
1649
1650 /*
1651 * Return rx_pause and tx_pause status according to actual setting of
1652 * the TFCE and RFCE bits in the CTRL register.
1653 */
1654 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1655 if (ctrl & E1000_CTRL_TFCE)
1656 tx_pause = 1;
1657 else
1658 tx_pause = 0;
1659
1660 if (ctrl & E1000_CTRL_RFCE)
1661 rx_pause = 1;
1662 else
1663 rx_pause = 0;
1664
1665 if (rx_pause && tx_pause)
1666 fc_conf->mode = RTE_FC_FULL;
1667 else if (rx_pause)
1668 fc_conf->mode = RTE_FC_RX_PAUSE;
1669 else if (tx_pause)
1670 fc_conf->mode = RTE_FC_TX_PAUSE;
1671 else
1672 fc_conf->mode = RTE_FC_NONE;
1673
1674 return 0;
1675 }
1676
1677 static int
1678 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1679 {
1680 struct e1000_hw *hw;
1681 int err;
1682 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1683 e1000_fc_none,
1684 e1000_fc_rx_pause,
1685 e1000_fc_tx_pause,
1686 e1000_fc_full
1687 };
1688 uint32_t rx_buf_size;
1689 uint32_t max_high_water;
1690 uint32_t rctl;
1691
1692 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1693 if (fc_conf->autoneg != hw->mac.autoneg)
1694 return -ENOTSUP;
1695 rx_buf_size = em_get_rx_buffer_size(hw);
1696 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1697
1698 /* At least reserve one Ethernet frame for watermark */
1699 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1700 if ((fc_conf->high_water > max_high_water) ||
1701 (fc_conf->high_water < fc_conf->low_water)) {
1702 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1703 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1704 return -EINVAL;
1705 }
1706
1707 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1708 hw->fc.pause_time = fc_conf->pause_time;
1709 hw->fc.high_water = fc_conf->high_water;
1710 hw->fc.low_water = fc_conf->low_water;
1711 hw->fc.send_xon = fc_conf->send_xon;
1712
1713 err = e1000_setup_link_generic(hw);
1714 if (err == E1000_SUCCESS) {
1715
1716 /* check if we want to forward MAC frames - driver doesn't have native
1717 * capability to do that, so we'll write the registers ourselves */
1718
1719 rctl = E1000_READ_REG(hw, E1000_RCTL);
1720
1721 /* set or clear MFLCN.PMCF bit depending on configuration */
1722 if (fc_conf->mac_ctrl_frame_fwd != 0)
1723 rctl |= E1000_RCTL_PMCF;
1724 else
1725 rctl &= ~E1000_RCTL_PMCF;
1726
1727 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1728 E1000_WRITE_FLUSH(hw);
1729
1730 return 0;
1731 }
1732
1733 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1734 return -EIO;
1735 }
1736
1737 static void
1738 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1739 uint32_t index, __rte_unused uint32_t pool)
1740 {
1741 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1742
1743 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1744 }
1745
1746 static void
1747 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1748 {
1749 uint8_t addr[ETHER_ADDR_LEN];
1750 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1751
1752 memset(addr, 0, sizeof(addr));
1753
1754 e1000_rar_set(hw, addr, index);
1755 }
1756
1757 static int
1758 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1759 {
1760 struct rte_eth_dev_info dev_info;
1761 struct e1000_hw *hw;
1762 uint32_t frame_size;
1763 uint32_t rctl;
1764
1765 eth_em_infos_get(dev, &dev_info);
1766 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1767
1768 /* check that mtu is within the allowed range */
1769 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1770 return -EINVAL;
1771
1772 /* refuse mtu that requires the support of scattered packets when this
1773 * feature has not been enabled before. */
1774 if (!dev->data->scattered_rx &&
1775 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1776 return -EINVAL;
1777
1778 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1779 rctl = E1000_READ_REG(hw, E1000_RCTL);
1780
1781 /* switch to jumbo mode if needed */
1782 if (frame_size > ETHER_MAX_LEN) {
1783 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1784 rctl |= E1000_RCTL_LPE;
1785 } else {
1786 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1787 rctl &= ~E1000_RCTL_LPE;
1788 }
1789 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1790
1791 /* update max frame size */
1792 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1793 return 0;
1794 }
1795
1796 static int
1797 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1798 struct ether_addr *mc_addr_set,
1799 uint32_t nb_mc_addr)
1800 {
1801 struct e1000_hw *hw;
1802
1803 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1804 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1805 return 0;
1806 }
1807
1808 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd.pci_drv);
1809 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
Ceph