ceph/src/dpdk/drivers/net/e1000/igb_regs.h

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33 #ifndef _IGB_REGS_H_
  34 #define _IGB_REGS_H_
  35
  36 #include "e1000_ethdev.h"
  37
  38 struct reg_info {
  39         uint32_t base_addr;
  40         uint32_t count;
  41         uint32_t stride;
  42         const char *name;
  43 };
  44
  45 static const struct reg_info igb_regs_general[] = {
  46         {E1000_CTRL, 1, 1, "E1000_CTRL"},
  47         {E1000_STATUS, 1, 1, "E1000_STATUS"},
  48         {E1000_CTRL_EXT, 1, 1, "E1000_CTRL_EXT"},
  49         {E1000_MDIC, 1, 1, "E1000_MDIC"},
  50         {E1000_SCTL, 1, 1, "E1000_SCTL"},
  51         {E1000_CONNSW, 1, 1, "E1000_CONNSW"},
  52         {E1000_VET, 1, 1, "E1000_VET"},
  53         {E1000_LEDCTL, 1, 1, "E1000_LEDCTL"},
  54         {E1000_PBA, 1, 1, "E1000_PBA"},
  55         {E1000_PBS, 1, 1, "E1000_PBS"},
  56         {E1000_FRTIMER, 1, 1, "E1000_FRTIMER"},
  57         {E1000_TCPTIMER, 1, 1, "E1000_TCPTIMER"},
  58         {0, 0, 0, ""}
  59 };
  60
  61 static const struct reg_info igb_regs_nvm[] = {
  62         {E1000_EECD, 1, 1, "E1000_EECD"},
  63         {0, 0, 0, ""}
  64 };
  65
  66 static const struct reg_info igb_regs_interrupt[] = {
  67         {E1000_EICS, 1, 1, "E1000_EICS"},
  68         {E1000_EIMS, 1, 1, "E1000_EIMS"},
  69         {E1000_EIMC, 1, 1, "E1000_EIMC"},
  70         {E1000_EIAC, 1, 1, "E1000_EIAC"},
  71         {E1000_EIAM, 1, 1, "E1000_EIAM"},
  72         {E1000_ICS, 1, 1, "E1000_ICS"},
  73         {E1000_IMS, 1, 1, "E1000_IMS"},
  74         {E1000_IMC, 1, 1, "E1000_IMC"},
  75         {E1000_IAC, 1, 1, "E1000_IAC"},
  76         {E1000_IAM,  1, 1, "E1000_IAM"},
  77         {E1000_IMIRVP, 1, 1, "E1000_IMIRVP"},
  78         {E1000_EITR(0), 10, 4, "E1000_EITR"},
  79         {E1000_IMIR(0), 8, 4, "E1000_IMIR"},
  80         {E1000_IMIREXT(0), 8, 4, "E1000_IMIREXT"},
  81         {0, 0, 0, ""}
  82 };
  83
  84 static const struct reg_info igb_regs_fctl[] = {
  85         {E1000_FCAL, 1, 1, "E1000_FCAL"},
  86         {E1000_FCAH, 1, 1, "E1000_FCAH"},
  87         {E1000_FCTTV, 1, 1, "E1000_FCTTV"},
  88         {E1000_FCRTL, 1, 1, "E1000_FCRTL"},
  89         {E1000_FCRTH, 1, 1, "E1000_FCRTH"},
  90         {E1000_FCRTV, 1, 1, "E1000_FCRTV"},
  91         {0, 0, 0, ""}
  92 };
  93
  94 static const struct reg_info igb_regs_rxdma[] = {
  95         {E1000_RDBAL(0), 4, 0x100, "E1000_RDBAL"},
  96         {E1000_RDBAH(0), 4, 0x100, "E1000_RDBAH"},
  97         {E1000_RDLEN(0), 4, 0x100, "E1000_RDLEN"},
  98         {E1000_RDH(0), 4, 0x100, "E1000_RDH"},
  99         {E1000_RDT(0), 4, 0x100, "E1000_RDT"},
 100         {E1000_RXCTL(0), 4, 0x100, "E1000_RXCTL"},
 101         {E1000_SRRCTL(0), 4, 0x100, "E1000_SRRCTL"},
 102         {E1000_DCA_RXCTRL(0), 4, 0x100, "E1000_DCA_RXCTRL"},
 103         {0, 0, 0, ""}
 104 };
 105
 106 static const struct reg_info igb_regs_rx[] = {
 107         {E1000_RCTL, 1, 1, "E1000_RCTL"},
 108         {E1000_RXCSUM, 1, 1, "E1000_RXCSUM"},
 109         {E1000_RLPML, 1, 1, "E1000_RLPML"},
 110         {E1000_RFCTL, 1, 1, "E1000_RFCTL"},
 111         {E1000_MRQC, 1, 1, "E1000_MRQC"},
 112         {E1000_VT_CTL, 1, 1, "E1000_VT_CTL"},
 113         {E1000_RAL(0), 16, 8, "E1000_RAL"},
 114         {E1000_RAH(0), 16, 8, "E1000_RAH"},
 115         {0, 0, 0, ""}
 116 };
 117
 118 static const struct reg_info igb_regs_tx[] = {
 119         {E1000_TCTL, 1, 1, "E1000_TCTL"},
 120         {E1000_TCTL_EXT, 1, 1, "E1000_TCTL_EXT"},
 121         {E1000_TIPG, 1, 1, "E1000_TIPG"},
 122         {E1000_DTXCTL, 1, 1, "E1000_DTXCTL"},
 123         {E1000_TDBAL(0), 4, 0x100, "E1000_TDBAL"},
 124         {E1000_TDBAH(0), 4, 0x100, "E1000_TDBAH"},
 125         {E1000_TDLEN(0), 4, 0x100, "E1000_TDLEN"},
 126         {E1000_TDH(0), 4, 0x100, "E1000_TDLEN"},
 127         {E1000_TDT(0), 4, 0x100, "E1000_TDT"},
 128         {E1000_TXDCTL(0), 4, 0x100, "E1000_TXDCTL"},
 129         {E1000_TDWBAL(0), 4, 0x100, "E1000_TDWBAL"},
 130         {E1000_TDWBAH(0), 4, 0x100, "E1000_TDWBAH"},
 131         {E1000_DCA_TXCTRL(0), 4, 0x100, "E1000_DCA_TXCTRL"},
 132         {E1000_TDFH, 1, 1, "E1000_TDFH"},
 133         {E1000_TDFT, 1, 1, "E1000_TDFT"},
 134         {E1000_TDFHS, 1, 1, "E1000_TDFHS"},
 135         {E1000_TDFPC, 1, 1, "E1000_TDFPC"},
 136         {0, 0, 0, ""}
 137 };
 138
 139 static const struct reg_info igb_regs_wakeup[] = {
 140         {E1000_WUC, 1, 1, "E1000_WUC"},
 141         {E1000_WUFC, 1, 1, "E1000_WUFC"},
 142         {E1000_WUS, 1, 1, "E1000_WUS"},
 143         {E1000_IPAV, 1, 1, "E1000_IPAV"},
 144         {E1000_WUPL, 1, 1, "E1000_WUPL"},
 145         {E1000_IP4AT_REG(0), 4, 8, "E1000_IP4AT_REG"},
 146         {E1000_IP6AT_REG(0), 4, 4, "E1000_IP6AT_REG"},
 147         {E1000_WUPM_REG(0), 4, 4, "E1000_WUPM_REG"},
 148         {E1000_FFMT_REG(0), 4, 8, "E1000_FFMT_REG"},
 149         {E1000_FFVT_REG(0), 4, 8, "E1000_FFVT_REG"},
 150         {E1000_FFLT_REG(0), 4, 8, "E1000_FFLT_REG"},
 151         {0, 0, 0, ""}
 152 };
 153
 154 static const struct reg_info igb_regs_mac[] = {
 155         {E1000_PCS_CFG0, 1, 1, "E1000_PCS_CFG0"},
 156         {E1000_PCS_LCTL, 1, 1, "E1000_PCS_LCTL"},
 157         {E1000_PCS_LSTAT, 1, 1, "E1000_PCS_LSTAT"},
 158         {E1000_PCS_ANADV, 1, 1, "E1000_PCS_ANADV"},
 159         {E1000_PCS_LPAB, 1, 1, "E1000_PCS_LPAB"},
 160         {E1000_PCS_NPTX, 1, 1, "E1000_PCS_NPTX"},
 161         {E1000_PCS_LPABNP, 1, 1, "E1000_PCS_LPABNP"},
 162         {0, 0, 0, ""}
 163 };
 164
 165 static const struct reg_info *igb_regs[] = {
 166                                 igb_regs_general,
 167                                 igb_regs_nvm,
 168                                 igb_regs_interrupt,
 169                                 igb_regs_fctl,
 170                                 igb_regs_rxdma,
 171                                 igb_regs_rx,
 172                                 igb_regs_tx,
 173                                 igb_regs_wakeup,
 174                                 igb_regs_mac,
 175                                 NULL};
 176
 177 /* FIXME: reading igb_regs_interrupt results side-effect which doesn't
 178  * work with VFIO; re-install igb_regs_interrupt once issue is resolved.
 179  */
 180 static const struct reg_info *igbvf_regs[] = {
 181                                 igb_regs_general,
 182                                 igb_regs_rxdma,
 183                                 igb_regs_tx,
 184                                 NULL};
 185
 186 static inline int
 187 igb_read_regs(struct e1000_hw *hw, const struct reg_info *reg,
 188         uint32_t *reg_buf)
 189 {
 190         unsigned int i;
 191
 192         for (i = 0; i < reg->count; i++) {
 193                 reg_buf[i] = E1000_READ_REG(hw,
 194                                 reg->base_addr + i * reg->stride);
 195         }
 196         return reg->count;
 197 };
 198
 199 static inline int
 200 igb_reg_group_count(const struct reg_info *regs)
 201 {
 202         int count = 0;
 203         int i = 0;
 204
 205         while (regs[i].count)
 206                 count += regs[i++].count;
 207         return count;
 208 };
 209
 210 static inline int
 211 igb_read_regs_group(struct rte_eth_dev *dev, uint32_t *reg_buf,
 212                 const struct reg_info *regs)
 213 {
 214         int count = 0;
 215         int i = 0;
 216         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217
 218         while (regs[i].count)
 219                 count += igb_read_regs(hw, &regs[i++], &reg_buf[count]);
 220         return count;
 221 };
 222
 223 #endif /* _IGB_REGS_H_ */