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[ceph.git] / ceph / src / dpdk / drivers / net / ena / base / ena_com.c
1 /*-
2 * BSD LICENSE
3 *
4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include "ena_com.h"
35
36 /*****************************************************************************/
37 /*****************************************************************************/
38
39 /* Timeout in micro-sec */
40 #define ADMIN_CMD_TIMEOUT_US (1000000)
41
42 #define ENA_ASYNC_QUEUE_DEPTH 4
43 #define ENA_ADMIN_QUEUE_DEPTH 32
44
45 #define MIN_ENA_VER (((ENA_COMMON_SPEC_VERSION_MAJOR) << \
46 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) \
47 | (ENA_COMMON_SPEC_VERSION_MINOR))
48
49 #define ENA_CTRL_MAJOR 0
50 #define ENA_CTRL_MINOR 0
51 #define ENA_CTRL_SUB_MINOR 1
52
53 #define MIN_ENA_CTRL_VER \
54 (((ENA_CTRL_MAJOR) << \
55 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
56 ((ENA_CTRL_MINOR) << \
57 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
58 (ENA_CTRL_SUB_MINOR))
59
60 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x)))
61 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32))
62
63 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
64
65 static int ena_alloc_cnt;
66
67 /*****************************************************************************/
68 /*****************************************************************************/
69 /*****************************************************************************/
70
71 enum ena_cmd_status {
72 ENA_CMD_SUBMITTED,
73 ENA_CMD_COMPLETED,
74 /* Abort - canceled by the driver */
75 ENA_CMD_ABORTED,
76 };
77
78 struct ena_comp_ctx {
79 ena_wait_event_t wait_event;
80 struct ena_admin_acq_entry *user_cqe;
81 u32 comp_size;
82 enum ena_cmd_status status;
83 /* status from the device */
84 u8 comp_status;
85 u8 cmd_opcode;
86 bool occupied;
87 };
88
89 static inline int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
90 struct ena_common_mem_addr *ena_addr,
91 dma_addr_t addr)
92 {
93 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
94 ena_trc_err("dma address has more bits that the device supports\n");
95 return ENA_COM_INVAL;
96 }
97
98 ena_addr->mem_addr_low = (u32)addr;
99 ena_addr->mem_addr_high =
100 ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 32)) >> 32);
101
102 return 0;
103 }
104
105 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
106 {
107 ENA_MEM_ALLOC_COHERENT(queue->q_dmadev,
108 ADMIN_SQ_SIZE(queue->q_depth),
109 queue->sq.entries,
110 queue->sq.dma_addr,
111 queue->sq.mem_handle);
112
113 if (!queue->sq.entries) {
114 ena_trc_err("memory allocation failed");
115 return ENA_COM_NO_MEM;
116 }
117
118 queue->sq.head = 0;
119 queue->sq.tail = 0;
120 queue->sq.phase = 1;
121
122 queue->sq.db_addr = NULL;
123
124 return 0;
125 }
126
127 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
128 {
129 ENA_MEM_ALLOC_COHERENT(queue->q_dmadev,
130 ADMIN_CQ_SIZE(queue->q_depth),
131 queue->cq.entries,
132 queue->cq.dma_addr,
133 queue->cq.mem_handle);
134
135 if (!queue->cq.entries) {
136 ena_trc_err("memory allocation failed");
137 return ENA_COM_NO_MEM;
138 }
139
140 queue->cq.head = 0;
141 queue->cq.phase = 1;
142
143 return 0;
144 }
145
146 static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
147 struct ena_aenq_handlers *aenq_handlers)
148 {
149 u32 addr_low, addr_high, aenq_caps;
150
151 dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
152 ENA_MEM_ALLOC_COHERENT(dev->dmadev,
153 ADMIN_AENQ_SIZE(dev->aenq.q_depth),
154 dev->aenq.entries,
155 dev->aenq.dma_addr,
156 dev->aenq.mem_handle);
157
158 if (!dev->aenq.entries) {
159 ena_trc_err("memory allocation failed");
160 return ENA_COM_NO_MEM;
161 }
162
163 dev->aenq.head = dev->aenq.q_depth;
164 dev->aenq.phase = 1;
165
166 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(dev->aenq.dma_addr);
167 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(dev->aenq.dma_addr);
168
169 ENA_REG_WRITE32(addr_low, (unsigned char *)dev->reg_bar
170 + ENA_REGS_AENQ_BASE_LO_OFF);
171 ENA_REG_WRITE32(addr_high, (unsigned char *)dev->reg_bar
172 + ENA_REGS_AENQ_BASE_HI_OFF);
173
174 aenq_caps = 0;
175 aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
176 aenq_caps |= (sizeof(struct ena_admin_aenq_entry) <<
177 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
178 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
179
180 ENA_REG_WRITE32(aenq_caps, (unsigned char *)dev->reg_bar
181 + ENA_REGS_AENQ_CAPS_OFF);
182
183 if (unlikely(!aenq_handlers))
184 ena_trc_err("aenq handlers pointer is NULL\n");
185
186 dev->aenq.aenq_handlers = aenq_handlers;
187
188 return 0;
189 }
190
191 static inline void comp_ctxt_release(struct ena_com_admin_queue *queue,
192 struct ena_comp_ctx *comp_ctx)
193 {
194 comp_ctx->occupied = false;
195 ATOMIC32_DEC(&queue->outstanding_cmds);
196 }
197
198 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
199 u16 command_id, bool capture)
200 {
201 if (unlikely(command_id >= queue->q_depth)) {
202 ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
203 command_id, queue->q_depth);
204 return NULL;
205 }
206
207 if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
208 ena_trc_err("Completion context is occupied\n");
209 return NULL;
210 }
211
212 if (capture) {
213 ATOMIC32_INC(&queue->outstanding_cmds);
214 queue->comp_ctx[command_id].occupied = true;
215 }
216
217 return &queue->comp_ctx[command_id];
218 }
219
220 static struct ena_comp_ctx *
221 __ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
222 struct ena_admin_aq_entry *cmd,
223 size_t cmd_size_in_bytes,
224 struct ena_admin_acq_entry *comp,
225 size_t comp_size_in_bytes)
226 {
227 struct ena_comp_ctx *comp_ctx;
228 u16 tail_masked, cmd_id;
229 u16 queue_size_mask;
230 u16 cnt;
231
232 queue_size_mask = admin_queue->q_depth - 1;
233
234 tail_masked = admin_queue->sq.tail & queue_size_mask;
235
236 /* In case of queue FULL */
237 cnt = admin_queue->sq.tail - admin_queue->sq.head;
238 if (cnt >= admin_queue->q_depth) {
239 ena_trc_dbg("admin queue is FULL (tail %d head %d depth: %d)\n",
240 admin_queue->sq.tail,
241 admin_queue->sq.head,
242 admin_queue->q_depth);
243 admin_queue->stats.out_of_space++;
244 return ERR_PTR(ENA_COM_NO_SPACE);
245 }
246
247 cmd_id = admin_queue->curr_cmd_id;
248
249 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
250 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
251
252 cmd->aq_common_descriptor.command_id |= cmd_id &
253 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
254
255 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
256
257 comp_ctx->status = ENA_CMD_SUBMITTED;
258 comp_ctx->comp_size = (u32)comp_size_in_bytes;
259 comp_ctx->user_cqe = comp;
260 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
261
262 ENA_WAIT_EVENT_CLEAR(comp_ctx->wait_event);
263
264 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
265
266 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
267 queue_size_mask;
268
269 admin_queue->sq.tail++;
270 admin_queue->stats.submitted_cmd++;
271
272 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
273 admin_queue->sq.phase = !admin_queue->sq.phase;
274
275 ENA_REG_WRITE32(admin_queue->sq.tail, admin_queue->sq.db_addr);
276
277 return comp_ctx;
278 }
279
280 static inline int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
281 {
282 size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
283 struct ena_comp_ctx *comp_ctx;
284 u16 i;
285
286 queue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size);
287 if (unlikely(!queue->comp_ctx)) {
288 ena_trc_err("memory allocation failed");
289 return ENA_COM_NO_MEM;
290 }
291
292 for (i = 0; i < queue->q_depth; i++) {
293 comp_ctx = get_comp_ctxt(queue, i, false);
294 if (comp_ctx)
295 ENA_WAIT_EVENT_INIT(comp_ctx->wait_event);
296 }
297
298 return 0;
299 }
300
301 static struct ena_comp_ctx *
302 ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
303 struct ena_admin_aq_entry *cmd,
304 size_t cmd_size_in_bytes,
305 struct ena_admin_acq_entry *comp,
306 size_t comp_size_in_bytes)
307 {
308 unsigned long flags = 0;
309 struct ena_comp_ctx *comp_ctx;
310
311 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
312 if (unlikely(!admin_queue->running_state)) {
313 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
314 return ERR_PTR(ENA_COM_NO_DEVICE);
315 }
316 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
317 cmd_size_in_bytes,
318 comp,
319 comp_size_in_bytes);
320 if (unlikely(IS_ERR(comp_ctx)))
321 admin_queue->running_state = false;
322 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
323
324 return comp_ctx;
325 }
326
327 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
328 struct ena_com_create_io_ctx *ctx,
329 struct ena_com_io_sq *io_sq)
330 {
331 size_t size;
332 int dev_node = 0;
333
334 ENA_TOUCH(ctx);
335
336 memset(&io_sq->desc_addr, 0x0, sizeof(struct ena_com_io_desc_addr));
337
338 io_sq->desc_entry_size =
339 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
340 sizeof(struct ena_eth_io_tx_desc) :
341 sizeof(struct ena_eth_io_rx_desc);
342
343 size = io_sq->desc_entry_size * io_sq->q_depth;
344
345 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
346 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
347 size,
348 io_sq->desc_addr.virt_addr,
349 io_sq->desc_addr.phys_addr,
350 ctx->numa_node,
351 dev_node);
352 if (!io_sq->desc_addr.virt_addr)
353 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
354 size,
355 io_sq->desc_addr.virt_addr,
356 io_sq->desc_addr.phys_addr,
357 io_sq->desc_addr.mem_handle);
358 } else {
359 ENA_MEM_ALLOC_NODE(ena_dev->dmadev,
360 size,
361 io_sq->desc_addr.virt_addr,
362 ctx->numa_node,
363 dev_node);
364 if (!io_sq->desc_addr.virt_addr)
365 io_sq->desc_addr.virt_addr =
366 ENA_MEM_ALLOC(ena_dev->dmadev, size);
367 }
368
369 if (!io_sq->desc_addr.virt_addr) {
370 ena_trc_err("memory allocation failed");
371 return ENA_COM_NO_MEM;
372 }
373
374 io_sq->tail = 0;
375 io_sq->next_to_comp = 0;
376 io_sq->phase = 1;
377
378 return 0;
379 }
380
381 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
382 struct ena_com_create_io_ctx *ctx,
383 struct ena_com_io_cq *io_cq)
384 {
385 size_t size;
386 int prev_node = 0;
387
388 ENA_TOUCH(ctx);
389 memset(&io_cq->cdesc_addr, 0x0, sizeof(struct ena_com_io_desc_addr));
390
391 /* Use the basic completion descriptor for Rx */
392 io_cq->cdesc_entry_size_in_bytes =
393 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
394 sizeof(struct ena_eth_io_tx_cdesc) :
395 sizeof(struct ena_eth_io_rx_cdesc_base);
396
397 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
398
399 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
400 size,
401 io_cq->cdesc_addr.virt_addr,
402 io_cq->cdesc_addr.phys_addr,
403 ctx->numa_node,
404 prev_node);
405 if (!io_cq->cdesc_addr.virt_addr)
406 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
407 size,
408 io_cq->cdesc_addr.virt_addr,
409 io_cq->cdesc_addr.phys_addr,
410 io_cq->cdesc_addr.mem_handle);
411
412 if (!io_cq->cdesc_addr.virt_addr) {
413 ena_trc_err("memory allocation failed");
414 return ENA_COM_NO_MEM;
415 }
416
417 io_cq->phase = 1;
418 io_cq->head = 0;
419
420 return 0;
421 }
422
423 static void
424 ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
425 struct ena_admin_acq_entry *cqe)
426 {
427 struct ena_comp_ctx *comp_ctx;
428 u16 cmd_id;
429
430 cmd_id = cqe->acq_common_descriptor.command &
431 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
432
433 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
434 if (unlikely(!comp_ctx)) {
435 ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n");
436 admin_queue->running_state = false;
437 return;
438 }
439
440 comp_ctx->status = ENA_CMD_COMPLETED;
441 comp_ctx->comp_status = cqe->acq_common_descriptor.status;
442
443 if (comp_ctx->user_cqe)
444 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
445
446 if (!admin_queue->polling)
447 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
448 }
449
450 static void
451 ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
452 {
453 struct ena_admin_acq_entry *cqe = NULL;
454 u16 comp_num = 0;
455 u16 head_masked;
456 u8 phase;
457
458 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
459 phase = admin_queue->cq.phase;
460
461 cqe = &admin_queue->cq.entries[head_masked];
462
463 /* Go over all the completions */
464 while ((cqe->acq_common_descriptor.flags &
465 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
466 /* Do not read the rest of the completion entry before the
467 * phase bit was validated
468 */
469 rmb();
470 ena_com_handle_single_admin_completion(admin_queue, cqe);
471
472 head_masked++;
473 comp_num++;
474 if (unlikely(head_masked == admin_queue->q_depth)) {
475 head_masked = 0;
476 phase = !phase;
477 }
478
479 cqe = &admin_queue->cq.entries[head_masked];
480 }
481
482 admin_queue->cq.head += comp_num;
483 admin_queue->cq.phase = phase;
484 admin_queue->sq.head += comp_num;
485 admin_queue->stats.completed_cmd += comp_num;
486 }
487
488 static int ena_com_comp_status_to_errno(u8 comp_status)
489 {
490 if (unlikely(comp_status != 0))
491 ena_trc_err("admin command failed[%u]\n", comp_status);
492
493 if (unlikely(comp_status > ENA_ADMIN_UNKNOWN_ERROR))
494 return ENA_COM_INVAL;
495
496 switch (comp_status) {
497 case ENA_ADMIN_SUCCESS:
498 return 0;
499 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
500 return ENA_COM_NO_MEM;
501 case ENA_ADMIN_UNSUPPORTED_OPCODE:
502 return ENA_COM_PERMISSION;
503 case ENA_ADMIN_BAD_OPCODE:
504 case ENA_ADMIN_MALFORMED_REQUEST:
505 case ENA_ADMIN_ILLEGAL_PARAMETER:
506 case ENA_ADMIN_UNKNOWN_ERROR:
507 return ENA_COM_INVAL;
508 }
509
510 return 0;
511 }
512
513 static int
514 ena_com_wait_and_process_admin_cq_polling(
515 struct ena_comp_ctx *comp_ctx,
516 struct ena_com_admin_queue *admin_queue)
517 {
518 unsigned long flags = 0;
519 u64 start_time;
520 int ret;
521
522 start_time = ENA_GET_SYSTEM_USECS();
523
524 while (comp_ctx->status == ENA_CMD_SUBMITTED) {
525 if ((ENA_GET_SYSTEM_USECS() - start_time) >
526 ADMIN_CMD_TIMEOUT_US) {
527 ena_trc_err("Wait for completion (polling) timeout\n");
528 /* ENA didn't have any completion */
529 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
530 admin_queue->stats.no_completion++;
531 admin_queue->running_state = false;
532 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
533
534 ret = ENA_COM_TIMER_EXPIRED;
535 goto err;
536 }
537
538 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
539 ena_com_handle_admin_completion(admin_queue);
540 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
541 }
542
543 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
544 ena_trc_err("Command was aborted\n");
545 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
546 admin_queue->stats.aborted_cmd++;
547 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
548 ret = ENA_COM_NO_DEVICE;
549 goto err;
550 }
551
552 ENA_ASSERT(comp_ctx->status == ENA_CMD_COMPLETED,
553 "Invalid comp status %d\n", comp_ctx->status);
554
555 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
556 err:
557 comp_ctxt_release(admin_queue, comp_ctx);
558 return ret;
559 }
560
561 static int
562 ena_com_wait_and_process_admin_cq_interrupts(
563 struct ena_comp_ctx *comp_ctx,
564 struct ena_com_admin_queue *admin_queue)
565 {
566 unsigned long flags = 0;
567 int ret = 0;
568
569 ENA_WAIT_EVENT_WAIT(comp_ctx->wait_event,
570 ADMIN_CMD_TIMEOUT_US);
571
572 /* In case the command wasn't completed find out the root cause.
573 * There might be 2 kinds of errors
574 * 1) No completion (timeout reached)
575 * 2) There is completion but the device didn't get any msi-x interrupt.
576 */
577 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
578 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
579 ena_com_handle_admin_completion(admin_queue);
580 admin_queue->stats.no_completion++;
581 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
582
583 if (comp_ctx->status == ENA_CMD_COMPLETED)
584 ena_trc_err("The ena device have completion but the driver didn't receive any MSI-X interrupt (cmd %d)\n",
585 comp_ctx->cmd_opcode);
586 else
587 ena_trc_err("The ena device doesn't send any completion for the admin cmd %d status %d\n",
588 comp_ctx->cmd_opcode, comp_ctx->status);
589
590 admin_queue->running_state = false;
591 ret = ENA_COM_TIMER_EXPIRED;
592 goto err;
593 }
594
595 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
596 err:
597 comp_ctxt_release(admin_queue, comp_ctx);
598 return ret;
599 }
600
601 /* This method read the hardware device register through posting writes
602 * and waiting for response
603 * On timeout the function will return ENA_MMIO_READ_TIMEOUT
604 */
605 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
606 {
607 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
608 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
609 mmio_read->read_resp;
610 u32 mmio_read_reg, ret;
611 unsigned long flags = 0;
612 int i;
613
614 ENA_MIGHT_SLEEP();
615
616 /* If readless is disabled, perform regular read */
617 if (!mmio_read->readless_supported)
618 return ENA_REG_READ32((unsigned char *)ena_dev->reg_bar +
619 offset);
620
621 ENA_SPINLOCK_LOCK(mmio_read->lock, flags);
622 mmio_read->seq_num++;
623
624 read_resp->req_id = mmio_read->seq_num + 0xDEAD;
625 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
626 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
627 mmio_read_reg |= mmio_read->seq_num &
628 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
629
630 /* make sure read_resp->req_id get updated before the hw can write
631 * there
632 */
633 wmb();
634
635 ENA_REG_WRITE32(mmio_read_reg, (unsigned char *)ena_dev->reg_bar
636 + ENA_REGS_MMIO_REG_READ_OFF);
637
638 for (i = 0; i < ENA_REG_READ_TIMEOUT; i++) {
639 if (read_resp->req_id == mmio_read->seq_num)
640 break;
641
642 ENA_UDELAY(1);
643 }
644
645 if (unlikely(i == ENA_REG_READ_TIMEOUT)) {
646 ena_trc_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
647 mmio_read->seq_num,
648 offset,
649 read_resp->req_id,
650 read_resp->reg_off);
651 ret = ENA_MMIO_READ_TIMEOUT;
652 goto err;
653 }
654
655 if (read_resp->reg_off != offset) {
656 ena_trc_err("reading failed for wrong offset value");
657 ret = ENA_MMIO_READ_TIMEOUT;
658 } else {
659 ret = read_resp->reg_val;
660 }
661 err:
662 ENA_SPINLOCK_UNLOCK(mmio_read->lock, flags);
663
664 return ret;
665 }
666
667 /* There are two types to wait for completion.
668 * Polling mode - wait until the completion is available.
669 * Async mode - wait on wait queue until the completion is ready
670 * (or the timeout expired).
671 * It is expected that the IRQ called ena_com_handle_admin_completion
672 * to mark the completions.
673 */
674 static int
675 ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
676 struct ena_com_admin_queue *admin_queue)
677 {
678 if (admin_queue->polling)
679 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
680 admin_queue);
681
682 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
683 admin_queue);
684 }
685
686 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
687 struct ena_com_io_sq *io_sq)
688 {
689 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
690 struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
691 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
692 u8 direction;
693 int ret;
694
695 memset(&destroy_cmd, 0x0, sizeof(struct ena_admin_aq_destroy_sq_cmd));
696
697 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
698 direction = ENA_ADMIN_SQ_DIRECTION_TX;
699 else
700 direction = ENA_ADMIN_SQ_DIRECTION_RX;
701
702 destroy_cmd.sq.sq_identity |= (direction <<
703 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
704 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
705
706 destroy_cmd.sq.sq_idx = io_sq->idx;
707 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
708
709 ret = ena_com_execute_admin_command(
710 admin_queue,
711 (struct ena_admin_aq_entry *)&destroy_cmd,
712 sizeof(destroy_cmd),
713 (struct ena_admin_acq_entry *)&destroy_resp,
714 sizeof(destroy_resp));
715
716 if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
717 ena_trc_err("failed to destroy io sq error: %d\n", ret);
718
719 return ret;
720 }
721
722 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
723 struct ena_com_io_sq *io_sq,
724 struct ena_com_io_cq *io_cq)
725 {
726 size_t size;
727
728 if (io_cq->cdesc_addr.virt_addr) {
729 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
730
731 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
732 size,
733 io_cq->cdesc_addr.virt_addr,
734 io_cq->cdesc_addr.phys_addr,
735 io_cq->cdesc_addr.mem_handle);
736
737 io_cq->cdesc_addr.virt_addr = NULL;
738 }
739
740 if (io_sq->desc_addr.virt_addr) {
741 size = io_sq->desc_entry_size * io_sq->q_depth;
742
743 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
744 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
745 size,
746 io_sq->desc_addr.virt_addr,
747 io_sq->desc_addr.phys_addr,
748 io_sq->desc_addr.mem_handle);
749 else
750 ENA_MEM_FREE(ena_dev->dmadev,
751 io_sq->desc_addr.virt_addr);
752
753 io_sq->desc_addr.virt_addr = NULL;
754 }
755 }
756
757 static int wait_for_reset_state(struct ena_com_dev *ena_dev,
758 u32 timeout, u16 exp_state)
759 {
760 u32 val, i;
761
762 for (i = 0; i < timeout; i++) {
763 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
764
765 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
766 ena_trc_err("Reg read timeout occurred\n");
767 return ENA_COM_TIMER_EXPIRED;
768 }
769
770 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
771 exp_state)
772 return 0;
773
774 /* The resolution of the timeout is 100ms */
775 ENA_MSLEEP(100);
776 }
777
778 return ENA_COM_TIMER_EXPIRED;
779 }
780
781 static bool
782 ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
783 enum ena_admin_aq_feature_id feature_id)
784 {
785 u32 feature_mask = 1 << feature_id;
786
787 /* Device attributes is always supported */
788 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
789 !(ena_dev->supported_features & feature_mask))
790 return false;
791
792 return true;
793 }
794
795 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
796 struct ena_admin_get_feat_resp *get_resp,
797 enum ena_admin_aq_feature_id feature_id,
798 dma_addr_t control_buf_dma_addr,
799 u32 control_buff_size)
800 {
801 struct ena_com_admin_queue *admin_queue;
802 struct ena_admin_get_feat_cmd get_cmd;
803 int ret;
804
805 if (!ena_dev) {
806 ena_trc_err("%s : ena_dev is NULL\n", __func__);
807 return ENA_COM_NO_DEVICE;
808 }
809
810 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
811 ena_trc_info("Feature %d isn't supported\n", feature_id);
812 return ENA_COM_PERMISSION;
813 }
814
815 memset(&get_cmd, 0x0, sizeof(get_cmd));
816 admin_queue = &ena_dev->admin_queue;
817
818 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
819
820 if (control_buff_size)
821 get_cmd.aq_common_descriptor.flags =
822 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
823 else
824 get_cmd.aq_common_descriptor.flags = 0;
825
826 ret = ena_com_mem_addr_set(ena_dev,
827 &get_cmd.control_buffer.address,
828 control_buf_dma_addr);
829 if (unlikely(ret)) {
830 ena_trc_err("memory address set failed\n");
831 return ret;
832 }
833
834 get_cmd.control_buffer.length = control_buff_size;
835
836 get_cmd.feat_common.feature_id = feature_id;
837
838 ret = ena_com_execute_admin_command(admin_queue,
839 (struct ena_admin_aq_entry *)
840 &get_cmd,
841 sizeof(get_cmd),
842 (struct ena_admin_acq_entry *)
843 get_resp,
844 sizeof(*get_resp));
845
846 if (unlikely(ret))
847 ena_trc_err("Failed to submit get_feature command %d error: %d\n",
848 feature_id, ret);
849
850 return ret;
851 }
852
853 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
854 struct ena_admin_get_feat_resp *get_resp,
855 enum ena_admin_aq_feature_id feature_id)
856 {
857 return ena_com_get_feature_ex(ena_dev,
858 get_resp,
859 feature_id,
860 0,
861 0);
862 }
863
864 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
865 {
866 struct ena_rss *rss = &ena_dev->rss;
867
868 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
869 sizeof(*rss->hash_key),
870 rss->hash_key,
871 rss->hash_key_dma_addr,
872 rss->hash_key_mem_handle);
873
874 if (unlikely(!rss->hash_key))
875 return ENA_COM_NO_MEM;
876
877 return 0;
878 }
879
880 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
881 {
882 struct ena_rss *rss = &ena_dev->rss;
883
884 if (rss->hash_key)
885 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
886 sizeof(*rss->hash_key),
887 rss->hash_key,
888 rss->hash_key_dma_addr,
889 rss->hash_key_mem_handle);
890 rss->hash_key = NULL;
891 }
892
893 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
894 {
895 struct ena_rss *rss = &ena_dev->rss;
896
897 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
898 sizeof(*rss->hash_ctrl),
899 rss->hash_ctrl,
900 rss->hash_ctrl_dma_addr,
901 rss->hash_ctrl_mem_handle);
902
903 if (unlikely(!rss->hash_ctrl))
904 return ENA_COM_NO_MEM;
905
906 return 0;
907 }
908
909 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
910 {
911 struct ena_rss *rss = &ena_dev->rss;
912
913 if (rss->hash_ctrl)
914 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
915 sizeof(*rss->hash_ctrl),
916 rss->hash_ctrl,
917 rss->hash_ctrl_dma_addr,
918 rss->hash_ctrl_mem_handle);
919 rss->hash_ctrl = NULL;
920 }
921
922 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
923 u16 log_size)
924 {
925 struct ena_rss *rss = &ena_dev->rss;
926 struct ena_admin_get_feat_resp get_resp;
927 size_t tbl_size;
928 int ret;
929
930 ret = ena_com_get_feature(ena_dev, &get_resp,
931 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
932 if (unlikely(ret))
933 return ret;
934
935 if ((get_resp.u.ind_table.min_size > log_size) ||
936 (get_resp.u.ind_table.max_size < log_size)) {
937 ena_trc_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
938 1 << log_size,
939 1 << get_resp.u.ind_table.min_size,
940 1 << get_resp.u.ind_table.max_size);
941 return ENA_COM_INVAL;
942 }
943
944 tbl_size = (1ULL << log_size) *
945 sizeof(struct ena_admin_rss_ind_table_entry);
946
947 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
948 tbl_size,
949 rss->rss_ind_tbl,
950 rss->rss_ind_tbl_dma_addr,
951 rss->rss_ind_tbl_mem_handle);
952 if (unlikely(!rss->rss_ind_tbl))
953 goto mem_err1;
954
955 tbl_size = (1ULL << log_size) * sizeof(u16);
956 rss->host_rss_ind_tbl =
957 ENA_MEM_ALLOC(ena_dev->dmadev, tbl_size);
958 if (unlikely(!rss->host_rss_ind_tbl))
959 goto mem_err2;
960
961 rss->tbl_log_size = log_size;
962
963 return 0;
964
965 mem_err2:
966 tbl_size = (1ULL << log_size) *
967 sizeof(struct ena_admin_rss_ind_table_entry);
968
969 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
970 tbl_size,
971 rss->rss_ind_tbl,
972 rss->rss_ind_tbl_dma_addr,
973 rss->rss_ind_tbl_mem_handle);
974 rss->rss_ind_tbl = NULL;
975 mem_err1:
976 rss->tbl_log_size = 0;
977 return ENA_COM_NO_MEM;
978 }
979
980 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
981 {
982 struct ena_rss *rss = &ena_dev->rss;
983 size_t tbl_size = (1ULL << rss->tbl_log_size) *
984 sizeof(struct ena_admin_rss_ind_table_entry);
985
986 if (rss->rss_ind_tbl)
987 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
988 tbl_size,
989 rss->rss_ind_tbl,
990 rss->rss_ind_tbl_dma_addr,
991 rss->rss_ind_tbl_mem_handle);
992 rss->rss_ind_tbl = NULL;
993
994 if (rss->host_rss_ind_tbl)
995 ENA_MEM_FREE(ena_dev->dmadev, rss->host_rss_ind_tbl);
996 rss->host_rss_ind_tbl = NULL;
997 }
998
999 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1000 struct ena_com_io_sq *io_sq, u16 cq_idx)
1001 {
1002 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1003 struct ena_admin_aq_create_sq_cmd create_cmd;
1004 struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1005 u8 direction;
1006 int ret;
1007
1008 memset(&create_cmd, 0x0, sizeof(struct ena_admin_aq_create_sq_cmd));
1009
1010 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1011
1012 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1013 direction = ENA_ADMIN_SQ_DIRECTION_TX;
1014 else
1015 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1016
1017 create_cmd.sq_identity |= (direction <<
1018 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1019 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1020
1021 create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1022 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1023
1024 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1025 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1026 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1027
1028 create_cmd.sq_caps_3 |=
1029 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1030
1031 create_cmd.cq_idx = cq_idx;
1032 create_cmd.sq_depth = io_sq->q_depth;
1033
1034 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1035 ret = ena_com_mem_addr_set(ena_dev,
1036 &create_cmd.sq_ba,
1037 io_sq->desc_addr.phys_addr);
1038 if (unlikely(ret)) {
1039 ena_trc_err("memory address set failed\n");
1040 return ret;
1041 }
1042 }
1043
1044 ret = ena_com_execute_admin_command(
1045 admin_queue,
1046 (struct ena_admin_aq_entry *)&create_cmd,
1047 sizeof(create_cmd),
1048 (struct ena_admin_acq_entry *)&cmd_completion,
1049 sizeof(cmd_completion));
1050 if (unlikely(ret)) {
1051 ena_trc_err("Failed to create IO SQ. error: %d\n", ret);
1052 return ret;
1053 }
1054
1055 io_sq->idx = cmd_completion.sq_idx;
1056
1057 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1058 (uintptr_t)cmd_completion.sq_doorbell_offset);
1059
1060 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1061 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1062 + cmd_completion.llq_headers_offset);
1063
1064 io_sq->desc_addr.pbuf_dev_addr =
1065 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1066 cmd_completion.llq_descriptors_offset);
1067 }
1068
1069 ena_trc_dbg("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1070
1071 return ret;
1072 }
1073
1074 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1075 {
1076 struct ena_rss *rss = &ena_dev->rss;
1077 struct ena_com_io_sq *io_sq;
1078 u16 qid;
1079 int i;
1080
1081 for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1082 qid = rss->host_rss_ind_tbl[i];
1083 if (qid >= ENA_TOTAL_NUM_QUEUES)
1084 return ENA_COM_INVAL;
1085
1086 io_sq = &ena_dev->io_sq_queues[qid];
1087
1088 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1089 return ENA_COM_INVAL;
1090
1091 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1092 }
1093
1094 return 0;
1095 }
1096
1097 static int ena_com_ind_tbl_convert_from_device(struct ena_com_dev *ena_dev)
1098 {
1099 u16 dev_idx_to_host_tbl[ENA_TOTAL_NUM_QUEUES] = { (u16)-1 };
1100 struct ena_rss *rss = &ena_dev->rss;
1101 u8 idx;
1102 u16 i;
1103
1104 for (i = 0; i < ENA_TOTAL_NUM_QUEUES; i++)
1105 dev_idx_to_host_tbl[ena_dev->io_sq_queues[i].idx] = i;
1106
1107 for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1108 if (rss->rss_ind_tbl[i].cq_idx > ENA_TOTAL_NUM_QUEUES)
1109 return ENA_COM_INVAL;
1110 idx = (u8)rss->rss_ind_tbl[i].cq_idx;
1111
1112 if (dev_idx_to_host_tbl[idx] > ENA_TOTAL_NUM_QUEUES)
1113 return ENA_COM_INVAL;
1114
1115 rss->host_rss_ind_tbl[i] = dev_idx_to_host_tbl[idx];
1116 }
1117
1118 return 0;
1119 }
1120
1121 static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev)
1122 {
1123 size_t size;
1124
1125 size = sizeof(struct ena_intr_moder_entry) * ENA_INTR_MAX_NUM_OF_LEVELS;
1126
1127 ena_dev->intr_moder_tbl = ENA_MEM_ALLOC(ena_dev->dmadev, size);
1128 if (!ena_dev->intr_moder_tbl)
1129 return ENA_COM_NO_MEM;
1130
1131 ena_com_config_default_interrupt_moderation_table(ena_dev);
1132
1133 return 0;
1134 }
1135
1136 static void
1137 ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1138 u16 intr_delay_resolution)
1139 {
1140 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
1141 unsigned int i;
1142
1143 if (!intr_delay_resolution) {
1144 ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1145 intr_delay_resolution = 1;
1146 }
1147 ena_dev->intr_delay_resolution = intr_delay_resolution;
1148
1149 /* update Rx */
1150 for (i = 0; i < ENA_INTR_MAX_NUM_OF_LEVELS; i++)
1151 intr_moder_tbl[i].intr_moder_interval /= intr_delay_resolution;
1152
1153 /* update Tx */
1154 ena_dev->intr_moder_tx_interval /= intr_delay_resolution;
1155 }
1156
1157 /*****************************************************************************/
1158 /******************************* API ******************************/
1159 /*****************************************************************************/
1160
1161 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1162 struct ena_admin_aq_entry *cmd,
1163 size_t cmd_size,
1164 struct ena_admin_acq_entry *comp,
1165 size_t comp_size)
1166 {
1167 struct ena_comp_ctx *comp_ctx;
1168 int ret = 0;
1169
1170 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1171 comp, comp_size);
1172 if (unlikely(IS_ERR(comp_ctx))) {
1173 ena_trc_err("Failed to submit command [%ld]\n",
1174 PTR_ERR(comp_ctx));
1175 return PTR_ERR(comp_ctx);
1176 }
1177
1178 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1179 if (unlikely(ret)) {
1180 if (admin_queue->running_state)
1181 ena_trc_err("Failed to process command. ret = %d\n",
1182 ret);
1183 else
1184 ena_trc_dbg("Failed to process command. ret = %d\n",
1185 ret);
1186 }
1187 return ret;
1188 }
1189
1190 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1191 struct ena_com_io_cq *io_cq)
1192 {
1193 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1194 struct ena_admin_aq_create_cq_cmd create_cmd;
1195 struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1196 int ret;
1197
1198 memset(&create_cmd, 0x0, sizeof(struct ena_admin_aq_create_cq_cmd));
1199
1200 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1201
1202 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1203 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1204 create_cmd.cq_caps_1 |=
1205 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1206
1207 create_cmd.msix_vector = io_cq->msix_vector;
1208 create_cmd.cq_depth = io_cq->q_depth;
1209
1210 ret = ena_com_mem_addr_set(ena_dev,
1211 &create_cmd.cq_ba,
1212 io_cq->cdesc_addr.phys_addr);
1213 if (unlikely(ret)) {
1214 ena_trc_err("memory address set failed\n");
1215 return ret;
1216 }
1217
1218 ret = ena_com_execute_admin_command(
1219 admin_queue,
1220 (struct ena_admin_aq_entry *)&create_cmd,
1221 sizeof(create_cmd),
1222 (struct ena_admin_acq_entry *)&cmd_completion,
1223 sizeof(cmd_completion));
1224 if (unlikely(ret)) {
1225 ena_trc_err("Failed to create IO CQ. error: %d\n", ret);
1226 return ret;
1227 }
1228
1229 io_cq->idx = cmd_completion.cq_idx;
1230
1231 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1232 cmd_completion.cq_interrupt_unmask_register_offset);
1233
1234 if (cmd_completion.cq_head_db_register_offset)
1235 io_cq->cq_head_db_reg =
1236 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1237 cmd_completion.cq_head_db_register_offset);
1238
1239 if (cmd_completion.numa_node_register_offset)
1240 io_cq->numa_node_cfg_reg =
1241 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1242 cmd_completion.numa_node_register_offset);
1243
1244 ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1245
1246 return ret;
1247 }
1248
1249 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1250 struct ena_com_io_sq **io_sq,
1251 struct ena_com_io_cq **io_cq)
1252 {
1253 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1254 ena_trc_err("Invalid queue number %d but the max is %d\n",
1255 qid, ENA_TOTAL_NUM_QUEUES);
1256 return ENA_COM_INVAL;
1257 }
1258
1259 *io_sq = &ena_dev->io_sq_queues[qid];
1260 *io_cq = &ena_dev->io_cq_queues[qid];
1261
1262 return 0;
1263 }
1264
1265 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1266 {
1267 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1268 struct ena_comp_ctx *comp_ctx;
1269 u16 i;
1270
1271 if (!admin_queue->comp_ctx)
1272 return;
1273
1274 for (i = 0; i < admin_queue->q_depth; i++) {
1275 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1276 if (unlikely(!comp_ctx))
1277 break;
1278
1279 comp_ctx->status = ENA_CMD_ABORTED;
1280
1281 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
1282 }
1283 }
1284
1285 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1286 {
1287 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1288 unsigned long flags = 0;
1289
1290 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1291 while (ATOMIC32_READ(&admin_queue->outstanding_cmds) != 0) {
1292 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1293 ENA_MSLEEP(20);
1294 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1295 }
1296 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1297 }
1298
1299 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1300 struct ena_com_io_cq *io_cq)
1301 {
1302 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1303 struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1304 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1305 int ret;
1306
1307 memset(&destroy_cmd, 0x0, sizeof(struct ena_admin_aq_destroy_sq_cmd));
1308
1309 destroy_cmd.cq_idx = io_cq->idx;
1310 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1311
1312 ret = ena_com_execute_admin_command(
1313 admin_queue,
1314 (struct ena_admin_aq_entry *)&destroy_cmd,
1315 sizeof(destroy_cmd),
1316 (struct ena_admin_acq_entry *)&destroy_resp,
1317 sizeof(destroy_resp));
1318
1319 if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
1320 ena_trc_err("Failed to destroy IO CQ. error: %d\n", ret);
1321
1322 return ret;
1323 }
1324
1325 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1326 {
1327 return ena_dev->admin_queue.running_state;
1328 }
1329
1330 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1331 {
1332 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1333 unsigned long flags = 0;
1334
1335 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1336 ena_dev->admin_queue.running_state = state;
1337 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1338 }
1339
1340 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1341 {
1342 u16 depth = ena_dev->aenq.q_depth;
1343
1344 ENA_ASSERT(ena_dev->aenq.head == depth, "Invalid AENQ state\n");
1345
1346 /* Init head_db to mark that all entries in the queue
1347 * are initially available
1348 */
1349 ENA_REG_WRITE32(depth, (unsigned char *)ena_dev->reg_bar
1350 + ENA_REGS_AENQ_HEAD_DB_OFF);
1351 }
1352
1353 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1354 {
1355 struct ena_com_admin_queue *admin_queue;
1356 struct ena_admin_set_feat_cmd cmd;
1357 struct ena_admin_set_feat_resp resp;
1358 struct ena_admin_get_feat_resp get_resp;
1359 int ret = 0;
1360
1361 if (unlikely(!ena_dev)) {
1362 ena_trc_err("%s : ena_dev is NULL\n", __func__);
1363 return ENA_COM_NO_DEVICE;
1364 }
1365
1366 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG);
1367 if (ret) {
1368 ena_trc_info("Can't get aenq configuration\n");
1369 return ret;
1370 }
1371
1372 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1373 ena_trc_warn("Trying to set unsupported aenq events. supported flag: %x asked flag: %x\n",
1374 get_resp.u.aenq.supported_groups,
1375 groups_flag);
1376 return ENA_COM_PERMISSION;
1377 }
1378
1379 memset(&cmd, 0x0, sizeof(cmd));
1380 admin_queue = &ena_dev->admin_queue;
1381
1382 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1383 cmd.aq_common_descriptor.flags = 0;
1384 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1385 cmd.u.aenq.enabled_groups = groups_flag;
1386
1387 ret = ena_com_execute_admin_command(admin_queue,
1388 (struct ena_admin_aq_entry *)&cmd,
1389 sizeof(cmd),
1390 (struct ena_admin_acq_entry *)&resp,
1391 sizeof(resp));
1392
1393 if (unlikely(ret))
1394 ena_trc_err("Failed to config AENQ ret: %d\n", ret);
1395
1396 return ret;
1397 }
1398
1399 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1400 {
1401 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1402 int width;
1403
1404 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1405 ena_trc_err("Reg read timeout occurred\n");
1406 return ENA_COM_TIMER_EXPIRED;
1407 }
1408
1409 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1410 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1411
1412 ena_trc_dbg("ENA dma width: %d\n", width);
1413
1414 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1415 ena_trc_err("DMA width illegal value: %d\n", width);
1416 return ENA_COM_INVAL;
1417 }
1418
1419 ena_dev->dma_addr_bits = width;
1420
1421 return width;
1422 }
1423
1424 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1425 {
1426 u32 ver;
1427 u32 ctrl_ver;
1428 u32 ctrl_ver_masked;
1429
1430 /* Make sure the ENA version and the controller version are at least
1431 * as the driver expects
1432 */
1433 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1434 ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1435 ENA_REGS_CONTROLLER_VERSION_OFF);
1436
1437 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1438 (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1439 ena_trc_err("Reg read timeout occurred\n");
1440 return ENA_COM_TIMER_EXPIRED;
1441 }
1442
1443 ena_trc_info("ena device version: %d.%d\n",
1444 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1445 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1446 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1447
1448 if (ver < MIN_ENA_VER) {
1449 ena_trc_err("ENA version is lower than the minimal version the driver supports\n");
1450 return -1;
1451 }
1452
1453 ena_trc_info("ena controller version: %d.%d.%d implementation version %d\n",
1454 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK)
1455 >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1456 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK)
1457 >> ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1458 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1459 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1460 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1461
1462 ctrl_ver_masked =
1463 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1464 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1465 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1466
1467 /* Validate the ctrl version without the implementation ID */
1468 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1469 ena_trc_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1470 return -1;
1471 }
1472
1473 return 0;
1474 }
1475
1476 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1477 {
1478 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1479
1480 if (!admin_queue)
1481 return;
1482
1483 if (admin_queue->comp_ctx)
1484 ENA_MEM_FREE(ena_dev->dmadev, admin_queue->comp_ctx);
1485 admin_queue->comp_ctx = NULL;
1486
1487 if (admin_queue->sq.entries)
1488 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1489 ADMIN_SQ_SIZE(admin_queue->q_depth),
1490 admin_queue->sq.entries,
1491 admin_queue->sq.dma_addr,
1492 admin_queue->sq.mem_handle);
1493 admin_queue->sq.entries = NULL;
1494
1495 if (admin_queue->cq.entries)
1496 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1497 ADMIN_CQ_SIZE(admin_queue->q_depth),
1498 admin_queue->cq.entries,
1499 admin_queue->cq.dma_addr,
1500 admin_queue->cq.mem_handle);
1501 admin_queue->cq.entries = NULL;
1502
1503 if (ena_dev->aenq.entries)
1504 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1505 ADMIN_AENQ_SIZE(ena_dev->aenq.q_depth),
1506 ena_dev->aenq.entries,
1507 ena_dev->aenq.dma_addr,
1508 ena_dev->aenq.mem_handle);
1509 ena_dev->aenq.entries = NULL;
1510 }
1511
1512 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1513 {
1514 ena_dev->admin_queue.polling = polling;
1515 }
1516
1517 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1518 {
1519 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1520
1521 ENA_SPINLOCK_INIT(mmio_read->lock);
1522 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1523 sizeof(*mmio_read->read_resp),
1524 mmio_read->read_resp,
1525 mmio_read->read_resp_dma_addr,
1526 mmio_read->read_resp_mem_handle);
1527 if (unlikely(!mmio_read->read_resp))
1528 return ENA_COM_NO_MEM;
1529
1530 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1531
1532 mmio_read->read_resp->req_id = 0x0;
1533 mmio_read->seq_num = 0x0;
1534 mmio_read->readless_supported = true;
1535
1536 return 0;
1537 }
1538
1539 void
1540 ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1541 {
1542 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1543
1544 mmio_read->readless_supported = readless_supported;
1545 }
1546
1547 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1548 {
1549 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1550
1551 ENA_REG_WRITE32(0x0, (unsigned char *)ena_dev->reg_bar
1552 + ENA_REGS_MMIO_RESP_LO_OFF);
1553 ENA_REG_WRITE32(0x0, (unsigned char *)ena_dev->reg_bar
1554 + ENA_REGS_MMIO_RESP_HI_OFF);
1555
1556 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1557 sizeof(*mmio_read->read_resp),
1558 mmio_read->read_resp,
1559 mmio_read->read_resp_dma_addr,
1560 mmio_read->read_resp_mem_handle);
1561
1562 mmio_read->read_resp = NULL;
1563 }
1564
1565 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1566 {
1567 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1568 u32 addr_low, addr_high;
1569
1570 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1571 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1572
1573 ENA_REG_WRITE32(addr_low, (unsigned char *)ena_dev->reg_bar
1574 + ENA_REGS_MMIO_RESP_LO_OFF);
1575 ENA_REG_WRITE32(addr_high, (unsigned char *)ena_dev->reg_bar
1576 + ENA_REGS_MMIO_RESP_HI_OFF);
1577 }
1578
1579 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1580 struct ena_aenq_handlers *aenq_handlers,
1581 bool init_spinlock)
1582 {
1583 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1584 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1585 int ret;
1586
1587 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1588
1589 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1590 ena_trc_err("Reg read timeout occurred\n");
1591 return ENA_COM_TIMER_EXPIRED;
1592 }
1593
1594 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1595 ena_trc_err("Device isn't ready, abort com init\n");
1596 return ENA_COM_NO_DEVICE;
1597 }
1598
1599 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1600
1601 admin_queue->q_dmadev = ena_dev->dmadev;
1602 admin_queue->polling = false;
1603 admin_queue->curr_cmd_id = 0;
1604
1605 ATOMIC32_SET(&admin_queue->outstanding_cmds, 0);
1606
1607 if (init_spinlock)
1608 ENA_SPINLOCK_INIT(admin_queue->q_lock);
1609
1610 ret = ena_com_init_comp_ctxt(admin_queue);
1611 if (ret)
1612 goto error;
1613
1614 ret = ena_com_admin_init_sq(admin_queue);
1615 if (ret)
1616 goto error;
1617
1618 ret = ena_com_admin_init_cq(admin_queue);
1619 if (ret)
1620 goto error;
1621
1622 admin_queue->sq.db_addr = (u32 __iomem *)
1623 ((unsigned char *)ena_dev->reg_bar + ENA_REGS_AQ_DB_OFF);
1624
1625 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1626 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1627
1628 ENA_REG_WRITE32(addr_low, (unsigned char *)ena_dev->reg_bar
1629 + ENA_REGS_AQ_BASE_LO_OFF);
1630 ENA_REG_WRITE32(addr_high, (unsigned char *)ena_dev->reg_bar
1631 + ENA_REGS_AQ_BASE_HI_OFF);
1632
1633 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1634 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1635
1636 ENA_REG_WRITE32(addr_low, (unsigned char *)ena_dev->reg_bar
1637 + ENA_REGS_ACQ_BASE_LO_OFF);
1638 ENA_REG_WRITE32(addr_high, (unsigned char *)ena_dev->reg_bar
1639 + ENA_REGS_ACQ_BASE_HI_OFF);
1640
1641 aq_caps = 0;
1642 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1643 aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1644 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1645 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1646
1647 acq_caps = 0;
1648 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1649 acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1650 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1651 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1652
1653 ENA_REG_WRITE32(aq_caps, (unsigned char *)ena_dev->reg_bar
1654 + ENA_REGS_AQ_CAPS_OFF);
1655 ENA_REG_WRITE32(acq_caps, (unsigned char *)ena_dev->reg_bar
1656 + ENA_REGS_ACQ_CAPS_OFF);
1657 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1658 if (ret)
1659 goto error;
1660
1661 admin_queue->running_state = true;
1662
1663 return 0;
1664 error:
1665 ena_com_admin_destroy(ena_dev);
1666
1667 return ret;
1668 }
1669
1670 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1671 struct ena_com_create_io_ctx *ctx)
1672 {
1673 struct ena_com_io_sq *io_sq;
1674 struct ena_com_io_cq *io_cq;
1675 int ret = 0;
1676
1677 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1678 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1679 ctx->qid, ENA_TOTAL_NUM_QUEUES);
1680 return ENA_COM_INVAL;
1681 }
1682
1683 io_sq = &ena_dev->io_sq_queues[ctx->qid];
1684 io_cq = &ena_dev->io_cq_queues[ctx->qid];
1685
1686 memset(io_sq, 0x0, sizeof(struct ena_com_io_sq));
1687 memset(io_cq, 0x0, sizeof(struct ena_com_io_cq));
1688
1689 /* Init CQ */
1690 io_cq->q_depth = ctx->queue_size;
1691 io_cq->direction = ctx->direction;
1692 io_cq->qid = ctx->qid;
1693
1694 io_cq->msix_vector = ctx->msix_vector;
1695
1696 io_sq->q_depth = ctx->queue_size;
1697 io_sq->direction = ctx->direction;
1698 io_sq->qid = ctx->qid;
1699
1700 io_sq->mem_queue_type = ctx->mem_queue_type;
1701
1702 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1703 /* header length is limited to 8 bits */
1704 io_sq->tx_max_header_size =
1705 ENA_MIN32(ena_dev->tx_max_header_size, SZ_256);
1706
1707 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1708 if (ret)
1709 goto error;
1710 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1711 if (ret)
1712 goto error;
1713
1714 ret = ena_com_create_io_cq(ena_dev, io_cq);
1715 if (ret)
1716 goto error;
1717
1718 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1719 if (ret)
1720 goto destroy_io_cq;
1721
1722 return 0;
1723
1724 destroy_io_cq:
1725 ena_com_destroy_io_cq(ena_dev, io_cq);
1726 error:
1727 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1728 return ret;
1729 }
1730
1731 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1732 {
1733 struct ena_com_io_sq *io_sq;
1734 struct ena_com_io_cq *io_cq;
1735
1736 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1737 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1738 qid, ENA_TOTAL_NUM_QUEUES);
1739 return;
1740 }
1741
1742 io_sq = &ena_dev->io_sq_queues[qid];
1743 io_cq = &ena_dev->io_cq_queues[qid];
1744
1745 ena_com_destroy_io_sq(ena_dev, io_sq);
1746 ena_com_destroy_io_cq(ena_dev, io_cq);
1747
1748 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1749 }
1750
1751 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1752 struct ena_admin_get_feat_resp *resp)
1753 {
1754 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG);
1755 }
1756
1757 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1758 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1759 {
1760 struct ena_admin_get_feat_resp get_resp;
1761 int rc;
1762
1763 rc = ena_com_get_feature(ena_dev, &get_resp,
1764 ENA_ADMIN_DEVICE_ATTRIBUTES);
1765 if (rc)
1766 return rc;
1767
1768 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1769 sizeof(get_resp.u.dev_attr));
1770 ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1771
1772 rc = ena_com_get_feature(ena_dev, &get_resp,
1773 ENA_ADMIN_MAX_QUEUES_NUM);
1774 if (rc)
1775 return rc;
1776
1777 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1778 sizeof(get_resp.u.max_queue));
1779 ena_dev->tx_max_header_size = get_resp.u.max_queue.max_header_size;
1780
1781 rc = ena_com_get_feature(ena_dev, &get_resp,
1782 ENA_ADMIN_AENQ_CONFIG);
1783 if (rc)
1784 return rc;
1785
1786 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1787 sizeof(get_resp.u.aenq));
1788
1789 rc = ena_com_get_feature(ena_dev, &get_resp,
1790 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);
1791 if (rc)
1792 return rc;
1793
1794 memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
1795 sizeof(get_resp.u.offload));
1796
1797 return 0;
1798 }
1799
1800 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
1801 {
1802 ena_com_handle_admin_completion(&ena_dev->admin_queue);
1803 }
1804
1805 /* ena_handle_specific_aenq_event:
1806 * return the handler that is relevant to the specific event group
1807 */
1808 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
1809 u16 group)
1810 {
1811 struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
1812
1813 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
1814 return aenq_handlers->handlers[group];
1815
1816 return aenq_handlers->unimplemented_handler;
1817 }
1818
1819 /* ena_aenq_intr_handler:
1820 * handles the aenq incoming events.
1821 * pop events from the queue and apply the specific handler
1822 */
1823 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
1824 {
1825 struct ena_admin_aenq_entry *aenq_e;
1826 struct ena_admin_aenq_common_desc *aenq_common;
1827 struct ena_com_aenq *aenq = &dev->aenq;
1828 ena_aenq_handler handler_cb;
1829 u16 masked_head, processed = 0;
1830 u8 phase;
1831
1832 masked_head = aenq->head & (aenq->q_depth - 1);
1833 phase = aenq->phase;
1834 aenq_e = &aenq->entries[masked_head]; /* Get first entry */
1835 aenq_common = &aenq_e->aenq_common_desc;
1836
1837 /* Go over all the events */
1838 while ((aenq_common->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) ==
1839 phase) {
1840 ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n",
1841 aenq_common->group,
1842 aenq_common->syndrom,
1843 (unsigned long long)aenq_common->timestamp_low +
1844 ((u64)aenq_common->timestamp_high << 32));
1845
1846 /* Handle specific event*/
1847 handler_cb = ena_com_get_specific_aenq_cb(dev,
1848 aenq_common->group);
1849 handler_cb(data, aenq_e); /* call the actual event handler*/
1850
1851 /* Get next event entry */
1852 masked_head++;
1853 processed++;
1854
1855 if (unlikely(masked_head == aenq->q_depth)) {
1856 masked_head = 0;
1857 phase = !phase;
1858 }
1859 aenq_e = &aenq->entries[masked_head];
1860 aenq_common = &aenq_e->aenq_common_desc;
1861 }
1862
1863 aenq->head += processed;
1864 aenq->phase = phase;
1865
1866 /* Don't update aenq doorbell if there weren't any processed events */
1867 if (!processed)
1868 return;
1869
1870 /* write the aenq doorbell after all AENQ descriptors were read */
1871 mb();
1872 ENA_REG_WRITE32((u32)aenq->head, (unsigned char *)dev->reg_bar
1873 + ENA_REGS_AENQ_HEAD_DB_OFF);
1874 }
1875
1876 int ena_com_dev_reset(struct ena_com_dev *ena_dev)
1877 {
1878 u32 stat, timeout, cap, reset_val;
1879 int rc;
1880
1881 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1882 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1883
1884 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
1885 (cap == ENA_MMIO_READ_TIMEOUT))) {
1886 ena_trc_err("Reg read32 timeout occurred\n");
1887 return ENA_COM_TIMER_EXPIRED;
1888 }
1889
1890 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
1891 ena_trc_err("Device isn't ready, can't reset device\n");
1892 return ENA_COM_INVAL;
1893 }
1894
1895 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
1896 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
1897 if (timeout == 0) {
1898 ena_trc_err("Invalid timeout value\n");
1899 return ENA_COM_INVAL;
1900 }
1901
1902 /* start reset */
1903 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
1904 ENA_REG_WRITE32(reset_val, (unsigned char *)ena_dev->reg_bar
1905 + ENA_REGS_DEV_CTL_OFF);
1906
1907 /* Write again the MMIO read request address */
1908 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1909
1910 rc = wait_for_reset_state(ena_dev, timeout,
1911 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
1912 if (rc != 0) {
1913 ena_trc_err("Reset indication didn't turn on\n");
1914 return rc;
1915 }
1916
1917 /* reset done */
1918 ENA_REG_WRITE32(0, (unsigned char *)ena_dev->reg_bar
1919 + ENA_REGS_DEV_CTL_OFF);
1920 rc = wait_for_reset_state(ena_dev, timeout, 0);
1921 if (rc != 0) {
1922 ena_trc_err("Reset indication didn't turn off\n");
1923 return rc;
1924 }
1925
1926 return 0;
1927 }
1928
1929 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
1930 struct ena_admin_aq_get_stats_cmd *get_cmd,
1931 struct ena_admin_acq_get_stats_resp *get_resp,
1932 enum ena_admin_get_stats_type type)
1933 {
1934 struct ena_com_admin_queue *admin_queue;
1935 int ret = 0;
1936
1937 if (!ena_dev) {
1938 ena_trc_err("%s : ena_dev is NULL\n", __func__);
1939 return ENA_COM_NO_DEVICE;
1940 }
1941
1942 admin_queue = &ena_dev->admin_queue;
1943
1944 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
1945 get_cmd->aq_common_descriptor.flags = 0;
1946 get_cmd->type = type;
1947
1948 ret = ena_com_execute_admin_command(
1949 admin_queue,
1950 (struct ena_admin_aq_entry *)get_cmd,
1951 sizeof(*get_cmd),
1952 (struct ena_admin_acq_entry *)get_resp,
1953 sizeof(*get_resp));
1954
1955 if (unlikely(ret))
1956 ena_trc_err("Failed to get stats. error: %d\n", ret);
1957
1958 return ret;
1959 }
1960
1961 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
1962 struct ena_admin_basic_stats *stats)
1963 {
1964 int ret = 0;
1965 struct ena_admin_aq_get_stats_cmd get_cmd;
1966 struct ena_admin_acq_get_stats_resp get_resp;
1967
1968 memset(&get_cmd, 0x0, sizeof(get_cmd));
1969 ret = ena_get_dev_stats(ena_dev, &get_cmd, &get_resp,
1970 ENA_ADMIN_GET_STATS_TYPE_BASIC);
1971 if (likely(ret == 0))
1972 memcpy(stats, &get_resp.basic_stats,
1973 sizeof(get_resp.basic_stats));
1974
1975 return ret;
1976 }
1977
1978 int ena_com_get_dev_extended_stats(struct ena_com_dev *ena_dev, char *buff,
1979 u32 len)
1980 {
1981 int ret = 0;
1982 struct ena_admin_aq_get_stats_cmd get_cmd;
1983 struct ena_admin_acq_get_stats_resp get_resp;
1984 ena_mem_handle_t mem_handle = 0;
1985 void *virt_addr;
1986 dma_addr_t phys_addr;
1987
1988 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, len,
1989 virt_addr, phys_addr, mem_handle);
1990 if (!virt_addr) {
1991 ret = ENA_COM_NO_MEM;
1992 goto done;
1993 }
1994 memset(&get_cmd, 0x0, sizeof(get_cmd));
1995 ret = ena_com_mem_addr_set(ena_dev,
1996 &get_cmd.u.control_buffer.address,
1997 phys_addr);
1998 if (unlikely(ret)) {
1999 ena_trc_err("memory address set failed\n");
2000 return ret;
2001 }
2002 get_cmd.u.control_buffer.length = len;
2003
2004 get_cmd.device_id = ena_dev->stats_func;
2005 get_cmd.queue_idx = ena_dev->stats_queue;
2006
2007 ret = ena_get_dev_stats(ena_dev, &get_cmd, &get_resp,
2008 ENA_ADMIN_GET_STATS_TYPE_EXTENDED);
2009 if (ret < 0)
2010 goto free_ext_stats_mem;
2011
2012 ret = snprintf(buff, len, "%s", (char *)virt_addr);
2013
2014 free_ext_stats_mem:
2015 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, len, virt_addr, phys_addr,
2016 mem_handle);
2017 done:
2018 return ret;
2019 }
2020
2021 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
2022 {
2023 struct ena_com_admin_queue *admin_queue;
2024 struct ena_admin_set_feat_cmd cmd;
2025 struct ena_admin_set_feat_resp resp;
2026 int ret = 0;
2027
2028 if (unlikely(!ena_dev)) {
2029 ena_trc_err("%s : ena_dev is NULL\n", __func__);
2030 return ENA_COM_NO_DEVICE;
2031 }
2032
2033 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2034 ena_trc_info("Feature %d isn't supported\n", ENA_ADMIN_MTU);
2035 return ENA_COM_PERMISSION;
2036 }
2037
2038 memset(&cmd, 0x0, sizeof(cmd));
2039 admin_queue = &ena_dev->admin_queue;
2040
2041 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2042 cmd.aq_common_descriptor.flags = 0;
2043 cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2044 cmd.u.mtu.mtu = mtu;
2045
2046 ret = ena_com_execute_admin_command(admin_queue,
2047 (struct ena_admin_aq_entry *)&cmd,
2048 sizeof(cmd),
2049 (struct ena_admin_acq_entry *)&resp,
2050 sizeof(resp));
2051
2052 if (unlikely(ret)) {
2053 ena_trc_err("Failed to set mtu %d. error: %d\n", mtu, ret);
2054 return ENA_COM_INVAL;
2055 }
2056 return 0;
2057 }
2058
2059 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
2060 struct ena_admin_feature_offload_desc *offload)
2061 {
2062 int ret;
2063 struct ena_admin_get_feat_resp resp;
2064
2065 ret = ena_com_get_feature(ena_dev, &resp,
2066 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);
2067 if (unlikely(ret)) {
2068 ena_trc_err("Failed to get offload capabilities %d\n", ret);
2069 return ENA_COM_INVAL;
2070 }
2071
2072 memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
2073
2074 return 0;
2075 }
2076
2077 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2078 {
2079 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2080 struct ena_rss *rss = &ena_dev->rss;
2081 struct ena_admin_set_feat_cmd cmd;
2082 struct ena_admin_set_feat_resp resp;
2083 struct ena_admin_get_feat_resp get_resp;
2084 int ret;
2085
2086 if (!ena_com_check_supported_feature_id(ena_dev,
2087 ENA_ADMIN_RSS_HASH_FUNCTION)) {
2088 ena_trc_info("Feature %d isn't supported\n",
2089 ENA_ADMIN_RSS_HASH_FUNCTION);
2090 return ENA_COM_PERMISSION;
2091 }
2092
2093 /* Validate hash function is supported */
2094 ret = ena_com_get_feature(ena_dev, &get_resp,
2095 ENA_ADMIN_RSS_HASH_FUNCTION);
2096 if (unlikely(ret))
2097 return ret;
2098
2099 if (get_resp.u.flow_hash_func.supported_func & (1 << rss->hash_func)) {
2100 ena_trc_err("Func hash %d isn't supported by device, abort\n",
2101 rss->hash_func);
2102 return ENA_COM_PERMISSION;
2103 }
2104
2105 memset(&cmd, 0x0, sizeof(cmd));
2106
2107 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2108 cmd.aq_common_descriptor.flags =
2109 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2110 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2111 cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2112 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2113
2114 ret = ena_com_mem_addr_set(ena_dev,
2115 &cmd.control_buffer.address,
2116 rss->hash_key_dma_addr);
2117 if (unlikely(ret)) {
2118 ena_trc_err("memory address set failed\n");
2119 return ret;
2120 }
2121
2122 cmd.control_buffer.length = sizeof(*rss->hash_key);
2123
2124 ret = ena_com_execute_admin_command(admin_queue,
2125 (struct ena_admin_aq_entry *)&cmd,
2126 sizeof(cmd),
2127 (struct ena_admin_acq_entry *)&resp,
2128 sizeof(resp));
2129 if (unlikely(ret)) {
2130 ena_trc_err("Failed to set hash function %d. error: %d\n",
2131 rss->hash_func, ret);
2132 return ENA_COM_INVAL;
2133 }
2134
2135 return 0;
2136 }
2137
2138 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2139 enum ena_admin_hash_functions func,
2140 const u8 *key, u16 key_len, u32 init_val)
2141 {
2142 struct ena_rss *rss = &ena_dev->rss;
2143 struct ena_admin_get_feat_resp get_resp;
2144 struct ena_admin_feature_rss_flow_hash_control *hash_key =
2145 rss->hash_key;
2146 int rc;
2147
2148 /* Make sure size is a mult of DWs */
2149 if (unlikely(key_len & 0x3))
2150 return ENA_COM_INVAL;
2151
2152 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2153 ENA_ADMIN_RSS_HASH_FUNCTION,
2154 rss->hash_key_dma_addr,
2155 sizeof(*rss->hash_key));
2156 if (unlikely(rc))
2157 return rc;
2158
2159 if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) {
2160 ena_trc_err("Flow hash function %d isn't supported\n", func);
2161 return ENA_COM_PERMISSION;
2162 }
2163
2164 switch (func) {
2165 case ENA_ADMIN_TOEPLITZ:
2166 if (key_len > sizeof(hash_key->key)) {
2167 ena_trc_err("key len (%hu) is bigger than the max supported (%zu)\n",
2168 key_len, sizeof(hash_key->key));
2169 return ENA_COM_INVAL;
2170 }
2171
2172 memcpy(hash_key->key, key, key_len);
2173 rss->hash_init_val = init_val;
2174 hash_key->keys_num = key_len >> 2;
2175 break;
2176 case ENA_ADMIN_CRC32:
2177 rss->hash_init_val = init_val;
2178 break;
2179 default:
2180 ena_trc_err("Invalid hash function (%d)\n", func);
2181 return ENA_COM_INVAL;
2182 }
2183
2184 rc = ena_com_set_hash_function(ena_dev);
2185
2186 /* Restore the old function */
2187 if (unlikely(rc))
2188 ena_com_get_hash_function(ena_dev, NULL, NULL);
2189
2190 return rc;
2191 }
2192
2193 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2194 enum ena_admin_hash_functions *func,
2195 u8 *key)
2196 {
2197 struct ena_rss *rss = &ena_dev->rss;
2198 struct ena_admin_get_feat_resp get_resp;
2199 struct ena_admin_feature_rss_flow_hash_control *hash_key =
2200 rss->hash_key;
2201 int rc;
2202
2203 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2204 ENA_ADMIN_RSS_HASH_FUNCTION,
2205 rss->hash_key_dma_addr,
2206 sizeof(*rss->hash_key));
2207 if (unlikely(rc))
2208 return rc;
2209
2210 rss->hash_func = (enum ena_admin_hash_functions)get_resp.u.flow_hash_func.selected_func;
2211 if (func)
2212 *func = rss->hash_func;
2213
2214 if (key)
2215 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2216
2217 return 0;
2218 }
2219
2220 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2221 enum ena_admin_flow_hash_proto proto,
2222 u16 *fields)
2223 {
2224 struct ena_rss *rss = &ena_dev->rss;
2225 struct ena_admin_get_feat_resp get_resp;
2226 int rc;
2227
2228 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2229 ENA_ADMIN_RSS_HASH_INPUT,
2230 rss->hash_ctrl_dma_addr,
2231 sizeof(*rss->hash_ctrl));
2232 if (unlikely(rc))
2233 return rc;
2234
2235 if (fields)
2236 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2237
2238 return 0;
2239 }
2240
2241 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2242 {
2243 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2244 struct ena_rss *rss = &ena_dev->rss;
2245 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2246 struct ena_admin_set_feat_cmd cmd;
2247 struct ena_admin_set_feat_resp resp;
2248 int ret;
2249
2250 if (!ena_com_check_supported_feature_id(ena_dev,
2251 ENA_ADMIN_RSS_HASH_INPUT)) {
2252 ena_trc_info("Feature %d isn't supported\n",
2253 ENA_ADMIN_RSS_HASH_INPUT);
2254 return ENA_COM_PERMISSION;
2255 }
2256
2257 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2258 cmd.aq_common_descriptor.flags =
2259 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2260 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2261 cmd.u.flow_hash_input.enabled_input_sort =
2262 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2263 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2264
2265 ret = ena_com_mem_addr_set(ena_dev,
2266 &cmd.control_buffer.address,
2267 rss->hash_ctrl_dma_addr);
2268 if (unlikely(ret)) {
2269 ena_trc_err("memory address set failed\n");
2270 return ret;
2271 }
2272 cmd.control_buffer.length = sizeof(*hash_ctrl);
2273
2274 ret = ena_com_execute_admin_command(admin_queue,
2275 (struct ena_admin_aq_entry *)&cmd,
2276 sizeof(cmd),
2277 (struct ena_admin_acq_entry *)&resp,
2278 sizeof(resp));
2279 if (unlikely(ret)) {
2280 ena_trc_err("Failed to set hash input. error: %d\n", ret);
2281 ret = ENA_COM_INVAL;
2282 }
2283
2284 return 0;
2285 }
2286
2287 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2288 {
2289 struct ena_rss *rss = &ena_dev->rss;
2290 struct ena_admin_feature_rss_hash_control *hash_ctrl =
2291 rss->hash_ctrl;
2292 u16 available_fields = 0;
2293 int rc, i;
2294
2295 /* Get the supported hash input */
2296 rc = ena_com_get_hash_ctrl(ena_dev, (enum ena_admin_flow_hash_proto)0, NULL);
2297 if (unlikely(rc))
2298 return rc;
2299
2300 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2301 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2302 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2303
2304 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2305 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2306 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2307
2308 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2309 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2310 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2311
2312 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2313 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2314 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2315
2316 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2317 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2318
2319 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2320 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2321
2322 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2323 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2324
2325 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2326 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2327
2328 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2329 available_fields = hash_ctrl->selected_fields[i].fields &
2330 hash_ctrl->supported_fields[i].fields;
2331 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2332 ena_trc_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2333 i, hash_ctrl->supported_fields[i].fields,
2334 hash_ctrl->selected_fields[i].fields);
2335 return ENA_COM_PERMISSION;
2336 }
2337 }
2338
2339 rc = ena_com_set_hash_ctrl(ena_dev);
2340
2341 /* In case of failure, restore the old hash ctrl */
2342 if (unlikely(rc))
2343 ena_com_get_hash_ctrl(ena_dev, (enum ena_admin_flow_hash_proto)0, NULL);
2344
2345 return rc;
2346 }
2347
2348 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2349 enum ena_admin_flow_hash_proto proto,
2350 u16 hash_fields)
2351 {
2352 struct ena_rss *rss = &ena_dev->rss;
2353 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2354 u16 supported_fields;
2355 int rc;
2356
2357 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2358 ena_trc_err("Invalid proto num (%u)\n", proto);
2359 return ENA_COM_INVAL;
2360 }
2361
2362 /* Get the ctrl table */
2363 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2364 if (unlikely(rc))
2365 return rc;
2366
2367 /* Make sure all the fields are supported */
2368 supported_fields = hash_ctrl->supported_fields[proto].fields;
2369 if ((hash_fields & supported_fields) != hash_fields) {
2370 ena_trc_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2371 proto, hash_fields, supported_fields);
2372 }
2373
2374 hash_ctrl->selected_fields[proto].fields = hash_fields;
2375
2376 rc = ena_com_set_hash_ctrl(ena_dev);
2377
2378 /* In case of failure, restore the old hash ctrl */
2379 if (unlikely(rc))
2380 ena_com_get_hash_ctrl(ena_dev, (enum ena_admin_flow_hash_proto)0, NULL);
2381
2382 return 0;
2383 }
2384
2385 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2386 u16 entry_idx, u16 entry_value)
2387 {
2388 struct ena_rss *rss = &ena_dev->rss;
2389
2390 if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2391 return ENA_COM_INVAL;
2392
2393 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2394 return ENA_COM_INVAL;
2395
2396 rss->host_rss_ind_tbl[entry_idx] = entry_value;
2397
2398 return 0;
2399 }
2400
2401 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2402 {
2403 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2404 struct ena_rss *rss = &ena_dev->rss;
2405 struct ena_admin_set_feat_cmd cmd;
2406 struct ena_admin_set_feat_resp resp;
2407 int ret = 0;
2408
2409 if (!ena_com_check_supported_feature_id(
2410 ena_dev,
2411 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2412 ena_trc_info("Feature %d isn't supported\n",
2413 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2414 return ENA_COM_PERMISSION;
2415 }
2416
2417 ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2418 if (ret) {
2419 ena_trc_err("Failed to convert host indirection table to device table\n");
2420 return ret;
2421 }
2422
2423 memset(&cmd, 0x0, sizeof(cmd));
2424
2425 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2426 cmd.aq_common_descriptor.flags =
2427 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2428 cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2429 cmd.u.ind_table.size = rss->tbl_log_size;
2430 cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2431
2432 ret = ena_com_mem_addr_set(ena_dev,
2433 &cmd.control_buffer.address,
2434 rss->rss_ind_tbl_dma_addr);
2435 if (unlikely(ret)) {
2436 ena_trc_err("memory address set failed\n");
2437 return ret;
2438 }
2439
2440 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2441 sizeof(struct ena_admin_rss_ind_table_entry);
2442
2443 ret = ena_com_execute_admin_command(admin_queue,
2444 (struct ena_admin_aq_entry *)&cmd,
2445 sizeof(cmd),
2446 (struct ena_admin_acq_entry *)&resp,
2447 sizeof(resp));
2448
2449 if (unlikely(ret)) {
2450 ena_trc_err("Failed to set indirect table. error: %d\n", ret);
2451 return ENA_COM_INVAL;
2452 }
2453
2454 return 0;
2455 }
2456
2457 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2458 {
2459 struct ena_rss *rss = &ena_dev->rss;
2460 struct ena_admin_get_feat_resp get_resp;
2461 u32 tbl_size;
2462 int i, rc;
2463
2464 tbl_size = (1ULL << rss->tbl_log_size) *
2465 sizeof(struct ena_admin_rss_ind_table_entry);
2466
2467 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2468 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2469 rss->rss_ind_tbl_dma_addr,
2470 tbl_size);
2471 if (unlikely(rc))
2472 return rc;
2473
2474 if (!ind_tbl)
2475 return 0;
2476
2477 rc = ena_com_ind_tbl_convert_from_device(ena_dev);
2478 if (unlikely(rc))
2479 return rc;
2480
2481 for (i = 0; i < (1 << rss->tbl_log_size); i++)
2482 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2483
2484 return 0;
2485 }
2486
2487 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2488 {
2489 int rc;
2490
2491 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2492
2493 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2494 if (unlikely(rc))
2495 goto err_indr_tbl;
2496
2497 rc = ena_com_hash_key_allocate(ena_dev);
2498 if (unlikely(rc))
2499 goto err_hash_key;
2500
2501 rc = ena_com_hash_ctrl_init(ena_dev);
2502 if (unlikely(rc))
2503 goto err_hash_ctrl;
2504
2505 return 0;
2506
2507 err_hash_ctrl:
2508 ena_com_hash_key_destroy(ena_dev);
2509 err_hash_key:
2510 ena_com_indirect_table_destroy(ena_dev);
2511 err_indr_tbl:
2512
2513 return rc;
2514 }
2515
2516 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2517 {
2518 ena_com_indirect_table_destroy(ena_dev);
2519 ena_com_hash_key_destroy(ena_dev);
2520 ena_com_hash_ctrl_destroy(ena_dev);
2521
2522 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2523 }
2524
2525 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2526 {
2527 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2528
2529 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2530 SZ_4K,
2531 host_attr->host_info,
2532 host_attr->host_info_dma_addr,
2533 host_attr->host_info_dma_handle);
2534 if (unlikely(!host_attr->host_info))
2535 return ENA_COM_NO_MEM;
2536
2537 return 0;
2538 }
2539
2540 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2541 u32 debug_area_size) {
2542 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2543
2544 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2545 debug_area_size,
2546 host_attr->debug_area_virt_addr,
2547 host_attr->debug_area_dma_addr,
2548 host_attr->debug_area_dma_handle);
2549 if (unlikely(!host_attr->debug_area_virt_addr)) {
2550 host_attr->debug_area_size = 0;
2551 return ENA_COM_NO_MEM;
2552 }
2553
2554 host_attr->debug_area_size = debug_area_size;
2555
2556 return 0;
2557 }
2558
2559 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2560 {
2561 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2562
2563 if (host_attr->host_info) {
2564 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2565 SZ_4K,
2566 host_attr->host_info,
2567 host_attr->host_info_dma_addr,
2568 host_attr->host_info_dma_handle);
2569 host_attr->host_info = NULL;
2570 }
2571 }
2572
2573 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2574 {
2575 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2576
2577 if (host_attr->debug_area_virt_addr) {
2578 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2579 host_attr->debug_area_size,
2580 host_attr->debug_area_virt_addr,
2581 host_attr->debug_area_dma_addr,
2582 host_attr->debug_area_dma_handle);
2583 host_attr->debug_area_virt_addr = NULL;
2584 }
2585 }
2586
2587 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2588 {
2589 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2590 struct ena_com_admin_queue *admin_queue;
2591 struct ena_admin_set_feat_cmd cmd;
2592 struct ena_admin_set_feat_resp resp;
2593
2594 int ret = 0;
2595
2596 if (unlikely(!ena_dev)) {
2597 ena_trc_err("%s : ena_dev is NULL\n", __func__);
2598 return ENA_COM_NO_DEVICE;
2599 }
2600
2601 if (!ena_com_check_supported_feature_id(ena_dev,
2602 ENA_ADMIN_HOST_ATTR_CONFIG)) {
2603 ena_trc_warn("Set host attribute isn't supported\n");
2604 return ENA_COM_PERMISSION;
2605 }
2606
2607 memset(&cmd, 0x0, sizeof(cmd));
2608 admin_queue = &ena_dev->admin_queue;
2609
2610 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2611 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2612
2613 ret = ena_com_mem_addr_set(ena_dev,
2614 &cmd.u.host_attr.debug_ba,
2615 host_attr->debug_area_dma_addr);
2616 if (unlikely(ret)) {
2617 ena_trc_err("memory address set failed\n");
2618 return ret;
2619 }
2620
2621 ret = ena_com_mem_addr_set(ena_dev,
2622 &cmd.u.host_attr.os_info_ba,
2623 host_attr->host_info_dma_addr);
2624 if (unlikely(ret)) {
2625 ena_trc_err("memory address set failed\n");
2626 return ret;
2627 }
2628
2629 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2630
2631 ret = ena_com_execute_admin_command(admin_queue,
2632 (struct ena_admin_aq_entry *)&cmd,
2633 sizeof(cmd),
2634 (struct ena_admin_acq_entry *)&resp,
2635 sizeof(resp));
2636
2637 if (unlikely(ret))
2638 ena_trc_err("Failed to set host attributes: %d\n", ret);
2639
2640 return ret;
2641 }
2642
2643 /* Interrupt moderation */
2644 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2645 {
2646 return ena_com_check_supported_feature_id(
2647 ena_dev,
2648 ENA_ADMIN_INTERRUPT_MODERATION);
2649 }
2650
2651 int
2652 ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2653 u32 tx_coalesce_usecs)
2654 {
2655 if (!ena_dev->intr_delay_resolution) {
2656 ena_trc_err("Illegal interrupt delay granularity value\n");
2657 return ENA_COM_FAULT;
2658 }
2659
2660 ena_dev->intr_moder_tx_interval = tx_coalesce_usecs /
2661 ena_dev->intr_delay_resolution;
2662
2663 return 0;
2664 }
2665
2666 int
2667 ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2668 u32 rx_coalesce_usecs)
2669 {
2670 if (!ena_dev->intr_delay_resolution) {
2671 ena_trc_err("Illegal interrupt delay granularity value\n");
2672 return ENA_COM_FAULT;
2673 }
2674
2675 /* We use LOWEST entry of moderation table for storing
2676 * nonadaptive interrupt coalescing values
2677 */
2678 ena_dev->intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval =
2679 rx_coalesce_usecs / ena_dev->intr_delay_resolution;
2680
2681 return 0;
2682 }
2683
2684 void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev)
2685 {
2686 if (ena_dev->intr_moder_tbl)
2687 ENA_MEM_FREE(ena_dev->dmadev, ena_dev->intr_moder_tbl);
2688 ena_dev->intr_moder_tbl = NULL;
2689 }
2690
2691 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2692 {
2693 struct ena_admin_get_feat_resp get_resp;
2694 u16 delay_resolution;
2695 int rc;
2696
2697 rc = ena_com_get_feature(ena_dev, &get_resp,
2698 ENA_ADMIN_INTERRUPT_MODERATION);
2699
2700 if (rc) {
2701 if (rc == ENA_COM_PERMISSION) {
2702 ena_trc_info("Feature %d isn't supported\n",
2703 ENA_ADMIN_INTERRUPT_MODERATION);
2704 rc = 0;
2705 } else {
2706 ena_trc_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
2707 rc);
2708 }
2709
2710 /* no moderation supported, disable adaptive support */
2711 ena_com_disable_adaptive_moderation(ena_dev);
2712 return rc;
2713 }
2714
2715 rc = ena_com_init_interrupt_moderation_table(ena_dev);
2716 if (rc)
2717 goto err;
2718
2719 /* if moderation is supported by device we set adaptive moderation */
2720 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2721 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2722 ena_com_enable_adaptive_moderation(ena_dev);
2723
2724 return 0;
2725 err:
2726 ena_com_destroy_interrupt_moderation(ena_dev);
2727 return rc;
2728 }
2729
2730 void
2731 ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev)
2732 {
2733 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2734
2735 if (!intr_moder_tbl)
2736 return;
2737
2738 intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval =
2739 ENA_INTR_LOWEST_USECS;
2740 intr_moder_tbl[ENA_INTR_MODER_LOWEST].pkts_per_interval =
2741 ENA_INTR_LOWEST_PKTS;
2742 intr_moder_tbl[ENA_INTR_MODER_LOWEST].bytes_per_interval =
2743 ENA_INTR_LOWEST_BYTES;
2744
2745 intr_moder_tbl[ENA_INTR_MODER_LOW].intr_moder_interval =
2746 ENA_INTR_LOW_USECS;
2747 intr_moder_tbl[ENA_INTR_MODER_LOW].pkts_per_interval =
2748 ENA_INTR_LOW_PKTS;
2749 intr_moder_tbl[ENA_INTR_MODER_LOW].bytes_per_interval =
2750 ENA_INTR_LOW_BYTES;
2751
2752 intr_moder_tbl[ENA_INTR_MODER_MID].intr_moder_interval =
2753 ENA_INTR_MID_USECS;
2754 intr_moder_tbl[ENA_INTR_MODER_MID].pkts_per_interval =
2755 ENA_INTR_MID_PKTS;
2756 intr_moder_tbl[ENA_INTR_MODER_MID].bytes_per_interval =
2757 ENA_INTR_MID_BYTES;
2758
2759 intr_moder_tbl[ENA_INTR_MODER_HIGH].intr_moder_interval =
2760 ENA_INTR_HIGH_USECS;
2761 intr_moder_tbl[ENA_INTR_MODER_HIGH].pkts_per_interval =
2762 ENA_INTR_HIGH_PKTS;
2763 intr_moder_tbl[ENA_INTR_MODER_HIGH].bytes_per_interval =
2764 ENA_INTR_HIGH_BYTES;
2765
2766 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].intr_moder_interval =
2767 ENA_INTR_HIGHEST_USECS;
2768 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].pkts_per_interval =
2769 ENA_INTR_HIGHEST_PKTS;
2770 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].bytes_per_interval =
2771 ENA_INTR_HIGHEST_BYTES;
2772 }
2773
2774 unsigned int
2775 ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2776 {
2777 return ena_dev->intr_moder_tx_interval;
2778 }
2779
2780 unsigned int
2781 ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2782 {
2783 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2784
2785 if (intr_moder_tbl)
2786 return intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval;
2787
2788 return 0;
2789 }
2790
2791 void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev,
2792 enum ena_intr_moder_level level,
2793 struct ena_intr_moder_entry *entry)
2794 {
2795 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2796
2797 if (level >= ENA_INTR_MAX_NUM_OF_LEVELS)
2798 return;
2799
2800 intr_moder_tbl[level].intr_moder_interval = entry->intr_moder_interval;
2801 if (ena_dev->intr_delay_resolution)
2802 intr_moder_tbl[level].intr_moder_interval /=
2803 ena_dev->intr_delay_resolution;
2804 intr_moder_tbl[level].pkts_per_interval = entry->pkts_per_interval;
2805 intr_moder_tbl[level].bytes_per_interval = entry->bytes_per_interval;
2806 }
2807
2808 void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,
2809 enum ena_intr_moder_level level,
2810 struct ena_intr_moder_entry *entry)
2811 {
2812 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2813
2814 if (level >= ENA_INTR_MAX_NUM_OF_LEVELS)
2815 return;
2816
2817 entry->intr_moder_interval = intr_moder_tbl[level].intr_moder_interval;
2818 if (ena_dev->intr_delay_resolution)
2819 entry->intr_moder_interval *= ena_dev->intr_delay_resolution;
2820 entry->pkts_per_interval =
2821 intr_moder_tbl[level].pkts_per_interval;
2822 entry->bytes_per_interval = intr_moder_tbl[level].bytes_per_interval;
2823 }
Ceph