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[ceph.git] / ceph / src / dpdk / drivers / net / fm10k / base / fm10k_type.h
1 /*******************************************************************************
2
3 Copyright (c) 2013 - 2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ***************************************************************************/
33
34 #ifndef _FM10K_TYPE_H_
35 #define _FM10K_TYPE_H_
36
37 /* forward declaration */
38 struct fm10k_hw;
39
40 #include "fm10k_osdep.h"
41 #include "fm10k_mbx.h"
42
43 #define FM10K_DEV_ID_PF 0x15A4
44 #define FM10K_DEV_ID_VF 0x15A5
45 #ifdef BOULDER_RAPIDS_HW
46 #define FM10K_DEV_ID_SDI_FM10420_QDA2 0x15D0
47 #endif /* BOULDER_RAPIDS_HW */
48 #ifdef ATWOOD_CHANNEL_HW
49 #define FM10K_DEV_ID_SDI_FM10420_DA2 0x15D5
50 #endif /* ATWOOD_CHANNEL_HW */
51
52 #ifndef LINUX_MACROS
53 #ifndef BIT
54 #define BIT(a) (1UL << (a))
55 #endif
56 #endif /* LINUX_MACROS */
57
58 #define FM10K_MAX_QUEUES 256
59 #define FM10K_MAX_QUEUES_PF 128
60 #define FM10K_MAX_QUEUES_POOL 16
61
62 #define FM10K_48_BIT_MASK 0x0000FFFFFFFFFFFFull
63 #define FM10K_STAT_VALID 0x80000000
64
65 /* PCI Bus Info */
66 #define FM10K_PCIE_LINK_CAP 0x7C
67 #define FM10K_PCIE_LINK_STATUS 0x82
68 #define FM10K_PCIE_LINK_WIDTH 0x3F0
69 #define FM10K_PCIE_LINK_WIDTH_1 0x10
70 #define FM10K_PCIE_LINK_WIDTH_2 0x20
71 #define FM10K_PCIE_LINK_WIDTH_4 0x40
72 #define FM10K_PCIE_LINK_WIDTH_8 0x80
73 #define FM10K_PCIE_LINK_SPEED 0xF
74 #define FM10K_PCIE_LINK_SPEED_2500 0x1
75 #define FM10K_PCIE_LINK_SPEED_5000 0x2
76 #define FM10K_PCIE_LINK_SPEED_8000 0x3
77
78 /* PCIe payload size */
79 #define FM10K_PCIE_DEV_CAP 0x74
80 #define FM10K_PCIE_DEV_CAP_PAYLOAD 0x07
81 #define FM10K_PCIE_DEV_CAP_PAYLOAD_128 0x00
82 #define FM10K_PCIE_DEV_CAP_PAYLOAD_256 0x01
83 #define FM10K_PCIE_DEV_CAP_PAYLOAD_512 0x02
84 #define FM10K_PCIE_DEV_CTRL 0x78
85 #define FM10K_PCIE_DEV_CTRL_PAYLOAD 0xE0
86 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_128 0x00
87 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_256 0x20
88 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_512 0x40
89
90 /* PCIe MSI-X Capability info */
91 #define FM10K_PCI_MSIX_MSG_CTRL 0xB2
92 #define FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK 0x7FF
93 #define FM10K_MAX_MSIX_VECTORS 256
94 #define FM10K_MAX_VECTORS_PF 256
95 #define FM10K_MAX_VECTORS_POOL 32
96
97 /* PCIe SR-IOV Info */
98 #define FM10K_PCIE_SRIOV_CTRL 0x190
99 #define FM10K_PCIE_SRIOV_CTRL_VFARI 0x10
100
101 #define FM10K_SUCCESS 0
102 #define FM10K_ERR_DEVICE_NOT_SUPPORTED -1
103 #define FM10K_ERR_PARAM -2
104 #define FM10K_ERR_NO_RESOURCES -3
105 #define FM10K_ERR_REQUESTS_PENDING -4
106 #define FM10K_ERR_RESET_REQUESTED -5
107 #define FM10K_ERR_DMA_PENDING -6
108 #define FM10K_ERR_RESET_FAILED -7
109 #define FM10K_ERR_INVALID_MAC_ADDR -8
110 #define FM10K_ERR_INVALID_VALUE -9
111 #define FM10K_NOT_IMPLEMENTED 0x7FFFFFFF
112
113 #define UNREFERENCED_XPARAMETER
114 #define UNREFERENCED_1PARAMETER(_p) (_p)
115 #define UNREFERENCED_2PARAMETER(_p, _q) do { (_p); (_q); } while (0)
116 #define UNREFERENCED_3PARAMETER(_p, _q, _r) do { (_p); (_q); (_r); } while (0)
117
118 /* Start of PF registers */
119 #define FM10K_CTRL 0x0000
120 #define FM10K_CTRL_BAR4_ALLOWED 0x00000004
121
122 #define FM10K_CTRL_EXT 0x0001
123 #define FM10K_GCR 0x0003
124 #define FM10K_GCR_EXT 0x0005
125
126 /* Interrupt control registers */
127 #define FM10K_EICR 0x0006
128 #define FM10K_EICR_FAULT_MASK 0x0000003F
129 #define FM10K_EICR_MAILBOX 0x00000040
130 #define FM10K_EICR_SWITCHREADY 0x00000080
131 #define FM10K_EICR_SWITCHNOTREADY 0x00000100
132 #define FM10K_EICR_SWITCHINTERRUPT 0x00000200
133 #define FM10K_EICR_VFLR 0x00000800
134 #define FM10K_EICR_MAXHOLDTIME 0x00001000
135 #define FM10K_EIMR 0x0007
136 #define FM10K_EIMR_PCA_FAULT 0x00000001
137 #define FM10K_EIMR_THI_FAULT 0x00000010
138 #define FM10K_EIMR_FUM_FAULT 0x00000400
139 #define FM10K_EIMR_MAILBOX 0x00001000
140 #define FM10K_EIMR_SWITCHREADY 0x00004000
141 #define FM10K_EIMR_SWITCHNOTREADY 0x00010000
142 #define FM10K_EIMR_SWITCHINTERRUPT 0x00040000
143 #define FM10K_EIMR_SRAMERROR 0x00100000
144 #define FM10K_EIMR_VFLR 0x00400000
145 #define FM10K_EIMR_MAXHOLDTIME 0x01000000
146 #define FM10K_EIMR_ALL 0x55555555
147 #define FM10K_EIMR_DISABLE(NAME) ((FM10K_EIMR_ ## NAME) << 0)
148 #define FM10K_EIMR_ENABLE(NAME) ((FM10K_EIMR_ ## NAME) << 1)
149 #define FM10K_FAULT_ADDR_LO 0x0
150 #define FM10K_FAULT_ADDR_HI 0x1
151 #define FM10K_FAULT_SPECINFO 0x2
152 #define FM10K_FAULT_FUNC 0x3
153 #define FM10K_FAULT_SIZE 0x4
154 #define FM10K_FAULT_FUNC_VALID 0x00008000
155 #define FM10K_FAULT_FUNC_PF 0x00004000
156 #define FM10K_FAULT_FUNC_VF_MASK 0x00003F00
157 #define FM10K_FAULT_FUNC_VF_SHIFT 8
158 #define FM10K_FAULT_FUNC_TYPE_MASK 0x000000FF
159
160 #define FM10K_PCA_FAULT 0x0008
161 #define FM10K_THI_FAULT 0x0010
162 #define FM10K_FUM_FAULT 0x001C
163
164 /* Rx queue timeout indicator */
165 #define FM10K_MAXHOLDQ(_n) ((_n) + 0x0020)
166
167 /* Switch Manager info */
168 #define FM10K_SM_AREA(_n) ((_n) + 0x0028)
169
170 /* GLORT mapping registers */
171 #define FM10K_DGLORTMAP(_n) ((_n) + 0x0030)
172 #define FM10K_DGLORT_COUNT 8
173 #define FM10K_DGLORTMAP_MASK_SHIFT 16
174 #define FM10K_DGLORTMAP_ANY 0x00000000
175 #define FM10K_DGLORTMAP_NONE 0x0000FFFF
176 #define FM10K_DGLORTMAP_ZERO 0xFFFF0000
177 #define FM10K_DGLORTDEC(_n) ((_n) + 0x0038)
178 #define FM10K_DGLORTDEC_VSILENGTH_SHIFT 4
179 #define FM10K_DGLORTDEC_VSIBASE_SHIFT 7
180 #define FM10K_DGLORTDEC_PCLENGTH_SHIFT 14
181 #define FM10K_DGLORTDEC_QBASE_SHIFT 16
182 #define FM10K_DGLORTDEC_RSSLENGTH_SHIFT 24
183 #define FM10K_DGLORTDEC_INNERRSS_ENABLE 0x08000000
184 #define FM10K_TUNNEL_CFG 0x0040
185 #define FM10K_TUNNEL_CFG_NVGRE_SHIFT 16
186 #define FM10K_SWPRI_MAP(_n) ((_n) + 0x0050)
187 #define FM10K_SWPRI_MAX 16
188 #define FM10K_RSSRK(_n, _m) (((_n) * 0x10) + (_m) + 0x0800)
189 #define FM10K_RSSRK_SIZE 10
190 #define FM10K_RSSRK_ENTRIES_PER_REG 4
191 #define FM10K_RETA(_n, _m) (((_n) * 0x20) + (_m) + 0x1000)
192 #define FM10K_RETA_SIZE 32
193 #define FM10K_RETA_ENTRIES_PER_REG 4
194 #define FM10K_MAX_RSS_INDICES 128
195
196 /* Rate limiting registers */
197 #define FM10K_TC_CREDIT(_n) ((_n) + 0x2000)
198 #define FM10K_TC_CREDIT_CREDIT_MASK 0x001FFFFF
199 #define FM10K_TC_MAXCREDIT(_n) ((_n) + 0x2040)
200 #define FM10K_TC_MAXCREDIT_64K 0x00010000
201 #define FM10K_TC_RATE(_n) ((_n) + 0x2080)
202 #define FM10K_TC_RATE_QUANTA_MASK 0x0000FFFF
203 #define FM10K_TC_RATE_INTERVAL_4US_GEN1 0x00020000
204 #define FM10K_TC_RATE_INTERVAL_4US_GEN2 0x00040000
205 #define FM10K_TC_RATE_INTERVAL_4US_GEN3 0x00080000
206
207 /* DMA control registers */
208 #define FM10K_DMA_CTRL 0x20C3
209 #define FM10K_DMA_CTRL_TX_ENABLE 0x00000001
210 #define FM10K_DMA_CTRL_TX_ACTIVE 0x00000008
211 #define FM10K_DMA_CTRL_RX_ENABLE 0x00000010
212 #define FM10K_DMA_CTRL_RX_ACTIVE 0x00000080
213 #define FM10K_DMA_CTRL_RX_DESC_SIZE 0x00000100
214 #define FM10K_DMA_CTRL_MINMSS_64 0x00008000
215 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3 0x04800000
216 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2 0x04000000
217 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1 0x03800000
218 #define FM10K_DMA_CTRL_DATAPATH_RESET 0x20000000
219 #define FM10K_DMA_CTRL_32_DESC 0x00000000
220
221 #define FM10K_DMA_CTRL2 0x20C4
222 #define FM10K_DMA_CTRL2_SWITCH_READY 0x00002000
223
224 /* TSO flags configuration
225 * First packet contains all flags except for fin and psh
226 * Middle packet contains only urg and ack
227 * Last packet contains urg, ack, fin, and psh
228 */
229 #define FM10K_TSO_FLAGS_LOW 0x00300FF6
230 #define FM10K_TSO_FLAGS_HI 0x00000039
231 #define FM10K_DTXTCPFLGL 0x20C5
232 #define FM10K_DTXTCPFLGH 0x20C6
233
234 #define FM10K_TPH_CTRL 0x20C7
235 #define FM10K_MRQC(_n) ((_n) + 0x2100)
236 #define FM10K_MRQC_TCP_IPV4 0x00000001
237 #define FM10K_MRQC_IPV4 0x00000002
238 #define FM10K_MRQC_IPV6 0x00000010
239 #define FM10K_MRQC_TCP_IPV6 0x00000020
240 #define FM10K_MRQC_UDP_IPV4 0x00000040
241 #define FM10K_MRQC_UDP_IPV6 0x00000080
242
243 #define FM10K_TQMAP(_n) ((_n) + 0x2800)
244 #define FM10K_TQMAP_TABLE_SIZE 2048
245 #define FM10K_RQMAP(_n) ((_n) + 0x3000)
246
247 /* Hardware Statistics */
248 #define FM10K_STATS_TIMEOUT 0x3800
249 #define FM10K_STATS_UR 0x3801
250 #define FM10K_STATS_CA 0x3802
251 #define FM10K_STATS_UM 0x3803
252 #define FM10K_STATS_XEC 0x3804
253 #define FM10K_STATS_VLAN_DROP 0x3805
254 #define FM10K_STATS_LOOPBACK_DROP 0x3806
255 #define FM10K_STATS_NODESC_DROP 0x3807
256
257 /* Timesync registers */
258 #define FM10K_SYSTIME 0x3814
259 #define FM10K_SYSTIME_CFG 0x3818
260 #define FM10K_SYSTIME_CFG_STEP_MASK 0x0000000F
261
262 /* PCIe state registers */
263 #define FM10K_PHYADDR 0x381C
264
265 /* Rx ring registers */
266 #define FM10K_RDBAL(_n) ((0x40 * (_n)) + 0x4000)
267 #define FM10K_RDBAH(_n) ((0x40 * (_n)) + 0x4001)
268 #define FM10K_RDLEN(_n) ((0x40 * (_n)) + 0x4002)
269 #define FM10K_TPH_RXCTRL(_n) ((0x40 * (_n)) + 0x4003)
270 #define FM10K_TPH_RXCTRL_DESC_TPHEN 0x00000020
271 #define FM10K_TPH_RXCTRL_DESC_RROEN 0x00000200
272 #define FM10K_TPH_RXCTRL_DATA_WROEN 0x00002000
273 #define FM10K_TPH_RXCTRL_HDR_WROEN 0x00008000
274 #define FM10K_RDH(_n) ((0x40 * (_n)) + 0x4004)
275 #define FM10K_RDT(_n) ((0x40 * (_n)) + 0x4005)
276 #define FM10K_RXQCTL(_n) ((0x40 * (_n)) + 0x4006)
277 #define FM10K_RXQCTL_ENABLE 0x00000001
278 #define FM10K_RXQCTL_PF 0x000000FC
279 #define FM10K_RXQCTL_VF_SHIFT 2
280 #define FM10K_RXQCTL_VF 0x00000100
281 #define FM10K_RXQCTL_ID_MASK (FM10K_RXQCTL_PF | FM10K_RXQCTL_VF)
282 #define FM10K_RXDCTL(_n) ((0x40 * (_n)) + 0x4007)
283 #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY 0x00000001
284 #define FM10K_RXDCTL_DROP_ON_EMPTY 0x00000200
285 #define FM10K_RXINT(_n) ((0x40 * (_n)) + 0x4008)
286 #define FM10K_SRRCTL(_n) ((0x40 * (_n)) + 0x4009)
287 #define FM10K_SRRCTL_BSIZEPKT_SHIFT 8 /* shift _right_ */
288 #define FM10K_SRRCTL_LOOPBACK_SUPPRESS 0x40000000
289 #define FM10K_SRRCTL_BUFFER_CHAINING_EN 0x80000000
290
291 /* Rx Statistics */
292 #define FM10K_QPRC(_n) ((0x40 * (_n)) + 0x400A)
293 #define FM10K_QPRDC(_n) ((0x40 * (_n)) + 0x400B)
294 #define FM10K_QBRC_L(_n) ((0x40 * (_n)) + 0x400C)
295 #define FM10K_QBRC_H(_n) ((0x40 * (_n)) + 0x400D)
296
297 /* Rx GLORT register */
298 #define FM10K_RX_SGLORT(_n) ((0x40 * (_n)) + 0x400E)
299
300 /* Tx ring registers */
301 #define FM10K_TDBAL(_n) ((0x40 * (_n)) + 0x8000)
302 #define FM10K_TDBAH(_n) ((0x40 * (_n)) + 0x8001)
303 #define FM10K_TDLEN(_n) ((0x40 * (_n)) + 0x8002)
304 /* When fist initialized, VFs need to know the Interrupt Throttle Rate (ITR)
305 * scale which is based on the PCIe speed but the speed information in the PCI
306 * configuration space may not be accurate. The PF already knows the ITR scale
307 * but there is no defined method to pass that information from the PF to the
308 * VF. This is accomplished during VF initialization by temporarily co-opting
309 * the yet-to-be-used TDLEN register to have the PF store the ITR shift for
310 * the VF to retrieve before the VF needs to use the TDLEN register for its
311 * intended purpose, i.e. before the Tx resources are allocated.
312 */
313 #define FM10K_TDLEN_ITR_SCALE_SHIFT 9
314 #define FM10K_TDLEN_ITR_SCALE_MASK 0x00000E00
315 #define FM10K_TDLEN_ITR_SCALE_GEN1 2
316 #define FM10K_TDLEN_ITR_SCALE_GEN2 1
317 #define FM10K_TDLEN_ITR_SCALE_GEN3 0
318 #define FM10K_TPH_TXCTRL(_n) ((0x40 * (_n)) + 0x8003)
319 #define FM10K_TPH_TXCTRL_DESC_TPHEN 0x00000020
320 #define FM10K_TPH_TXCTRL_DESC_RROEN 0x00000200
321 #define FM10K_TPH_TXCTRL_DESC_WROEN 0x00000800
322 #define FM10K_TPH_TXCTRL_DATA_RROEN 0x00002000
323 #define FM10K_TDH(_n) ((0x40 * (_n)) + 0x8004)
324 #define FM10K_TDT(_n) ((0x40 * (_n)) + 0x8005)
325 #define FM10K_TXDCTL(_n) ((0x40 * (_n)) + 0x8006)
326 #define FM10K_TXDCTL_ENABLE 0x00004000
327 #define FM10K_TXDCTL_MAX_TIME_SHIFT 16
328 #define FM10K_TXQCTL(_n) ((0x40 * (_n)) + 0x8007)
329 #define FM10K_TXQCTL_PF 0x0000003F
330 #define FM10K_TXQCTL_VF 0x00000040
331 #define FM10K_TXQCTL_ID_MASK (FM10K_TXQCTL_PF | FM10K_TXQCTL_VF)
332 #define FM10K_TXQCTL_PC_SHIFT 7
333 #define FM10K_TXQCTL_PC_MASK 0x00000380
334 #define FM10K_TXQCTL_TC_SHIFT 10
335 #define FM10K_TXQCTL_VID_SHIFT 16
336 #define FM10K_TXQCTL_VID_MASK 0x0FFF0000
337 #define FM10K_TXQCTL_UNLIMITED_BW 0x10000000
338 #define FM10K_TXINT(_n) ((0x40 * (_n)) + 0x8008)
339
340 /* Tx Statistics */
341 #define FM10K_QPTC(_n) ((0x40 * (_n)) + 0x8009)
342 #define FM10K_QBTC_L(_n) ((0x40 * (_n)) + 0x800A)
343 #define FM10K_QBTC_H(_n) ((0x40 * (_n)) + 0x800B)
344
345 /* Tx Push registers */
346 #define FM10K_TQDLOC(_n) ((0x40 * (_n)) + 0x800C)
347 #define FM10K_TQDLOC_BASE_32_DESC 0x08
348 #define FM10K_TQDLOC_SIZE_32_DESC 0x00050000
349
350 /* Tx GLORT registers */
351 #define FM10K_TX_SGLORT(_n) ((0x40 * (_n)) + 0x800D)
352 #define FM10K_PFVTCTL(_n) ((0x40 * (_n)) + 0x800E)
353 #define FM10K_PFVTCTL_FTAG_DESC_ENABLE 0x00000001
354
355 /* Interrupt moderation and control registers */
356 #define FM10K_INT_MAP(_n) ((_n) + 0x10080)
357 #define FM10K_INT_MAP_TIMER0 0x00000000
358 #define FM10K_INT_MAP_TIMER1 0x00000100
359 #define FM10K_INT_MAP_IMMEDIATE 0x00000200
360 #define FM10K_INT_MAP_DISABLE 0x00000300
361 #define FM10K_MSIX_VECTOR_MASK(_n) ((0x4 * (_n)) + 0x11003)
362 #define FM10K_INT_CTRL 0x12000
363 #define FM10K_INT_CTRL_ENABLEMODERATOR 0x00000400
364 #define FM10K_ITR(_n) ((_n) + 0x12400)
365 #define FM10K_ITR_INTERVAL1_SHIFT 12
366 #define FM10K_ITR_PENDING2 0x10000000
367 #define FM10K_ITR_AUTOMASK 0x20000000
368 #define FM10K_ITR_MASK_SET 0x40000000
369 #define FM10K_ITR_MASK_CLEAR 0x80000000
370 #define FM10K_ITR2(_n) ((0x2 * (_n)) + 0x12800)
371 #define FM10K_ITR_REG_COUNT 768
372 #define FM10K_ITR_REG_COUNT_PF 256
373
374 /* Switch manager interrupt registers */
375 #define FM10K_IP 0x13000
376 #define FM10K_IP_NOTINRESET 0x00000100
377
378 /* VLAN registers */
379 #define FM10K_VLAN_TABLE(_n, _m) ((0x80 * (_n)) + (_m) + 0x14000)
380 #define FM10K_VLAN_TABLE_SIZE 128
381
382 /* VLAN specific message offsets */
383 #define FM10K_VLAN_TABLE_VID_MAX 4096
384 #define FM10K_VLAN_TABLE_VSI_MAX 64
385 #define FM10K_VLAN_LENGTH_SHIFT 16
386 #define FM10K_VLAN_CLEAR BIT(15)
387 #define FM10K_VLAN_ALL \
388 ((FM10K_VLAN_TABLE_VID_MAX - 1) << FM10K_VLAN_LENGTH_SHIFT)
389
390 /* VF FLR event notification registers */
391 #define FM10K_PFVFLRE(_n) ((0x1 * (_n)) + 0x18844)
392 #define FM10K_PFVFLREC(_n) ((0x1 * (_n)) + 0x18846)
393
394 /* Defines for size of uncacheable and write-combining memories */
395 #define FM10K_UC_ADDR_START 0x000000 /* start of standard regs */
396 #define FM10K_WC_ADDR_START 0x100000 /* start of Tx Desc Cache */
397 #define FM10K_DBI_ADDR_START 0x200000 /* start of debug registers */
398 #define FM10K_UC_ADDR_SIZE (FM10K_WC_ADDR_START - FM10K_UC_ADDR_START)
399 #define FM10K_WC_ADDR_SIZE (FM10K_DBI_ADDR_START - FM10K_WC_ADDR_START)
400
401 /* Define timeouts for resets and disables */
402 #define FM10K_QUEUE_DISABLE_TIMEOUT 100
403 #define FM10K_RESET_TIMEOUT 150
404
405 /* Maximum supported combined inner and outer header length for encapsulation */
406 #define FM10K_TUNNEL_HEADER_LENGTH 184
407
408 /* VF registers */
409 #define FM10K_VFCTRL 0x00000
410 #define FM10K_VFCTRL_RST 0x00000008
411 #define FM10K_VFINT_MAP 0x00030
412 #define FM10K_VFSYSTIME 0x00040
413 #define FM10K_VFITR(_n) ((_n) + 0x00060)
414
415 /* Registers contained in BAR 4 for Switch management */
416 #define FM10K_SW_SYSTIME_ADJUST 0x0224D
417 #define FM10K_SW_SYSTIME_ADJUST_MASK 0x3FFFFFFF
418 #define FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE 0x80000000
419 #define FM10K_SW_SYSTIME_PULSE(_n) ((_n) + 0x02252)
420
421 #ifndef ETH_ALEN
422 #define ETH_ALEN 6
423 #endif /* ETH_ALEN */
424
425 #ifndef FM10K_IS_ZERO_ETHER_ADDR
426 /* make certain address is not 0 */
427 #define FM10K_IS_ZERO_ETHER_ADDR(addr) \
428 (!((addr)[0] | (addr)[1] | (addr)[2] | (addr)[3] | (addr)[4] | (addr)[5]))
429 #endif
430
431 #ifndef FM10K_IS_MULTICAST_ETHER_ADDR
432 #define FM10K_IS_MULTICAST_ETHER_ADDR(addr) ((addr)[0] & 0x1)
433 #endif
434
435 #ifndef FM10K_IS_VALID_ETHER_ADDR
436 /* make certain address is not multicast or 0 */
437 #define FM10K_IS_VALID_ETHER_ADDR(addr) \
438 (!FM10K_IS_MULTICAST_ETHER_ADDR(addr) && !FM10K_IS_ZERO_ETHER_ADDR(addr))
439 #endif
440
441 enum fm10k_int_source {
442 fm10k_int_mailbox = 0,
443 fm10k_int_pcie_fault = 1,
444 fm10k_int_switch_up_down = 2,
445 fm10k_int_switch_event = 3,
446 fm10k_int_sram = 4,
447 fm10k_int_vflr = 5,
448 fm10k_int_max_hold_time = 6,
449 fm10k_int_sources_max_pf
450 };
451
452 /* PCIe bus speeds */
453 enum fm10k_bus_speed {
454 fm10k_bus_speed_unknown = 0,
455 fm10k_bus_speed_2500 = 2500,
456 fm10k_bus_speed_5000 = 5000,
457 fm10k_bus_speed_8000 = 8000,
458 fm10k_bus_speed_reserved
459 };
460
461 /* PCIe bus widths */
462 enum fm10k_bus_width {
463 fm10k_bus_width_unknown = 0,
464 fm10k_bus_width_pcie_x1 = 1,
465 fm10k_bus_width_pcie_x2 = 2,
466 fm10k_bus_width_pcie_x4 = 4,
467 fm10k_bus_width_pcie_x8 = 8,
468 fm10k_bus_width_reserved
469 };
470
471 /* PCIe payload sizes */
472 enum fm10k_bus_payload {
473 fm10k_bus_payload_unknown = 0,
474 fm10k_bus_payload_128 = 1,
475 fm10k_bus_payload_256 = 2,
476 fm10k_bus_payload_512 = 3,
477 fm10k_bus_payload_reserved
478 };
479
480 /* Bus parameters */
481 struct fm10k_bus_info {
482 enum fm10k_bus_speed speed;
483 enum fm10k_bus_width width;
484 enum fm10k_bus_payload payload;
485 };
486
487 /* Statistics related declarations */
488 struct fm10k_hw_stat {
489 u64 count;
490 u32 base_l;
491 u32 base_h;
492 };
493
494 struct fm10k_hw_stats_q {
495 struct fm10k_hw_stat tx_bytes;
496 struct fm10k_hw_stat tx_packets;
497 #define tx_stats_idx tx_packets.base_h
498 struct fm10k_hw_stat rx_bytes;
499 struct fm10k_hw_stat rx_packets;
500 #define rx_stats_idx rx_packets.base_h
501 struct fm10k_hw_stat rx_drops;
502 };
503
504 struct fm10k_hw_stats {
505 struct fm10k_hw_stat timeout;
506 #define stats_idx timeout.base_h
507 struct fm10k_hw_stat ur;
508 struct fm10k_hw_stat ca;
509 struct fm10k_hw_stat um;
510 struct fm10k_hw_stat xec;
511 struct fm10k_hw_stat vlan_drop;
512 struct fm10k_hw_stat loopback_drop;
513 struct fm10k_hw_stat nodesc_drop;
514 struct fm10k_hw_stats_q q[FM10K_MAX_QUEUES_PF];
515 };
516
517 /* Establish DGLORT feature priority */
518 enum fm10k_dglortdec_idx {
519 fm10k_dglort_default = 0,
520 fm10k_dglort_vf_rsvd0 = 1,
521 fm10k_dglort_vf_rss = 2,
522 fm10k_dglort_pf_rsvd0 = 3,
523 fm10k_dglort_pf_queue = 4,
524 fm10k_dglort_pf_vsi = 5,
525 fm10k_dglort_pf_rsvd1 = 6,
526 fm10k_dglort_pf_rss = 7
527 };
528
529 struct fm10k_dglort_cfg {
530 u16 glort; /* GLORT base */
531 u16 queue_b; /* Base value for queue */
532 u8 vsi_b; /* Base value for VSI */
533 u8 idx; /* index of DGLORTDEC entry */
534 u8 rss_l; /* RSS indices */
535 u8 pc_l; /* Priority Class indices */
536 u8 vsi_l; /* Number of bits from GLORT used to determine VSI */
537 u8 queue_l; /* Number of bits from GLORT used to determine queue */
538 u8 shared_l; /* Ignored bits from GLORT resulting in shared VSI */
539 u8 inner_rss; /* Boolean value if inner header is used for RSS */
540 };
541
542 enum fm10k_pca_fault {
543 PCA_NO_FAULT,
544 PCA_UNMAPPED_ADDR,
545 PCA_BAD_QACCESS_PF,
546 PCA_BAD_QACCESS_VF,
547 PCA_MALICIOUS_REQ,
548 PCA_POISONED_TLP,
549 PCA_TLP_ABORT,
550 __PCA_MAX
551 };
552
553 enum fm10k_thi_fault {
554 THI_NO_FAULT,
555 THI_MAL_DIS_Q_FAULT,
556 __THI_MAX
557 };
558
559 enum fm10k_fum_fault {
560 FUM_NO_FAULT,
561 FUM_UNMAPPED_ADDR,
562 FUM_POISONED_TLP,
563 FUM_BAD_VF_QACCESS,
564 FUM_ADD_DECODE_ERR,
565 FUM_RO_ERROR,
566 FUM_QPRC_CRC_ERROR,
567 FUM_CSR_TIMEOUT,
568 FUM_INVALID_TYPE,
569 FUM_INVALID_LENGTH,
570 FUM_INVALID_BE,
571 FUM_INVALID_ALIGN,
572 __FUM_MAX
573 };
574
575 struct fm10k_fault {
576 u64 address; /* Address at the time fault was detected */
577 u32 specinfo; /* Extra info on this fault (fault dependent) */
578 u8 type; /* Fault value dependent on subunit */
579 u8 func; /* Function number of the fault */
580 };
581
582 struct fm10k_mac_ops {
583 /* basic bring-up and tear-down */
584 s32 (*reset_hw)(struct fm10k_hw *);
585 s32 (*init_hw)(struct fm10k_hw *);
586 s32 (*start_hw)(struct fm10k_hw *);
587 s32 (*stop_hw)(struct fm10k_hw *);
588 s32 (*get_bus_info)(struct fm10k_hw *);
589 s32 (*get_host_state)(struct fm10k_hw *, bool *);
590 #ifndef NO_IS_SLOT_APPROPRIATE_CHECK
591 bool (*is_slot_appropriate)(struct fm10k_hw *);
592 #endif
593 s32 (*update_vlan)(struct fm10k_hw *, u32, u8, bool);
594 s32 (*read_mac_addr)(struct fm10k_hw *);
595 s32 (*update_uc_addr)(struct fm10k_hw *, u16, const u8 *,
596 u16, bool, u8);
597 s32 (*update_mc_addr)(struct fm10k_hw *, u16, const u8 *, u16, bool);
598 s32 (*update_xcast_mode)(struct fm10k_hw *, u16, u8);
599 void (*update_int_moderator)(struct fm10k_hw *);
600 s32 (*update_lport_state)(struct fm10k_hw *, u16, u16, bool);
601 void (*update_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);
602 void (*rebind_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);
603 s32 (*configure_dglort_map)(struct fm10k_hw *,
604 struct fm10k_dglort_cfg *);
605 void (*set_dma_mask)(struct fm10k_hw *, u64);
606 s32 (*get_fault)(struct fm10k_hw *, int, struct fm10k_fault *);
607 s32 (*adjust_systime)(struct fm10k_hw *, s32 ppb);
608 s32 (*notify_offset)(struct fm10k_hw *, u64 offset);
609 u64 (*read_systime)(struct fm10k_hw *);
610 };
611
612 enum fm10k_mac_type {
613 fm10k_mac_unknown = 0,
614 fm10k_mac_pf,
615 fm10k_mac_vf,
616 fm10k_num_macs
617 };
618
619 struct fm10k_mac_info {
620 struct fm10k_mac_ops ops;
621 enum fm10k_mac_type type;
622 u8 addr[ETH_ALEN];
623 u8 perm_addr[ETH_ALEN];
624 u16 default_vid;
625 u16 max_msix_vectors;
626 u16 max_queues;
627 bool vlan_override;
628 bool get_host_state;
629 bool tx_ready;
630 u32 dglort_map;
631 u8 itr_scale;
632 };
633
634 struct fm10k_swapi_table_info {
635 u32 used;
636 u32 avail;
637 };
638
639 struct fm10k_swapi_info {
640 u32 status;
641 struct fm10k_swapi_table_info mac;
642 struct fm10k_swapi_table_info nexthop;
643 struct fm10k_swapi_table_info ffu;
644 };
645
646 enum fm10k_xcast_modes {
647 FM10K_XCAST_MODE_ALLMULTI = 0,
648 FM10K_XCAST_MODE_MULTI = 1,
649 FM10K_XCAST_MODE_PROMISC = 2,
650 FM10K_XCAST_MODE_NONE = 3,
651 FM10K_XCAST_MODE_DISABLE = 4
652 };
653
654 enum fm10k_timestamp_modes {
655 FM10K_TIMESTAMP_MODE_NONE = 0,
656 FM10K_TIMESTAMP_MODE_PEP_TO_PEP = 1,
657 FM10K_TIMESTAMP_MODE_PEP_TO_ANY = 2,
658 };
659
660 #define FM10K_VF_TC_MAX 100000 /* 100,000 Mb/s aka 100Gb/s */
661 #define FM10K_VF_TC_MIN 1 /* 1 Mb/s is the slowest rate */
662
663 struct fm10k_vf_info {
664 /* mbx must be first field in struct unless all default IOV message
665 * handlers are redone as the assumption is that vf_info starts
666 * at the same offset as the mailbox
667 */
668 struct fm10k_mbx_info mbx; /* PF side of VF mailbox */
669 int rate; /* Tx BW cap as defined by OS */
670 u16 glort; /* resource tag for this VF */
671 u16 sw_vid; /* Switch API assigned VLAN */
672 u16 pf_vid; /* PF assigned Default VLAN */
673 u8 mac[ETH_ALEN]; /* PF Default MAC address */
674 u8 vsi; /* VSI identifier */
675 u8 vf_idx; /* which VF this is */
676 u8 vf_flags; /* flags indicating what modes
677 * are supported for the port
678 */
679 };
680
681 #define FM10K_VF_FLAG_ALLMULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_ALLMULTI))
682 #define FM10K_VF_FLAG_MULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_MULTI))
683 #define FM10K_VF_FLAG_PROMISC_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_PROMISC))
684 #define FM10K_VF_FLAG_NONE_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_NONE))
685 #define FM10K_VF_FLAG_CAPABLE(vf_info) ((vf_info)->vf_flags & (u8)0xF)
686 #define FM10K_VF_FLAG_ENABLED(vf_info) ((vf_info)->vf_flags >> 4)
687 #define FM10K_VF_FLAG_SET_MODE(mode) ((u8)0x10 << (mode))
688 #define FM10K_VF_FLAG_SET_MODE_NONE \
689 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_NONE)
690 #define FM10K_VF_FLAG_MULTI_ENABLED \
691 (FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_ALLMULTI) | \
692 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_MULTI) | \
693 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_PROMISC))
694
695 struct fm10k_iov_ops {
696 /* IOV related bring-up and tear-down */
697 s32 (*assign_resources)(struct fm10k_hw *, u16, u16);
698 s32 (*configure_tc)(struct fm10k_hw *, u16, int);
699 s32 (*assign_int_moderator)(struct fm10k_hw *, u16);
700 s32 (*assign_default_mac_vlan)(struct fm10k_hw *,
701 struct fm10k_vf_info *);
702 s32 (*reset_resources)(struct fm10k_hw *,
703 struct fm10k_vf_info *);
704 s32 (*set_lport)(struct fm10k_hw *, struct fm10k_vf_info *, u16, u8);
705 void (*reset_lport)(struct fm10k_hw *, struct fm10k_vf_info *);
706 void (*update_stats)(struct fm10k_hw *, struct fm10k_hw_stats_q *, u16);
707 void (*notify_offset)(struct fm10k_hw *, struct fm10k_vf_info*, u64);
708 };
709
710 struct fm10k_iov_info {
711 struct fm10k_iov_ops ops;
712 u16 total_vfs;
713 u16 num_vfs;
714 u16 num_pools;
715 };
716
717 struct fm10k_hw {
718 u32 *hw_addr;
719 u32 *sw_addr;
720 void *back;
721 struct fm10k_mac_info mac;
722 struct fm10k_bus_info bus;
723 struct fm10k_bus_info bus_caps;
724 struct fm10k_iov_info iov;
725 struct fm10k_mbx_info mbx;
726 struct fm10k_swapi_info swapi;
727 u16 device_id;
728 u16 vendor_id;
729 u16 subsystem_device_id;
730 u16 subsystem_vendor_id;
731 u8 revision_id;
732 u32 flags;
733 #define FM10K_HW_FLAG_CLOCK_OWNER BIT(0)
734 };
735
736 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
737 #define FM10K_REQ_TX_DESCRIPTOR_MULTIPLE 8
738 #define FM10K_REQ_RX_DESCRIPTOR_MULTIPLE 8
739
740 /* Transmit Descriptor */
741 struct fm10k_tx_desc {
742 __le64 buffer_addr; /* Address of the descriptor's data buffer */
743 __le16 buflen; /* Length of data to be DMAed */
744 __le16 vlan; /* VLAN_ID and VPRI to be inserted in FTAG */
745 __le16 mss; /* MSS for segmentation offload */
746 u8 hdrlen; /* Header size for segmentation offload */
747 u8 flags; /* Status and offload request flags */
748 };
749
750 /* Transmit Descriptor Cache Structure */
751 struct fm10k_tx_desc_cache {
752 struct fm10k_tx_desc tx_desc[256];
753 };
754
755 #define FM10K_TXD_FLAG_INT 0x01
756 #define FM10K_TXD_FLAG_TIME 0x02
757 #define FM10K_TXD_FLAG_CSUM 0x04
758 #define FM10K_TXD_FLAG_FTAG 0x10
759 #define FM10K_TXD_FLAG_RS 0x20
760 #define FM10K_TXD_FLAG_LAST 0x40
761 #define FM10K_TXD_FLAG_DONE 0x80
762
763
764 /* These macros are meant to enable optimal placement of the RS and INT
765 * bits. It will point us to the last descriptor in the cache for either the
766 * start of the packet, or the end of the packet. If the index is actually
767 * at the start of the FIFO it will point to the offset for the last index
768 * in the FIFO to prevent an unnecessary write.
769 */
770 #define FM10K_TXD_WB_FIFO_SIZE 4
771
772 /* Receive Descriptor - 32B */
773 union fm10k_rx_desc {
774 struct {
775 __le64 pkt_addr; /* Packet buffer address */
776 __le64 hdr_addr; /* Header buffer address */
777 __le64 reserved; /* Empty space, RSS hash */
778 __le64 timestamp;
779 } q; /* Read, Writeback, 64b quad-words */
780 struct {
781 __le32 data; /* RSS and header data */
782 __le32 rss; /* RSS Hash */
783 __le32 staterr;
784 __le32 vlan_len;
785 __le32 glort; /* sglort/dglort */
786 } d; /* Writeback, 32b double-words */
787 struct {
788 __le16 pkt_info; /* RSS, Pkt type */
789 __le16 hdr_info; /* Splithdr, hdrlen, xC */
790 __le16 rss_lower;
791 __le16 rss_upper;
792 __le16 status; /* status/error */
793 __le16 csum_err; /* checksum or extended error value */
794 __le16 length; /* Packet length */
795 __le16 vlan; /* VLAN tag */
796 __le16 dglort;
797 __le16 sglort;
798 } w; /* Writeback, 16b words */
799 };
800
801 #define FM10K_RXD_RSSTYPE_MASK 0x000F
802 enum fm10k_rdesc_rss_type {
803 FM10K_RSSTYPE_NONE = 0x0,
804 FM10K_RSSTYPE_IPV4_TCP = 0x1,
805 FM10K_RSSTYPE_IPV4 = 0x2,
806 FM10K_RSSTYPE_IPV6_TCP = 0x3,
807 /* Reserved 0x4 */
808 FM10K_RSSTYPE_IPV6 = 0x5,
809 /* Reserved 0x6 */
810 FM10K_RSSTYPE_IPV4_UDP = 0x7,
811 FM10K_RSSTYPE_IPV6_UDP = 0x8
812 /* Reserved 0x9 - 0xF */
813 };
814
815
816 #define FM10K_RXD_HDR_INFO_XC_MASK 0x0006
817 enum fm10k_rxdesc_xc {
818 FM10K_XC_UNICAST = 0x0,
819 FM10K_XC_MULTICAST = 0x4,
820 FM10K_XC_BROADCAST = 0x6
821 };
822
823
824 #define FM10K_RXD_STATUS_DD 0x0001 /* Descriptor done */
825 #define FM10K_RXD_STATUS_EOP 0x0002 /* End of packet */
826 #define FM10K_RXD_STATUS_L4CS 0x0010 /* Indicates an L4 csum */
827 #define FM10K_RXD_STATUS_L4CS2 0x0040 /* Inner header L4 csum */
828 #define FM10K_RXD_STATUS_L4E2 0x0800 /* Inner header L4 csum err */
829 #define FM10K_RXD_STATUS_IPE2 0x1000 /* Inner header IPv4 csum err */
830 #define FM10K_RXD_STATUS_RXE 0x2000 /* Generic Rx error */
831 #define FM10K_RXD_STATUS_L4E 0x4000 /* L4 csum error */
832 #define FM10K_RXD_STATUS_IPE 0x8000 /* IPv4 csum error */
833
834 #define FM10K_RXD_ERR_SWITCH_ERROR 0x0001 /* Switch found bad packet */
835 #define FM10K_RXD_ERR_NO_DESCRIPTOR 0x0002 /* No descriptor available */
836 #define FM10K_RXD_ERR_PP_ERROR 0x0004 /* RAM error during processing */
837 #define FM10K_RXD_ERR_SWITCH_READY 0x0008 /* Link transition mid-packet */
838 #define FM10K_RXD_ERR_TOO_BIG 0x0010 /* Pkt too big for single buf */
839
840
841 struct fm10k_ftag {
842 __be16 swpri_type_user;
843 __be16 vlan;
844 __be16 sglort;
845 __be16 dglort;
846 };
847
848 #endif /* _FM10K_TYPE_H */
Ceph