ceph/src/dpdk/drivers/net/qede/base/ecore_hsi_eth.h

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #ifndef __ECORE_HSI_ETH__
  10 #define __ECORE_HSI_ETH__
  11 /************************************************************************/
  12 /* Add include to common eth target for both eCore and protocol driver */
  13 /************************************************************************/
  14 #include "eth_common.h"
  15
  16 /*
  17  * The eth storm context for the Tstorm
  18  */
  19 struct tstorm_eth_conn_st_ctx {
  20         __le32 reserved[4];
  21 };
  22
  23 /*
  24  * The eth storm context for the Pstorm
  25  */
  26 struct pstorm_eth_conn_st_ctx {
  27         __le32 reserved[8];
  28 };
  29
  30 /*
  31  * The eth storm context for the Xstorm
  32  */
  33 struct xstorm_eth_conn_st_ctx {
  34         __le32 reserved[60];
  35 };
  36
  37 struct xstorm_eth_conn_ag_ctx {
  38         u8 reserved0 /* cdu_validation */;
  39         u8 eth_state /* state */;
  40         u8 flags0;
  41 /* exist_in_qm0 */
  42 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK            0x1
  43 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT           0
  44 /* exist_in_qm1 */
  45 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK               0x1
  46 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT              1
  47 /* exist_in_qm2 */
  48 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK               0x1
  49 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT              2
  50 /* exist_in_qm3 */
  51 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK            0x1
  52 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT           3
  53 /* bit4 */
  54 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK               0x1
  55 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT              4
  56 /* cf_array_active */
  57 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK               0x1
  58 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT              5
  59 /* bit6 */
  60 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK               0x1
  61 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT              6
  62 /* bit7 */
  63 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK               0x1
  64 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT              7
  65         u8 flags1;
  66 /* bit8 */
  67 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK               0x1
  68 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT              0
  69 /* bit9 */
  70 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK               0x1
  71 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT              1
  72 /* bit10 */
  73 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK               0x1
  74 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT              2
  75 /* bit11 */
  76 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK                   0x1
  77 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT                  3
  78 /* bit12 */
  79 #define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK                   0x1
  80 #define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT                  4
  81 /* bit13 */
  82 #define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK                   0x1
  83 #define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT                  5
  84 /* bit14 */
  85 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK          0x1
  86 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT         6
  87 /* bit15 */
  88 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK            0x1
  89 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT           7
  90         u8 flags2;
  91 /* timer0cf */
  92 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK                     0x3
  93 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT                    0
  94 /* timer1cf */
  95 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK                     0x3
  96 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT                    2
  97 /* timer2cf */
  98 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK                     0x3
  99 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT                    4
 100 /* timer_stop_all */
 101 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK                     0x3
 102 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT                    6
 103         u8 flags3;
 104 /* cf4 */
 105 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK                     0x3
 106 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT                    0
 107 /* cf5 */
 108 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK                     0x3
 109 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT                    2
 110 /* cf6 */
 111 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK                     0x3
 112 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT                    4
 113 /* cf7 */
 114 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK                     0x3
 115 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT                    6
 116         u8 flags4;
 117 /* cf8 */
 118 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK                     0x3
 119 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT                    0
 120 /* cf9 */
 121 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK                     0x3
 122 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT                    2
 123 /* cf10 */
 124 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK                    0x3
 125 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT                   4
 126 /* cf11 */
 127 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK                    0x3
 128 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT                   6
 129         u8 flags5;
 130 /* cf12 */
 131 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK                    0x3
 132 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT                   0
 133 /* cf13 */
 134 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK                    0x3
 135 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT                   2
 136 /* cf14 */
 137 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK                    0x3
 138 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT                   4
 139 /* cf15 */
 140 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK                    0x3
 141 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT                   6
 142         u8 flags6;
 143 /* cf16 */
 144 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK        0x3
 145 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT       0
 146 /* cf_array_cf */
 147 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK        0x3
 148 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT       2
 149 /* cf18 */
 150 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK                   0x3
 151 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT                  4
 152 /* cf19 */
 153 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK            0x3
 154 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT           6
 155         u8 flags7;
 156 /* cf20 */
 157 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK                0x3
 158 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT               0
 159 /* cf21 */
 160 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK              0x3
 161 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT             2
 162 /* cf22 */
 163 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK               0x3
 164 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT              4
 165 /* cf0en */
 166 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK                   0x1
 167 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT                  6
 168 /* cf1en */
 169 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK                   0x1
 170 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT                  7
 171         u8 flags8;
 172 /* cf2en */
 173 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK                   0x1
 174 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                  0
 175 /* cf3en */
 176 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK                   0x1
 177 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT                  1
 178 /* cf4en */
 179 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK                   0x1
 180 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT                  2
 181 /* cf5en */
 182 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK                   0x1
 183 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT                  3
 184 /* cf6en */
 185 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK                   0x1
 186 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT                  4
 187 /* cf7en */
 188 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK                   0x1
 189 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT                  5
 190 /* cf8en */
 191 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK                   0x1
 192 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT                  6
 193 /* cf9en */
 194 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK                   0x1
 195 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT                  7
 196         u8 flags9;
 197 /* cf10en */
 198 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK                  0x1
 199 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT                 0
 200 /* cf11en */
 201 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK                  0x1
 202 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT                 1
 203 /* cf12en */
 204 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK                  0x1
 205 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT                 2
 206 /* cf13en */
 207 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK                  0x1
 208 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT                 3
 209 /* cf14en */
 210 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK                  0x1
 211 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT                 4
 212 /* cf15en */
 213 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK                  0x1
 214 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT                 5
 215 /* cf16en */
 216 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK     0x1
 217 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT    6
 218 /* cf_array_cf_en */
 219 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK     0x1
 220 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT    7
 221         u8 flags10;
 222 /* cf18en */
 223 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK                0x1
 224 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT               0
 225 /* cf19en */
 226 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK         0x1
 227 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT        1
 228 /* cf20en */
 229 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK             0x1
 230 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT            2
 231 /* cf21en */
 232 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK              0x1
 233 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT             3
 234 /* cf22en */
 235 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK            0x1
 236 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT           4
 237 /* cf23en */
 238 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK  0x1
 239 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
 240 /* rule0en */
 241 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK              0x1
 242 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT             6
 243 /* rule1en */
 244 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK              0x1
 245 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT             7
 246         u8 flags11;
 247 /* rule2en */
 248 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK              0x1
 249 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT             0
 250 /* rule3en */
 251 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK              0x1
 252 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT             1
 253 /* rule4en */
 254 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK          0x1
 255 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT         2
 256 /* rule5en */
 257 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK                 0x1
 258 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT                3
 259 /* rule6en */
 260 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK                 0x1
 261 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT                4
 262 /* rule7en */
 263 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK                 0x1
 264 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT                5
 265 /* rule8en */
 266 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK            0x1
 267 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT           6
 268 /* rule9en */
 269 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK                 0x1
 270 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT                7
 271         u8 flags12;
 272 /* rule10en */
 273 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK                0x1
 274 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT               0
 275 /* rule11en */
 276 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK                0x1
 277 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT               1
 278 /* rule12en */
 279 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK            0x1
 280 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT           2
 281 /* rule13en */
 282 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK            0x1
 283 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT           3
 284 /* rule14en */
 285 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK                0x1
 286 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT               4
 287 /* rule15en */
 288 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK                0x1
 289 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT               5
 290 /* rule16en */
 291 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK                0x1
 292 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT               6
 293 /* rule17en */
 294 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK                0x1
 295 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT               7
 296         u8 flags13;
 297 /* rule18en */
 298 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK                0x1
 299 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT               0
 300 /* rule19en */
 301 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK                0x1
 302 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT               1
 303 /* rule20en */
 304 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK            0x1
 305 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT           2
 306 /* rule21en */
 307 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK            0x1
 308 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT           3
 309 /* rule22en */
 310 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK            0x1
 311 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT           4
 312 /* rule23en */
 313 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK            0x1
 314 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT           5
 315 /* rule24en */
 316 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK            0x1
 317 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT           6
 318 /* rule25en */
 319 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK            0x1
 320 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT           7
 321         u8 flags14;
 322 /* bit16 */
 323 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK        0x1
 324 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT       0
 325 /* bit17 */
 326 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK      0x1
 327 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT     1
 328 /* bit18 */
 329 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK    0x1
 330 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT   2
 331 /* bit19 */
 332 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK    0x1
 333 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT   3
 334 /* bit20 */
 335 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK          0x1
 336 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT         4
 337 /* bit21 */
 338 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK        0x1
 339 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT       5
 340 /* cf23 */
 341 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK              0x3
 342 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT             6
 343         u8 edpm_event_id /* byte2 */;
 344         __le16 physical_q0 /* physical_q0 */;
 345         __le16 quota /* physical_q1 */;
 346         __le16 edpm_num_bds /* physical_q2 */;
 347         __le16 tx_bd_cons /* word3 */;
 348         __le16 tx_bd_prod /* word4 */;
 349         __le16 tx_class /* word5 */;
 350         __le16 conn_dpi /* conn_dpi */;
 351         u8 byte3 /* byte3 */;
 352         u8 byte4 /* byte4 */;
 353         u8 byte5 /* byte5 */;
 354         u8 byte6 /* byte6 */;
 355         __le32 reg0 /* reg0 */;
 356         __le32 reg1 /* reg1 */;
 357         __le32 reg2 /* reg2 */;
 358         __le32 reg3 /* reg3 */;
 359         __le32 reg4 /* reg4 */;
 360         __le32 reg5 /* cf_array0 */;
 361         __le32 reg6 /* cf_array1 */;
 362         __le16 word7 /* word7 */;
 363         __le16 word8 /* word8 */;
 364         __le16 word9 /* word9 */;
 365         __le16 word10 /* word10 */;
 366         __le32 reg7 /* reg7 */;
 367         __le32 reg8 /* reg8 */;
 368         __le32 reg9 /* reg9 */;
 369         u8 byte7 /* byte7 */;
 370         u8 byte8 /* byte8 */;
 371         u8 byte9 /* byte9 */;
 372         u8 byte10 /* byte10 */;
 373         u8 byte11 /* byte11 */;
 374         u8 byte12 /* byte12 */;
 375         u8 byte13 /* byte13 */;
 376         u8 byte14 /* byte14 */;
 377         u8 byte15 /* byte15 */;
 378         u8 byte16 /* byte16 */;
 379         __le16 word11 /* word11 */;
 380         __le32 reg10 /* reg10 */;
 381         __le32 reg11 /* reg11 */;
 382         __le32 reg12 /* reg12 */;
 383         __le32 reg13 /* reg13 */;
 384         __le32 reg14 /* reg14 */;
 385         __le32 reg15 /* reg15 */;
 386         __le32 reg16 /* reg16 */;
 387         __le32 reg17 /* reg17 */;
 388         __le32 reg18 /* reg18 */;
 389         __le32 reg19 /* reg19 */;
 390         __le16 word12 /* word12 */;
 391         __le16 word13 /* word13 */;
 392         __le16 word14 /* word14 */;
 393         __le16 word15 /* word15 */;
 394 };
 395
 396 /*
 397  * The eth storm context for the Ystorm
 398  */
 399 struct ystorm_eth_conn_st_ctx {
 400         __le32 reserved[8];
 401 };
 402
 403 struct ystorm_eth_conn_ag_ctx {
 404         u8 byte0 /* cdu_validation */;
 405         u8 state /* state */;
 406         u8 flags0;
 407 /* exist_in_qm0 */
 408 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK                  0x1
 409 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT                 0
 410 /* exist_in_qm1 */
 411 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK                  0x1
 412 #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT                 1
 413 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK     0x3 /* cf0 */
 414 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT    2
 415 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK      0x3 /* cf1 */
 416 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT     4
 417 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK                   0x3 /* cf2 */
 418 #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT                  6
 419         u8 flags1;
 420 /* cf0en */
 421 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK  0x1
 422 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
 423 /* cf1en */
 424 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK   0x1
 425 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT  1
 426 /* cf2en */
 427 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK                 0x1
 428 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                2
 429 /* rule0en */
 430 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK               0x1
 431 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT              3
 432 /* rule1en */
 433 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK               0x1
 434 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT              4
 435 /* rule2en */
 436 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK               0x1
 437 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT              5
 438 /* rule3en */
 439 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK               0x1
 440 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT              6
 441 /* rule4en */
 442 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK               0x1
 443 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT              7
 444         u8 tx_q0_int_coallecing_timeset /* byte2 */;
 445         u8 byte3 /* byte3 */;
 446         __le16 word0 /* word0 */;
 447         __le32 terminate_spqe /* reg0 */;
 448         __le32 reg1 /* reg1 */;
 449         __le16 tx_bd_cons_upd /* word1 */;
 450         __le16 word2 /* word2 */;
 451         __le16 word3 /* word3 */;
 452         __le16 word4 /* word4 */;
 453         __le32 reg2 /* reg2 */;
 454         __le32 reg3 /* reg3 */;
 455 };
 456
 457 struct tstorm_eth_conn_ag_ctx {
 458         u8 byte0 /* cdu_validation */;
 459         u8 byte1 /* state */;
 460         u8 flags0;
 461 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK      0x1 /* exist_in_qm0 */
 462 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT     0
 463 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK      0x1 /* exist_in_qm1 */
 464 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT     1
 465 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK      0x1 /* bit2 */
 466 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT     2
 467 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK      0x1 /* bit3 */
 468 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT     3
 469 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK      0x1 /* bit4 */
 470 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT     4
 471 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK      0x1 /* bit5 */
 472 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT     5
 473 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK       0x3 /* timer0cf */
 474 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT      6
 475         u8 flags1;
 476 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK       0x3 /* timer1cf */
 477 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT      0
 478 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK       0x3 /* timer2cf */
 479 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT      2
 480 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK       0x3 /* timer_stop_all */
 481 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT      4
 482 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK       0x3 /* cf4 */
 483 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT      6
 484         u8 flags2;
 485 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK       0x3 /* cf5 */
 486 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT      0
 487 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK       0x3 /* cf6 */
 488 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT      2
 489 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK       0x3 /* cf7 */
 490 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT      4
 491 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK       0x3 /* cf8 */
 492 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT      6
 493         u8 flags3;
 494 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK       0x3 /* cf9 */
 495 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT      0
 496 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK      0x3 /* cf10 */
 497 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT     2
 498 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK     0x1 /* cf0en */
 499 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT    4
 500 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK     0x1 /* cf1en */
 501 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT    5
 502 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK     0x1 /* cf2en */
 503 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT    6
 504 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK     0x1 /* cf3en */
 505 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT    7
 506         u8 flags4;
 507 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK     0x1 /* cf4en */
 508 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT    0
 509 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK     0x1 /* cf5en */
 510 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT    1
 511 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK     0x1 /* cf6en */
 512 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT    2
 513 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK     0x1 /* cf7en */
 514 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT    3
 515 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK     0x1 /* cf8en */
 516 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT    4
 517 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK     0x1 /* cf9en */
 518 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT    5
 519 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK    0x1 /* cf10en */
 520 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT   6
 521 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK   0x1 /* rule0en */
 522 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT  7
 523         u8 flags5;
 524 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK   0x1 /* rule1en */
 525 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT  0
 526 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK   0x1 /* rule2en */
 527 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT  1
 528 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK   0x1 /* rule3en */
 529 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT  2
 530 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK   0x1 /* rule4en */
 531 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT  3
 532 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK   0x1 /* rule5en */
 533 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT  4
 534 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK  0x1 /* rule6en */
 535 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
 536 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK   0x1 /* rule7en */
 537 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT  6
 538 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK   0x1 /* rule8en */
 539 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT  7
 540         __le32 reg0 /* reg0 */;
 541         __le32 reg1 /* reg1 */;
 542         __le32 reg2 /* reg2 */;
 543         __le32 reg3 /* reg3 */;
 544         __le32 reg4 /* reg4 */;
 545         __le32 reg5 /* reg5 */;
 546         __le32 reg6 /* reg6 */;
 547         __le32 reg7 /* reg7 */;
 548         __le32 reg8 /* reg8 */;
 549         u8 byte2 /* byte2 */;
 550         u8 byte3 /* byte3 */;
 551         __le16 rx_bd_cons /* word0 */;
 552         u8 byte4 /* byte4 */;
 553         u8 byte5 /* byte5 */;
 554         __le16 rx_bd_prod /* word1 */;
 555         __le16 word2 /* conn_dpi */;
 556         __le16 word3 /* word3 */;
 557         __le32 reg9 /* reg9 */;
 558         __le32 reg10 /* reg10 */;
 559 };
 560
 561 struct ustorm_eth_conn_ag_ctx {
 562         u8 byte0 /* cdu_validation */;
 563         u8 byte1 /* state */;
 564         u8 flags0;
 565 /* exist_in_qm0 */
 566 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK                    0x1
 567 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT                   0
 568 /* exist_in_qm1 */
 569 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK                    0x1
 570 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT                   1
 571 /* timer0cf */
 572 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK     0x3
 573 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT    2
 574 /* timer1cf */
 575 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK     0x3
 576 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT    4
 577 /* timer2cf */
 578 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK                     0x3
 579 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT                    6
 580         u8 flags1;
 581 /* timer_stop_all */
 582 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK                     0x3
 583 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT                    0
 584 /* cf4 */
 585 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK               0x3
 586 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT              2
 587 /* cf5 */
 588 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK               0x3
 589 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT              4
 590 /* cf6 */
 591 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK       0x3
 592 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT      6
 593         u8 flags2;
 594 /* cf0en */
 595 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK  0x1
 596 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
 597 /* cf1en */
 598 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK  0x1
 599 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
 600 /* cf2en */
 601 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK                   0x1
 602 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                  2
 603 /* cf3en */
 604 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK                   0x1
 605 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT                  3
 606 /* cf4en */
 607 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK            0x1
 608 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT           4
 609 /* cf5en */
 610 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK            0x1
 611 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT           5
 612 /* cf6en */
 613 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK    0x1
 614 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT   6
 615 /* rule0en */
 616 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK                 0x1
 617 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT                7
 618         u8 flags3;
 619 /* rule1en */
 620 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK                 0x1
 621 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT                0
 622 /* rule2en */
 623 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK                 0x1
 624 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT                1
 625 /* rule3en */
 626 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK                 0x1
 627 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT                2
 628 /* rule4en */
 629 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK                 0x1
 630 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT                3
 631 /* rule5en */
 632 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK                 0x1
 633 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT                4
 634 /* rule6en */
 635 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK                 0x1
 636 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT                5
 637 /* rule7en */
 638 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK                 0x1
 639 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT                6
 640 /* rule8en */
 641 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK                 0x1
 642 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT                7
 643         u8 byte2 /* byte2 */;
 644         u8 byte3 /* byte3 */;
 645         __le16 word0 /* conn_dpi */;
 646         __le16 tx_bd_cons /* word1 */;
 647         __le32 reg0 /* reg0 */;
 648         __le32 reg1 /* reg1 */;
 649         __le32 reg2 /* reg2 */;
 650         __le32 tx_int_coallecing_timeset /* reg3 */;
 651         __le16 tx_drv_bd_cons /* word2 */;
 652         __le16 rx_drv_cqe_cons /* word3 */;
 653 };
 654
 655 /*
 656  * The eth storm context for the Ustorm
 657  */
 658 struct ustorm_eth_conn_st_ctx {
 659         __le32 reserved[40];
 660 };
 661
 662 /*
 663  * The eth storm context for the Mstorm
 664  */
 665 struct mstorm_eth_conn_st_ctx {
 666         __le32 reserved[8];
 667 };
 668
 669 /*
 670  * eth connection context
 671  */
 672 struct eth_conn_context {
 673 /* tstorm storm context */
 674         struct tstorm_eth_conn_st_ctx tstorm_st_context;
 675         struct regpair tstorm_st_padding[2] /* padding */;
 676 /* pstorm storm context */
 677         struct pstorm_eth_conn_st_ctx pstorm_st_context;
 678 /* xstorm storm context */
 679         struct xstorm_eth_conn_st_ctx xstorm_st_context;
 680 /* xstorm aggregative context */
 681         struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
 682 /* ystorm storm context */
 683         struct ystorm_eth_conn_st_ctx ystorm_st_context;
 684 /* ystorm aggregative context */
 685         struct ystorm_eth_conn_ag_ctx ystorm_ag_context;
 686 /* tstorm aggregative context */
 687         struct tstorm_eth_conn_ag_ctx tstorm_ag_context;
 688 /* ustorm aggregative context */
 689         struct ustorm_eth_conn_ag_ctx ustorm_ag_context;
 690 /* ustorm storm context */
 691         struct ustorm_eth_conn_st_ctx ustorm_st_context;
 692 /* mstorm storm context */
 693         struct mstorm_eth_conn_st_ctx mstorm_st_context;
 694 };
 695
 696
 697 /*
 698  * Ethernet filter types: mac/vlan/pair
 699  */
 700 enum eth_error_code {
 701         ETH_OK = 0x00 /* command succeeded */,
 702 /* mac add filters command failed due to cam full state */
 703         ETH_FILTERS_MAC_ADD_FAIL_FULL,
 704 /* mac add filters command failed due to mtt2 full state */
 705         ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
 706 /* mac add filters command failed due to duplicate mac address */
 707         ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
 708 /* mac add filters command failed due to duplicate mac address */
 709         ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
 710 /* mac delete filters command failed due to not found state */
 711         ETH_FILTERS_MAC_DEL_FAIL_NOF,
 712 /* mac delete filters command failed due to not found state */
 713         ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
 714 /* mac delete filters command failed due to not found state */
 715         ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
 716 /* mac add filters command failed due to MAC Address of 00:00:00:00:00:00 */
 717         ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
 718 /* vlan add filters command failed due to cam full state */
 719         ETH_FILTERS_VLAN_ADD_FAIL_FULL,
 720 /* vlan add filters command failed due to duplicate VLAN filter */
 721         ETH_FILTERS_VLAN_ADD_FAIL_DUP,
 722 /* vlan delete filters command failed due to not found state */
 723         ETH_FILTERS_VLAN_DEL_FAIL_NOF,
 724 /* vlan delete filters command failed due to not found state */
 725         ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
 726 /* pair add filters command failed due to duplicate request */
 727         ETH_FILTERS_PAIR_ADD_FAIL_DUP,
 728 /* pair add filters command failed due to full state */
 729         ETH_FILTERS_PAIR_ADD_FAIL_FULL,
 730 /* pair add filters command failed due to full state */
 731         ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
 732 /* pair add filters command failed due not found state */
 733         ETH_FILTERS_PAIR_DEL_FAIL_NOF,
 734 /* pair add filters command failed due not found state */
 735         ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
 736 /* pair add filters command failed due to MAC Address of 00:00:00:00:00:00 */
 737         ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
 738 /* vni add filters command failed due to cam full state */
 739         ETH_FILTERS_VNI_ADD_FAIL_FULL,
 740 /* vni add filters command failed due to duplicate VNI filter */
 741         ETH_FILTERS_VNI_ADD_FAIL_DUP,
 742         MAX_ETH_ERROR_CODE
 743 };
 744
 745
 746 /*
 747  * opcodes for the event ring
 748  */
 749 enum eth_event_opcode {
 750         ETH_EVENT_UNUSED,
 751         ETH_EVENT_VPORT_START,
 752         ETH_EVENT_VPORT_UPDATE,
 753         ETH_EVENT_VPORT_STOP,
 754         ETH_EVENT_TX_QUEUE_START,
 755         ETH_EVENT_TX_QUEUE_STOP,
 756         ETH_EVENT_RX_QUEUE_START,
 757         ETH_EVENT_RX_QUEUE_UPDATE,
 758         ETH_EVENT_RX_QUEUE_STOP,
 759         ETH_EVENT_FILTERS_UPDATE,
 760         ETH_EVENT_RX_ADD_OPENFLOW_FILTER,
 761         ETH_EVENT_RX_DELETE_OPENFLOW_FILTER,
 762         ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
 763         ETH_EVENT_RX_ADD_UDP_FILTER,
 764         ETH_EVENT_RX_DELETE_UDP_FILTER,
 765         ETH_EVENT_RX_CREATE_GFT_ACTION,
 766         ETH_EVENT_RX_GFT_UPDATE_FILTER,
 767         MAX_ETH_EVENT_OPCODE
 768 };
 769
 770
 771 /*
 772  * Classify rule types in E2/E3
 773  */
 774 enum eth_filter_action {
 775         ETH_FILTER_ACTION_UNUSED,
 776         ETH_FILTER_ACTION_REMOVE,
 777         ETH_FILTER_ACTION_ADD,
 778 /* Remove all filters of given type and vport ID. */
 779         ETH_FILTER_ACTION_REMOVE_ALL,
 780         MAX_ETH_FILTER_ACTION
 781 };
 782
 783
 784 /*
 785  * Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$
 786  */
 787 struct eth_filter_cmd {
 788         u8 type /* Filter Type (MAC/VLAN/Pair/VNI) */;
 789         u8 vport_id /* the vport id */;
 790         u8 action /* filter command action: add/remove/replace */;
 791         u8 reserved0;
 792         __le32 vni;
 793         __le16 mac_lsb;
 794         __le16 mac_mid;
 795         __le16 mac_msb;
 796         __le16 vlan_id;
 797 };
 798
 799
 800 /*
 801  *  $$KEEP_ENDIANNESS$$
 802  */
 803 struct eth_filter_cmd_header {
 804         u8 rx /* If set, apply these commands to the RX path */;
 805         u8 tx /* If set, apply these commands to the TX path */;
 806         u8 cmd_cnt /* Number of filter commands */;
 807 /* 0 - dont assert in case of filter configuration error. Just return an error
 808  * code. 1 - assert in case of filter configuration error.
 809  */
 810         u8 assert_on_error;
 811         u8 reserved1[4];
 812 };
 813
 814
 815 /*
 816  * Ethernet filter types: mac/vlan/pair
 817  */
 818 enum eth_filter_type {
 819         ETH_FILTER_TYPE_UNUSED,
 820         ETH_FILTER_TYPE_MAC /* Add/remove a MAC address */,
 821         ETH_FILTER_TYPE_VLAN /* Add/remove a VLAN */,
 822         ETH_FILTER_TYPE_PAIR /* Add/remove a MAC-VLAN pair */,
 823         ETH_FILTER_TYPE_INNER_MAC /* Add/remove a inner MAC address */,
 824         ETH_FILTER_TYPE_INNER_VLAN /* Add/remove a inner VLAN */,
 825         ETH_FILTER_TYPE_INNER_PAIR /* Add/remove a inner MAC-VLAN pair */,
 826 /* Add/remove a inner MAC-VNI pair */
 827         ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
 828         ETH_FILTER_TYPE_MAC_VNI_PAIR /* Add/remove a MAC-VNI pair */,
 829         ETH_FILTER_TYPE_VNI /* Add/remove a VNI */,
 830         MAX_ETH_FILTER_TYPE
 831 };
 832
 833
 834 /*
 835  * eth IPv4 Fragment Type
 836  */
 837 enum eth_ipv4_frag_type {
 838         ETH_IPV4_NOT_FRAG /* IPV4 Packet Not Fragmented */,
 839 /* First Fragment of IPv4 Packet (contains headers) */
 840         ETH_IPV4_FIRST_FRAG,
 841 /* Non-First Fragment of IPv4 Packet (does not contain headers) */
 842         ETH_IPV4_NON_FIRST_FRAG,
 843         MAX_ETH_IPV4_FRAG_TYPE
 844 };
 845
 846
 847 /*
 848  * eth IPv4 Fragment Type
 849  */
 850 enum eth_ip_type {
 851         ETH_IPV4 /* IPv4 */,
 852         ETH_IPV6 /* IPv6 */,
 853         MAX_ETH_IP_TYPE
 854 };
 855
 856
 857 /*
 858  * Ethernet Ramrod Command IDs
 859  */
 860 enum eth_ramrod_cmd_id {
 861         ETH_RAMROD_UNUSED,
 862         ETH_RAMROD_VPORT_START /* VPort Start Ramrod */,
 863         ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */,
 864         ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */,
 865         ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
 866         ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
 867         ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
 868         ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
 869         ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */,
 870         ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */,
 871 /* RX - Create an Openflow Action */
 872         ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
 873 /* RX - Add an Openflow Filter to the Searcher */
 874         ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
 875 /* RX - Delete an Openflow Filter to the Searcher */
 876         ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
 877 /* RX - Add a UDP Filter to the Searcher */
 878         ETH_RAMROD_RX_ADD_UDP_FILTER,
 879 /* RX - Delete a UDP Filter to the Searcher */
 880         ETH_RAMROD_RX_DELETE_UDP_FILTER,
 881         ETH_RAMROD_RX_CREATE_GFT_ACTION /* RX - Create a Gft Action */,
 882 /* RX - Add/Delete a GFT Filter to the Searcher */
 883         ETH_RAMROD_GFT_UPDATE_FILTER,
 884         MAX_ETH_RAMROD_CMD_ID
 885 };
 886
 887
 888 /*
 889  * return code from eth sp ramrods
 890  */
 891 struct eth_return_code {
 892         u8 value;
 893 /* error code (use enum eth_error_code) */
 894 #define ETH_RETURN_CODE_ERR_CODE_MASK  0x1F
 895 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
 896 #define ETH_RETURN_CODE_RESERVED_MASK  0x3
 897 #define ETH_RETURN_CODE_RESERVED_SHIFT 5
 898 /* rx path - 0, tx path - 1 */
 899 #define ETH_RETURN_CODE_RX_TX_MASK     0x1
 900 #define ETH_RETURN_CODE_RX_TX_SHIFT    7
 901 };
 902
 903
 904 /*
 905  * What to do in case an error occurs
 906  */
 907 enum eth_tx_err {
 908         ETH_TX_ERR_DROP /* Drop erroneous packet. */,
 909 /* Assert an interrupt for PF, declare as malicious for VF */
 910         ETH_TX_ERR_ASSERT_MALICIOUS,
 911         MAX_ETH_TX_ERR
 912 };
 913
 914
 915 /*
 916  * Array of the different error type behaviors
 917  */
 918 struct eth_tx_err_vals {
 919         __le16 values;
 920 /* Wrong VLAN insertion mode (use enum eth_tx_err) */
 921 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK            0x1
 922 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT           0
 923 /* Packet is below minimal size (use enum eth_tx_err) */
 924 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK             0x1
 925 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT            1
 926 /* Vport has sent spoofed packet (use enum eth_tx_err) */
 927 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK            0x1
 928 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT           2
 929 /* Packet with illegal type of inband tag (use enum eth_tx_err) */
 930 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK          0x1
 931 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT         3
 932 /* Packet marked for VLAN insertion when inband tag is present
 933  * (use enum eth_tx_err)
 934  */
 935 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK  0x1
 936 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
 937 /* Non LSO packet larger than MTU (use enum eth_tx_err) */
 938 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK                0x1
 939 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT               5
 940 /* VF/PF has sent LLDP/PFC or any other type of control packet which is not
 941  * allowed to (use enum eth_tx_err)
 942  */
 943 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK        0x1
 944 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT       6
 945 #define ETH_TX_ERR_VALS_RESERVED_MASK                     0x1FF
 946 #define ETH_TX_ERR_VALS_RESERVED_SHIFT                    7
 947 };
 948
 949
 950 /*
 951  * vport rss configuration data
 952  */
 953 struct eth_vport_rss_config {
 954         __le16 capabilities;
 955 /* configuration of the IpV4 2-tuple capability */
 956 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK        0x1
 957 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT       0
 958 /* configuration of the IpV6 2-tuple capability */
 959 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK        0x1
 960 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT       1
 961 /* configuration of the IpV4 4-tuple capability for TCP */
 962 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK    0x1
 963 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT   2
 964 /* configuration of the IpV6 4-tuple capability for TCP */
 965 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK    0x1
 966 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT   3
 967 /* configuration of the IpV4 4-tuple capability for UDP */
 968 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK    0x1
 969 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT   4
 970 /* configuration of the IpV6 4-tuple capability for UDP */
 971 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK    0x1
 972 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT   5
 973 /* configuration of the 5-tuple capability */
 974 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK  0x1
 975 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
 976 /* if set update the rss keys */
 977 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK              0x1FF
 978 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT             7
 979 /* The RSS engine ID. Must be allocated to each vport with RSS enabled.
 980  * Total number of RSS engines is ETH_RSS_ENGINE_NUM_ , according to chip type.
 981  */
 982         u8 rss_id;
 983         u8 rss_mode /* The RSS mode for this function */;
 984         u8 update_rss_key /* if set update the rss key */;
 985         u8 update_rss_ind_table /* if set update the indirection table */;
 986         u8 update_rss_capabilities /* if set update the capabilities */;
 987         u8 tbl_size /* rss mask (Tbl size) */;
 988         __le32 reserved2[2];
 989 /* RSS indirection table */
 990         __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
 991 /* RSS key supplied to us by OS */
 992         __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
 993         __le32 reserved3[2];
 994 };
 995
 996
 997 /*
 998  * eth vport RSS mode
 999  */
1000 enum eth_vport_rss_mode {
1001         ETH_VPORT_RSS_MODE_DISABLED /* RSS Disabled */,
1002         ETH_VPORT_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */,
1003         MAX_ETH_VPORT_RSS_MODE
1004 };
1005
1006
1007 /*
1008  * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$
1009  */
1010 struct eth_vport_rx_mode {
1011         __le16 state;
1012 /* drop all unicast packets */
1013 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK          0x1
1014 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT         0
1015 /* accept all unicast packets (subject to vlan) */
1016 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK        0x1
1017 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT       1
1018 /* accept all unmatched unicast packets */
1019 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK  0x1
1020 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
1021 /* drop all multicast packets */
1022 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK          0x1
1023 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT         3
1024 /* accept all multicast packets (subject to vlan) */
1025 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK        0x1
1026 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT       4
1027 /* accept all broadcast packets (subject to vlan) */
1028 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK        0x1
1029 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT       5
1030 #define ETH_VPORT_RX_MODE_RESERVED1_MASK               0x3FF
1031 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT              6
1032         __le16 reserved2[3];
1033 };
1034
1035
1036 /*
1037  * Command for setting tpa parameters
1038  */
1039 struct eth_vport_tpa_param {
1040         u8 tpa_ipv4_en_flg /* Enable TPA for IPv4 packets */;
1041         u8 tpa_ipv6_en_flg /* Enable TPA for IPv6 packets */;
1042         u8 tpa_ipv4_tunn_en_flg /* Enable TPA for IPv4 over tunnel */;
1043         u8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */;
1044 /* If set, start each tpa segment on new SGE (GRO mode). One SGE per segment
1045  * allowed
1046  */
1047         u8 tpa_pkt_split_flg;
1048 /* If set, put header of first TPA segment on bd and data on SGE */
1049         u8 tpa_hdr_data_split_flg;
1050 /* If set, GRO data consistent will checked for TPA continue */
1051         u8 tpa_gro_consistent_flg;
1052 /* maximum number of opened aggregations per v-port  */
1053         u8 tpa_max_aggs_num;
1054         __le16 tpa_max_size /* maximal size for the aggregated TPA packets */;
1055 /* minimum TCP payload size for a packet to start aggregation */
1056         __le16 tpa_min_size_to_start;
1057 /* minimum TCP payload size for a packet to continue aggregation */
1058         __le16 tpa_min_size_to_cont;
1059 /* maximal number of buffers that can be used for one aggregation */
1060         u8 max_buff_num;
1061         u8 reserved;
1062 };
1063
1064
1065 /*
1066  * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$
1067  */
1068 struct eth_vport_tx_mode {
1069         __le16 state;
1070 /* drop all unicast packets */
1071 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK    0x1
1072 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT   0
1073 /* accept all unicast packets (subject to vlan) */
1074 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK  0x1
1075 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
1076 /* drop all multicast packets */
1077 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK    0x1
1078 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT   2
1079 /* accept all multicast packets (subject to vlan) */
1080 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK  0x1
1081 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
1082 /* accept all broadcast packets (subject to vlan) */
1083 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK  0x1
1084 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
1085 #define ETH_VPORT_TX_MODE_RESERVED1_MASK         0x7FF
1086 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT        5
1087         __le16 reserved2[3];
1088 };
1089
1090
1091 /*
1092  * Ramrod data for rx create gft action
1093  */
1094 enum gft_filter_update_action {
1095         GFT_ADD_FILTER,
1096         GFT_DELETE_FILTER,
1097         MAX_GFT_FILTER_UPDATE_ACTION
1098 };
1099
1100
1101 /*
1102  * Ramrod data for rx create gft action
1103  */
1104 enum gft_logic_filter_type {
1105         GFT_FILTER_TYPE /* flow FW is GFT-logic as well */,
1106         RFS_FILTER_TYPE /* flow FW is A-RFS-logic */,
1107         MAX_GFT_LOGIC_FILTER_TYPE
1108 };
1109
1110
1111
1112
1113 /*
1114  * Ramrod data for rx add openflow filter
1115  */
1116 struct rx_add_openflow_filter_data {
1117         __le16 action_icid /* CID of Action to run for this filter */;
1118         u8 priority /* Searcher String - Packet priority */;
1119         u8 reserved0;
1120         __le32 tenant_id /* Searcher String - Tenant ID */;
1121 /* Searcher String - Destination Mac Bytes 0 to 1 */
1122         __le16 dst_mac_hi;
1123 /* Searcher String - Destination Mac Bytes 2 to 3 */
1124         __le16 dst_mac_mid;
1125 /* Searcher String - Destination Mac Bytes 4 to 5 */
1126         __le16 dst_mac_lo;
1127         __le16 src_mac_hi /* Searcher String - Source Mac 0 to 1 */;
1128         __le16 src_mac_mid /* Searcher String - Source Mac 2 to 3 */;
1129         __le16 src_mac_lo /* Searcher String - Source Mac 4 to 5 */;
1130         __le16 vlan_id /* Searcher String - Vlan ID */;
1131         __le16 l2_eth_type /* Searcher String - Last L2 Ethertype */;
1132         u8 ipv4_dscp /* Searcher String - IPv4 6 MSBs of the TOS Field */;
1133         u8 ipv4_frag_type /* Searcher String - IPv4 Fragmentation Type */;
1134         u8 ipv4_over_ip /* Searcher String - IPv4 Over IP Type */;
1135         u8 tenant_id_exists /* Searcher String - Tenant ID Exists */;
1136         __le32 ipv4_dst_addr /* Searcher String - IPv4 Destination Address */;
1137         __le32 ipv4_src_addr /* Searcher String - IPv4 Source Address */;
1138         __le16 l4_dst_port /* Searcher String - TCP/UDP Destination Port */;
1139         __le16 l4_src_port /* Searcher String - TCP/UDP Source Port */;
1140 };
1141
1142
1143 /*
1144  * Ramrod data for rx create gft action
1145  */
1146 struct rx_create_gft_action_data {
1147         u8 vport_id /* Vport Id of GFT Action  */;
1148         u8 reserved[7];
1149 };
1150
1151
1152 /*
1153  * Ramrod data for rx create openflow action
1154  */
1155 struct rx_create_openflow_action_data {
1156         u8 vport_id /* ID of RX queue */;
1157         u8 reserved[7];
1158 };
1159
1160
1161 /*
1162  * Ramrod data for rx queue start ramrod
1163  */
1164 struct rx_queue_start_ramrod_data {
1165         __le16 rx_queue_id /* ID of RX queue */;
1166         __le16 num_of_pbl_pages /* Num of pages in CQE PBL */;
1167         __le16 bd_max_bytes /* maximal bytes that can be places on the bd */;
1168         __le16 sb_id /* Status block ID */;
1169         u8 sb_index /* index of the protocol index */;
1170         u8 vport_id /* ID of virtual port */;
1171         u8 default_rss_queue_flg /* set queue as default rss queue if set */;
1172         u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1173         u8 complete_event_flg /* post completion to the event ring if set */;
1174         u8 stats_counter_id /* Statistics counter ID */;
1175         u8 pin_context /* Pin context in CCFC to improve performance */;
1176         u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD/SGE fetch */;
1177 /* PXP command TPH Valid - for packet placement */
1178         u8 pxp_tph_valid_pkt;
1179 /* PXP command Steering tag hint. Use enum pxp_tph_st_hint */
1180         u8 pxp_st_hint;
1181         __le16 pxp_st_index /* PXP command Steering tag index */;
1182 /* Indicates that current queue belongs to poll-mode driver */
1183         u8 pmd_mode;
1184 /* Indicates that the current queue is using the TX notification queue
1185  * mechanism - should be set only for PMD queue
1186  */
1187         u8 notify_en;
1188 /* Initial value for the toggle valid bit - used in PMD mode */
1189         u8 toggle_val;
1190 /* Index of RX producers in VF zone. Used for VF only. */
1191         u8 vf_rx_prod_index;
1192 /* Backward compatibility mode. If set, unprotected mStorm queue zone will used
1193  * for VF RX producers instead of VF zone.
1194  */
1195         u8 vf_rx_prod_use_zone_a;
1196         u8 reserved[5];
1197         __le16 reserved1 /* FW reserved. */;
1198         struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */;
1199         struct regpair bd_base /* bd address of the first bd page */;
1200         struct regpair reserved2 /* FW reserved. */;
1201 };
1202
1203
1204 /*
1205  * Ramrod data for rx queue stop ramrod
1206  */
1207 struct rx_queue_stop_ramrod_data {
1208         __le16 rx_queue_id /* ID of RX queue */;
1209         u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1210         u8 complete_event_flg /* post completion to the event ring if set */;
1211         u8 vport_id /* ID of virtual port */;
1212         u8 reserved[3];
1213 };
1214
1215
1216 /*
1217  * Ramrod data for rx queue update ramrod
1218  */
1219 struct rx_queue_update_ramrod_data {
1220         __le16 rx_queue_id /* ID of RX queue */;
1221         u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1222         u8 complete_event_flg /* post completion to the event ring if set */;
1223         u8 vport_id /* ID of virtual port */;
1224         u8 reserved[4];
1225         u8 reserved1 /* FW reserved. */;
1226         u8 reserved2 /* FW reserved. */;
1227         u8 reserved3 /* FW reserved. */;
1228         __le16 reserved4 /* FW reserved. */;
1229         __le16 reserved5 /* FW reserved. */;
1230         struct regpair reserved6 /* FW reserved. */;
1231 };
1232
1233
1234 /*
1235  * Ramrod data for rx Add UDP Filter
1236  */
1237 struct rx_udp_filter_data {
1238         __le16 action_icid /* CID of Action to run for this filter */;
1239         __le16 vlan_id /* Searcher String - Vlan ID */;
1240         u8 ip_type /* Searcher String - IP Type */;
1241         u8 tenant_id_exists /* Searcher String - Tenant ID Exists */;
1242         __le16 reserved1;
1243 /* Searcher String - IP Destination Address, for IPv4 use ip_dst_addr[0] only */
1244         __le32 ip_dst_addr[4];
1245 /* Searcher String - IP Source Address, for IPv4 use ip_dst_addr[0] only */
1246         __le32 ip_src_addr[4];
1247         __le16 udp_dst_port /* Searcher String - UDP Destination Port */;
1248         __le16 udp_src_port /* Searcher String - UDP Source Port */;
1249         __le32 tenant_id /* Searcher String - Tenant ID */;
1250 };
1251
1252
1253 /*
1254  * Ramrod to add filter - filter is packet headr of type of packet wished to
1255  * pass certin FW flow
1256  */
1257 struct rx_update_gft_filter_data {
1258 /* Pointer to Packet Header That Defines GFT Filter */
1259         struct regpair pkt_hdr_addr;
1260         __le16 pkt_hdr_length /* Packet Header Length */;
1261 /* If is_rfs flag is set: Queue Id to associate filter with else: action icid */
1262         __le16 rx_qid_or_action_icid;
1263 /* Field is used if is_rfs flag is set: vport Id of which to associate filter
1264  * with
1265  */
1266         u8 vport_id;
1267 /* Use enum to set type of flow using gft HW logic blocks */
1268         u8 filter_type;
1269         u8 filter_action /* Use to set type of action on filter */;
1270         u8 reserved;
1271 };
1272
1273
1274
1275 /*
1276  * Ramrod data for tx queue start ramrod
1277  */
1278 struct tx_queue_start_ramrod_data {
1279         __le16 sb_id /* Status block ID */;
1280         u8 sb_index /* Status block protocol index */;
1281         u8 vport_id /* VPort ID */;
1282         u8 reserved0 /* FW reserved. (qcn_rl_en) */;
1283         u8 stats_counter_id /* Statistics counter ID to use */;
1284         __le16 qm_pq_id /* QM PQ ID */;
1285         u8 flags;
1286 /* 0: Enable QM opportunistic flow. 1: Disable QM opportunistic flow */
1287 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK  0x1
1288 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
1289 /* If set, Test Mode - packets will be duplicated by Xstorm handler */
1290 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK      0x1
1291 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT     1
1292 /* If set, Test Mode - packets destination will be determined by dest_port_mode
1293  * field from Tx BD
1294  */
1295 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK      0x1
1296 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT     2
1297 /* Indicates that current queue belongs to poll-mode driver */
1298 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK               0x1
1299 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT              3
1300 /* Indicates that the current queue is using the TX notification queue
1301  * mechanism - should be set only for PMD queue
1302  */
1303 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK              0x1
1304 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT             4
1305 /* Pin context in CCFC to improve performance */
1306 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK            0x1
1307 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT           5
1308 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK              0x3
1309 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT             6
1310         u8 pxp_st_hint /* PXP command Steering tag hint */;
1311         u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD fetch */;
1312         u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet fetch */;
1313         __le16 pxp_st_index /* PXP command Steering tag index */;
1314 /* TX completion min agg size - for PMD queues */
1315         __le16 comp_agg_size;
1316         __le16 queue_zone_id /* queue zone ID to use */;
1317         __le16 reserved2 /* FW reserved. (test_dup_count) */;
1318         __le16 pbl_size /* Number of BD pages pointed by PBL */;
1319 /* unique Queue ID - currently used only by PMD flow */
1320         __le16 tx_queue_id;
1321 /* Unique Same-As-Last Resource ID - improves performance for same-as-last
1322  * packets per connection (range 0..ETH_TX_NUM_SAME_AS_LAST_ENTRIES-1 IDs
1323  * available)
1324  */
1325         __le16 same_as_last_id;
1326         __le16 reserved[3];
1327         struct regpair pbl_base_addr /* address of the pbl page */;
1328 /* BD consumer address in host - for PMD queues */
1329         struct regpair bd_cons_address;
1330 };
1331
1332
1333 /*
1334  * Ramrod data for tx queue stop ramrod
1335  */
1336 struct tx_queue_stop_ramrod_data {
1337         __le16 reserved[4];
1338 };
1339
1340
1341
1342 /*
1343  * Ramrod data for vport update ramrod
1344  */
1345 struct vport_filter_update_ramrod_data {
1346 /* Header for Filter Commands (RX/TX, Add/Remove/Replace, etc) */
1347         struct eth_filter_cmd_header filter_cmd_hdr;
1348 /* Filter Commands */
1349         struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
1350 };
1351
1352
1353 /*
1354  * Ramrod data for vport start ramrod
1355  */
1356 struct vport_start_ramrod_data {
1357         u8 vport_id;
1358         u8 sw_fid;
1359         __le16 mtu;
1360         u8 drop_ttl0_en /* if set, drop packet with ttl=0 */;
1361         u8 inner_vlan_removal_en;
1362         struct eth_vport_rx_mode rx_mode /* Rx filter data */;
1363         struct eth_vport_tx_mode tx_mode /* Tx filter data */;
1364 /* TPA configuration parameters */
1365         struct eth_vport_tpa_param tpa_param;
1366         __le16 default_vlan /* Default Vlan value to be forced by FW */;
1367         u8 tx_switching_en /* Tx switching is enabled for current Vport */;
1368 /* Anti-spoofing verification is set for current Vport */
1369         u8 anti_spoofing_en;
1370 /* If set, the default Vlan value is forced by the FW */
1371         u8 default_vlan_en;
1372 /* If set, the vport handles PTP Timesync Packets */
1373         u8 handle_ptp_pkts;
1374 /* If enable then innerVlan will be striped and not written to cqe */
1375         u8 silent_vlan_removal_en;
1376 /* If set untagged filter (vlan0) is added to current Vport, otherwise port is
1377  * marked as any-vlan
1378  */
1379         u8 untagged;
1380 /* Desired behavior per TX error type */
1381         struct eth_tx_err_vals tx_err_behav;
1382 /* If set, ETH header padding will not inserted. placement_offset will be zero.
1383  */
1384         u8 zero_placement_offset;
1385 /* If set, Contorl frames will be filtered according to MAC check. */
1386         u8 ctl_frame_mac_check_en;
1387 /* If set, Contorl frames will be filtered according to ethtype check. */
1388         u8 ctl_frame_ethtype_check_en;
1389         u8 reserved[5];
1390 };
1391
1392
1393 /*
1394  * Ramrod data for vport stop ramrod
1395  */
1396 struct vport_stop_ramrod_data {
1397         u8 vport_id;
1398         u8 reserved[7];
1399 };
1400
1401
1402 /*
1403  * Ramrod data for vport update ramrod
1404  */
1405 struct vport_update_ramrod_data_cmn {
1406         u8 vport_id;
1407         u8 update_rx_active_flg /* set if rx active flag should be handled */;
1408         u8 rx_active_flg /* rx active flag value */;
1409         u8 update_tx_active_flg /* set if tx active flag should be handled */;
1410         u8 tx_active_flg /* tx active flag value */;
1411         u8 update_rx_mode_flg /* set if rx state data should be handled */;
1412         u8 update_tx_mode_flg /* set if tx state data should be handled */;
1413 /* set if approx. mcast data should be handled */
1414         u8 update_approx_mcast_flg;
1415         u8 update_rss_flg /* set if rss data should be handled  */;
1416 /* set if inner_vlan_removal_en should be handled */
1417         u8 update_inner_vlan_removal_en_flg;
1418         u8 inner_vlan_removal_en;
1419 /* set if tpa parameters should be handled, TPA must be disable before */
1420         u8 update_tpa_param_flg;
1421         u8 update_tpa_en_flg /* set if tpa enable changes */;
1422 /* set if tx switching en flag should be handled */
1423         u8 update_tx_switching_en_flg;
1424         u8 tx_switching_en /* tx switching en value */;
1425 /* set if anti spoofing flag should be handled */
1426         u8 update_anti_spoofing_en_flg;
1427         u8 anti_spoofing_en /* Anti-spoofing verification en value */;
1428 /* set if handle_ptp_pkts should be handled. */
1429         u8 update_handle_ptp_pkts;
1430 /* If set, the vport handles PTP Timesync Packets */
1431         u8 handle_ptp_pkts;
1432 /* If set, the default Vlan enable flag is updated */
1433         u8 update_default_vlan_en_flg;
1434 /* If set, the default Vlan value is forced by the FW */
1435         u8 default_vlan_en;
1436 /* If set, the default Vlan value is updated */
1437         u8 update_default_vlan_flg;
1438         __le16 default_vlan /* Default Vlan value to be forced by FW */;
1439 /* set if accept_any_vlan should be handled */
1440         u8 update_accept_any_vlan_flg;
1441         u8 accept_any_vlan /* accept_any_vlan updated value */;
1442 /* Set to remove vlan silently, update_inner_vlan_removal_en_flg must be enabled
1443  * as well. If Rx is in noSgl mode send rx_queue_update_ramrod_data
1444  */
1445         u8 silent_vlan_removal_en;
1446 /* If set, MTU will be updated. Vport must be not active. */
1447         u8 update_mtu_flg;
1448         __le16 mtu /* New MTU value. Used if update_mtu_flg are set */;
1449         u8 reserved[2];
1450 };
1451
1452 struct vport_update_ramrod_mcast {
1453         __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS] /* multicast bins */;
1454 };
1455
1456 /*
1457  * Ramrod data for vport update ramrod
1458  */
1459 struct vport_update_ramrod_data {
1460 /* Common data for all vport update ramrods */
1461         struct vport_update_ramrod_data_cmn common;
1462         struct eth_vport_rx_mode rx_mode /* vport rx mode bitmap */;
1463         struct eth_vport_tx_mode tx_mode /* vport tx mode bitmap */;
1464 /* TPA configuration parameters */
1465         struct eth_vport_tpa_param tpa_param;
1466         struct vport_update_ramrod_mcast approx_mcast;
1467         struct eth_vport_rss_config rss_config /* rss config data */;
1468 };
1469
1470
1471
1472
1473
1474
1475 /*
1476  * GFT CAM line struct
1477  */
1478 struct gft_cam_line {
1479         __le32 camline;
1480 /* Indication if the line is valid. */
1481 #define GFT_CAM_LINE_VALID_MASK      0x1
1482 #define GFT_CAM_LINE_VALID_SHIFT     0
1483 /* Data bits, the word that compared with the profile key */
1484 #define GFT_CAM_LINE_DATA_MASK       0x3FFF
1485 #define GFT_CAM_LINE_DATA_SHIFT      1
1486 /* Mask bits, indicate the bits in the data that are Dont-Care */
1487 #define GFT_CAM_LINE_MASK_BITS_MASK  0x3FFF
1488 #define GFT_CAM_LINE_MASK_BITS_SHIFT 15
1489 #define GFT_CAM_LINE_RESERVED1_MASK  0x7
1490 #define GFT_CAM_LINE_RESERVED1_SHIFT 29
1491 };
1492
1493
1494 /*
1495  * GFT CAM line struct (for driversim use)
1496  */
1497 struct gft_cam_line_mapped {
1498         __le32 camline;
1499 /* Indication if the line is valid. */
1500 #define GFT_CAM_LINE_MAPPED_VALID_MASK                     0x1
1501 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT                    0
1502 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
1503 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK                0x1
1504 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT               1
1505 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
1506 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK         0x1
1507 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT        2
1508 /* use enum gft_profile_upper_protocol_type
1509  * (use enum gft_profile_upper_protocol_type)
1510  */
1511 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK       0xF
1512 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT      3
1513 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
1514 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK               0xF
1515 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT              7
1516 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK                     0xF
1517 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT                    11
1518 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
1519 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK           0x1
1520 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT          15
1521 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
1522 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK    0x1
1523 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT   16
1524 /* use enum gft_profile_upper_protocol_type
1525  * (use enum gft_profile_upper_protocol_type)
1526  */
1527 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK  0xF
1528 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17
1529 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
1530 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK          0xF
1531 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT         21
1532 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK                0xF
1533 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT               25
1534 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK                 0x7
1535 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT                29
1536 };
1537
1538
1539 union gft_cam_line_union {
1540         struct gft_cam_line cam_line;
1541         struct gft_cam_line_mapped cam_line_mapped;
1542 };
1543
1544
1545 /*
1546  * Used in gft_profile_key: Indication for ip version
1547  */
1548 enum gft_profile_ip_version {
1549         GFT_PROFILE_IPV4 = 0,
1550         GFT_PROFILE_IPV6 = 1,
1551         MAX_GFT_PROFILE_IP_VERSION
1552 };
1553
1554
1555 /*
1556  * Profile key stucr fot GFT logic in Prs
1557  */
1558 struct gft_profile_key {
1559         __le16 profile_key;
1560 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
1561 #define GFT_PROFILE_KEY_IP_VERSION_MASK           0x1
1562 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT          0
1563 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
1564 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK    0x1
1565 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT   1
1566 /* use enum gft_profile_upper_protocol_type
1567  * (use enum gft_profile_upper_protocol_type)
1568  */
1569 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK  0xF
1570 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2
1571 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
1572 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK          0xF
1573 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT         6
1574 #define GFT_PROFILE_KEY_PF_ID_MASK                0xF
1575 #define GFT_PROFILE_KEY_PF_ID_SHIFT               10
1576 #define GFT_PROFILE_KEY_RESERVED0_MASK            0x3
1577 #define GFT_PROFILE_KEY_RESERVED0_SHIFT           14
1578 };
1579
1580
1581 /*
1582  * Used in gft_profile_key: Indication for tunnel type
1583  */
1584 enum gft_profile_tunnel_type {
1585         GFT_PROFILE_NO_TUNNEL = 0,
1586         GFT_PROFILE_VXLAN_TUNNEL = 1,
1587         GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
1588         GFT_PROFILE_GRE_IP_TUNNEL = 3,
1589         GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
1590         GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
1591         MAX_GFT_PROFILE_TUNNEL_TYPE
1592 };
1593
1594
1595 /*
1596  * Used in gft_profile_key: Indication for protocol type
1597  */
1598 enum gft_profile_upper_protocol_type {
1599         GFT_PROFILE_ROCE_PROTOCOL = 0,
1600         GFT_PROFILE_RROCE_PROTOCOL = 1,
1601         GFT_PROFILE_FCOE_PROTOCOL = 2,
1602         GFT_PROFILE_ICMP_PROTOCOL = 3,
1603         GFT_PROFILE_ARP_PROTOCOL = 4,
1604         GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
1605         GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
1606         GFT_PROFILE_TCP_PROTOCOL = 7,
1607         GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
1608         GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
1609         GFT_PROFILE_UDP_PROTOCOL = 10,
1610         GFT_PROFILE_USER_IP_1_INNER = 11,
1611         GFT_PROFILE_USER_IP_2_OUTER = 12,
1612         GFT_PROFILE_USER_ETH_1_INNER = 13,
1613         GFT_PROFILE_USER_ETH_2_OUTER = 14,
1614         GFT_PROFILE_RAW = 15,
1615         MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
1616 };
1617
1618
1619 /*
1620  * GFT RAM line struct
1621  */
1622 struct gft_ram_line {
1623         __le32 low32bits;
1624 /*  (use enum gft_vlan_select) */
1625 #define GFT_RAM_LINE_VLAN_SELECT_MASK              0x3
1626 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT             0
1627 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK          0x1
1628 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT         2
1629 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK     0x1
1630 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT    3
1631 #define GFT_RAM_LINE_TUNNEL_TTL_MASK               0x1
1632 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT              4
1633 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK         0x1
1634 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT        5
1635 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK          0x1
1636 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT         6
1637 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK          0x1
1638 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT         7
1639 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK              0x1
1640 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT             8
1641 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK  0x1
1642 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9
1643 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK            0x1
1644 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT           10
1645 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK            0x1
1646 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT           11
1647 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK          0x1
1648 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT         12
1649 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK     0x1
1650 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT    13
1651 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK              0x1
1652 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT             14
1653 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK           0x1
1654 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT          15
1655 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK           0x1
1656 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT          16
1657 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK            0x1
1658 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT           17
1659 #define GFT_RAM_LINE_TTL_MASK                      0x1
1660 #define GFT_RAM_LINE_TTL_SHIFT                     18
1661 #define GFT_RAM_LINE_ETHERTYPE_MASK                0x1
1662 #define GFT_RAM_LINE_ETHERTYPE_SHIFT               19
1663 #define GFT_RAM_LINE_RESERVED0_MASK                0x1
1664 #define GFT_RAM_LINE_RESERVED0_SHIFT               20
1665 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK             0x1
1666 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT            21
1667 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK             0x1
1668 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT            22
1669 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK             0x1
1670 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT            23
1671 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK             0x1
1672 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT            24
1673 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK             0x1
1674 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT            25
1675 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK             0x1
1676 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT            26
1677 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK             0x1
1678 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT            27
1679 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK             0x1
1680 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT            28
1681 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK              0x1
1682 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT             29
1683 #define GFT_RAM_LINE_DST_PORT_MASK                 0x1
1684 #define GFT_RAM_LINE_DST_PORT_SHIFT                30
1685 #define GFT_RAM_LINE_SRC_PORT_MASK                 0x1
1686 #define GFT_RAM_LINE_SRC_PORT_SHIFT                31
1687         __le32 high32bits;
1688 #define GFT_RAM_LINE_DSCP_MASK                     0x1
1689 #define GFT_RAM_LINE_DSCP_SHIFT                    0
1690 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK         0x1
1691 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT        1
1692 #define GFT_RAM_LINE_DST_IP_MASK                   0x1
1693 #define GFT_RAM_LINE_DST_IP_SHIFT                  2
1694 #define GFT_RAM_LINE_SRC_IP_MASK                   0x1
1695 #define GFT_RAM_LINE_SRC_IP_SHIFT                  3
1696 #define GFT_RAM_LINE_PRIORITY_MASK                 0x1
1697 #define GFT_RAM_LINE_PRIORITY_SHIFT                4
1698 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK            0x1
1699 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT           5
1700 #define GFT_RAM_LINE_VLAN_MASK                     0x1
1701 #define GFT_RAM_LINE_VLAN_SHIFT                    6
1702 #define GFT_RAM_LINE_DST_MAC_MASK                  0x1
1703 #define GFT_RAM_LINE_DST_MAC_SHIFT                 7
1704 #define GFT_RAM_LINE_SRC_MAC_MASK                  0x1
1705 #define GFT_RAM_LINE_SRC_MAC_SHIFT                 8
1706 #define GFT_RAM_LINE_TENANT_ID_MASK                0x1
1707 #define GFT_RAM_LINE_TENANT_ID_SHIFT               9
1708 #define GFT_RAM_LINE_RESERVED1_MASK                0x3FFFFF
1709 #define GFT_RAM_LINE_RESERVED1_SHIFT               10
1710 };
1711
1712
1713 /*
1714  * Used in the first 2 bits for gft_ram_line: Indication for vlan mask
1715  */
1716 enum gft_vlan_select {
1717         INNER_PROVIDER_VLAN = 0,
1718         INNER_VLAN = 1,
1719         OUTER_PROVIDER_VLAN = 2,
1720         OUTER_VLAN = 3,
1721         MAX_GFT_VLAN_SELECT
1722 };
1723
1724
1725 struct mstorm_eth_conn_ag_ctx {
1726         u8 byte0 /* cdu_validation */;
1727         u8 byte1 /* state */;
1728         u8 flags0;
1729 /* exist_in_qm0 */
1730 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK  0x1
1731 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1732 /* exist_in_qm1 */
1733 #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK          0x1
1734 #define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT         1
1735 #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK           0x3 /* cf0 */
1736 #define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT          2
1737 #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK           0x3 /* cf1 */
1738 #define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT          4
1739 #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK           0x3 /* cf2 */
1740 #define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT          6
1741         u8 flags1;
1742 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK         0x1 /* cf0en */
1743 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT        0
1744 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK         0x1 /* cf1en */
1745 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT        1
1746 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK         0x1 /* cf2en */
1747 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT        2
1748 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK       0x1 /* rule0en */
1749 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT      3
1750 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK       0x1 /* rule1en */
1751 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT      4
1752 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK       0x1 /* rule2en */
1753 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT      5
1754 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK       0x1 /* rule3en */
1755 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT      6
1756 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK       0x1 /* rule4en */
1757 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT      7
1758         __le16 word0 /* word0 */;
1759         __le16 word1 /* word1 */;
1760         __le32 reg0 /* reg0 */;
1761         __le32 reg1 /* reg1 */;
1762 };
1763
1764
1765
1766
1767 struct xstormEthConnAgCtxDqExtLdPart {
1768         u8 reserved0 /* cdu_validation */;
1769         u8 eth_state /* state */;
1770         u8 flags0;
1771 /* exist_in_qm0 */
1772 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK            0x1
1773 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT           0
1774 /* exist_in_qm1 */
1775 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK               0x1
1776 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT              1
1777 /* exist_in_qm2 */
1778 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK               0x1
1779 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT              2
1780 /* exist_in_qm3 */
1781 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK            0x1
1782 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT           3
1783 /* bit4 */
1784 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK               0x1
1785 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT              4
1786 /* cf_array_active */
1787 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK               0x1
1788 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT              5
1789 /* bit6 */
1790 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK               0x1
1791 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT              6
1792 /* bit7 */
1793 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK               0x1
1794 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT              7
1795         u8 flags1;
1796 /* bit8 */
1797 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK               0x1
1798 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT              0
1799 /* bit9 */
1800 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK               0x1
1801 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT              1
1802 /* bit10 */
1803 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK               0x1
1804 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT              2
1805 /* bit11 */
1806 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK                   0x1
1807 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT                  3
1808 /* bit12 */
1809 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK                   0x1
1810 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT                  4
1811 /* bit13 */
1812 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK                   0x1
1813 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT                  5
1814 /* bit14 */
1815 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK          0x1
1816 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT         6
1817 /* bit15 */
1818 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK            0x1
1819 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT           7
1820         u8 flags2;
1821 /* timer0cf */
1822 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK                     0x3
1823 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT                    0
1824 /* timer1cf */
1825 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK                     0x3
1826 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT                    2
1827 /* timer2cf */
1828 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK                     0x3
1829 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT                    4
1830 /* timer_stop_all */
1831 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK                     0x3
1832 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT                    6
1833         u8 flags3;
1834 /* cf4 */
1835 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK                     0x3
1836 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT                    0
1837 /* cf5 */
1838 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK                     0x3
1839 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT                    2
1840 /* cf6 */
1841 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK                     0x3
1842 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT                    4
1843 /* cf7 */
1844 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK                     0x3
1845 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT                    6
1846         u8 flags4;
1847 /* cf8 */
1848 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK                     0x3
1849 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT                    0
1850 /* cf9 */
1851 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK                     0x3
1852 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT                    2
1853 /* cf10 */
1854 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK                    0x3
1855 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT                   4
1856 /* cf11 */
1857 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK                    0x3
1858 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT                   6
1859         u8 flags5;
1860 /* cf12 */
1861 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK                    0x3
1862 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT                   0
1863 /* cf13 */
1864 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK                    0x3
1865 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT                   2
1866 /* cf14 */
1867 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK                    0x3
1868 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT                   4
1869 /* cf15 */
1870 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK                    0x3
1871 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT                   6
1872         u8 flags6;
1873 /* cf16 */
1874 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK        0x3
1875 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT       0
1876 /* cf_array_cf */
1877 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK        0x3
1878 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT       2
1879 /* cf18 */
1880 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK                   0x3
1881 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT                  4
1882 /* cf19 */
1883 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK            0x3
1884 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT           6
1885         u8 flags7;
1886 /* cf20 */
1887 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK                0x3
1888 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT               0
1889 /* cf21 */
1890 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK              0x3
1891 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT             2
1892 /* cf22 */
1893 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK               0x3
1894 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT              4
1895 /* cf0en */
1896 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK                   0x1
1897 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT                  6
1898 /* cf1en */
1899 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK                   0x1
1900 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT                  7
1901         u8 flags8;
1902 /* cf2en */
1903 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK                   0x1
1904 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT                  0
1905 /* cf3en */
1906 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK                   0x1
1907 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT                  1
1908 /* cf4en */
1909 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK                   0x1
1910 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT                  2
1911 /* cf5en */
1912 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK                   0x1
1913 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT                  3
1914 /* cf6en */
1915 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK                   0x1
1916 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT                  4
1917 /* cf7en */
1918 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK                   0x1
1919 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT                  5
1920 /* cf8en */
1921 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK                   0x1
1922 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT                  6
1923 /* cf9en */
1924 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK                   0x1
1925 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT                  7
1926         u8 flags9;
1927 /* cf10en */
1928 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK                  0x1
1929 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT                 0
1930 /* cf11en */
1931 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK                  0x1
1932 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT                 1
1933 /* cf12en */
1934 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK                  0x1
1935 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT                 2
1936 /* cf13en */
1937 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK                  0x1
1938 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT                 3
1939 /* cf14en */
1940 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK                  0x1
1941 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT                 4
1942 /* cf15en */
1943 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK                  0x1
1944 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT                 5
1945 /* cf16en */
1946 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK     0x1
1947 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT    6
1948 /* cf_array_cf_en */
1949 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK     0x1
1950 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT    7
1951         u8 flags10;
1952 /* cf18en */
1953 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK                0x1
1954 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT               0
1955 /* cf19en */
1956 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK         0x1
1957 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT        1
1958 /* cf20en */
1959 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK             0x1
1960 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT            2
1961 /* cf21en */
1962 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK              0x1
1963 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT             3
1964 /* cf22en */
1965 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK            0x1
1966 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT           4
1967 /* cf23en */
1968 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK  0x1
1969 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
1970 /* rule0en */
1971 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK              0x1
1972 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT             6
1973 /* rule1en */
1974 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK              0x1
1975 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT             7
1976         u8 flags11;
1977 /* rule2en */
1978 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK              0x1
1979 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT             0
1980 /* rule3en */
1981 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK              0x1
1982 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT             1
1983 /* rule4en */
1984 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK          0x1
1985 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT         2
1986 /* rule5en */
1987 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK                 0x1
1988 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT                3
1989 /* rule6en */
1990 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK                 0x1
1991 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT                4
1992 /* rule7en */
1993 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK                 0x1
1994 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT                5
1995 /* rule8en */
1996 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK            0x1
1997 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT           6
1998 /* rule9en */
1999 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK                 0x1
2000 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT                7
2001         u8 flags12;
2002 /* rule10en */
2003 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK                0x1
2004 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT               0
2005 /* rule11en */
2006 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK                0x1
2007 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT               1
2008 /* rule12en */
2009 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK            0x1
2010 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT           2
2011 /* rule13en */
2012 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK            0x1
2013 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT           3
2014 /* rule14en */
2015 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK                0x1
2016 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT               4
2017 /* rule15en */
2018 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK                0x1
2019 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT               5
2020 /* rule16en */
2021 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK                0x1
2022 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT               6
2023 /* rule17en */
2024 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK                0x1
2025 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT               7
2026         u8 flags13;
2027 /* rule18en */
2028 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK                0x1
2029 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT               0
2030 /* rule19en */
2031 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK                0x1
2032 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT               1
2033 /* rule20en */
2034 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK            0x1
2035 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT           2
2036 /* rule21en */
2037 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK            0x1
2038 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT           3
2039 /* rule22en */
2040 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK            0x1
2041 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT           4
2042 /* rule23en */
2043 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK            0x1
2044 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT           5
2045 /* rule24en */
2046 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK            0x1
2047 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT           6
2048 /* rule25en */
2049 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK            0x1
2050 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT           7
2051         u8 flags14;
2052 /* bit16 */
2053 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK        0x1
2054 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT       0
2055 /* bit17 */
2056 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK      0x1
2057 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT     1
2058 /* bit18 */
2059 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK    0x1
2060 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT   2
2061 /* bit19 */
2062 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK    0x1
2063 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT   3
2064 /* bit20 */
2065 #define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK          0x1
2066 #define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT         4
2067 /* bit21 */
2068 #define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK        0x1
2069 #define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT       5
2070 /* cf23 */
2071 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK              0x3
2072 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT             6
2073         u8 edpm_event_id /* byte2 */;
2074         __le16 physical_q0 /* physical_q0 */;
2075         __le16 quota /* physical_q1 */;
2076         __le16 edpm_num_bds /* physical_q2 */;
2077         __le16 tx_bd_cons /* word3 */;
2078         __le16 tx_bd_prod /* word4 */;
2079         __le16 tx_class /* word5 */;
2080         __le16 conn_dpi /* conn_dpi */;
2081         u8 byte3 /* byte3 */;
2082         u8 byte4 /* byte4 */;
2083         u8 byte5 /* byte5 */;
2084         u8 byte6 /* byte6 */;
2085         __le32 reg0 /* reg0 */;
2086         __le32 reg1 /* reg1 */;
2087         __le32 reg2 /* reg2 */;
2088         __le32 reg3 /* reg3 */;
2089         __le32 reg4 /* reg4 */;
2090 };
2091
2092
2093
2094 struct xstorm_eth_hw_conn_ag_ctx {
2095         u8 reserved0 /* cdu_validation */;
2096         u8 eth_state /* state */;
2097         u8 flags0;
2098 /* exist_in_qm0 */
2099 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK            0x1
2100 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT           0
2101 /* exist_in_qm1 */
2102 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK               0x1
2103 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT              1
2104 /* exist_in_qm2 */
2105 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK               0x1
2106 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT              2
2107 /* exist_in_qm3 */
2108 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK            0x1
2109 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT           3
2110 /* bit4 */
2111 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK               0x1
2112 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT              4
2113 /* cf_array_active */
2114 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK               0x1
2115 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT              5
2116 /* bit6 */
2117 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK               0x1
2118 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT              6
2119 /* bit7 */
2120 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK               0x1
2121 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT              7
2122         u8 flags1;
2123 /* bit8 */
2124 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK               0x1
2125 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT              0
2126 /* bit9 */
2127 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK               0x1
2128 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT              1
2129 /* bit10 */
2130 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK               0x1
2131 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT              2
2132 /* bit11 */
2133 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK                   0x1
2134 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT                  3
2135 /* bit12 */
2136 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK                   0x1
2137 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT                  4
2138 /* bit13 */
2139 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK                   0x1
2140 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT                  5
2141 /* bit14 */
2142 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK          0x1
2143 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT         6
2144 /* bit15 */
2145 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK            0x1
2146 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT           7
2147         u8 flags2;
2148 /* timer0cf */
2149 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK                     0x3
2150 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT                    0
2151 /* timer1cf */
2152 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK                     0x3
2153 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT                    2
2154 /* timer2cf */
2155 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK                     0x3
2156 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT                    4
2157 /* timer_stop_all */
2158 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK                     0x3
2159 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT                    6
2160         u8 flags3;
2161 /* cf4 */
2162 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK                     0x3
2163 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT                    0
2164 /* cf5 */
2165 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK                     0x3
2166 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT                    2
2167 /* cf6 */
2168 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK                     0x3
2169 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT                    4
2170 /* cf7 */
2171 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK                     0x3
2172 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT                    6
2173         u8 flags4;
2174 /* cf8 */
2175 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK                     0x3
2176 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT                    0
2177 /* cf9 */
2178 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK                     0x3
2179 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT                    2
2180 /* cf10 */
2181 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK                    0x3
2182 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT                   4
2183 /* cf11 */
2184 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK                    0x3
2185 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT                   6
2186         u8 flags5;
2187 /* cf12 */
2188 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK                    0x3
2189 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT                   0
2190 /* cf13 */
2191 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK                    0x3
2192 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT                   2
2193 /* cf14 */
2194 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK                    0x3
2195 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT                   4
2196 /* cf15 */
2197 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK                    0x3
2198 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT                   6
2199         u8 flags6;
2200 /* cf16 */
2201 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK        0x3
2202 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT       0
2203 /* cf_array_cf */
2204 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK        0x3
2205 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT       2
2206 /* cf18 */
2207 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK                   0x3
2208 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT                  4
2209 /* cf19 */
2210 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK            0x3
2211 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT           6
2212         u8 flags7;
2213 /* cf20 */
2214 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK                0x3
2215 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT               0
2216 /* cf21 */
2217 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK              0x3
2218 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT             2
2219 /* cf22 */
2220 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK               0x3
2221 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT              4
2222 /* cf0en */
2223 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK                   0x1
2224 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT                  6
2225 /* cf1en */
2226 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK                   0x1
2227 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT                  7
2228         u8 flags8;
2229 /* cf2en */
2230 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK                   0x1
2231 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT                  0
2232 /* cf3en */
2233 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK                   0x1
2234 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT                  1
2235 /* cf4en */
2236 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK                   0x1
2237 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT                  2
2238 /* cf5en */
2239 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK                   0x1
2240 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT                  3
2241 /* cf6en */
2242 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK                   0x1
2243 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT                  4
2244 /* cf7en */
2245 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK                   0x1
2246 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT                  5
2247 /* cf8en */
2248 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK                   0x1
2249 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT                  6
2250 /* cf9en */
2251 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK                   0x1
2252 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT                  7
2253         u8 flags9;
2254 /* cf10en */
2255 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK                  0x1
2256 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT                 0
2257 /* cf11en */
2258 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK                  0x1
2259 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT                 1
2260 /* cf12en */
2261 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK                  0x1
2262 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT                 2
2263 /* cf13en */
2264 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK                  0x1
2265 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT                 3
2266 /* cf14en */
2267 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK                  0x1
2268 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT                 4
2269 /* cf15en */
2270 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK                  0x1
2271 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT                 5
2272 /* cf16en */
2273 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK     0x1
2274 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT    6
2275 /* cf_array_cf_en */
2276 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK     0x1
2277 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT    7
2278         u8 flags10;
2279 /* cf18en */
2280 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK                0x1
2281 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT               0
2282 /* cf19en */
2283 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK         0x1
2284 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT        1
2285 /* cf20en */
2286 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK             0x1
2287 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT            2
2288 /* cf21en */
2289 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK              0x1
2290 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT             3
2291 /* cf22en */
2292 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK            0x1
2293 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT           4
2294 /* cf23en */
2295 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK  0x1
2296 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
2297 /* rule0en */
2298 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK              0x1
2299 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT             6
2300 /* rule1en */
2301 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK              0x1
2302 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT             7
2303         u8 flags11;
2304 /* rule2en */
2305 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK              0x1
2306 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT             0
2307 /* rule3en */
2308 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK              0x1
2309 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT             1
2310 /* rule4en */
2311 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK          0x1
2312 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT         2
2313 /* rule5en */
2314 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK                 0x1
2315 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT                3
2316 /* rule6en */
2317 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK                 0x1
2318 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT                4
2319 /* rule7en */
2320 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK                 0x1
2321 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT                5
2322 /* rule8en */
2323 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK            0x1
2324 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT           6
2325 /* rule9en */
2326 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK                 0x1
2327 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT                7
2328         u8 flags12;
2329 /* rule10en */
2330 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK                0x1
2331 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT               0
2332 /* rule11en */
2333 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK                0x1
2334 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT               1
2335 /* rule12en */
2336 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK            0x1
2337 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT           2
2338 /* rule13en */
2339 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK            0x1
2340 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT           3
2341 /* rule14en */
2342 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK                0x1
2343 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT               4
2344 /* rule15en */
2345 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK                0x1
2346 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT               5
2347 /* rule16en */
2348 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK                0x1
2349 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT               6
2350 /* rule17en */
2351 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK                0x1
2352 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT               7
2353         u8 flags13;
2354 /* rule18en */
2355 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK                0x1
2356 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT               0
2357 /* rule19en */
2358 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK                0x1
2359 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT               1
2360 /* rule20en */
2361 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK            0x1
2362 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT           2
2363 /* rule21en */
2364 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK            0x1
2365 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT           3
2366 /* rule22en */
2367 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK            0x1
2368 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT           4
2369 /* rule23en */
2370 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK            0x1
2371 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT           5
2372 /* rule24en */
2373 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK            0x1
2374 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT           6
2375 /* rule25en */
2376 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK            0x1
2377 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT           7
2378         u8 flags14;
2379 /* bit16 */
2380 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK        0x1
2381 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT       0
2382 /* bit17 */
2383 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK      0x1
2384 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT     1
2385 /* bit18 */
2386 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK    0x1
2387 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT   2
2388 /* bit19 */
2389 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK    0x1
2390 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT   3
2391 /* bit20 */
2392 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK          0x1
2393 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT         4
2394 /* bit21 */
2395 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK        0x1
2396 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT       5
2397 /* cf23 */
2398 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK              0x3
2399 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT             6
2400         u8 edpm_event_id /* byte2 */;
2401         __le16 physical_q0 /* physical_q0 */;
2402         __le16 quota /* physical_q1 */;
2403         __le16 edpm_num_bds /* physical_q2 */;
2404         __le16 tx_bd_cons /* word3 */;
2405         __le16 tx_bd_prod /* word4 */;
2406         __le16 tx_class /* word5 */;
2407         __le16 conn_dpi /* conn_dpi */;
2408 };
2409
2410
2411 #endif /* __ECORE_HSI_ETH__ */