ceph/src/dpdk/drivers/net/qede/base/ecore_iro_values.h

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #ifndef __IRO_VALUES_H__
  10 #define __IRO_VALUES_H__
  11
  12 static const struct iro iro_arr[47] = {
  13 /* YSTORM_FLOW_CONTROL_MODE_OFFSET */
  14         {      0x0,      0x0,      0x0,      0x0,      0x8},
  15 /* TSTORM_PORT_STAT_OFFSET(port_id) */
  16         {   0x4cb0,     0x78,      0x0,      0x0,     0x78},
  17 /* TSTORM_LL2_PORT_STAT_OFFSET(port_id) */
  18         {   0x6318,     0x20,      0x0,      0x0,     0x20},
  19 /* USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) */
  20         {    0xb00,      0x8,      0x0,      0x0,      0x4},
  21 /* USTORM_FLR_FINAL_ACK_OFFSET(pf_id) */
  22         {    0xa80,      0x8,      0x0,      0x0,      0x4},
  23 /* USTORM_EQE_CONS_OFFSET(pf_id) */
  24         {      0x0,      0x8,      0x0,      0x0,      0x2},
  25 /* USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) */
  26         {     0x80,      0x8,      0x0,      0x0,      0x4},
  27 /* USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) */
  28         {     0x84,      0x8,      0x0,      0x0,      0x2},
  29 /* XSTORM_INTEG_TEST_DATA_OFFSET */
  30         {   0x4bc0,      0x0,      0x0,      0x0,     0x78},
  31 /* YSTORM_INTEG_TEST_DATA_OFFSET */
  32         {   0x3df0,      0x0,      0x0,      0x0,     0x78},
  33 /* PSTORM_INTEG_TEST_DATA_OFFSET */
  34         {   0x29b0,      0x0,      0x0,      0x0,     0x78},
  35 /* TSTORM_INTEG_TEST_DATA_OFFSET */
  36         {   0x4c38,      0x0,      0x0,      0x0,     0x78},
  37 /* MSTORM_INTEG_TEST_DATA_OFFSET */
  38         {   0x4990,      0x0,      0x0,      0x0,     0x78},
  39 /* USTORM_INTEG_TEST_DATA_OFFSET */
  40         {   0x7e48,      0x0,      0x0,      0x0,     0x78},
  41 /* TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) */
  42         {    0xa28,      0x8,      0x0,      0x0,      0x8},
  43 /* CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) */
  44         {   0x60f8,     0x10,      0x0,      0x0,     0x10},
  45 /* CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) */
  46         {   0xb820,     0x30,      0x0,      0x0,     0x30},
  47 /* CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) */
  48         {   0x95b8,     0x30,      0x0,      0x0,     0x30},
  49 /* MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) */
  50         {   0x4b60,     0x80,      0x0,      0x0,     0x40},
  51 /* MSTORM_ETH_PF_PRODS_OFFSET(queue_id) */
  52         {    0x1f8,      0x4,      0x0,      0x0,      0x4},
  53 /* MSTORM_ETH_VF_PRODS_OFFSET(vf_id,vf_queue_id) */
  54         {   0x53a0,     0x80,      0x4,      0x0,      0x4},
  55 /* MSTORM_TPA_TIMEOUT_US_OFFSET */
  56         {   0xc8f0,      0x0,      0x0,      0x0,      0x4},
  57 /* MSTORM_ETH_PF_STAT_OFFSET(pf_id) */
  58         {   0x4ba0,     0x80,      0x0,      0x0,     0x20},
  59 /* USTORM_QUEUE_STAT_OFFSET(stat_counter_id) */
  60         {   0x8050,     0x40,      0x0,      0x0,     0x30},
  61 /* USTORM_ETH_PF_STAT_OFFSET(pf_id) */
  62         {   0xe770,     0x60,      0x0,      0x0,     0x60},
  63 /* PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) */
  64         {   0x2b48,     0x80,      0x0,      0x0,     0x38},
  65 /* PSTORM_ETH_PF_STAT_OFFSET(pf_id) */
  66         {   0xf188,     0x78,      0x0,      0x0,     0x78},
  67 /* PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethType_id) */
  68         {    0x1f8,      0x4,      0x0,      0x0,      0x4},
  69 /* TSTORM_ETH_PRS_INPUT_OFFSET */
  70         {   0xacf0,      0x0,      0x0,      0x0,     0xf0},
  71 /* ETH_RX_RATE_LIMIT_OFFSET(pf_id) */
  72         {   0xade0,      0x8,      0x0,      0x0,      0x8},
  73 /* XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) */
  74         {    0x1f8,      0x8,      0x0,      0x0,      0x8},
  75 /* YSTORM_TOE_CQ_PROD_OFFSET(rss_id) */
  76         {    0xac0,      0x8,      0x0,      0x0,      0x8},
  77 /* USTORM_TOE_CQ_PROD_OFFSET(rss_id) */
  78         {   0x2578,      0x8,      0x0,      0x0,      0x8},
  79 /* USTORM_TOE_GRQ_PROD_OFFSET(pf_id) */
  80         {   0x24f8,      0x8,      0x0,      0x0,      0x8},
  81 /* TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) */
  82         {      0x0,      0x8,      0x0,      0x0,      0x8},
  83 /* TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id,bdq_id) */
  84         {    0x200,     0x10,      0x8,      0x0,      0x8},
  85 /* MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id,bdq_id) */
  86         {    0xb78,     0x10,      0x8,      0x0,      0x2},
  87 /* TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) */
  88         {   0xd888,     0x38,      0x0,      0x0,     0x24},
  89 /* MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) */
  90         {  0x12c38,     0x10,      0x0,      0x0,      0x8},
  91 /* USTORM_ISCSI_RX_STATS_OFFSET(pf_id) */
  92         {  0x11aa0,     0x38,      0x0,      0x0,     0x18},
  93 /* XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */
  94         {   0xa8c0,     0x30,      0x0,      0x0,     0x10},
  95 /* YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */
  96         {   0x86f8,     0x28,      0x0,      0x0,     0x18},
  97 /* PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */
  98         {  0x101f8,     0x10,      0x0,      0x0,     0x10},
  99 /* TSTORM_FCOE_RX_STATS_OFFSET(pf_id) */
 100         {   0xdd08,     0x48,      0x0,      0x0,     0x38},
 101 /* PSTORM_FCOE_TX_STATS_OFFSET(pf_id) */
 102         {  0x10660,     0x20,      0x0,      0x0,     0x20},
 103 /* PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) */
 104         {   0x2b80,     0x80,      0x0,      0x0,     0x10},
 105 /* TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) */
 106         {   0x5000,     0x10,      0x0,      0x0,     0x10},
 107 };
 108
 109 #endif /* __IRO_VALUES_H__ */