4 * Copyright (C) Cavium networks Ltd. 2016.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Cavium networks nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #ifndef _THUNDERX_NICVF_HW_H
34 #define _THUNDERX_NICVF_HW_H
38 #include "nicvf_hw_defs.h"
40 #define PCI_VENDOR_ID_CAVIUM 0x177D
41 #define PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF 0x0011
42 #define PCI_DEVICE_ID_THUNDERX_NICVF 0xA034
43 #define PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF 0xA11E
44 #define PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF 0xA134
45 #define PCI_SUB_DEVICE_ID_CN81XX_NICVF 0xA234
46 #define PCI_SUB_DEVICE_ID_CN83XX_NICVF 0xA334
48 #define NICVF_ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
50 #define NICVF_GET_RX_STATS(reg) \
51 nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | (reg << 3))
52 #define NICVF_GET_TX_STATS(reg) \
53 nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | (reg << 3))
55 #define NICVF_CAP_TUNNEL_PARSING (1ULL << 0)
56 /* Additional word in Rx descriptor to hold optional tunneling extension info */
57 #define NICVF_CAP_CQE_RX2 (1ULL << 1)
58 /* The device capable of setting NIC_CQE_RX_S[APAD] == 0 */
59 #define NICVF_CAP_DISABLE_APAD (1ULL << 2)
68 NICVF_ERR_SET_QS
= -8191,/* -8191 */
69 NICVF_ERR_RESET_QS
, /* -8190 */
70 NICVF_ERR_REG_POLL
, /* -8189 */
71 NICVF_ERR_RBDR_RESET
, /* -8188 */
72 NICVF_ERR_RBDR_DISABLE
, /* -8187 */
73 NICVF_ERR_RBDR_PREFETCH
, /* -8186 */
74 NICVF_ERR_RBDR_RESET1
, /* -8185 */
75 NICVF_ERR_RBDR_RESET2
, /* -8184 */
76 NICVF_ERR_RQ_CLAIM
, /* -8183 */
77 NICVF_ERR_RQ_PF_CFG
, /* -8182 */
78 NICVF_ERR_RQ_BP_CFG
, /* -8181 */
79 NICVF_ERR_RQ_DROP_CFG
, /* -8180 */
80 NICVF_ERR_CQ_DISABLE
, /* -8179 */
81 NICVF_ERR_CQ_RESET
, /* -8178 */
82 NICVF_ERR_SQ_DISABLE
, /* -8177 */
83 NICVF_ERR_SQ_RESET
, /* -8176 */
84 NICVF_ERR_SQ_PF_CFG
, /* -8175 */
85 NICVF_ERR_LOOPBACK_CFG
, /* -8174 */
86 NICVF_ERR_BASE_INIT
, /* -8173 */
87 NICVF_ERR_RSS_TBL_UPDATE
,/* -8172 */
88 NICVF_ERR_RSS_GET_SZ
, /* -8171 */
91 typedef nicvf_phys_addr_t (*rbdr_pool_get_handler
)(void *dev
, void *opaque
);
93 struct nicvf_hw_rx_qstats
{
95 uint64_t q_rx_packets
;
98 struct nicvf_hw_tx_qstats
{
100 uint64_t q_tx_packets
;
103 struct nicvf_hw_stats
{
105 uint64_t rx_ucast_frames
;
106 uint64_t rx_bcast_frames
;
107 uint64_t rx_mcast_frames
;
108 uint64_t rx_fcs_errors
;
109 uint64_t rx_l2_errors
;
110 uint64_t rx_drop_red
;
111 uint64_t rx_drop_red_bytes
;
112 uint64_t rx_drop_overrun
;
113 uint64_t rx_drop_overrun_bytes
;
114 uint64_t rx_drop_bcast
;
115 uint64_t rx_drop_mcast
;
116 uint64_t rx_drop_l3_bcast
;
117 uint64_t rx_drop_l3_mcast
;
119 uint64_t tx_bytes_ok
;
120 uint64_t tx_ucast_frames_ok
;
121 uint64_t tx_bcast_frames_ok
;
122 uint64_t tx_mcast_frames_ok
;
126 struct nicvf_rss_reta_info
{
129 uint8_t ind_tbl
[NIC_MAX_RSS_IDR_TBL_SIZE
];
132 /* Common structs used in DPDK and base layer are defined in DPDK layer */
133 #include "../nicvf_struct.h"
135 NICVF_STATIC_ASSERT(sizeof(struct nicvf_rbdr
) <= 128);
136 NICVF_STATIC_ASSERT(sizeof(struct nicvf_txq
) <= 128);
137 NICVF_STATIC_ASSERT(sizeof(struct nicvf_rxq
) <= 128);
140 nicvf_reg_write(struct nicvf
*nic
, uint32_t offset
, uint64_t val
)
142 nicvf_addr_write(nic
->reg_base
+ offset
, val
);
145 static inline uint64_t
146 nicvf_reg_read(struct nicvf
*nic
, uint32_t offset
)
148 return nicvf_addr_read(nic
->reg_base
+ offset
);
151 static inline uintptr_t
152 nicvf_qset_base(struct nicvf
*nic
, uint32_t qidx
)
154 return nic
->reg_base
+ (qidx
<< NIC_Q_NUM_SHIFT
);
158 nicvf_queue_reg_write(struct nicvf
*nic
, uint32_t offset
, uint32_t qidx
,
161 nicvf_addr_write(nicvf_qset_base(nic
, qidx
) + offset
, val
);
164 static inline uint64_t
165 nicvf_queue_reg_read(struct nicvf
*nic
, uint32_t offset
, uint32_t qidx
)
167 return nicvf_addr_read(nicvf_qset_base(nic
, qidx
) + offset
);
171 nicvf_disable_all_interrupts(struct nicvf
*nic
)
173 nicvf_reg_write(nic
, NIC_VF_ENA_W1C
, NICVF_INTR_ALL_MASK
);
174 nicvf_reg_write(nic
, NIC_VF_INT
, NICVF_INTR_ALL_MASK
);
177 static inline uint32_t
178 nicvf_hw_version(struct nicvf
*nic
)
180 return nic
->subsystem_device_id
;
183 static inline uint64_t
184 nicvf_hw_cap(struct nicvf
*nic
)
189 int nicvf_base_init(struct nicvf
*nic
);
191 int nicvf_reg_get_count(void);
192 int nicvf_reg_poll_interrupts(struct nicvf
*nic
);
193 int nicvf_reg_dump(struct nicvf
*nic
, uint64_t *data
);
195 int nicvf_qset_config(struct nicvf
*nic
);
196 int nicvf_qset_reclaim(struct nicvf
*nic
);
198 int nicvf_qset_rbdr_config(struct nicvf
*nic
, uint16_t qidx
);
199 int nicvf_qset_rbdr_reclaim(struct nicvf
*nic
, uint16_t qidx
);
200 int nicvf_qset_rbdr_precharge(void *dev
, struct nicvf
*nic
,
201 uint16_t ridx
, rbdr_pool_get_handler handler
,
203 int nicvf_qset_rbdr_active(struct nicvf
*nic
, uint16_t qidx
);
205 int nicvf_qset_rq_config(struct nicvf
*nic
, uint16_t qidx
,
206 struct nicvf_rxq
*rxq
);
207 int nicvf_qset_rq_reclaim(struct nicvf
*nic
, uint16_t qidx
);
209 int nicvf_qset_cq_config(struct nicvf
*nic
, uint16_t qidx
,
210 struct nicvf_rxq
*rxq
);
211 int nicvf_qset_cq_reclaim(struct nicvf
*nic
, uint16_t qidx
);
213 int nicvf_qset_sq_config(struct nicvf
*nic
, uint16_t qidx
,
214 struct nicvf_txq
*txq
);
215 int nicvf_qset_sq_reclaim(struct nicvf
*nic
, uint16_t qidx
);
217 uint32_t nicvf_qsize_rbdr_roundup(uint32_t val
);
218 uint32_t nicvf_qsize_cq_roundup(uint32_t val
);
219 uint32_t nicvf_qsize_sq_roundup(uint32_t val
);
221 void nicvf_vlan_hw_strip(struct nicvf
*nic
, bool enable
);
223 void nicvf_apad_config(struct nicvf
*nic
, bool enable
);
225 int nicvf_rss_config(struct nicvf
*nic
, uint32_t qcnt
, uint64_t cfg
);
226 int nicvf_rss_term(struct nicvf
*nic
);
228 int nicvf_rss_reta_update(struct nicvf
*nic
, uint8_t *tbl
, uint32_t max_count
);
229 int nicvf_rss_reta_query(struct nicvf
*nic
, uint8_t *tbl
, uint32_t max_count
);
231 void nicvf_rss_set_key(struct nicvf
*nic
, uint8_t *key
);
232 void nicvf_rss_get_key(struct nicvf
*nic
, uint8_t *key
);
234 void nicvf_rss_set_cfg(struct nicvf
*nic
, uint64_t val
);
235 uint64_t nicvf_rss_get_cfg(struct nicvf
*nic
);
237 int nicvf_loopback_config(struct nicvf
*nic
, bool enable
);
239 void nicvf_hw_get_stats(struct nicvf
*nic
, struct nicvf_hw_stats
*stats
);
240 void nicvf_hw_get_rx_qstats(struct nicvf
*nic
,
241 struct nicvf_hw_rx_qstats
*qstats
, uint16_t qidx
);
242 void nicvf_hw_get_tx_qstats(struct nicvf
*nic
,
243 struct nicvf_hw_tx_qstats
*qstats
, uint16_t qidx
);
245 #endif /* _THUNDERX_NICVF_HW_H */