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1 ; BSD LICENSE
2 ;
3 ; Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
4 ; All rights reserved.
5 ;
6 ; Redistribution and use in source and binary forms, with or without
7 ; modification, are permitted provided that the following conditions
8 ; are met:
9 ;
10 ; * Redistributions of source code must retain the above copyright
11 ; notice, this list of conditions and the following disclaimer.
12 ; * Redistributions in binary form must reproduce the above copyright
13 ; notice, this list of conditions and the following disclaimer in
14 ; the documentation and/or other materials provided with the
15 ; distribution.
16 ; * Neither the name of Intel Corporation nor the names of its
17 ; contributors may be used to endorse or promote products derived
18 ; from this software without specific prior written permission.
19 ;
20 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31
32
33 ; An edge router typically sits between two networks such as the provider
34 ; core network and the provider access network. A typical packet processing
35 ; pipeline for the upstream traffic (i.e. traffic from access to core
36 ; network) contains the following functional blocks: Packet RX & Firewall,
37 ; Flow classification, Metering, Routing and Packet TX. The input packets
38 ; are assumed to be Q-in-Q IPv4, while the output packets are MPLS IPv4
39 ; (with variable number of labels per route).
40 ;
41 ; A simple implementation for this functional pipeline is presented below.
42 ;
43 ; Packet RX & Pass-Through Flow Classification Flow Actions Routing
44 : Firewall
45 ; __________ SWQ0 __________ SWQ4 __________ SWQ8 __________ SWQ12 __________
46 ; RXQ0.0 --->| |------>| |------>| |------>| |------>| |------> TXQ0.0
47 ; | | SWQ1 | | SWQ5 | | SWQ9 | | SWQ13 | |
48 ; RXQ1.0 --->| |------>| |------>| |------>| |------>| |------> TXQ1.0
49 ; | (P1) | SWQ2 | (P2) | SWQ6 | (P3) | SWQ10 | (P4) | SWQ14 | (P5) |
50 ; RXQ2.0 --->| |------>| |------>| |------>| |------>| |------> TXQ2.0
51 ; | | SWQ3 | | SWQ7 | | SWQ11 | | SWQ15 | |
52 ; RXQ3.0 --->| |------>| |------>| |------>| |------>| |------> TXQ3.0
53 ; |__________| |__________| |__________| |__________| |__________|
54 ; | | |
55 ; +--> SINK0 (Default) +--> SINK1 (Default) +--> SINK2 (Default)
56 ;
57 ; Input packet: Ethernet/QinQ/IPv4
58 ; Output packet: Ethernet/MPLS/IPv4
59 ;
60 ; Packet buffer layout:
61 ; # Field Name Offset (Bytes) Size (Bytes)
62 ; 0 Mbuf 0 128
63 ; 1 Headroom 128 128
64 ; 2 Ethernet header 256 14
65 ; 3 QinQ header 270 8
66 ; 4 IPv4 header 278 20
67
68 [EAL]
69 log_level = 0
70
71 [PIPELINE0]
72 type = MASTER
73 core = 0
74
75 [PIPELINE1]
76 type = FIREWALL
77 core = 1
78 pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0
79 pktq_out = SWQ0 SWQ1 SWQ2 SWQ3 SINK0
80 n_rules = 4096
81 pkt_type = qinq_ipv4
82
83 [PIPELINE2]
84 type = PASS-THROUGH
85 core = 2
86 pktq_in = SWQ0 SWQ1 SWQ2 SWQ3
87 pktq_out = SWQ4 SWQ5 SWQ6 SWQ7
88 dma_size = 8
89 dma_dst_offset = 128
90 dma_src_offset = 268; 1st Ethertype offset
91 dma_src_mask = 00000FFF00000FFF; qinq
92 dma_hash_offset = 136; dma_dst_offset + dma_size
93
94 [PIPELINE3]
95 type = FLOW_CLASSIFICATION
96 core = 2
97 pktq_in = SWQ4 SWQ5 SWQ6 SWQ7
98 pktq_out = SWQ8 SWQ9 SWQ10 SWQ11 SINK1
99 n_flows = 65536
100 key_size = 8; dma_size
101 key_offset = 128; dma_dst_offset
102 hash_offset = 136; dma_hash_offset
103 flowid_offset = 192
104
105 [PIPELINE4]
106 type = FLOW_ACTIONS
107 core = 3
108 pktq_in = SWQ8 SWQ9 SWQ10 SWQ11
109 pktq_out = SWQ12 SWQ13 SWQ14 SWQ15
110 n_flows = 65536
111 n_meters_per_flow = 1
112 flow_id_offset = 192; flowid_offset
113 ip_hdr_offset = 278
114 color_offset = 196; flowid_offset + sizeof(flow_id)
115
116 [PIPELINE5]
117 type = ROUTING
118 core = 4
119 pktq_in = SWQ12 SWQ13 SWQ14 SWQ15
120 pktq_out = TXQ0.0 TXQ1.0 TXQ2.0 TXQ3.0 SINK2
121 encap = ethernet_mpls
122 mpls_color_mark = yes
123 ip_hdr_offset = 278
124 color_offset = 196; flowid_offset + sizeof(flow_id)