ceph/src/dpdk/examples/load_balancer/main.h

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #ifndef _MAIN_H_
  35 #define _MAIN_H_
  36
  37 /* Logical cores */
  38 #ifndef APP_MAX_SOCKETS
  39 #define APP_MAX_SOCKETS 2
  40 #endif
  41
  42 #ifndef APP_MAX_LCORES
  43 #define APP_MAX_LCORES       RTE_MAX_LCORE
  44 #endif
  45
  46 #ifndef APP_MAX_NIC_PORTS
  47 #define APP_MAX_NIC_PORTS    RTE_MAX_ETHPORTS
  48 #endif
  49
  50 #ifndef APP_MAX_RX_QUEUES_PER_NIC_PORT
  51 #define APP_MAX_RX_QUEUES_PER_NIC_PORT 128
  52 #endif
  53
  54 #ifndef APP_MAX_TX_QUEUES_PER_NIC_PORT
  55 #define APP_MAX_TX_QUEUES_PER_NIC_PORT 128
  56 #endif
  57
  58 #ifndef APP_MAX_IO_LCORES
  59 #define APP_MAX_IO_LCORES 16
  60 #endif
  61 #if (APP_MAX_IO_LCORES > APP_MAX_LCORES)
  62 #error "APP_MAX_IO_LCORES is too big"
  63 #endif
  64
  65 #ifndef APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE
  66 #define APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE 16
  67 #endif
  68
  69 #ifndef APP_MAX_NIC_TX_PORTS_PER_IO_LCORE
  70 #define APP_MAX_NIC_TX_PORTS_PER_IO_LCORE 16
  71 #endif
  72 #if (APP_MAX_NIC_TX_PORTS_PER_IO_LCORE > APP_MAX_NIC_PORTS)
  73 #error "APP_MAX_NIC_TX_PORTS_PER_IO_LCORE too big"
  74 #endif
  75
  76 #ifndef APP_MAX_WORKER_LCORES
  77 #define APP_MAX_WORKER_LCORES 16
  78 #endif
  79 #if (APP_MAX_WORKER_LCORES > APP_MAX_LCORES)
  80 #error "APP_MAX_WORKER_LCORES is too big"
  81 #endif
  82
  83
  84 /* Mempools */
  85 #ifndef APP_DEFAULT_MBUF_DATA_SIZE
  86 #define APP_DEFAULT_MBUF_DATA_SIZE  RTE_MBUF_DEFAULT_BUF_SIZE
  87 #endif
  88
  89 #ifndef APP_DEFAULT_MEMPOOL_BUFFERS
  90 #define APP_DEFAULT_MEMPOOL_BUFFERS   8192 * 4
  91 #endif
  92
  93 #ifndef APP_DEFAULT_MEMPOOL_CACHE_SIZE
  94 #define APP_DEFAULT_MEMPOOL_CACHE_SIZE  256
  95 #endif
  96
  97 /* LPM Tables */
  98 #ifndef APP_MAX_LPM_RULES
  99 #define APP_MAX_LPM_RULES 1024
 100 #endif
 101
 102 /* NIC RX */
 103 #ifndef APP_DEFAULT_NIC_RX_RING_SIZE
 104 #define APP_DEFAULT_NIC_RX_RING_SIZE 1024
 105 #endif
 106
 107 /*
 108  * RX and TX Prefetch, Host, and Write-back threshold values should be
 109  * carefully set for optimal performance. Consult the network
 110  * controller's datasheet and supporting DPDK documentation for guidance
 111  * on how these parameters should be set.
 112  */
 113 #ifndef APP_DEFAULT_NIC_RX_PTHRESH
 114 #define APP_DEFAULT_NIC_RX_PTHRESH  8
 115 #endif
 116
 117 #ifndef APP_DEFAULT_NIC_RX_HTHRESH
 118 #define APP_DEFAULT_NIC_RX_HTHRESH  8
 119 #endif
 120
 121 #ifndef APP_DEFAULT_NIC_RX_WTHRESH
 122 #define APP_DEFAULT_NIC_RX_WTHRESH  4
 123 #endif
 124
 125 #ifndef APP_DEFAULT_NIC_RX_FREE_THRESH
 126 #define APP_DEFAULT_NIC_RX_FREE_THRESH  64
 127 #endif
 128
 129 #ifndef APP_DEFAULT_NIC_RX_DROP_EN
 130 #define APP_DEFAULT_NIC_RX_DROP_EN 0
 131 #endif
 132
 133 /* NIC TX */
 134 #ifndef APP_DEFAULT_NIC_TX_RING_SIZE
 135 #define APP_DEFAULT_NIC_TX_RING_SIZE 1024
 136 #endif
 137
 138 /*
 139  * These default values are optimized for use with the Intel(R) 82599 10 GbE
 140  * Controller and the DPDK ixgbe PMD. Consider using other values for other
 141  * network controllers and/or network drivers.
 142  */
 143 #ifndef APP_DEFAULT_NIC_TX_PTHRESH
 144 #define APP_DEFAULT_NIC_TX_PTHRESH  36
 145 #endif
 146
 147 #ifndef APP_DEFAULT_NIC_TX_HTHRESH
 148 #define APP_DEFAULT_NIC_TX_HTHRESH  0
 149 #endif
 150
 151 #ifndef APP_DEFAULT_NIC_TX_WTHRESH
 152 #define APP_DEFAULT_NIC_TX_WTHRESH  0
 153 #endif
 154
 155 #ifndef APP_DEFAULT_NIC_TX_FREE_THRESH
 156 #define APP_DEFAULT_NIC_TX_FREE_THRESH  0
 157 #endif
 158
 159 #ifndef APP_DEFAULT_NIC_TX_RS_THRESH
 160 #define APP_DEFAULT_NIC_TX_RS_THRESH  0
 161 #endif
 162
 163 /* Software Rings */
 164 #ifndef APP_DEFAULT_RING_RX_SIZE
 165 #define APP_DEFAULT_RING_RX_SIZE 1024
 166 #endif
 167
 168 #ifndef APP_DEFAULT_RING_TX_SIZE
 169 #define APP_DEFAULT_RING_TX_SIZE 1024
 170 #endif
 171
 172 /* Bursts */
 173 #ifndef APP_MBUF_ARRAY_SIZE
 174 #define APP_MBUF_ARRAY_SIZE   512
 175 #endif
 176
 177 #ifndef APP_DEFAULT_BURST_SIZE_IO_RX_READ
 178 #define APP_DEFAULT_BURST_SIZE_IO_RX_READ  144
 179 #endif
 180 #if (APP_DEFAULT_BURST_SIZE_IO_RX_READ > APP_MBUF_ARRAY_SIZE)
 181 #error "APP_DEFAULT_BURST_SIZE_IO_RX_READ is too big"
 182 #endif
 183
 184 #ifndef APP_DEFAULT_BURST_SIZE_IO_RX_WRITE
 185 #define APP_DEFAULT_BURST_SIZE_IO_RX_WRITE  144
 186 #endif
 187 #if (APP_DEFAULT_BURST_SIZE_IO_RX_WRITE > APP_MBUF_ARRAY_SIZE)
 188 #error "APP_DEFAULT_BURST_SIZE_IO_RX_WRITE is too big"
 189 #endif
 190
 191 #ifndef APP_DEFAULT_BURST_SIZE_IO_TX_READ
 192 #define APP_DEFAULT_BURST_SIZE_IO_TX_READ  144
 193 #endif
 194 #if (APP_DEFAULT_BURST_SIZE_IO_TX_READ > APP_MBUF_ARRAY_SIZE)
 195 #error "APP_DEFAULT_BURST_SIZE_IO_TX_READ is too big"
 196 #endif
 197
 198 #ifndef APP_DEFAULT_BURST_SIZE_IO_TX_WRITE
 199 #define APP_DEFAULT_BURST_SIZE_IO_TX_WRITE  144
 200 #endif
 201 #if (APP_DEFAULT_BURST_SIZE_IO_TX_WRITE > APP_MBUF_ARRAY_SIZE)
 202 #error "APP_DEFAULT_BURST_SIZE_IO_TX_WRITE is too big"
 203 #endif
 204
 205 #ifndef APP_DEFAULT_BURST_SIZE_WORKER_READ
 206 #define APP_DEFAULT_BURST_SIZE_WORKER_READ  144
 207 #endif
 208 #if ((2 * APP_DEFAULT_BURST_SIZE_WORKER_READ) > APP_MBUF_ARRAY_SIZE)
 209 #error "APP_DEFAULT_BURST_SIZE_WORKER_READ is too big"
 210 #endif
 211
 212 #ifndef APP_DEFAULT_BURST_SIZE_WORKER_WRITE
 213 #define APP_DEFAULT_BURST_SIZE_WORKER_WRITE  144
 214 #endif
 215 #if (APP_DEFAULT_BURST_SIZE_WORKER_WRITE > APP_MBUF_ARRAY_SIZE)
 216 #error "APP_DEFAULT_BURST_SIZE_WORKER_WRITE is too big"
 217 #endif
 218
 219 /* Load balancing logic */
 220 #ifndef APP_DEFAULT_IO_RX_LB_POS
 221 #define APP_DEFAULT_IO_RX_LB_POS 29
 222 #endif
 223 #if (APP_DEFAULT_IO_RX_LB_POS >= 64)
 224 #error "APP_DEFAULT_IO_RX_LB_POS is too big"
 225 #endif
 226
 227 struct app_mbuf_array {
 228         struct rte_mbuf *array[APP_MBUF_ARRAY_SIZE];
 229         uint32_t n_mbufs;
 230 };
 231
 232 enum app_lcore_type {
 233         e_APP_LCORE_DISABLED = 0,
 234         e_APP_LCORE_IO,
 235         e_APP_LCORE_WORKER
 236 };
 237
 238 struct app_lcore_params_io {
 239         /* I/O RX */
 240         struct {
 241                 /* NIC */
 242                 struct {
 243                         uint8_t port;
 244                         uint8_t queue;
 245                 } nic_queues[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
 246                 uint32_t n_nic_queues;
 247
 248                 /* Rings */
 249                 struct rte_ring *rings[APP_MAX_WORKER_LCORES];
 250                 uint32_t n_rings;
 251
 252                 /* Internal buffers */
 253                 struct app_mbuf_array mbuf_in;
 254                 struct app_mbuf_array mbuf_out[APP_MAX_WORKER_LCORES];
 255                 uint8_t mbuf_out_flush[APP_MAX_WORKER_LCORES];
 256
 257                 /* Stats */
 258                 uint32_t nic_queues_count[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
 259                 uint32_t nic_queues_iters[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
 260                 uint32_t rings_count[APP_MAX_WORKER_LCORES];
 261                 uint32_t rings_iters[APP_MAX_WORKER_LCORES];
 262         } rx;
 263
 264         /* I/O TX */
 265         struct {
 266                 /* Rings */
 267                 struct rte_ring *rings[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
 268
 269                 /* NIC */
 270                 uint8_t nic_ports[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
 271                 uint32_t n_nic_ports;
 272
 273                 /* Internal buffers */
 274                 struct app_mbuf_array mbuf_out[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
 275                 uint8_t mbuf_out_flush[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
 276
 277                 /* Stats */
 278                 uint32_t rings_count[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
 279                 uint32_t rings_iters[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
 280                 uint32_t nic_ports_count[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
 281                 uint32_t nic_ports_iters[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
 282         } tx;
 283 };
 284
 285 struct app_lcore_params_worker {
 286         /* Rings */
 287         struct rte_ring *rings_in[APP_MAX_IO_LCORES];
 288         uint32_t n_rings_in;
 289         struct rte_ring *rings_out[APP_MAX_NIC_PORTS];
 290
 291         /* LPM table */
 292         struct rte_lpm *lpm_table;
 293         uint32_t worker_id;
 294
 295         /* Internal buffers */
 296         struct app_mbuf_array mbuf_in;
 297         struct app_mbuf_array mbuf_out[APP_MAX_NIC_PORTS];
 298         uint8_t mbuf_out_flush[APP_MAX_NIC_PORTS];
 299
 300         /* Stats */
 301         uint32_t rings_in_count[APP_MAX_IO_LCORES];
 302         uint32_t rings_in_iters[APP_MAX_IO_LCORES];
 303         uint32_t rings_out_count[APP_MAX_NIC_PORTS];
 304         uint32_t rings_out_iters[APP_MAX_NIC_PORTS];
 305 };
 306
 307 struct app_lcore_params {
 308         union {
 309                 struct app_lcore_params_io io;
 310                 struct app_lcore_params_worker worker;
 311         };
 312         enum app_lcore_type type;
 313         struct rte_mempool *pool;
 314 } __rte_cache_aligned;
 315
 316 struct app_lpm_rule {
 317         uint32_t ip;
 318         uint8_t depth;
 319         uint8_t if_out;
 320 };
 321
 322 struct app_params {
 323         /* lcore */
 324         struct app_lcore_params lcore_params[APP_MAX_LCORES];
 325
 326         /* NIC */
 327         uint8_t nic_rx_queue_mask[APP_MAX_NIC_PORTS][APP_MAX_RX_QUEUES_PER_NIC_PORT];
 328         uint8_t nic_tx_port_mask[APP_MAX_NIC_PORTS];
 329
 330         /* mbuf pools */
 331         struct rte_mempool *pools[APP_MAX_SOCKETS];
 332
 333         /* LPM tables */
 334         struct rte_lpm *lpm_tables[APP_MAX_SOCKETS];
 335         struct app_lpm_rule lpm_rules[APP_MAX_LPM_RULES];
 336         uint32_t n_lpm_rules;
 337
 338         /* rings */
 339         uint32_t nic_rx_ring_size;
 340         uint32_t nic_tx_ring_size;
 341         uint32_t ring_rx_size;
 342         uint32_t ring_tx_size;
 343
 344         /* burst size */
 345         uint32_t burst_size_io_rx_read;
 346         uint32_t burst_size_io_rx_write;
 347         uint32_t burst_size_io_tx_read;
 348         uint32_t burst_size_io_tx_write;
 349         uint32_t burst_size_worker_read;
 350         uint32_t burst_size_worker_write;
 351
 352         /* load balancing */
 353         uint8_t pos_lb;
 354 } __rte_cache_aligned;
 355
 356 extern struct app_params app;
 357
 358 int app_parse_args(int argc, char **argv);
 359 void app_print_usage(void);
 360 void app_init(void);
 361 int app_lcore_main_loop(void *arg);
 362
 363 int app_get_nic_rx_queues_per_port(uint8_t port);
 364 int app_get_lcore_for_nic_rx(uint8_t port, uint8_t queue, uint32_t *lcore_out);
 365 int app_get_lcore_for_nic_tx(uint8_t port, uint32_t *lcore_out);
 366 int app_is_socket_used(uint32_t socket);
 367 uint32_t app_get_lcores_io_rx(void);
 368 uint32_t app_get_lcores_worker(void);
 369 void app_print_params(void);
 370
 371 #endif /* _MAIN_H_ */