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45 #include <rte_lcore.h>
46 #include <rte_string_fns.h>
50 #define APP_NAME "qos_sched"
51 #define MAX_OPT_VALUES 8
52 #define SYS_CPU_DIR "/sys/devices/system/cpu/cpu%u/topology/"
54 static uint32_t app_master_core
= 1;
55 static uint32_t app_numa_mask
;
56 static uint64_t app_used_core_mask
= 0;
57 static uint64_t app_used_port_mask
= 0;
58 static uint64_t app_used_rx_port_mask
= 0;
59 static uint64_t app_used_tx_port_mask
= 0;
62 static const char usage
[] =
66 "Application mandatory parameters: \n"
67 " --pfc \"RX PORT, TX PORT, RX LCORE, WT LCORE\" : Packet flow configuration \n"
68 " multiple pfc can be configured in command line \n"
70 "Application optional parameters: \n"
71 " --i : run in interactive mode (default value is %u) \n"
72 " --mst I : master core index (default value is %u) \n"
73 " --rsz \"A, B, C\" : Ring sizes \n"
74 " A = Size (in number of buffer descriptors) of each of the NIC RX \n"
75 " rings read by the I/O RX lcores (default value is %u) \n"
76 " B = Size (in number of elements) of each of the SW rings used by the\n"
77 " I/O RX lcores to send packets to worker lcores (default value is\n"
79 " C = Size (in number of buffer descriptors) of each of the NIC TX \n"
80 " rings written by worker lcores (default value is %u) \n"
81 " --bsz \"A, B, C, D\": Burst sizes \n"
82 " A = I/O RX lcore read burst size from NIC RX (default value is %u) \n"
83 " B = I/O RX lcore write burst size to output SW rings, \n"
84 " Worker lcore read burst size from input SW rings, \n"
85 " QoS enqueue size (default value is %u) \n"
86 " C = QoS dequeue size (default value is %u) \n"
87 " D = Worker lcore write burst size to NIC TX (default value is %u) \n"
88 " --msz M : Mempool size (in number of mbufs) for each pfc (default %u) \n"
89 " --rth \"A, B, C\" : RX queue threshold parameters \n"
90 " A = RX prefetch threshold (default value is %u) \n"
91 " B = RX host threshold (default value is %u) \n"
92 " C = RX write-back threshold (default value is %u) \n"
93 " --tth \"A, B, C\" : TX queue threshold parameters \n"
94 " A = TX prefetch threshold (default value is %u) \n"
95 " B = TX host threshold (default value is %u) \n"
96 " C = TX write-back threshold (default value is %u) \n"
97 " --cfg FILE : profile configuration to load \n"
102 app_usage(const char *prgname
)
104 printf(usage
, prgname
, APP_INTERACTIVE_DEFAULT
, app_master_core
,
105 APP_RX_DESC_DEFAULT
, APP_RING_SIZE
, APP_TX_DESC_DEFAULT
,
106 MAX_PKT_RX_BURST
, PKT_ENQUEUE
, PKT_DEQUEUE
,
107 MAX_PKT_TX_BURST
, NB_MBUF
,
108 RX_PTHRESH
, RX_HTHRESH
, RX_WTHRESH
,
109 TX_PTHRESH
, TX_HTHRESH
, TX_WTHRESH
113 static inline int str_is(const char *str
, const char *is
)
115 return strcmp(str
, is
) == 0;
118 /* returns core mask used by DPDK */
120 app_eal_core_mask(void)
124 struct rte_config
*cfg
= rte_eal_get_configuration();
126 for (i
= 0; i
< APP_MAX_LCORE
; i
++) {
127 if (cfg
->lcore_role
[i
] == ROLE_RTE
)
131 cm
|= (1ULL << cfg
->master_lcore
);
137 /* returns total number of cores presented in a system */
139 app_cpu_core_count(void)
145 for (i
= 0; i
< APP_MAX_LCORE
; i
++) {
146 len
= snprintf(path
, sizeof(path
), SYS_CPU_DIR
, i
);
147 if (len
<= 0 || (unsigned)len
>= sizeof(path
))
150 if (access(path
, F_OK
) == 0)
158 number of values parsed
162 app_parse_opt_vals(const char *conf_str
, char separator
, uint32_t n_vals
, uint32_t *opt_vals
)
166 char *tokens
[MAX_OPT_VALUES
];
168 if (conf_str
== NULL
|| opt_vals
== NULL
|| n_vals
== 0 || n_vals
> MAX_OPT_VALUES
)
171 /* duplicate configuration string before splitting it to tokens */
172 string
= strdup(conf_str
);
176 n_tokens
= rte_strsplit(string
, strnlen(string
, 32), tokens
, n_vals
, separator
);
178 if (n_tokens
> MAX_OPT_VALUES
)
181 for (i
= 0; i
< n_tokens
; i
++)
182 opt_vals
[i
] = (uint32_t)atol(tokens
[i
]);
190 app_parse_ring_conf(const char *conf_str
)
195 ret
= app_parse_opt_vals(conf_str
, ',', 3, vals
);
199 ring_conf
.rx_size
= vals
[0];
200 ring_conf
.ring_size
= vals
[1];
201 ring_conf
.tx_size
= vals
[2];
207 app_parse_rth_conf(const char *conf_str
)
212 ret
= app_parse_opt_vals(conf_str
, ',', 3, vals
);
216 rx_thresh
.pthresh
= (uint8_t)vals
[0];
217 rx_thresh
.hthresh
= (uint8_t)vals
[1];
218 rx_thresh
.wthresh
= (uint8_t)vals
[2];
224 app_parse_tth_conf(const char *conf_str
)
229 ret
= app_parse_opt_vals(conf_str
, ',', 3, vals
);
233 tx_thresh
.pthresh
= (uint8_t)vals
[0];
234 tx_thresh
.hthresh
= (uint8_t)vals
[1];
235 tx_thresh
.wthresh
= (uint8_t)vals
[2];
241 app_parse_flow_conf(const char *conf_str
)
245 struct flow_conf
*pconf
;
248 ret
= app_parse_opt_vals(conf_str
, ',', 6, vals
);
249 if (ret
< 4 || ret
> 5)
252 pconf
= &qos_conf
[nb_pfc
];
254 pconf
->rx_port
= (uint8_t)vals
[0];
255 pconf
->tx_port
= (uint8_t)vals
[1];
256 pconf
->rx_core
= (uint8_t)vals
[2];
257 pconf
->wt_core
= (uint8_t)vals
[3];
259 pconf
->tx_core
= (uint8_t)vals
[4];
261 pconf
->tx_core
= pconf
->wt_core
;
263 if (pconf
->rx_core
== pconf
->wt_core
) {
264 RTE_LOG(ERR
, APP
, "pfc %u: rx thread and worker thread cannot share same core\n", nb_pfc
);
268 if (pconf
->rx_port
>= RTE_MAX_ETHPORTS
) {
269 RTE_LOG(ERR
, APP
, "pfc %u: invalid rx port %"PRIu8
" index\n",
270 nb_pfc
, pconf
->rx_port
);
273 if (pconf
->tx_port
>= RTE_MAX_ETHPORTS
) {
274 RTE_LOG(ERR
, APP
, "pfc %u: invalid tx port %"PRIu8
" index\n",
275 nb_pfc
, pconf
->tx_port
);
279 mask
= 1lu << pconf
->rx_port
;
280 if (app_used_rx_port_mask
& mask
) {
281 RTE_LOG(ERR
, APP
, "pfc %u: rx port %"PRIu8
" is used already\n",
282 nb_pfc
, pconf
->rx_port
);
285 app_used_rx_port_mask
|= mask
;
286 app_used_port_mask
|= mask
;
288 mask
= 1lu << pconf
->tx_port
;
289 if (app_used_tx_port_mask
& mask
) {
290 RTE_LOG(ERR
, APP
, "pfc %u: port %"PRIu8
" is used already\n",
291 nb_pfc
, pconf
->tx_port
);
294 app_used_tx_port_mask
|= mask
;
295 app_used_port_mask
|= mask
;
297 mask
= 1lu << pconf
->rx_core
;
298 app_used_core_mask
|= mask
;
300 mask
= 1lu << pconf
->wt_core
;
301 app_used_core_mask
|= mask
;
303 mask
= 1lu << pconf
->tx_core
;
304 app_used_core_mask
|= mask
;
312 app_parse_burst_conf(const char *conf_str
)
317 ret
= app_parse_opt_vals(conf_str
, ',', 4, vals
);
321 burst_conf
.rx_burst
= (uint16_t)vals
[0];
322 burst_conf
.ring_burst
= (uint16_t)vals
[1];
323 burst_conf
.qos_dequeue
= (uint16_t)vals
[2];
324 burst_conf
.tx_burst
= (uint16_t)vals
[3];
330 * Parses the argument given in the command line of the application,
331 * calculates mask for used cores and initializes EAL with calculated core mask
334 app_parse_args(int argc
, char **argv
)
339 char *prgname
= argv
[0];
340 uint32_t i
, nb_lcores
;
342 static struct option lgopts
[] = {
354 /* initialize EAL first */
355 ret
= rte_eal_init(argc
, argv
);
362 /* set en_US locale to print big numbers with ',' */
363 setlocale(LC_NUMERIC
, "en_US.utf-8");
365 while ((opt
= getopt_long(argc
, argv
, "i",
366 lgopts
, &option_index
)) != EOF
) {
370 printf("Interactive-mode selected\n");
375 optname
= lgopts
[option_index
].name
;
376 if (str_is(optname
, "pfc")) {
377 ret
= app_parse_flow_conf(optarg
);
379 RTE_LOG(ERR
, APP
, "Invalid pipe configuration %s\n", optarg
);
384 if (str_is(optname
, "mst")) {
385 app_master_core
= (uint32_t)atoi(optarg
);
388 if (str_is(optname
, "rsz")) {
389 ret
= app_parse_ring_conf(optarg
);
391 RTE_LOG(ERR
, APP
, "Invalid ring configuration %s\n", optarg
);
396 if (str_is(optname
, "bsz")) {
397 ret
= app_parse_burst_conf(optarg
);
399 RTE_LOG(ERR
, APP
, "Invalid burst configuration %s\n", optarg
);
404 if (str_is(optname
, "msz")) {
405 mp_size
= atoi(optarg
);
407 RTE_LOG(ERR
, APP
, "Invalid mempool size %s\n", optarg
);
412 if (str_is(optname
, "rth")) {
413 ret
= app_parse_rth_conf(optarg
);
415 RTE_LOG(ERR
, APP
, "Invalid RX threshold configuration %s\n", optarg
);
420 if (str_is(optname
, "tth")) {
421 ret
= app_parse_tth_conf(optarg
);
423 RTE_LOG(ERR
, APP
, "Invalid TX threshold configuration %s\n", optarg
);
428 if (str_is(optname
, "cfg")) {
429 cfg_profile
= optarg
;
440 /* check master core index validity */
441 for(i
= 0; i
<= app_master_core
; i
++) {
442 if (app_used_core_mask
& (1u << app_master_core
)) {
443 RTE_LOG(ERR
, APP
, "Master core index is not configured properly\n");
448 app_used_core_mask
|= 1u << app_master_core
;
450 if ((app_used_core_mask
!= app_eal_core_mask()) ||
451 (app_master_core
!= rte_get_master_lcore())) {
452 RTE_LOG(ERR
, APP
, "EAL core mask not configured properly, must be %" PRIx64
453 " instead of %" PRIx64
"\n" , app_used_core_mask
, app_eal_core_mask());
458 RTE_LOG(ERR
, APP
, "Packet flow not configured!\n");
463 /* sanity check for cores assignment */
464 nb_lcores
= app_cpu_core_count();
466 for(i
= 0; i
< nb_pfc
; i
++) {
467 if (qos_conf
[i
].rx_core
>= nb_lcores
) {
468 RTE_LOG(ERR
, APP
, "pfc %u: invalid RX lcore index %u\n", i
+ 1,
469 qos_conf
[i
].rx_core
);
472 if (qos_conf
[i
].wt_core
>= nb_lcores
) {
473 RTE_LOG(ERR
, APP
, "pfc %u: invalid WT lcore index %u\n", i
+ 1,
474 qos_conf
[i
].wt_core
);
477 uint32_t rx_sock
= rte_lcore_to_socket_id(qos_conf
[i
].rx_core
);
478 uint32_t wt_sock
= rte_lcore_to_socket_id(qos_conf
[i
].wt_core
);
479 if (rx_sock
!= wt_sock
) {
480 RTE_LOG(ERR
, APP
, "pfc %u: RX and WT must be on the same socket\n", i
+ 1);
483 app_numa_mask
|= 1 << rte_lcore_to_socket_id(qos_conf
[i
].rx_core
);