ceph/src/dpdk/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h

   1 /*
   2  *   BSD LICENSE
   3  *
   4  *   Copyright (C) Cavium networks Ltd. 2015.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Cavium networks nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31 */
  32
  33 #ifndef _RTE_ATOMIC_ARM64_H_
  34 #define _RTE_ATOMIC_ARM64_H_
  35
  36 #ifndef RTE_FORCE_INTRINSICS
  37 #  error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS
  38 #endif
  39
  40 #ifdef __cplusplus
  41 extern "C" {
  42 #endif
  43
  44 #include "generic/rte_atomic.h"
  45
  46 #define dmb(opt)  do { asm volatile("dmb " #opt : : : "memory"); } while (0)
  47
  48 /**
  49  * General memory barrier.
  50  *
  51  * Guarantees that the LOAD and STORE operations generated before the
  52  * barrier occur before the LOAD and STORE operations generated after.
  53  * This function is architecture dependent.
  54  */
  55 static inline void rte_mb(void)
  56 {
  57         dmb(ish);
  58 }
  59
  60 /**
  61  * Write memory barrier.
  62  *
  63  * Guarantees that the STORE operations generated before the barrier
  64  * occur before the STORE operations generated after.
  65  * This function is architecture dependent.
  66  */
  67 static inline void rte_wmb(void)
  68 {
  69         dmb(ishst);
  70 }
  71
  72 /**
  73  * Read memory barrier.
  74  *
  75  * Guarantees that the LOAD operations generated before the barrier
  76  * occur before the LOAD operations generated after.
  77  * This function is architecture dependent.
  78  */
  79 static inline void rte_rmb(void)
  80 {
  81         dmb(ishld);
  82 }
  83
  84 #ifdef __cplusplus
  85 }
  86 #endif
  87
  88 #endif /* _RTE_ATOMIC_ARM64_H_ */