ceph/src/dpdk/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h

   1 /*
   2  *   BSD LICENSE
   3  *
   4  *   Copyright (C) Cavium networks Ltd. 2015.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Cavium networks nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31 */
  32
  33 #ifndef _RTE_CYCLES_ARM64_H_
  34 #define _RTE_CYCLES_ARM64_H_
  35
  36 #ifdef __cplusplus
  37 extern "C" {
  38 #endif
  39
  40 #include "generic/rte_cycles.h"
  41
  42 /**
  43  * Read the time base register.
  44  *
  45  * @return
  46  *   The time base for this lcore.
  47  */
  48 #ifndef RTE_ARM_EAL_RDTSC_USE_PMU
  49 /**
  50  * This call is portable to any ARMv8 architecture, however, typically
  51  * cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks.
  52  */
  53 static inline uint64_t
  54 rte_rdtsc(void)
  55 {
  56         uint64_t tsc;
  57
  58         asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
  59         return tsc;
  60 }
  61 #else
  62 /**
  63  * This is an alternative method to enable rte_rdtsc() with high resolution
  64  * PMU cycles counter.The cycle counter runs at cpu frequency and this scheme
  65  * uses ARMv8 PMU subsystem to get the cycle counter at userspace, However,
  66  * access to PMU cycle counter from user space is not enabled by default in
  67  * arm64 linux kernel.
  68  * It is possible to enable cycle counter at user space access by configuring
  69  * the PMU from the privileged mode (kernel space).
  70  *
  71  * asm volatile("msr pmintenset_el1, %0" : : "r" ((u64)(0 << 31)));
  72  * asm volatile("msr pmcntenset_el0, %0" :: "r" BIT(31));
  73  * asm volatile("msr pmuserenr_el0, %0" : : "r"(BIT(0) | BIT(2)));
  74  * asm volatile("mrs %0, pmcr_el0" : "=r" (val));
  75  * val |= (BIT(0) | BIT(2));
  76  * isb();
  77  * asm volatile("msr pmcr_el0, %0" : : "r" (val));
  78  *
  79  */
  80 static inline uint64_t
  81 rte_rdtsc(void)
  82 {
  83         uint64_t tsc;
  84
  85         asm volatile("mrs %0, pmccntr_el0" : "=r"(tsc));
  86         return tsc;
  87 }
  88 #endif
  89
  90 static inline uint64_t
  91 rte_rdtsc_precise(void)
  92 {
  93         rte_mb();
  94         return rte_rdtsc();
  95 }
  96
  97 static inline uint64_t
  98 rte_get_tsc_cycles(void) { return rte_rdtsc(); }
  99
 100 #ifdef __cplusplus
 101 }
 102 #endif
 103
 104 #endif /* _RTE_CYCLES_ARM64_H_ */