1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "LICENSE.GPL".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
31 #include "e1000_osdep.h"
32 #include "e1000_regs.h"
33 #include "e1000_defines.h"
37 #define E1000_DEV_ID_82576 0x10C9
38 #define E1000_DEV_ID_82576_FIBER 0x10E6
39 #define E1000_DEV_ID_82576_SERDES 0x10E7
40 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
41 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
42 #define E1000_DEV_ID_82576_NS 0x150A
43 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
44 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
45 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
46 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
47 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
48 #define E1000_DEV_ID_82580_COPPER 0x150E
49 #define E1000_DEV_ID_82580_FIBER 0x150F
50 #define E1000_DEV_ID_82580_SERDES 0x1510
51 #define E1000_DEV_ID_82580_SGMII 0x1511
52 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
53 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
54 #define E1000_DEV_ID_I350_COPPER 0x1521
55 #define E1000_DEV_ID_I350_FIBER 0x1522
56 #define E1000_DEV_ID_I350_SERDES 0x1523
57 #define E1000_DEV_ID_I350_SGMII 0x1524
58 #define E1000_DEV_ID_I350_DA4 0x1546
59 #define E1000_DEV_ID_I210_COPPER 0x1533
60 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534
61 #define E1000_DEV_ID_I210_COPPER_IT 0x1535
62 #define E1000_DEV_ID_I210_FIBER 0x1536
63 #define E1000_DEV_ID_I210_SERDES 0x1537
64 #define E1000_DEV_ID_I210_SGMII 0x1538
65 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B
66 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C
67 #define E1000_DEV_ID_I211_COPPER 0x1539
68 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
69 #define E1000_DEV_ID_I354_SGMII 0x1F41
70 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
71 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
72 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
73 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
74 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440
76 #define E1000_REVISION_0 0
77 #define E1000_REVISION_1 1
78 #define E1000_REVISION_2 2
79 #define E1000_REVISION_3 3
80 #define E1000_REVISION_4 4
82 #define E1000_FUNC_0 0
83 #define E1000_FUNC_1 1
84 #define E1000_FUNC_2 2
85 #define E1000_FUNC_3 3
87 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
88 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
89 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
90 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
101 e1000_num_macs
/* List is 1-based, so subtract 1 for true count. */
104 enum e1000_media_type
{
105 e1000_media_type_unknown
= 0,
106 e1000_media_type_copper
= 1,
107 e1000_media_type_fiber
= 2,
108 e1000_media_type_internal_serdes
= 3,
109 e1000_num_media_types
112 enum e1000_nvm_type
{
113 e1000_nvm_unknown
= 0,
115 e1000_nvm_eeprom_spi
,
121 enum e1000_nvm_override
{
122 e1000_nvm_override_none
= 0,
123 e1000_nvm_override_spi_small
,
124 e1000_nvm_override_spi_large
,
127 enum e1000_phy_type
{
128 e1000_phy_unknown
= 0,
141 enum e1000_bus_type
{
142 e1000_bus_type_unknown
= 0,
145 e1000_bus_type_pci_express
,
146 e1000_bus_type_reserved
149 enum e1000_bus_speed
{
150 e1000_bus_speed_unknown
= 0,
156 e1000_bus_speed_2500
,
157 e1000_bus_speed_5000
,
158 e1000_bus_speed_reserved
161 enum e1000_bus_width
{
162 e1000_bus_width_unknown
= 0,
163 e1000_bus_width_pcie_x1
,
164 e1000_bus_width_pcie_x2
,
165 e1000_bus_width_pcie_x4
= 4,
166 e1000_bus_width_pcie_x8
= 8,
169 e1000_bus_width_reserved
172 enum e1000_1000t_rx_status
{
173 e1000_1000t_rx_status_not_ok
= 0,
174 e1000_1000t_rx_status_ok
,
175 e1000_1000t_rx_status_undefined
= 0xFF
178 enum e1000_rev_polarity
{
179 e1000_rev_polarity_normal
= 0,
180 e1000_rev_polarity_reversed
,
181 e1000_rev_polarity_undefined
= 0xFF
189 e1000_fc_default
= 0xFF
193 e1000_ms_hw_default
= 0,
194 e1000_ms_force_master
,
195 e1000_ms_force_slave
,
199 enum e1000_smart_speed
{
200 e1000_smart_speed_default
= 0,
201 e1000_smart_speed_on
,
202 e1000_smart_speed_off
205 enum e1000_serdes_link_state
{
206 e1000_serdes_link_down
= 0,
207 e1000_serdes_link_autoneg_progress
,
208 e1000_serdes_link_autoneg_complete
,
209 e1000_serdes_link_forced_up
221 /* Receive Descriptor */
222 struct e1000_rx_desc
{
223 __le64 buffer_addr
; /* Address of the descriptor's data buffer */
224 __le16 length
; /* Length of data DMAed into data buffer */
225 __le16 csum
; /* Packet checksum */
226 u8 status
; /* Descriptor status */
227 u8 errors
; /* Descriptor Errors */
231 /* Receive Descriptor - Extended */
232 union e1000_rx_desc_extended
{
239 __le32 mrq
; /* Multiple Rx Queues */
241 __le32 rss
; /* RSS Hash */
243 __le16 ip_id
; /* IP id */
244 __le16 csum
; /* Packet Checksum */
249 __le32 status_error
; /* ext status/error */
251 __le16 vlan
; /* VLAN tag */
253 } wb
; /* writeback */
256 #define MAX_PS_BUFFERS 4
258 /* Number of packet split data buffers (not including the header buffer) */
259 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
261 /* Receive Descriptor - Packet Split */
262 union e1000_rx_desc_packet_split
{
264 /* one buffer for protocol header(s), three data buffers */
265 __le64 buffer_addr
[MAX_PS_BUFFERS
];
269 __le32 mrq
; /* Multiple Rx Queues */
271 __le32 rss
; /* RSS Hash */
273 __le16 ip_id
; /* IP id */
274 __le16 csum
; /* Packet Checksum */
279 __le32 status_error
; /* ext status/error */
280 __le16 length0
; /* length of buffer 0 */
281 __le16 vlan
; /* VLAN tag */
284 __le16 header_status
;
285 /* length of buffers 1-3 */
286 __le16 length
[PS_PAGE_BUFFERS
];
289 } wb
; /* writeback */
292 /* Transmit Descriptor */
293 struct e1000_tx_desc
{
294 __le64 buffer_addr
; /* Address of the descriptor's data buffer */
298 __le16 length
; /* Data buffer length */
299 u8 cso
; /* Checksum offset */
300 u8 cmd
; /* Descriptor control */
306 u8 status
; /* Descriptor status */
307 u8 css
; /* Checksum start */
313 /* Offload Context Descriptor */
314 struct e1000_context_desc
{
318 u8 ipcss
; /* IP checksum start */
319 u8 ipcso
; /* IP checksum offset */
320 __le16 ipcse
; /* IP checksum end */
326 u8 tucss
; /* TCP checksum start */
327 u8 tucso
; /* TCP checksum offset */
328 __le16 tucse
; /* TCP checksum end */
331 __le32 cmd_and_length
;
335 u8 status
; /* Descriptor status */
336 u8 hdr_len
; /* Header length */
337 __le16 mss
; /* Maximum segment size */
342 /* Offload data descriptor */
343 struct e1000_data_desc
{
344 __le64 buffer_addr
; /* Address of the descriptor's buffer address */
348 __le16 length
; /* Data buffer length */
356 u8 status
; /* Descriptor status */
357 u8 popts
; /* Packet Options */
363 /* Statistics counters collected by the MAC */
364 struct e1000_hw_stats
{
448 struct e1000_phy_stats
{
453 struct e1000_host_mng_dhcp_cookie
{
464 /* Host Interface "Rev 1" */
465 struct e1000_host_command_header
{
472 #define E1000_HI_MAX_DATA_LENGTH 252
473 struct e1000_host_command_info
{
474 struct e1000_host_command_header command_header
;
475 u8 command_data
[E1000_HI_MAX_DATA_LENGTH
];
478 /* Host Interface "Rev 2" */
479 struct e1000_host_mng_command_header
{
487 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
488 struct e1000_host_mng_command_info
{
489 struct e1000_host_mng_command_header command_header
;
490 u8 command_data
[E1000_HI_MAX_MNG_DATA_LENGTH
];
493 #include "e1000_mac.h"
494 #include "e1000_phy.h"
495 #include "e1000_nvm.h"
496 #include "e1000_manage.h"
497 #include "e1000_mbx.h"
499 /* Function pointers for the MAC. */
500 struct e1000_mac_operations
{
501 s32 (*init_params
)(struct e1000_hw
*);
502 s32 (*id_led_init
)(struct e1000_hw
*);
503 s32 (*blink_led
)(struct e1000_hw
*);
504 bool (*check_mng_mode
)(struct e1000_hw
*);
505 s32 (*check_for_link
)(struct e1000_hw
*);
506 s32 (*cleanup_led
)(struct e1000_hw
*);
507 void (*clear_hw_cntrs
)(struct e1000_hw
*);
508 void (*clear_vfta
)(struct e1000_hw
*);
509 s32 (*get_bus_info
)(struct e1000_hw
*);
510 void (*set_lan_id
)(struct e1000_hw
*);
511 s32 (*get_link_up_info
)(struct e1000_hw
*, u16
*, u16
*);
512 s32 (*led_on
)(struct e1000_hw
*);
513 s32 (*led_off
)(struct e1000_hw
*);
514 void (*update_mc_addr_list
)(struct e1000_hw
*, u8
*, u32
);
515 s32 (*reset_hw
)(struct e1000_hw
*);
516 s32 (*init_hw
)(struct e1000_hw
*);
517 void (*shutdown_serdes
)(struct e1000_hw
*);
518 void (*power_up_serdes
)(struct e1000_hw
*);
519 s32 (*setup_link
)(struct e1000_hw
*);
520 s32 (*setup_physical_interface
)(struct e1000_hw
*);
521 s32 (*setup_led
)(struct e1000_hw
*);
522 void (*write_vfta
)(struct e1000_hw
*, u32
, u32
);
523 void (*config_collision_dist
)(struct e1000_hw
*);
524 void (*rar_set
)(struct e1000_hw
*, u8
*, u32
);
525 s32 (*read_mac_addr
)(struct e1000_hw
*);
526 s32 (*validate_mdi_setting
)(struct e1000_hw
*);
527 s32 (*get_thermal_sensor_data
)(struct e1000_hw
*);
528 s32 (*init_thermal_sensor_thresh
)(struct e1000_hw
*);
529 s32 (*acquire_swfw_sync
)(struct e1000_hw
*, u16
);
530 void (*release_swfw_sync
)(struct e1000_hw
*, u16
);
533 /* When to use various PHY register access functions:
536 * Function Does Does When to use
537 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
538 * X_reg L,P,A n/a for simple PHY reg accesses
539 * X_reg_locked P,A L for multiple accesses of different regs
541 * X_reg_page A L,P for multiple accesses of different regs
544 * Where X=[read|write], L=locking, P=sets page, A=register access
547 struct e1000_phy_operations
{
548 s32 (*init_params
)(struct e1000_hw
*);
549 s32 (*acquire
)(struct e1000_hw
*);
550 s32 (*check_polarity
)(struct e1000_hw
*);
551 s32 (*check_reset_block
)(struct e1000_hw
*);
552 s32 (*commit
)(struct e1000_hw
*);
553 s32 (*force_speed_duplex
)(struct e1000_hw
*);
554 s32 (*get_cfg_done
)(struct e1000_hw
*hw
);
555 s32 (*get_cable_length
)(struct e1000_hw
*);
556 s32 (*get_info
)(struct e1000_hw
*);
557 s32 (*set_page
)(struct e1000_hw
*, u16
);
558 s32 (*read_reg
)(struct e1000_hw
*, u32
, u16
*);
559 s32 (*read_reg_locked
)(struct e1000_hw
*, u32
, u16
*);
560 s32 (*read_reg_page
)(struct e1000_hw
*, u32
, u16
*);
561 void (*release
)(struct e1000_hw
*);
562 s32 (*reset
)(struct e1000_hw
*);
563 s32 (*set_d0_lplu_state
)(struct e1000_hw
*, bool);
564 s32 (*set_d3_lplu_state
)(struct e1000_hw
*, bool);
565 s32 (*write_reg
)(struct e1000_hw
*, u32
, u16
);
566 s32 (*write_reg_locked
)(struct e1000_hw
*, u32
, u16
);
567 s32 (*write_reg_page
)(struct e1000_hw
*, u32
, u16
);
568 void (*power_up
)(struct e1000_hw
*);
569 void (*power_down
)(struct e1000_hw
*);
570 s32 (*read_i2c_byte
)(struct e1000_hw
*, u8
, u8
, u8
*);
571 s32 (*write_i2c_byte
)(struct e1000_hw
*, u8
, u8
, u8
);
574 /* Function pointers for the NVM. */
575 struct e1000_nvm_operations
{
576 s32 (*init_params
)(struct e1000_hw
*);
577 s32 (*acquire
)(struct e1000_hw
*);
578 s32 (*read
)(struct e1000_hw
*, u16
, u16
, u16
*);
579 void (*release
)(struct e1000_hw
*);
580 void (*reload
)(struct e1000_hw
*);
581 s32 (*update
)(struct e1000_hw
*);
582 s32 (*valid_led_default
)(struct e1000_hw
*, u16
*);
583 s32 (*validate
)(struct e1000_hw
*);
584 s32 (*write
)(struct e1000_hw
*, u16
, u16
, u16
*);
587 #define E1000_MAX_SENSORS 3
589 struct e1000_thermal_diode_data
{
596 struct e1000_thermal_sensor_data
{
597 struct e1000_thermal_diode_data sensor
[E1000_MAX_SENSORS
];
600 struct e1000_mac_info
{
601 struct e1000_mac_operations ops
;
602 u8 addr
[ETH_ADDR_LEN
];
603 u8 perm_addr
[ETH_ADDR_LEN
];
605 enum e1000_mac_type type
;
623 /* Maximum size of the MTA register table in all supported adapters */
624 #define MAX_MTA_REG 128
625 u32 mta_shadow
[MAX_MTA_REG
];
628 u8 forced_speed_duplex
;
632 bool arc_subsystem_valid
;
633 bool asf_firmware_present
;
636 bool get_link_status
;
638 enum e1000_serdes_link_state serdes_link_state
;
639 bool serdes_has_link
;
640 bool tx_pkt_filtering
;
641 struct e1000_thermal_sensor_data thermal_sensor_data
;
644 struct e1000_phy_info
{
645 struct e1000_phy_operations ops
;
646 enum e1000_phy_type type
;
648 enum e1000_1000t_rx_status local_rx
;
649 enum e1000_1000t_rx_status remote_rx
;
650 enum e1000_ms_type ms_type
;
651 enum e1000_ms_type original_ms_type
;
652 enum e1000_rev_polarity cable_polarity
;
653 enum e1000_smart_speed smart_speed
;
657 u32 reset_delay_us
; /* in usec */
660 enum e1000_media_type media_type
;
662 u16 autoneg_advertised
;
665 u16 max_cable_length
;
666 u16 min_cable_length
;
670 bool disable_polarity_correction
;
672 bool polarity_correction
;
674 bool speed_downgraded
;
675 bool autoneg_wait_to_complete
;
678 struct e1000_nvm_info
{
679 struct e1000_nvm_operations ops
;
680 enum e1000_nvm_type type
;
681 enum e1000_nvm_override override
;
693 struct e1000_bus_info
{
694 enum e1000_bus_type type
;
695 enum e1000_bus_speed speed
;
696 enum e1000_bus_width width
;
702 struct e1000_fc_info
{
703 u32 high_water
; /* Flow control high-water mark */
704 u32 low_water
; /* Flow control low-water mark */
705 u16 pause_time
; /* Flow control pause timer */
706 u16 refresh_time
; /* Flow control refresh timer */
707 bool send_xon
; /* Flow control send XON */
708 bool strict_ieee
; /* Strict IEEE mode */
709 enum e1000_fc_mode current_mode
; /* FC mode in effect */
710 enum e1000_fc_mode requested_mode
; /* FC mode requested by caller */
713 struct e1000_mbx_operations
{
714 s32 (*init_params
)(struct e1000_hw
*hw
);
715 s32 (*read
)(struct e1000_hw
*, u32
*, u16
, u16
);
716 s32 (*write
)(struct e1000_hw
*, u32
*, u16
, u16
);
717 s32 (*read_posted
)(struct e1000_hw
*, u32
*, u16
, u16
);
718 s32 (*write_posted
)(struct e1000_hw
*, u32
*, u16
, u16
);
719 s32 (*check_for_msg
)(struct e1000_hw
*, u16
);
720 s32 (*check_for_ack
)(struct e1000_hw
*, u16
);
721 s32 (*check_for_rst
)(struct e1000_hw
*, u16
);
724 struct e1000_mbx_stats
{
733 struct e1000_mbx_info
{
734 struct e1000_mbx_operations ops
;
735 struct e1000_mbx_stats stats
;
741 struct e1000_dev_spec_82575
{
743 bool global_device_reset
;
746 bool clear_semaphore_once
;
748 struct sfp_e1000_flags eth_flags
;
753 struct e1000_dev_spec_vf
{
762 u8 __iomem
*flash_address
;
763 unsigned long io_base
;
765 struct e1000_mac_info mac
;
766 struct e1000_fc_info fc
;
767 struct e1000_phy_info phy
;
768 struct e1000_nvm_info nvm
;
769 struct e1000_bus_info bus
;
770 struct e1000_mbx_info mbx
;
771 struct e1000_host_mng_dhcp_cookie mng_cookie
;
774 struct e1000_dev_spec_82575 _82575
;
775 struct e1000_dev_spec_vf vf
;
779 u16 subsystem_vendor_id
;
780 u16 subsystem_device_id
;
786 #include "e1000_82575.h"
787 #include "e1000_i210.h"
789 /* These functions must be implemented by drivers */
790 s32
e1000_read_pcie_cap_reg(struct e1000_hw
*hw
, u32 reg
, u16
*value
);
791 s32
e1000_write_pcie_cap_reg(struct e1000_hw
*hw
, u32 reg
, u16
*value
);