1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "LICENSE.GPL".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include "ixgbe_x540.h"
29 #include "ixgbe_type.h"
30 #include "ixgbe_api.h"
31 #include "ixgbe_common.h"
32 #include "ixgbe_phy.h"
34 static s32
ixgbe_update_flash_X540(struct ixgbe_hw
*hw
);
35 static s32
ixgbe_poll_flash_update_done_X540(struct ixgbe_hw
*hw
);
36 static s32
ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw
*hw
);
37 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw
*hw
);
40 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
41 * @hw: pointer to hardware structure
43 * Initialize the function pointers and assign the MAC type for X540.
44 * Does not touch the hardware.
46 s32
ixgbe_init_ops_X540(struct ixgbe_hw
*hw
)
48 struct ixgbe_mac_info
*mac
= &hw
->mac
;
49 struct ixgbe_phy_info
*phy
= &hw
->phy
;
50 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
53 ret_val
= ixgbe_init_phy_ops_generic(hw
);
54 ret_val
= ixgbe_init_ops_generic(hw
);
58 eeprom
->ops
.init_params
= &ixgbe_init_eeprom_params_X540
;
59 eeprom
->ops
.read
= &ixgbe_read_eerd_X540
;
60 eeprom
->ops
.read_buffer
= &ixgbe_read_eerd_buffer_X540
;
61 eeprom
->ops
.write
= &ixgbe_write_eewr_X540
;
62 eeprom
->ops
.write_buffer
= &ixgbe_write_eewr_buffer_X540
;
63 eeprom
->ops
.update_checksum
= &ixgbe_update_eeprom_checksum_X540
;
64 eeprom
->ops
.validate_checksum
= &ixgbe_validate_eeprom_checksum_X540
;
65 eeprom
->ops
.calc_checksum
= &ixgbe_calc_eeprom_checksum_X540
;
68 phy
->ops
.init
= &ixgbe_init_phy_ops_generic
;
69 phy
->ops
.reset
= NULL
;
72 mac
->ops
.reset_hw
= &ixgbe_reset_hw_X540
;
73 mac
->ops
.get_media_type
= &ixgbe_get_media_type_X540
;
74 mac
->ops
.get_supported_physical_layer
=
75 &ixgbe_get_supported_physical_layer_X540
;
76 mac
->ops
.read_analog_reg8
= NULL
;
77 mac
->ops
.write_analog_reg8
= NULL
;
78 mac
->ops
.start_hw
= &ixgbe_start_hw_X540
;
79 mac
->ops
.get_san_mac_addr
= &ixgbe_get_san_mac_addr_generic
;
80 mac
->ops
.set_san_mac_addr
= &ixgbe_set_san_mac_addr_generic
;
81 mac
->ops
.get_device_caps
= &ixgbe_get_device_caps_generic
;
82 mac
->ops
.get_wwn_prefix
= &ixgbe_get_wwn_prefix_generic
;
83 mac
->ops
.get_fcoe_boot_status
= &ixgbe_get_fcoe_boot_status_generic
;
84 mac
->ops
.acquire_swfw_sync
= &ixgbe_acquire_swfw_sync_X540
;
85 mac
->ops
.release_swfw_sync
= &ixgbe_release_swfw_sync_X540
;
86 mac
->ops
.disable_sec_rx_path
= &ixgbe_disable_sec_rx_path_generic
;
87 mac
->ops
.enable_sec_rx_path
= &ixgbe_enable_sec_rx_path_generic
;
89 /* RAR, Multicast, VLAN */
90 mac
->ops
.set_vmdq
= &ixgbe_set_vmdq_generic
;
91 mac
->ops
.set_vmdq_san_mac
= &ixgbe_set_vmdq_san_mac_generic
;
92 mac
->ops
.clear_vmdq
= &ixgbe_clear_vmdq_generic
;
93 mac
->ops
.insert_mac_addr
= &ixgbe_insert_mac_addr_generic
;
94 mac
->rar_highwater
= 1;
95 mac
->ops
.set_vfta
= &ixgbe_set_vfta_generic
;
96 mac
->ops
.set_vlvf
= &ixgbe_set_vlvf_generic
;
97 mac
->ops
.clear_vfta
= &ixgbe_clear_vfta_generic
;
98 mac
->ops
.init_uta_tables
= &ixgbe_init_uta_tables_generic
;
99 mac
->ops
.set_mac_anti_spoofing
= &ixgbe_set_mac_anti_spoofing
;
100 mac
->ops
.set_vlan_anti_spoofing
= &ixgbe_set_vlan_anti_spoofing
;
103 mac
->ops
.get_link_capabilities
=
104 &ixgbe_get_copper_link_capabilities_generic
;
105 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_X540
;
106 mac
->ops
.setup_rxpba
= &ixgbe_set_rxpba_generic
;
107 mac
->ops
.check_link
= &ixgbe_check_mac_link_generic
;
109 mac
->mcft_size
= 128;
111 mac
->num_rar_entries
= 128;
112 mac
->rx_pb_size
= 384;
113 mac
->max_tx_queues
= 128;
114 mac
->max_rx_queues
= 128;
115 mac
->max_msix_vectors
= ixgbe_get_pcie_msix_count_generic(hw
);
119 * ARC supported; valid only if manageability features are
122 mac
->arc_subsystem_valid
= (IXGBE_READ_REG(hw
, IXGBE_FWSM
) &
123 IXGBE_FWSM_MODE_MASK
) ? true : false;
125 //hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
128 mac
->ops
.blink_led_start
= ixgbe_blink_led_start_X540
;
129 mac
->ops
.blink_led_stop
= ixgbe_blink_led_stop_X540
;
131 /* Manageability interface */
132 mac
->ops
.set_fw_drv_ver
= &ixgbe_set_fw_drv_ver_generic
;
138 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
139 * @hw: pointer to hardware structure
140 * @speed: pointer to link speed
141 * @autoneg: true when autoneg or autotry is enabled
143 * Determines the link capabilities by reading the AUTOC register.
145 s32
ixgbe_get_link_capabilities_X540(struct ixgbe_hw
*hw
,
146 ixgbe_link_speed
*speed
,
149 ixgbe_get_copper_link_capabilities_generic(hw
, speed
, autoneg
);
155 * ixgbe_get_media_type_X540 - Get media type
156 * @hw: pointer to hardware structure
158 * Returns the media type (fiber, copper, backplane)
160 enum ixgbe_media_type
ixgbe_get_media_type_X540(struct ixgbe_hw
*hw
)
162 return ixgbe_media_type_copper
;
166 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
167 * @hw: pointer to hardware structure
168 * @speed: new link speed
169 * @autoneg: true if autonegotiation enabled
170 * @autoneg_wait_to_complete: true when waiting for completion is needed
172 s32
ixgbe_setup_mac_link_X540(struct ixgbe_hw
*hw
,
173 ixgbe_link_speed speed
, bool autoneg
,
174 bool autoneg_wait_to_complete
)
176 return hw
->phy
.ops
.setup_link_speed(hw
, speed
, autoneg
,
177 autoneg_wait_to_complete
);
181 * ixgbe_reset_hw_X540 - Perform hardware reset
182 * @hw: pointer to hardware structure
184 * Resets the hardware by resetting the transmit and receive units, masks
185 * and clears all interrupts, and perform a reset.
187 s32
ixgbe_reset_hw_X540(struct ixgbe_hw
*hw
)
192 * Userland DPDK takes the ownershiop of device
193 * Kernel driver here used as the simple path for ethtool only
194 * Won't real reset device anyway
199 /* Call adapter stop to disable tx/rx and clear interrupts */
200 status
= hw
->mac
.ops
.stop_adapter(hw
);
204 /* flush pending Tx transactions */
205 ixgbe_clear_tx_pending(hw
);
208 ctrl
= IXGBE_CTRL_RST
;
209 ctrl
|= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
210 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
211 IXGBE_WRITE_FLUSH(hw
);
213 /* Poll for reset bit to self-clear indicating reset is complete */
214 for (i
= 0; i
< 10; i
++) {
216 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
217 if (!(ctrl
& IXGBE_CTRL_RST_MASK
))
221 if (ctrl
& IXGBE_CTRL_RST_MASK
) {
222 status
= IXGBE_ERR_RESET_FAILED
;
223 hw_dbg(hw
, "Reset polling failed to complete.\n");
228 * Double resets are required for recovery from certain error
229 * conditions. Between resets, it is necessary to stall to allow time
230 * for any pending HW events to complete.
232 if (hw
->mac
.flags
& IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
) {
233 hw
->mac
.flags
&= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
237 /* Set the Rx packet buffer size. */
238 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT
);
242 /* Store the permanent mac address */
243 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.perm_addr
);
246 * Store MAC address from RAR0, clear receive address registers, and
247 * clear the multicast table. Also reset num_rar_entries to 128,
248 * since we modify this value when programming the SAN MAC address.
250 hw
->mac
.num_rar_entries
= 128;
251 hw
->mac
.ops
.init_rx_addrs(hw
);
253 /* Store the permanent SAN mac address */
254 hw
->mac
.ops
.get_san_mac_addr(hw
, hw
->mac
.san_addr
);
256 /* Add the SAN MAC address to the RAR only if it's a valid address */
257 if (ixgbe_validate_mac_addr(hw
->mac
.san_addr
) == 0) {
258 hw
->mac
.ops
.set_rar(hw
, hw
->mac
.num_rar_entries
- 1,
259 hw
->mac
.san_addr
, 0, IXGBE_RAH_AV
);
261 /* Save the SAN MAC RAR index */
262 hw
->mac
.san_mac_rar_index
= hw
->mac
.num_rar_entries
- 1;
264 /* Reserve the last RAR for the SAN MAC address */
265 hw
->mac
.num_rar_entries
--;
268 /* Store the alternative WWNN/WWPN prefix */
269 hw
->mac
.ops
.get_wwn_prefix(hw
, &hw
->mac
.wwnn_prefix
,
270 &hw
->mac
.wwpn_prefix
);
277 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
278 * @hw: pointer to hardware structure
280 * Starts the hardware using the generic start_hw function
281 * and the generation start_hw function.
282 * Then performs revision-specific operations, if any.
284 s32
ixgbe_start_hw_X540(struct ixgbe_hw
*hw
)
288 ret_val
= ixgbe_start_hw_generic(hw
);
292 ret_val
= ixgbe_start_hw_gen2(hw
);
299 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
300 * @hw: pointer to hardware structure
302 * Determines physical layer capabilities of the current configuration.
304 u32
ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw
*hw
)
306 u32 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
309 hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_PHY_EXT_ABILITY
,
310 IXGBE_MDIO_PMA_PMD_DEV_TYPE
, &ext_ability
);
311 if (ext_ability
& IXGBE_MDIO_PHY_10GBASET_ABILITY
)
312 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_T
;
313 if (ext_ability
& IXGBE_MDIO_PHY_1000BASET_ABILITY
)
314 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
315 if (ext_ability
& IXGBE_MDIO_PHY_100BASETX_ABILITY
)
316 physical_layer
|= IXGBE_PHYSICAL_LAYER_100BASE_TX
;
318 return physical_layer
;
322 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
323 * @hw: pointer to hardware structure
325 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
326 * ixgbe_hw struct in order to set up EEPROM access.
328 s32
ixgbe_init_eeprom_params_X540(struct ixgbe_hw
*hw
)
330 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
334 if (eeprom
->type
== ixgbe_eeprom_uninitialized
) {
335 eeprom
->semaphore_delay
= 10;
336 eeprom
->type
= ixgbe_flash
;
338 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
339 eeprom_size
= (u16
)((eec
& IXGBE_EEC_SIZE
) >>
340 IXGBE_EEC_SIZE_SHIFT
);
341 eeprom
->word_size
= 1 << (eeprom_size
+
342 IXGBE_EEPROM_WORD_SIZE_SHIFT
);
344 hw_dbg(hw
, "Eeprom params: type = %d, size = %d\n",
345 eeprom
->type
, eeprom
->word_size
);
352 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
353 * @hw: pointer to hardware structure
354 * @offset: offset of word in the EEPROM to read
355 * @data: word read from the EEPROM
357 * Reads a 16 bit word from the EEPROM using the EERD register.
359 s32
ixgbe_read_eerd_X540(struct ixgbe_hw
*hw
, u16 offset
, u16
*data
)
363 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) ==
365 status
= ixgbe_read_eerd_generic(hw
, offset
, data
);
367 status
= IXGBE_ERR_SWFW_SYNC
;
369 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
374 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
375 * @hw: pointer to hardware structure
376 * @offset: offset of word in the EEPROM to read
377 * @words: number of words
378 * @data: word(s) read from the EEPROM
380 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
382 s32
ixgbe_read_eerd_buffer_X540(struct ixgbe_hw
*hw
,
383 u16 offset
, u16 words
, u16
*data
)
387 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) ==
389 status
= ixgbe_read_eerd_buffer_generic(hw
, offset
,
392 status
= IXGBE_ERR_SWFW_SYNC
;
394 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
399 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
400 * @hw: pointer to hardware structure
401 * @offset: offset of word in the EEPROM to write
402 * @data: word write to the EEPROM
404 * Write a 16 bit word to the EEPROM using the EEWR register.
406 s32
ixgbe_write_eewr_X540(struct ixgbe_hw
*hw
, u16 offset
, u16 data
)
410 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) ==
412 status
= ixgbe_write_eewr_generic(hw
, offset
, data
);
414 status
= IXGBE_ERR_SWFW_SYNC
;
416 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
421 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
422 * @hw: pointer to hardware structure
423 * @offset: offset of word in the EEPROM to write
424 * @words: number of words
425 * @data: word(s) write to the EEPROM
427 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
429 s32
ixgbe_write_eewr_buffer_X540(struct ixgbe_hw
*hw
,
430 u16 offset
, u16 words
, u16
*data
)
434 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) ==
436 status
= ixgbe_write_eewr_buffer_generic(hw
, offset
,
439 status
= IXGBE_ERR_SWFW_SYNC
;
441 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
446 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
448 * This function does not use synchronization for EERD and EEWR. It can
449 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
451 * @hw: pointer to hardware structure
453 u16
ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw
*hw
)
463 * Do not use hw->eeprom.ops.read because we do not want to take
464 * the synchronization semaphores here. Instead use
465 * ixgbe_read_eerd_generic
468 /* Include 0x0-0x3F in the checksum */
469 for (i
= 0; i
< IXGBE_EEPROM_CHECKSUM
; i
++) {
470 if (ixgbe_read_eerd_generic(hw
, i
, &word
) != 0) {
471 hw_dbg(hw
, "EEPROM read failed\n");
478 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
479 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
481 for (i
= IXGBE_PCIE_ANALOG_PTR
; i
< IXGBE_FW_PTR
; i
++) {
482 if (i
== IXGBE_PHY_PTR
|| i
== IXGBE_OPTION_ROM_PTR
)
485 if (ixgbe_read_eerd_generic(hw
, i
, &pointer
) != 0) {
486 hw_dbg(hw
, "EEPROM read failed\n");
490 /* Skip pointer section if the pointer is invalid. */
491 if (pointer
== 0xFFFF || pointer
== 0 ||
492 pointer
>= hw
->eeprom
.word_size
)
495 if (ixgbe_read_eerd_generic(hw
, pointer
, &length
) !=
497 hw_dbg(hw
, "EEPROM read failed\n");
501 /* Skip pointer section if length is invalid. */
502 if (length
== 0xFFFF || length
== 0 ||
503 (pointer
+ length
) >= hw
->eeprom
.word_size
)
506 for (j
= pointer
+1; j
<= pointer
+length
; j
++) {
507 if (ixgbe_read_eerd_generic(hw
, j
, &word
) !=
509 hw_dbg(hw
, "EEPROM read failed\n");
516 checksum
= (u16
)IXGBE_EEPROM_SUM
- checksum
;
522 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
523 * @hw: pointer to hardware structure
524 * @checksum_val: calculated checksum
526 * Performs checksum calculation and validates the EEPROM checksum. If the
527 * caller does not need checksum_val, the value can be NULL.
529 s32
ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw
*hw
,
534 u16 read_checksum
= 0;
537 * Read the first word from the EEPROM. If this times out or fails, do
538 * not continue or we could be in for a very long wait while every
541 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
544 hw_dbg(hw
, "EEPROM read failed\n");
548 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) ==
550 checksum
= hw
->eeprom
.ops
.calc_checksum(hw
);
553 * Do not use hw->eeprom.ops.read because we do not want to take
554 * the synchronization semaphores twice here.
556 ixgbe_read_eerd_generic(hw
, IXGBE_EEPROM_CHECKSUM
,
560 * Verify read checksum from EEPROM is the same as
561 * calculated checksum
563 if (read_checksum
!= checksum
)
564 status
= IXGBE_ERR_EEPROM_CHECKSUM
;
566 /* If the user cares, return the calculated checksum */
568 *checksum_val
= checksum
;
570 status
= IXGBE_ERR_SWFW_SYNC
;
573 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
579 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
580 * @hw: pointer to hardware structure
582 * After writing EEPROM to shadow RAM using EEWR register, software calculates
583 * checksum and updates the EEPROM and instructs the hardware to update
586 s32
ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw
*hw
)
592 * Read the first word from the EEPROM. If this times out or fails, do
593 * not continue or we could be in for a very long wait while every
596 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
599 hw_dbg(hw
, "EEPROM read failed\n");
601 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) ==
603 checksum
= hw
->eeprom
.ops
.calc_checksum(hw
);
606 * Do not use hw->eeprom.ops.write because we do not want to
607 * take the synchronization semaphores twice here.
609 status
= ixgbe_write_eewr_generic(hw
, IXGBE_EEPROM_CHECKSUM
,
613 status
= ixgbe_update_flash_X540(hw
);
615 status
= IXGBE_ERR_SWFW_SYNC
;
618 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
624 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
625 * @hw: pointer to hardware structure
627 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
628 * EEPROM from shadow RAM to the flash device.
630 static s32
ixgbe_update_flash_X540(struct ixgbe_hw
*hw
)
633 s32 status
= IXGBE_ERR_EEPROM
;
635 status
= ixgbe_poll_flash_update_done_X540(hw
);
636 if (status
== IXGBE_ERR_EEPROM
) {
637 hw_dbg(hw
, "Flash update time out\n");
641 flup
= IXGBE_READ_REG(hw
, IXGBE_EEC
) | IXGBE_EEC_FLUP
;
642 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, flup
);
644 status
= ixgbe_poll_flash_update_done_X540(hw
);
646 hw_dbg(hw
, "Flash update complete\n");
648 hw_dbg(hw
, "Flash update time out\n");
650 if (hw
->revision_id
== 0) {
651 flup
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
653 if (flup
& IXGBE_EEC_SEC1VAL
) {
654 flup
|= IXGBE_EEC_FLUP
;
655 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, flup
);
658 status
= ixgbe_poll_flash_update_done_X540(hw
);
660 hw_dbg(hw
, "Flash update complete\n");
662 hw_dbg(hw
, "Flash update time out\n");
669 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
670 * @hw: pointer to hardware structure
672 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
673 * flash update is done.
675 static s32
ixgbe_poll_flash_update_done_X540(struct ixgbe_hw
*hw
)
679 s32 status
= IXGBE_ERR_EEPROM
;
681 for (i
= 0; i
< IXGBE_FLUDONE_ATTEMPTS
; i
++) {
682 reg
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
683 if (reg
& IXGBE_EEC_FLUDONE
) {
693 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
694 * @hw: pointer to hardware structure
695 * @mask: Mask to specify which semaphore to acquire
697 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
698 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
700 s32
ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw
*hw
, u16 mask
)
704 u32 fwmask
= mask
<< 5;
710 if (swmask
== IXGBE_GSSR_EEP_SM
)
711 hwmask
= IXGBE_GSSR_FLASH_SM
;
713 /* SW only mask doesn't have FW bit pair */
714 if (swmask
== IXGBE_GSSR_SW_MNG_SM
)
717 for (i
= 0; i
< timeout
; i
++) {
719 * SW NVM semaphore bit is used for access to all
720 * SW_FW_SYNC bits (not just NVM)
722 if (ixgbe_get_swfw_sync_semaphore(hw
)) {
723 ret_val
= IXGBE_ERR_SWFW_SYNC
;
727 swfw_sync
= IXGBE_READ_REG(hw
, IXGBE_SWFW_SYNC
);
728 if (!(swfw_sync
& (fwmask
| swmask
| hwmask
))) {
730 IXGBE_WRITE_REG(hw
, IXGBE_SWFW_SYNC
, swfw_sync
);
731 ixgbe_release_swfw_sync_semaphore(hw
);
736 * Firmware currently using resource (fwmask), hardware
737 * currently using resource (hwmask), or other software
738 * thread currently using resource (swmask)
740 ixgbe_release_swfw_sync_semaphore(hw
);
745 /* Failed to get SW only semaphore */
746 if (swmask
== IXGBE_GSSR_SW_MNG_SM
) {
747 ret_val
= IXGBE_ERR_SWFW_SYNC
;
751 /* If the resource is not released by the FW/HW the SW can assume that
752 * the FW/HW malfunctions. In that case the SW should sets the SW bit(s)
753 * of the requested resource(s) while ignoring the corresponding FW/HW
754 * bits in the SW_FW_SYNC register.
756 swfw_sync
= IXGBE_READ_REG(hw
, IXGBE_SWFW_SYNC
);
757 if (swfw_sync
& (fwmask
| hwmask
)) {
758 if (ixgbe_get_swfw_sync_semaphore(hw
)) {
759 ret_val
= IXGBE_ERR_SWFW_SYNC
;
764 IXGBE_WRITE_REG(hw
, IXGBE_SWFW_SYNC
, swfw_sync
);
765 ixgbe_release_swfw_sync_semaphore(hw
);
774 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
775 * @hw: pointer to hardware structure
776 * @mask: Mask to specify which semaphore to release
778 * Releases the SWFW semaphore through the SW_FW_SYNC register
779 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
781 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw
*hw
, u16 mask
)
786 ixgbe_get_swfw_sync_semaphore(hw
);
788 swfw_sync
= IXGBE_READ_REG(hw
, IXGBE_SWFW_SYNC
);
789 swfw_sync
&= ~swmask
;
790 IXGBE_WRITE_REG(hw
, IXGBE_SWFW_SYNC
, swfw_sync
);
792 ixgbe_release_swfw_sync_semaphore(hw
);
797 * ixgbe_get_nvm_semaphore - Get hardware semaphore
798 * @hw: pointer to hardware structure
800 * Sets the hardware semaphores so SW/FW can gain control of shared resources
802 static s32
ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw
*hw
)
804 s32 status
= IXGBE_ERR_EEPROM
;
809 /* Get SMBI software semaphore between device drivers first */
810 for (i
= 0; i
< timeout
; i
++) {
812 * If the SMBI bit is 0 when we read it, then the bit will be
813 * set and we have the semaphore
815 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
816 if (!(swsm
& IXGBE_SWSM_SMBI
)) {
823 /* Now get the semaphore between SW/FW through the REGSMP bit */
825 for (i
= 0; i
< timeout
; i
++) {
826 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWFW_SYNC
);
827 if (!(swsm
& IXGBE_SWFW_REGSMP
))
834 * Release semaphores and return error if SW NVM semaphore
835 * was not granted because we don't have access to the EEPROM
838 hw_dbg(hw
, "REGSMP Software NVM semaphore not "
840 ixgbe_release_swfw_sync_semaphore(hw
);
841 status
= IXGBE_ERR_EEPROM
;
844 hw_dbg(hw
, "Software semaphore SMBI between device drivers "
852 * ixgbe_release_nvm_semaphore - Release hardware semaphore
853 * @hw: pointer to hardware structure
855 * This function clears hardware semaphore bits.
857 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw
*hw
)
861 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
863 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
864 swsm
&= ~IXGBE_SWSM_SMBI
;
865 IXGBE_WRITE_REG(hw
, IXGBE_SWSM
, swsm
);
867 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWFW_SYNC
);
868 swsm
&= ~IXGBE_SWFW_REGSMP
;
869 IXGBE_WRITE_REG(hw
, IXGBE_SWFW_SYNC
, swsm
);
871 IXGBE_WRITE_FLUSH(hw
);
875 * ixgbe_blink_led_start_X540 - Blink LED based on index.
876 * @hw: pointer to hardware structure
877 * @index: led number to blink
879 * Devices that implement the version 2 interface:
882 s32
ixgbe_blink_led_start_X540(struct ixgbe_hw
*hw
, u32 index
)
886 ixgbe_link_speed speed
;
890 * Link should be up in order for the blink bit in the LED control
891 * register to work. Force link and speed in the MAC if link is down.
892 * This will be reversed when we stop the blinking.
894 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
895 if (link_up
== false) {
896 macc_reg
= IXGBE_READ_REG(hw
, IXGBE_MACC
);
897 macc_reg
|= IXGBE_MACC_FLU
| IXGBE_MACC_FSV_10G
| IXGBE_MACC_FS
;
898 IXGBE_WRITE_REG(hw
, IXGBE_MACC
, macc_reg
);
900 /* Set the LED to LINK_UP + BLINK. */
901 ledctl_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
902 ledctl_reg
&= ~IXGBE_LED_MODE_MASK(index
);
903 ledctl_reg
|= IXGBE_LED_BLINK(index
);
904 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, ledctl_reg
);
905 IXGBE_WRITE_FLUSH(hw
);
911 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
912 * @hw: pointer to hardware structure
913 * @index: led number to stop blinking
915 * Devices that implement the version 2 interface:
918 s32
ixgbe_blink_led_stop_X540(struct ixgbe_hw
*hw
, u32 index
)
923 /* Restore the LED to its default value. */
924 ledctl_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
925 ledctl_reg
&= ~IXGBE_LED_MODE_MASK(index
);
926 ledctl_reg
|= IXGBE_LED_LINK_ACTIVE
<< IXGBE_LED_MODE_SHIFT(index
);
927 ledctl_reg
&= ~IXGBE_LED_BLINK(index
);
928 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, ledctl_reg
);
930 /* Unforce link and speed in the MAC. */
931 macc_reg
= IXGBE_READ_REG(hw
, IXGBE_MACC
);
932 macc_reg
&= ~(IXGBE_MACC_FLU
| IXGBE_MACC_FSV_10G
| IXGBE_MACC_FS
);
933 IXGBE_WRITE_REG(hw
, IXGBE_MACC
, macc_reg
);
934 IXGBE_WRITE_FLUSH(hw
);