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28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
31 ;;; gf_2vect_dot_prod_avx512(len, vec, *g_tbls, **buffs, **dests);
34 %include "reg_sizes.asm"
36 %ifdef HAVE_AS_KNOWS_AVX512
38 %ifidn __OUTPUT_FORMAT__, elf64
48 %define tmp3 r12 ; must be saved and restored
62 %ifidn __OUTPUT_FORMAT__, win64
68 %define arg4 r12 ; must be saved, loaded and restored
69 %define arg5 r15 ; must be saved and restored
72 %define tmp3 r13 ; must be saved and restored
76 %define stack_size 9*16 + 5*8 ; must be an odd multiple of 8
77 %define arg(x) [rsp + stack_size + PS + PS*x]
79 %define func(x) proc_frame x
81 alloc_stack stack_size
82 vmovdqa [rsp + 0*16], xmm6
83 vmovdqa [rsp + 1*16], xmm7
84 vmovdqa [rsp + 2*16], xmm8
85 vmovdqa [rsp + 3*16], xmm9
86 vmovdqa [rsp + 4*16], xmm10
87 vmovdqa [rsp + 5*16], xmm11
88 vmovdqa [rsp + 6*16], xmm12
89 vmovdqa [rsp + 7*16], xmm13
90 vmovdqa [rsp + 8*16], xmm14
91 save_reg r12, 9*16 + 0*8
92 save_reg r13, 9*16 + 1*8
93 save_reg r14, 9*16 + 2*8
94 save_reg r15, 9*16 + 3*8
100 vmovdqa xmm6, [rsp + 0*16]
101 vmovdqa xmm7, [rsp + 1*16]
102 vmovdqa xmm8, [rsp + 2*16]
103 vmovdqa xmm9, [rsp + 3*16]
104 vmovdqa xmm10, [rsp + 4*16]
105 vmovdqa xmm11, [rsp + 5*16]
106 vmovdqa xmm12, [rsp + 6*16]
107 vmovdqa xmm13, [rsp + 7*16]
108 vmovdqa xmm14, [rsp + 8*16]
109 mov r12, [rsp + 9*16 + 0*8]
110 mov r13, [rsp + 9*16 + 1*8]
111 mov r14, [rsp + 9*16 + 2*8]
112 mov r15, [rsp + 9*16 + 3*8]
120 %define mul_array arg2
129 %ifndef EC_ALIGNED_ADDR
130 ;;; Use Un-aligned load/store
131 %define XLDR vmovdqu8
132 %define XSTR vmovdqu8
134 ;;; Use Non-temporal load/stor
139 %define XLDR vmovntdqa
140 %define XSTR vmovntdq
145 %define xgft1_lo zmm7
146 %define xgft1_loy ymm7
147 %define xgft1_hi zmm6
148 %define xgft2_lo zmm5
149 %define xgft2_loy ymm5
150 %define xgft2_hi zmm4
163 global gf_2vect_dot_prod_avx512:function
164 func(gf_2vect_dot_prod_avx512)
171 vpbroadcastb xmask0f, tmp ;Construct mask 0x0f0f0f...
172 sal vec, LOG_PS ;vec *= PS. Make vec_i count by PS
173 mov dest2, [dest1+PS]
184 XLDR x0, [ptr+pos] ;Get next source vector
187 vpandq xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
188 vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
189 vpandq x0, x0, xmask0f ;Mask high src nibble in bits 4-0
191 vmovdqu8 xgft1_loy, [tmp] ;Load array Ax{00}..{0f}, Ax{00}..{f0}
192 vmovdqu8 xgft2_loy, [tmp+vec*(32/PS)] ;Load array Bx{00}..{0f}, Bx{00}..{f0}
195 vshufi64x2 xgft1_hi, xgft1_lo, xgft1_lo, 0x55
196 vshufi64x2 xgft1_lo, xgft1_lo, xgft1_lo, 0x00
197 vshufi64x2 xgft2_hi, xgft2_lo, xgft2_lo, 0x55
198 vshufi64x2 xgft2_lo, xgft2_lo, xgft2_lo, 0x00
200 vpshufb xgft1_hi, xgft1_hi, x0 ;Lookup mul table of high nibble
201 vpshufb xgft1_lo, xgft1_lo, xtmpa ;Lookup mul table of low nibble
202 vpxorq xgft1_hi, xgft1_hi, xgft1_lo ;GF add high and low partials
203 vpxorq xp1, xp1, xgft1_hi ;xp1 += partial
205 vpshufb xgft2_hi, xgft2_hi, x0 ;Lookup mul table of high nibble
206 vpshufb xgft2_lo, xgft2_lo, xtmpa ;Lookup mul table of low nibble
207 vpxorq xgft2_hi, xgft2_hi, xgft2_lo ;GF add high and low partials
208 vpxorq xp2, xp2, xgft2_hi ;xp2 += partial
213 XSTR [dest1+pos], xp1
214 XSTR [dest2+pos], xp2
216 add pos, 64 ;Loop on 64 bytes at a time
225 mov pos, len ;Overlapped offset length-64
226 jmp .loop64 ;Do one more overlap pass
241 %ifidn __OUTPUT_FORMAT__, win64
242 global no_gf_2vect_dot_prod_avx512
243 no_gf_2vect_dot_prod_avx512:
245 %endif ; ifdef HAVE_AS_KNOWS_AVX512