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1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright 2014-2020, Intel Corporation */
4 * ARM inline assembly to flush and invalidate caches
6 * clflushopt => dc civac
12 * Cache instructions on ARM:
13 * ARMv8.0-a DC CVAC - cache clean to Point of Coherency
14 * Meant for thread synchronization, usually implies
15 * real memory flush but may mean less.
16 * ARMv8.2-a DC CVAP - cache clean to Point of Persistency
17 * Meant exactly for our use.
18 * ARMv8.5-a DC CVADP - cache clean to Point of Deep Persistency
19 * As of mid-2019 not on any commercially available CPU.
20 * Any of the above may be disabled for EL0, but it's probably safe to consider
21 * that a system configuration error.
22 * Other flags include I (like "DC CIVAC") that invalidates the cache line, but
27 * * DMB [ISH]ST SFENCE
28 * * DMB [ISH]LD LFENCE
30 * Memory domains (cache coherency):
31 * * non-shareable - local to a single core
32 * * inner shareable (ISH) - a group of CPU clusters/sockets/other hardware
33 * Linux requires that anything within one operating system/hypervisor
34 * is within the same Inner Shareable domain.
35 * * outer shareable (OSH) - one or more separate ISH domains
36 * * full system (SY) - anything that can possibly access memory
37 * Docs: ARM DDI 0487E.a page B2-144.
39 * Exception (privilege) levels:
40 * * EL0 - userspace (ring 3)
41 * * EL1 - kernel (ring 0)
42 * * EL2 - hypervisor (ring -1)
43 * * EL3 - "secure world" (ring -3)
46 #ifndef AARCH64_CACHEOPS_H
47 #define AARCH64_CACHEOPS_H
52 arm_clean_va_to_poc(void const *p
__attribute__((unused
)))
54 asm volatile("dc cvac, %0" : : "r" (p
) : "memory");
58 arm_store_memory_barrier(void)
60 asm volatile("dmb ishst" : : : "memory");