ceph/src/pmdk/src/libpmem2/aarch64/arm_cacheops.h

   1 /* SPDX-License-Identifier: BSD-3-Clause */
   2 /* Copyright 2014-2020, Intel Corporation */
   3 /*
   4  * ARM inline assembly to flush and invalidate caches
   5  * clwb => dc cvac
   6  * clflushopt => dc civac
   7  * fence => dmb ish
   8  * sfence => dmb ishst
   9  */
  10
  11 /*
  12  * Cache instructions on ARM:
  13  * ARMv8.0-a    DC CVAC  - cache clean to Point of Coherency
  14  *                         Meant for thread synchronization, usually implies
  15  *                         real memory flush but may mean less.
  16  * ARMv8.2-a    DC CVAP  - cache clean to Point of Persistency
  17  *                         Meant exactly for our use.
  18  * ARMv8.5-a    DC CVADP - cache clean to Point of Deep Persistency
  19  *                         As of mid-2019 not on any commercially available CPU.
  20  * Any of the above may be disabled for EL0, but it's probably safe to consider
  21  * that a system configuration error.
  22  * Other flags include I (like "DC CIVAC") that invalidates the cache line, but
  23  * we don't want that.
  24  *
  25  * Memory fences:
  26  * * DMB [ISH]    MFENCE
  27  * * DMB [ISH]ST  SFENCE
  28  * * DMB [ISH]LD  LFENCE
  29  *
  30  * Memory domains (cache coherency):
  31  * * non-shareable - local to a single core
  32  * * inner shareable (ISH) - a group of CPU clusters/sockets/other hardware
  33  *      Linux requires that anything within one operating system/hypervisor
  34  *      is within the same Inner Shareable domain.
  35  * * outer shareable (OSH) - one or more separate ISH domains
  36  * * full system (SY) - anything that can possibly access memory
  37  * Docs: ARM DDI 0487E.a page B2-144.
  38  *
  39  * Exception (privilege) levels:
  40  * * EL0 - userspace (ring 3)
  41  * * EL1 - kernel (ring 0)
  42  * * EL2 - hypervisor (ring -1)
  43  * * EL3 - "secure world" (ring -3)
  44  */
  45
  46 #ifndef AARCH64_CACHEOPS_H
  47 #define AARCH64_CACHEOPS_H
  48
  49 #include <stdlib.h>
  50
  51 static inline void
  52 arm_clean_va_to_poc(void const *p __attribute__((unused)))
  53 {
  54         asm volatile("dc cvac, %0" : : "r" (p) : "memory");
  55 }
  56
  57 static inline void
  58 arm_store_memory_barrier(void)
  59 {
  60         asm volatile("dmb ishst" : : : "memory");
  61 }
  62 #endif