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1 /*-
2 * BSD LICENSE
3 *
4 * Copyright(c) 2015 Akamai Technologies.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include "test.h"
35
36 #include <stdio.h>
37 #include <unistd.h>
38 #include <inttypes.h>
39 #include <rte_cycles.h>
40 #include <rte_timer.h>
41 #include <rte_common.h>
42 #include <rte_lcore.h>
43 #include <rte_random.h>
44 #include <rte_malloc.h>
45 #include <rte_pause.h>
46
47 #ifdef RTE_EXEC_ENV_LINUX
48 #define usec_delay(us) usleep(us)
49 #else
50 #define usec_delay(us) rte_delay_us(us)
51 #endif
52
53 #define BILLION (1UL << 30)
54
55 #define TEST_DURATION_S 4 /* in seconds */
56 #define N_TIMERS 50
57
58 static struct rte_timer timer[N_TIMERS];
59 static unsigned timer_lcore_id[N_TIMERS];
60
61 static unsigned master;
62 static volatile unsigned stop_slaves;
63
64 static int reload_timer(struct rte_timer *tim);
65
66 int timer_logtype_test;
67
68 RTE_INIT(test_timer_init_log)
69 {
70 timer_logtype_test = rte_log_register("test.timer");
71 }
72
73 static void
74 timer_cb(struct rte_timer *tim, void *arg __rte_unused)
75 {
76 /* Simulate slow callback function, 100 us. */
77 rte_delay_us(100);
78 if (tim == &timer[0])
79 rte_log(RTE_LOG_DEBUG, timer_logtype_test,
80 "------------------------------------------------\n");
81 rte_log(RTE_LOG_DEBUG, timer_logtype_test, "%s: core %u timer %"
82 PRIuPTR "\n", __func__, rte_lcore_id(), tim - timer);
83 (void)reload_timer(tim);
84 }
85
86 RTE_DEFINE_PER_LCORE(unsigned, n_reset_collisions);
87
88 static int
89 reload_timer(struct rte_timer *tim)
90 {
91 /* Make timer expire roughly when the TSC hits the next BILLION
92 * multiple. Add in timer's index to make them expire in nearly
93 * sorted order. This makes all timers somewhat synchronized,
94 * firing ~2-3 times per second, assuming 2-3 GHz TSCs.
95 */
96 uint64_t ticks = BILLION - (rte_get_timer_cycles() % BILLION) +
97 (tim - timer);
98 int ret;
99
100 ret = rte_timer_reset(tim, ticks, PERIODICAL, master, timer_cb, NULL);
101 if (ret != 0) {
102 rte_log(RTE_LOG_DEBUG, timer_logtype_test,
103 "- core %u failed to reset timer %" PRIuPTR " (OK)\n",
104 rte_lcore_id(), tim - timer);
105 RTE_PER_LCORE(n_reset_collisions) += 1;
106 }
107 return ret;
108 }
109
110 static int
111 slave_main_loop(__attribute__((unused)) void *arg)
112 {
113 unsigned lcore_id = rte_lcore_id();
114 unsigned i;
115
116 RTE_PER_LCORE(n_reset_collisions) = 0;
117
118 printf("Starting main loop on core %u\n", lcore_id);
119
120 while (!stop_slaves) {
121 /* Wait until the timer manager is running.
122 * We know it's running when we see timer[0] NOT pending.
123 */
124 if (rte_timer_pending(&timer[0])) {
125 rte_pause();
126 continue;
127 }
128
129 /* Now, go cause some havoc!
130 * Reload our timers.
131 */
132 for (i = 0; i < N_TIMERS; i++) {
133 if (timer_lcore_id[i] == lcore_id)
134 (void)reload_timer(&timer[i]);
135 }
136 usec_delay(100*1000); /* sleep 100 ms */
137 }
138
139 if (RTE_PER_LCORE(n_reset_collisions) != 0) {
140 printf("- core %u, %u reset collisions (OK)\n",
141 lcore_id, RTE_PER_LCORE(n_reset_collisions));
142 }
143 return 0;
144 }
145
146 static int
147 test_timer_racecond(void)
148 {
149 int ret;
150 uint64_t hz;
151 uint64_t cur_time;
152 uint64_t end_time;
153 int64_t diff = 0;
154 unsigned lcore_id;
155 unsigned i;
156
157 master = lcore_id = rte_lcore_id();
158 hz = rte_get_timer_hz();
159
160 /* init and start timers */
161 for (i = 0; i < N_TIMERS; i++) {
162 rte_timer_init(&timer[i]);
163 ret = reload_timer(&timer[i]);
164 TEST_ASSERT(ret == 0, "reload_timer failed");
165
166 /* Distribute timers to slaves.
167 * Note that we assign timer[0] to the master.
168 */
169 timer_lcore_id[i] = lcore_id;
170 lcore_id = rte_get_next_lcore(lcore_id, 1, 1);
171 }
172
173 /* calculate the "end of test" time */
174 cur_time = rte_get_timer_cycles();
175 end_time = cur_time + (hz * TEST_DURATION_S);
176
177 /* start slave cores */
178 stop_slaves = 0;
179 printf("Start timer manage race condition test (%u seconds)\n",
180 TEST_DURATION_S);
181 rte_eal_mp_remote_launch(slave_main_loop, NULL, SKIP_MASTER);
182
183 while (diff >= 0) {
184 /* run the timers */
185 rte_timer_manage();
186
187 /* wait 100 ms */
188 usec_delay(100*1000);
189
190 cur_time = rte_get_timer_cycles();
191 diff = end_time - cur_time;
192 }
193
194 /* stop slave cores */
195 printf("Stopping timer manage race condition test\n");
196 stop_slaves = 1;
197 rte_eal_mp_wait_lcore();
198
199 /* stop timers */
200 for (i = 0; i < N_TIMERS; i++) {
201 ret = rte_timer_stop(&timer[i]);
202 TEST_ASSERT(ret == 0, "rte_timer_stop failed");
203 }
204
205 return TEST_SUCCESS;
206 }
207
208 REGISTER_TEST_COMMAND(timer_racecond_autotest, test_timer_racecond);