ceph/src/seastar/dpdk/drivers/bus/dpaa/rte_dpaa_bus.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2017 NXP
   4  *
   5  */
   6 #ifndef __RTE_DPAA_BUS_H__
   7 #define __RTE_DPAA_BUS_H__
   8
   9 #include <rte_bus.h>
  10 #include <rte_mempool.h>
  11 #include <dpaax_iova_table.h>
  12
  13 #include <fsl_usd.h>
  14 #include <fsl_qman.h>
  15 #include <fsl_bman.h>
  16 #include <of.h>
  17 #include <netcfg.h>
  18
  19 #define DPAA_MEMPOOL_OPS_NAME   "dpaa"
  20
  21 #define DEV_TO_DPAA_DEVICE(ptr) \
  22                 container_of(ptr, struct rte_dpaa_device, device)
  23
  24 /* DPAA SoC identifier; If this is not available, it can be concluded
  25  * that board is non-DPAA. Single slot is currently supported.
  26  */
  27 #define DPAA_SOC_ID_FILE        "/sys/devices/soc0/soc_id"
  28
  29 #define SVR_LS1043A_FAMILY      0x87920000
  30 #define SVR_LS1046A_FAMILY      0x87070000
  31 #define SVR_MASK                0xffff0000
  32
  33 extern unsigned int dpaa_svr_family;
  34
  35 extern RTE_DEFINE_PER_LCORE(bool, dpaa_io);
  36
  37 struct rte_dpaa_device;
  38 struct rte_dpaa_driver;
  39
  40 /* DPAA Device and Driver lists for DPAA bus */
  41 TAILQ_HEAD(rte_dpaa_device_list, rte_dpaa_device);
  42 TAILQ_HEAD(rte_dpaa_driver_list, rte_dpaa_driver);
  43
  44 /* Configuration variables exported from DPAA bus */
  45 extern struct netcfg_info *dpaa_netcfg;
  46
  47 enum rte_dpaa_type {
  48         FSL_DPAA_ETH = 1,
  49         FSL_DPAA_CRYPTO,
  50 };
  51
  52 struct rte_dpaa_bus {
  53         struct rte_bus bus;
  54         struct rte_dpaa_device_list device_list;
  55         struct rte_dpaa_driver_list driver_list;
  56         int device_count;
  57         int detected;
  58 };
  59
  60 struct dpaa_device_id {
  61         uint8_t fman_id; /**< Fman interface ID, for ETH type device */
  62         uint8_t mac_id; /**< Fman MAC interface ID, for ETH type device */
  63         uint16_t dev_id; /**< Device Identifier from DPDK */
  64 };
  65
  66 struct rte_dpaa_device {
  67         TAILQ_ENTRY(rte_dpaa_device) next;
  68         struct rte_device device;
  69         union {
  70                 struct rte_eth_dev *eth_dev;
  71                 struct rte_cryptodev *crypto_dev;
  72         };
  73         struct rte_dpaa_driver *driver;
  74         struct dpaa_device_id id;
  75         enum rte_dpaa_type device_type; /**< Ethernet or crypto type device */
  76         char name[RTE_ETH_NAME_MAX_LEN];
  77 };
  78
  79 typedef int (*rte_dpaa_probe_t)(struct rte_dpaa_driver *dpaa_drv,
  80                                 struct rte_dpaa_device *dpaa_dev);
  81 typedef int (*rte_dpaa_remove_t)(struct rte_dpaa_device *dpaa_dev);
  82
  83 struct rte_dpaa_driver {
  84         TAILQ_ENTRY(rte_dpaa_driver) next;
  85         struct rte_driver driver;
  86         struct rte_dpaa_bus *dpaa_bus;
  87         enum rte_dpaa_type drv_type;
  88         rte_dpaa_probe_t probe;
  89         rte_dpaa_remove_t remove;
  90 };
  91
  92 struct dpaa_portal {
  93         uint32_t bman_idx; /**< BMAN Portal ID*/
  94         uint32_t qman_idx; /**< QMAN Portal ID*/
  95         uint64_t tid;/**< Parent Thread id for this portal */
  96 };
  97
  98 /* Various structures representing contiguous memory maps */
  99 struct dpaa_memseg {
 100         TAILQ_ENTRY(dpaa_memseg) next;
 101         char *vaddr;
 102         rte_iova_t iova;
 103         size_t len;
 104 };
 105
 106 TAILQ_HEAD(dpaa_memseg_list, dpaa_memseg);
 107 extern struct dpaa_memseg_list rte_dpaa_memsegs;
 108
 109 /* Either iterate over the list of internal memseg references or fallback to
 110  * EAL memseg based iova2virt.
 111  */
 112 static inline void *rte_dpaa_mem_ptov(phys_addr_t paddr)
 113 {
 114         struct dpaa_memseg *ms;
 115         void *va;
 116
 117         va = dpaax_iova_table_get_va(paddr);
 118         if (likely(va != NULL))
 119                 return va;
 120
 121         /* Check if the address is already part of the memseg list internally
 122          * maintained by the dpaa driver.
 123          */
 124         TAILQ_FOREACH(ms, &rte_dpaa_memsegs, next) {
 125                 if (paddr >= ms->iova && paddr <
 126                         ms->iova + ms->len)
 127                         return RTE_PTR_ADD(ms->vaddr, (uintptr_t)(paddr - ms->iova));
 128         }
 129
 130         /* If not, Fallback to full memseg list searching */
 131         return rte_mem_iova2virt(paddr);
 132 }
 133
 134 /**
 135  * Register a DPAA driver.
 136  *
 137  * @param driver
 138  *   A pointer to a rte_dpaa_driver structure describing the driver
 139  *   to be registered.
 140  */
 141 void rte_dpaa_driver_register(struct rte_dpaa_driver *driver);
 142
 143 /**
 144  * Unregister a DPAA driver.
 145  *
 146  * @param driver
 147  *      A pointer to a rte_dpaa_driver structure describing the driver
 148  *      to be unregistered.
 149  */
 150 void rte_dpaa_driver_unregister(struct rte_dpaa_driver *driver);
 151
 152 /**
 153  * Initialize a DPAA portal
 154  *
 155  * @param arg
 156  *      Per thread ID
 157  *
 158  * @return
 159  *      0 in case of success, error otherwise
 160  */
 161 int rte_dpaa_portal_init(void *arg);
 162
 163 int rte_dpaa_portal_fq_init(void *arg, struct qman_fq *fq);
 164
 165 int rte_dpaa_portal_fq_close(struct qman_fq *fq);
 166
 167 /**
 168  * Cleanup a DPAA Portal
 169  */
 170 void dpaa_portal_finish(void *arg);
 171
 172 /** Helper for DPAA device registration from driver (eth, crypto) instance */
 173 #define RTE_PMD_REGISTER_DPAA(nm, dpaa_drv) \
 174 RTE_INIT(dpaainitfn_ ##nm) \
 175 {\
 176         (dpaa_drv).driver.name = RTE_STR(nm);\
 177         rte_dpaa_driver_register(&dpaa_drv); \
 178 } \
 179 RTE_PMD_EXPORT_NAME(nm, __COUNTER__)
 180
 181 /* Create storage for dqrr entries per lcore */
 182 #define DPAA_PORTAL_DEQUEUE_DEPTH       16
 183 struct dpaa_portal_dqrr {
 184         void *mbuf[DPAA_PORTAL_DEQUEUE_DEPTH];
 185         uint64_t dqrr_held;
 186         uint8_t dqrr_size;
 187 };
 188
 189 RTE_DECLARE_PER_LCORE(struct dpaa_portal_dqrr, held_bufs);
 190
 191 #define DPAA_PER_LCORE_DQRR_SIZE       RTE_PER_LCORE(held_bufs).dqrr_size
 192 #define DPAA_PER_LCORE_DQRR_HELD       RTE_PER_LCORE(held_bufs).dqrr_held
 193 #define DPAA_PER_LCORE_DQRR_MBUF(i)    RTE_PER_LCORE(held_bufs).mbuf[i]
 194
 195 #ifdef __cplusplus
 196 }
 197 #endif
 198
 199 #endif /* __RTE_DPAA_BUS_H__ */