ceph/src/seastar/dpdk/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h

   1 /*
   2  *  This file is provided under a dual BSD/GPLv2 license.  When using or
   3  *  redistributing this file, you may do so under either license.
   4  *
   5  *  GPL LICENSE SUMMARY
   6  *  Copyright(c) 2015 Intel Corporation.
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of version 2 of the GNU General Public License as
   9  *  published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope that it will be useful, but
  12  *  WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  *  General Public License for more details.
  15  *
  16  *  Contact Information:
  17  *  qat-linux@intel.com
  18  *
  19  *  BSD LICENSE
  20  *  Copyright(c) 2015 Intel Corporation.
  21  *  Redistribution and use in source and binary forms, with or without
  22  *  modification, are permitted provided that the following conditions
  23  *  are met:
  24  *
  25  *    * Redistributions of source code must retain the above copyright
  26  *      notice, this list of conditions and the following disclaimer.
  27  *    * Redistributions in binary form must reproduce the above copyright
  28  *      notice, this list of conditions and the following disclaimer in
  29  *      the documentation and/or other materials provided with the
  30  *      distribution.
  31  *    * Neither the name of Intel Corporation nor the names of its
  32  *      contributors may be used to endorse or promote products derived
  33  *      from this software without specific prior written permission.
  34  *
  35  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  36  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  37  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  38  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  39  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  40  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  41  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  42  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  43  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  44  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  45  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  46  */
  47 #ifndef ADF_TRANSPORT_ACCESS_MACROS_H
  48 #define ADF_TRANSPORT_ACCESS_MACROS_H
  49
  50 #include <rte_io.h>
  51
  52 /* CSR write macro */
  53 #define ADF_CSR_WR(csrAddr, csrOffset, val)             \
  54         rte_write32(val, (((uint8_t *)csrAddr) + csrOffset))
  55
  56 /* CSR read macro */
  57 #define ADF_CSR_RD(csrAddr, csrOffset)                  \
  58         rte_read32((((uint8_t *)csrAddr) + csrOffset))
  59
  60 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
  61 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
  62 #define ADF_RING_CSR_RING_CONFIG 0x000
  63 #define ADF_RING_CSR_RING_LBASE 0x040
  64 #define ADF_RING_CSR_RING_UBASE 0x080
  65 #define ADF_RING_CSR_RING_HEAD 0x0C0
  66 #define ADF_RING_CSR_RING_TAIL 0x100
  67 #define ADF_RING_CSR_E_STAT 0x14C
  68 #define ADF_RING_CSR_INT_SRCSEL 0x174
  69 #define ADF_RING_CSR_INT_SRCSEL_2 0x178
  70 #define ADF_RING_CSR_INT_COL_EN 0x17C
  71 #define ADF_RING_CSR_INT_COL_CTL 0x180
  72 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
  73 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
  74 #define ADF_RING_BUNDLE_SIZE 0x1000
  75 #define ADF_RING_CONFIG_NEAR_FULL_WM 0x0A
  76 #define ADF_RING_CONFIG_NEAR_EMPTY_WM 0x05
  77 #define ADF_COALESCING_MIN_TIME 0x1FF
  78 #define ADF_COALESCING_MAX_TIME 0xFFFFF
  79 #define ADF_COALESCING_DEF_TIME 0x27FF
  80 #define ADF_RING_NEAR_WATERMARK_512 0x08
  81 #define ADF_RING_NEAR_WATERMARK_0 0x00
  82 #define ADF_RING_EMPTY_SIG 0x7F7F7F7F
  83
  84 /* Valid internal ring size values */
  85 #define ADF_RING_SIZE_128 0x01
  86 #define ADF_RING_SIZE_256 0x02
  87 #define ADF_RING_SIZE_512 0x03
  88 #define ADF_RING_SIZE_4K 0x06
  89 #define ADF_RING_SIZE_16K 0x08
  90 #define ADF_RING_SIZE_4M 0x10
  91 #define ADF_MIN_RING_SIZE ADF_RING_SIZE_128
  92 #define ADF_MAX_RING_SIZE ADF_RING_SIZE_4M
  93 #define ADF_DEFAULT_RING_SIZE ADF_RING_SIZE_16K
  94
  95 #define ADF_NUM_BUNDLES_PER_DEV         1
  96 #define ADF_NUM_SYM_QPS_PER_BUNDLE      2
  97
  98 /* Valid internal msg size values */
  99 #define ADF_MSG_SIZE_32 0x01
 100 #define ADF_MSG_SIZE_64 0x02
 101 #define ADF_MSG_SIZE_128 0x04
 102 #define ADF_MIN_MSG_SIZE ADF_MSG_SIZE_32
 103 #define ADF_MAX_MSG_SIZE ADF_MSG_SIZE_128
 104
 105 /* Size to bytes conversion macros for ring and msg size values */
 106 #define ADF_MSG_SIZE_TO_BYTES(SIZE) (SIZE << 5)
 107 #define ADF_BYTES_TO_MSG_SIZE(SIZE) (SIZE >> 5)
 108 #define ADF_SIZE_TO_RING_SIZE_IN_BYTES(SIZE) ((1 << (SIZE - 1)) << 7)
 109 #define ADF_RING_SIZE_IN_BYTES_TO_SIZE(SIZE) ((1 << (SIZE - 1)) >> 7)
 110
 111 /* Minimum ring bufer size for memory allocation */
 112 #define ADF_RING_SIZE_BYTES_MIN(SIZE) ((SIZE < ADF_RING_SIZE_4K) ? \
 113                                 ADF_RING_SIZE_4K : SIZE)
 114 #define ADF_RING_SIZE_MODULO(SIZE) (SIZE + 0x6)
 115 #define ADF_SIZE_TO_POW(SIZE) ((((SIZE & 0x4) >> 1) | ((SIZE & 0x4) >> 2) | \
 116                                 SIZE) & ~0x4)
 117 /* Max outstanding requests */
 118 #define ADF_MAX_INFLIGHTS(RING_SIZE, MSG_SIZE) \
 119         ((((1 << (RING_SIZE - 1)) << 3) >> ADF_SIZE_TO_POW(MSG_SIZE)) - 1)
 120 #define BUILD_RING_CONFIG(size) \
 121         ((ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_FULL_WM) \
 122         | (ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_EMPTY_WM) \
 123         | size)
 124 #define BUILD_RESP_RING_CONFIG(size, watermark_nf, watermark_ne) \
 125         ((watermark_nf << ADF_RING_CONFIG_NEAR_FULL_WM) \
 126         | (watermark_ne << ADF_RING_CONFIG_NEAR_EMPTY_WM) \
 127         | size)
 128 #define BUILD_RING_BASE_ADDR(addr, size) \
 129         ((addr >> 6) & (0xFFFFFFFFFFFFFFFFULL << size))
 130 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
 131         ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 132                         ADF_RING_CSR_RING_HEAD + (ring << 2))
 133 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
 134         ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 135                         ADF_RING_CSR_RING_TAIL + (ring << 2))
 136 #define READ_CSR_E_STAT(csr_base_addr, bank) \
 137         ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 138                         ADF_RING_CSR_E_STAT)
 139 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
 140         ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 141                 ADF_RING_CSR_RING_CONFIG + (ring << 2), value)
 142 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
 143 do { \
 144         uint32_t l_base = 0, u_base = 0; \
 145         l_base = (uint32_t)(value & 0xFFFFFFFF); \
 146         u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \
 147         ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 148                 ADF_RING_CSR_RING_LBASE + (ring << 2), l_base); \
 149         ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 150                 ADF_RING_CSR_RING_UBASE + (ring << 2), u_base); \
 151 } while (0)
 152 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
 153         ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 154                 ADF_RING_CSR_RING_HEAD + (ring << 2), value)
 155 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
 156         ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 157                 ADF_RING_CSR_RING_TAIL + (ring << 2), value)
 158 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
 159 do { \
 160         ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 161         ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0);  \
 162         ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 163         ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \
 164 } while (0)
 165 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
 166         ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 167                         ADF_RING_CSR_INT_COL_EN, value)
 168 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
 169         ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 170                         ADF_RING_CSR_INT_COL_CTL, \
 171                         ADF_RING_CSR_INT_COL_CTL_ENABLE | value)
 172 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
 173         ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 174                         ADF_RING_CSR_INT_FLAG_AND_COL, value)
 175 #endif