ceph/src/seastar/dpdk/drivers/net/ark/ark_mpu.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2018 Atomic Rules LLC
   3  */
   4
   5 #include <unistd.h>
   6
   7 #include "ark_logs.h"
   8 #include "ark_mpu.h"
   9
  10 uint16_t
  11 ark_api_num_queues(struct ark_mpu_t *mpu)
  12 {
  13         return mpu->hw.num_queues;
  14 }
  15
  16 uint16_t
  17 ark_api_num_queues_per_port(struct ark_mpu_t *mpu, uint16_t ark_ports)
  18 {
  19         return mpu->hw.num_queues / ark_ports;
  20 }
  21
  22 int
  23 ark_mpu_verify(struct ark_mpu_t *mpu, uint32_t obj_size)
  24 {
  25         uint32_t version;
  26
  27         version = mpu->id.vernum & 0x0000fF00;
  28         if ((mpu->id.idnum != 0x2055504d) ||
  29             (mpu->hw.obj_size != obj_size) ||
  30             (version != 0x00003100)) {
  31                 PMD_DRV_LOG(ERR,
  32                             "   MPU module not found as expected %08x"
  33                             " \"%c%c%c%c %c%c%c%c\"\n",
  34                             mpu->id.idnum,
  35                             mpu->id.id[0], mpu->id.id[1],
  36                             mpu->id.id[2], mpu->id.id[3],
  37                             mpu->id.ver[0], mpu->id.ver[1],
  38                             mpu->id.ver[2], mpu->id.ver[3]);
  39                 PMD_DRV_LOG(ERR,
  40                             "   MPU HW num_queues: %u hw_depth %u,"
  41                             " obj_size: %u, obj_per_mrr: %u"
  42                             " Expected size %u\n",
  43                             mpu->hw.num_queues,
  44                             mpu->hw.hw_depth,
  45                             mpu->hw.obj_size,
  46                             mpu->hw.obj_per_mrr,
  47                             obj_size);
  48                 return -1;
  49         }
  50         return 0;
  51 }
  52
  53 void
  54 ark_mpu_stop(struct ark_mpu_t *mpu)
  55 {
  56         mpu->cfg.command = MPU_CMD_STOP;
  57 }
  58
  59 void
  60 ark_mpu_start(struct ark_mpu_t *mpu)
  61 {
  62         mpu->cfg.command = MPU_CMD_RUN;
  63 }
  64
  65 int
  66 ark_mpu_reset(struct ark_mpu_t *mpu)
  67 {
  68         int cnt = 0;
  69
  70         mpu->cfg.command = MPU_CMD_RESET;
  71
  72         while (mpu->cfg.command != MPU_CMD_IDLE) {
  73                 if (cnt++ > 1000)
  74                         break;
  75                 usleep(10);
  76         }
  77         if (mpu->cfg.command != MPU_CMD_IDLE) {
  78                 mpu->cfg.command = MPU_CMD_FORCE_RESET;
  79                 usleep(10);
  80         }
  81         ark_mpu_reset_stats(mpu);
  82         return mpu->cfg.command != MPU_CMD_IDLE;
  83 }
  84
  85 void
  86 ark_mpu_reset_stats(struct ark_mpu_t *mpu)
  87 {
  88         mpu->stats.pci_request = 1;     /* reset stats */
  89 }
  90
  91 int
  92 ark_mpu_configure(struct ark_mpu_t *mpu, rte_iova_t ring, uint32_t ring_size,
  93                   int is_tx)
  94 {
  95         ark_mpu_reset(mpu);
  96
  97         if (!rte_is_power_of_2(ring_size)) {
  98                 PMD_DRV_LOG(ERR, "ARK: Invalid ring size for MPU %d\n",
  99                             ring_size);
 100                 return -1;
 101         }
 102
 103         mpu->cfg.ring_base = ring;
 104         mpu->cfg.ring_size = ring_size;
 105         mpu->cfg.ring_mask = ring_size - 1;
 106         mpu->cfg.min_host_move = is_tx ? 1 : mpu->hw.obj_per_mrr;
 107         mpu->cfg.min_hw_move = mpu->hw.obj_per_mrr;
 108         mpu->cfg.sw_prod_index = 0;
 109         mpu->cfg.hw_cons_index = 0;
 110         return 0;
 111 }
 112
 113 void
 114 ark_mpu_dump(struct ark_mpu_t *mpu, const char *code, uint16_t qid)
 115 {
 116         /* DUMP to see that we have started */
 117         PMD_DEBUG_LOG(DEBUG, "MPU: %s Q: %3u sw_prod %u, hw_cons: %u\n",
 118                       code, qid,
 119                       mpu->cfg.sw_prod_index, mpu->cfg.hw_cons_index);
 120         PMD_DEBUG_LOG(DEBUG, "MPU: %s state: %d count %d, reserved %d"
 121                       " data 0x%08x_%08x 0x%08x_%08x\n",
 122                       code,
 123                       mpu->debug.state, mpu->debug.count,
 124                       mpu->debug.reserved,
 125                       mpu->debug.peek[1],
 126                       mpu->debug.peek[0],
 127                       mpu->debug.peek[3],
 128                       mpu->debug.peek[2]
 129                       );
 130         PMD_STATS_LOG(INFO, "MPU: %s Q: %3u"
 131                       ARK_SU64 ARK_SU64 ARK_SU64 ARK_SU64
 132                       ARK_SU64 ARK_SU64 ARK_SU64 "\n",
 133                       code, qid,
 134                       "PCI Request:", mpu->stats.pci_request,
 135                       "Queue_empty", mpu->stats.q_empty,
 136                       "Queue_q1", mpu->stats.q_q1,
 137                       "Queue_q2", mpu->stats.q_q2,
 138                       "Queue_q3", mpu->stats.q_q3,
 139                       "Queue_q4", mpu->stats.q_q4,
 140                       "Queue_full", mpu->stats.q_full
 141                       );
 142 }
 143
 144 void
 145 ark_mpu_dump_setup(struct ark_mpu_t *mpu, uint16_t q_id)
 146 {
 147         PMD_DEBUG_LOG(DEBUG, "MPU Setup Q: %u"
 148                       ARK_SU64X "\n",
 149                       q_id,
 150                       "ring_base", mpu->cfg.ring_base
 151                       );
 152 }