ceph/src/seastar/dpdk/drivers/net/ark/ark_udm.h

   1 /*-
   2  * BSD LICENSE
   3  *
   4  * Copyright (c) 2015-2017 Atomic Rules LLC
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * * Redistributions of source code must retain the above copyright
  12  * notice, this list of conditions and the following disclaimer.
  13  * * Redistributions in binary form must reproduce the above copyright
  14  * notice, this list of conditions and the following disclaimer in
  15  * the documentation and/or other materials provided with the
  16  * distribution.
  17  * * Neither the name of copyright holder nor the names of its
  18  * contributors may be used to endorse or promote products derived
  19  * from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #ifndef _ARK_UDM_H_
  35 #define _ARK_UDM_H_
  36
  37 #include <stdint.h>
  38
  39 #include <rte_memory.h>
  40
  41 /* The UDM or Upstream Data Mover is an internal Arkville hardware
  42  * module for moving packet from the RX packet streams to host memory.
  43  * This module is *not* intended for end-user manipulation, hence
  44  * there is minimal documentation.
  45  */
  46
  47 /* Meta data structure apssed from FPGA, must match layout in FPGA */
  48 struct ark_rx_meta {
  49         uint64_t timestamp;
  50         uint64_t user_data;
  51         uint8_t port;
  52         uint8_t dst_queue;
  53         uint16_t pkt_len;
  54 };
  55
  56 /*
  57  * UDM hardware structures
  58  * These are overlay structures to a memory mapped FPGA device.  These
  59  * structs will never be instantiated in ram memory
  60  */
  61
  62 #define ARK_RX_WRITE_TIME_NS 2500
  63 #define ARK_UDM_SETUP 0
  64 #define ARK_UDM_CONST 0xbACECACE
  65 struct ark_udm_setup_t {
  66         uint32_t r0;
  67         uint32_t r4;
  68         volatile uint32_t cycle_count;
  69         uint32_t const0;
  70 };
  71
  72 #define ARK_UDM_CFG 0x010
  73 struct ark_udm_cfg_t {
  74         volatile uint32_t stop_flushed; /* RO */
  75         volatile uint32_t command;
  76         uint32_t dataroom;
  77         uint32_t headroom;
  78 };
  79
  80 typedef enum {
  81         ARK_UDM_START = 0x1,
  82         ARK_UDM_STOP = 0x2,
  83         ARK_UDM_RESET = 0x3
  84 } ark_udm_commands;
  85
  86 #define ARK_UDM_STATS 0x020
  87 struct ark_udm_stats_t {
  88         volatile uint64_t rx_byte_count;
  89         volatile uint64_t rx_packet_count;
  90         volatile uint64_t rx_mbuf_count;
  91         volatile uint64_t rx_sent_packets;
  92 };
  93
  94 #define ARK_UDM_PQ 0x040
  95 struct ark_udm_queue_stats_t {
  96         volatile uint64_t q_byte_count;
  97         volatile uint64_t q_packet_count;       /* includes drops */
  98         volatile uint64_t q_mbuf_count;
  99         volatile uint64_t q_ff_packet_count;
 100         volatile uint64_t q_pkt_drop;
 101         uint32_t q_enable;
 102 };
 103
 104 #define ARK_UDM_TLP 0x0070
 105 struct ark_udm_tlp_t {
 106         volatile uint64_t pkt_drop;     /* global */
 107         volatile uint32_t tlp_q1;
 108         volatile uint32_t tlp_q2;
 109         volatile uint32_t tlp_q3;
 110         volatile uint32_t tlp_q4;
 111         volatile uint32_t tlp_full;
 112 };
 113
 114 #define ARK_UDM_PCIBP 0x00a0
 115 struct ark_udm_pcibp_t {
 116         volatile uint32_t pci_clear;
 117         volatile uint32_t pci_empty;
 118         volatile uint32_t pci_q1;
 119         volatile uint32_t pci_q2;
 120         volatile uint32_t pci_q3;
 121         volatile uint32_t pci_q4;
 122         volatile uint32_t pci_full;
 123 };
 124
 125 #define ARK_UDM_TLP_PS 0x00bc
 126 struct ark_udm_tlp_ps_t {
 127         volatile uint32_t tlp_clear;
 128         volatile uint32_t tlp_ps_min;
 129         volatile uint32_t tlp_ps_max;
 130         volatile uint32_t tlp_full_ps_min;
 131         volatile uint32_t tlp_full_ps_max;
 132         volatile uint32_t tlp_dw_ps_min;
 133         volatile uint32_t tlp_dw_ps_max;
 134         volatile uint32_t tlp_pldw_ps_min;
 135         volatile uint32_t tlp_pldw_ps_max;
 136 };
 137
 138 #define ARK_UDM_RT_CFG 0x00e0
 139 struct ark_udm_rt_cfg_t {
 140         phys_addr_t hw_prod_addr;
 141         uint32_t write_interval;        /* 4ns cycles */
 142         volatile uint32_t prod_idx;     /* RO */
 143 };
 144
 145 /*  Consolidated structure */
 146 #define ARK_UDM_EXPECT_SIZE (0x00fc + 4)
 147 #define ARK_UDM_QOFFSET ARK_UDM_EXPECT_SIZE
 148 struct ark_udm_t {
 149         struct ark_udm_setup_t setup;
 150         struct ark_udm_cfg_t cfg;
 151         struct ark_udm_stats_t stats;
 152         struct ark_udm_queue_stats_t qstats;
 153         uint8_t reserved1[(ARK_UDM_TLP - ARK_UDM_PQ) -
 154                           sizeof(struct ark_udm_queue_stats_t)];
 155         struct ark_udm_tlp_t tlp;
 156         uint8_t reserved2[(ARK_UDM_PCIBP - ARK_UDM_TLP) -
 157                           sizeof(struct ark_udm_tlp_t)];
 158         struct ark_udm_pcibp_t pcibp;
 159         struct ark_udm_tlp_ps_t tlp_ps;
 160         struct ark_udm_rt_cfg_t rt_cfg;
 161         int8_t reserved3[(ARK_UDM_EXPECT_SIZE - ARK_UDM_RT_CFG) -
 162                          sizeof(struct ark_udm_rt_cfg_t)];
 163 };
 164
 165
 166 int ark_udm_verify(struct ark_udm_t *udm);
 167 int ark_udm_stop(struct ark_udm_t *udm, int wait);
 168 void ark_udm_start(struct ark_udm_t *udm);
 169 int ark_udm_reset(struct ark_udm_t *udm);
 170 void ark_udm_configure(struct ark_udm_t *udm,
 171                        uint32_t headroom,
 172                        uint32_t dataroom,
 173                        uint32_t write_interval_ns);
 174 void ark_udm_write_addr(struct ark_udm_t *udm, phys_addr_t addr);
 175 void ark_udm_stats_reset(struct ark_udm_t *udm);
 176 void ark_udm_dump_stats(struct ark_udm_t *udm, const char *msg);
 177 void ark_udm_dump_queue_stats(struct ark_udm_t *udm, const char *msg,
 178                               uint16_t qid);
 179 void ark_udm_dump(struct ark_udm_t *udm, const char *msg);
 180 void ark_udm_dump_perf(struct ark_udm_t *udm, const char *msg);
 181 void ark_udm_dump_setup(struct ark_udm_t *udm, uint16_t q_id);
 182 int ark_udm_is_flushed(struct ark_udm_t *udm);
 183
 184 /* Per queue data */
 185 uint64_t ark_udm_dropped(struct ark_udm_t *udm);
 186 uint64_t ark_udm_bytes(struct ark_udm_t *udm);
 187 uint64_t ark_udm_packets(struct ark_udm_t *udm);
 188
 189 void ark_udm_queue_stats_reset(struct ark_udm_t *udm);
 190 void ark_udm_queue_enable(struct ark_udm_t *udm, int enable);
 191
 192 #endif