ceph/src/seastar/dpdk/drivers/net/axgbe/axgbe_phy.h

   1 /*   SPDX-License-Identifier: BSD-3-Clause
   2  *   Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
   3  *   Copyright(c) 2018 Synopsys, Inc. All rights reserved.
   4  */
   5
   6 #ifndef __AXGBE_PHY_H__
   7 #define __AXGBE_PHY_H__
   8
   9 #define SPEED_10    10
  10 #define SPEED_100   100
  11 #define SPEED_1000  1000
  12 #define SPEED_2500  2500
  13 #define SPEED_10000 10000
  14
  15
  16 /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
  17  * IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips.
  18  */
  19 #define MII_ADDR_C45 (1 << 30)
  20
  21 /* Basic mode status register. */
  22 #define BMSR_LSTATUS            0x0004  /* Link status */
  23
  24 /* Status register 1. */
  25 #define MDIO_STAT1_LSTATUS              BMSR_LSTATUS
  26
  27 /* Generic MII registers. */
  28 #define MII_BMCR                0x00    /* Basic mode control register */
  29 #define MII_BMSR                0x01    /* Basic mode status register  */
  30 #define MII_PHYSID1             0x02    /* PHYS ID 1                   */
  31 #define MII_PHYSID2             0x03    /* PHYS ID 2                   */
  32 #define MII_ADVERTISE           0x04    /* Advertisement control reg   */
  33 #define MII_LPA                 0x05    /* Link partner ability reg    */
  34 #define MII_EXPANSION           0x06    /* Expansion register          */
  35 #define MII_CTRL1000            0x09    /* 1000BASE-T control          */
  36 #define MII_STAT1000            0x0a    /* 1000BASE-T status           */
  37 #define MII_MMD_CTRL            0x0d    /* MMD Access Control Register */
  38 #define MII_MMD_DATA            0x0e    /* MMD Access Data Register */
  39 #define MII_ESTATUS             0x0f    /* Extended Status             */
  40 #define MII_DCOUNTER            0x12    /* Disconnect counter          */
  41 #define MII_FCSCOUNTER          0x13    /* False carrier counter       */
  42 #define MII_NWAYTEST            0x14    /* N-way auto-neg test reg     */
  43 #define MII_RERRCOUNTER         0x15    /* Receive error counter       */
  44 #define MII_SREVISION           0x16    /* Silicon revision            */
  45 #define MII_RESV1               0x17    /* Reserved...                 */
  46 #define MII_LBRERROR            0x18    /* Lpback, rx, bypass error    */
  47 #define MII_PHYADDR             0x19    /* PHY address                 */
  48 #define MII_RESV2               0x1a    /* Reserved...                 */
  49 #define MII_TPISTATUS           0x1b    /* TPI status for 10mbps       */
  50 #define MII_NCONFIG             0x1c    /* Network interface config    */
  51
  52 /* Basic mode control register. */
  53 #define BMCR_RESV               0x003f  /* Unused...                   */
  54 #define BMCR_SPEED1000          0x0040  /* MSB of Speed (1000)         */
  55 #define BMCR_CTST               0x0080  /* Collision test              */
  56 #define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
  57 #define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
  58 #define BMCR_ISOLATE            0x0400  /* Isolate data paths from MII */
  59 #define BMCR_PDOWN              0x0800  /* Enable low power state      */
  60 #define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
  61 #define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
  62 #define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
  63 #define BMCR_RESET              0x8000  /* Reset to default state      */
  64 #define BMCR_SPEED10            0x0000  /* Select 10Mbps               */
  65
  66
  67 /* MDIO Manageable Devices (MMDs). */
  68 #define MDIO_MMD_PMAPMD         1       /* Physical Medium Attachment
  69                                          * Physical Medium Dependent
  70                                          */
  71 #define MDIO_MMD_WIS            2       /* WAN Interface Sublayer */
  72 #define MDIO_MMD_PCS            3       /* Physical Coding Sublayer */
  73 #define MDIO_MMD_PHYXS          4       /* PHY Extender Sublayer */
  74 #define MDIO_MMD_DTEXS          5       /* DTE Extender Sublayer */
  75 #define MDIO_MMD_TC             6       /* Transmission Convergence */
  76 #define MDIO_MMD_AN             7       /* Auto-Negotiation */
  77 #define MDIO_MMD_C22EXT         29      /* Clause 22 extension */
  78 #define MDIO_MMD_VEND1          30      /* Vendor specific 1 */
  79 #define MDIO_MMD_VEND2          31      /* Vendor specific 2 */
  80
  81 /* Generic MDIO registers. */
  82 #define MDIO_CTRL1              MII_BMCR
  83 #define MDIO_STAT1              MII_BMSR
  84 #define MDIO_DEVID1             MII_PHYSID1
  85 #define MDIO_DEVID2             MII_PHYSID2
  86 #define MDIO_SPEED              4       /* Speed ability */
  87 #define MDIO_DEVS1              5       /* Devices in package */
  88 #define MDIO_DEVS2              6
  89 #define MDIO_CTRL2              7       /* 10G control 2 */
  90 #define MDIO_STAT2              8       /* 10G status 2 */
  91 #define MDIO_PMA_TXDIS          9       /* 10G PMA/PMD transmit disable */
  92 #define MDIO_PMA_RXDET          10      /* 10G PMA/PMD receive signal detect */
  93 #define MDIO_PMA_EXTABLE        11      /* 10G PMA/PMD extended ability */
  94 #define MDIO_PKGID1             14      /* Package identifier */
  95 #define MDIO_PKGID2             15
  96 #define MDIO_AN_ADVERTISE       16      /* AN advertising (base page) */
  97 #define MDIO_AN_LPA             19      /* AN LP abilities (base page) */
  98 #define MDIO_PCS_EEE_ABLE       20      /* EEE Capability register */
  99 #define MDIO_PCS_EEE_WK_ERR     22      /* EEE wake error counter */
 100 #define MDIO_PHYXS_LNSTAT       24      /* PHY XGXS lane state */
 101 #define MDIO_AN_EEE_ADV         60      /* EEE advertisement */
 102 #define MDIO_AN_EEE_LPABLE      61      /* EEE link partner ability */
 103
 104 /* Media-dependent registers. */
 105 #define MDIO_PMA_10GBT_SWAPPOL  130     /* 10GBASE-T pair swap & polarity */
 106 #define MDIO_PMA_10GBT_TXPWR    131     /* 10GBASE-T TX power control */
 107 #define MDIO_PMA_10GBT_SNR      133     /* 10GBASE-T SNR margin, lane A.
 108                                          * Lanes B-D are numbered 134-136.
 109                                          */
 110 #define MDIO_PMA_10GBR_FECABLE  170     /* 10GBASE-R FEC ability */
 111 #define MDIO_PCS_10GBX_STAT1    24      /* 10GBASE-X PCS status 1 */
 112 #define MDIO_PCS_10GBRT_STAT1   32      /* 10GBASE-R/-T PCS status 1 */
 113 #define MDIO_PCS_10GBRT_STAT2   33      /* 10GBASE-R/-T PCS status 2 */
 114 #define MDIO_AN_10GBT_CTRL      32      /* 10GBASE-T auto-negotiation control */
 115 #define MDIO_AN_10GBT_STAT      33      /* 10GBASE-T auto-negotiation status */
 116
 117 /* Control register 1. */
 118 /* Enable extended speed selection */
 119 #define MDIO_CTRL1_SPEEDSELEXT          (BMCR_SPEED1000 | BMCR_SPEED100)
 120 /* All speed selection bits */
 121 #define MDIO_CTRL1_SPEEDSEL             (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
 122 #define MDIO_CTRL1_FULLDPLX             BMCR_FULLDPLX
 123 #define MDIO_CTRL1_LPOWER               BMCR_PDOWN
 124 #define MDIO_CTRL1_RESET                BMCR_RESET
 125 #define MDIO_PMA_CTRL1_LOOPBACK         0x0001
 126 #define MDIO_PMA_CTRL1_SPEED1000        BMCR_SPEED1000
 127 #define MDIO_PMA_CTRL1_SPEED100         BMCR_SPEED100
 128 #define MDIO_PCS_CTRL1_LOOPBACK         BMCR_LOOPBACK
 129 #define MDIO_PHYXS_CTRL1_LOOPBACK       BMCR_LOOPBACK
 130 #define MDIO_AN_CTRL1_RESTART           BMCR_ANRESTART
 131 #define MDIO_AN_CTRL1_ENABLE            BMCR_ANENABLE
 132 #define MDIO_AN_CTRL1_XNP               0x2000  /* Enable extended next page */
 133 #define MDIO_PCS_CTRL1_CLKSTOP_EN       0x400   /* Stop the clock during LPI */
 134
 135
 136
 137
 138
 139 /* PMA 10GBASE-R FEC ability register. */
 140 #define MDIO_PMA_10GBR_FECABLE_ABLE     0x0001  /* FEC ability */
 141 #define MDIO_PMA_10GBR_FECABLE_ERRABLE  0x0002  /* FEC error indic. ability */
 142
 143
 144 /* Autoneg related */
 145 #define ADVERTISED_Autoneg              (1 << 6)
 146 #define SUPPORTED_Autoneg               (1 << 6)
 147 #define AUTONEG_DISABLE                 0x00
 148 #define AUTONEG_ENABLE                  0x01
 149
 150 #define ADVERTISED_Pause                (1 << 13)
 151 #define ADVERTISED_Asym_Pause           (1 << 14)
 152
 153 #define SUPPORTED_Pause                 (1 << 13)
 154 #define SUPPORTED_Asym_Pause            (1 << 14)
 155
 156 #define SUPPORTED_Backplane             (1 << 16)
 157 #define SUPPORTED_TP                    (1 << 7)
 158
 159 #define ADVERTISED_10000baseR_FEC       (1 << 20)
 160
 161 #define SUPPORTED_10000baseR_FEC        (1 << 20)
 162
 163 #define SUPPORTED_FIBRE                 (1 << 10)
 164
 165 #define ADVERTISED_10000baseKR_Full     (1 << 19)
 166 #define ADVERTISED_10000baseT_Full      (1 << 12)
 167 #define ADVERTISED_2500baseX_Full       (1 << 15)
 168 #define ADVERTISED_1000baseKX_Full      (1 << 17)
 169 #define ADVERTISED_1000baseT_Full       (1 << 5)
 170 #define ADVERTISED_100baseT_Full        (1 << 3)
 171 #define ADVERTISED_TP                   (1 << 7)
 172 #define ADVERTISED_FIBRE                (1 << 10)
 173 #define ADVERTISED_Backplane            (1 << 16)
 174
 175 #define SUPPORTED_1000baseKX_Full       (1 << 17)
 176 #define SUPPORTED_10000baseKR_Full      (1 << 19)
 177 #define SUPPORTED_2500baseX_Full        (1 << 15)
 178 #define SUPPORTED_100baseT_Full         (1 << 2)
 179 #define SUPPORTED_1000baseT_Full        (1 << 5)
 180 #define SUPPORTED_10000baseT_Full       (1 << 12)
 181 #define SUPPORTED_2500baseX_Full        (1 << 15)
 182
 183
 184 #define SPEED_UNKNOWN           -1
 185
 186 /* Duplex, half or full. */
 187 #define DUPLEX_HALF             0x00
 188 #define DUPLEX_FULL             0x01
 189 #define DUPLEX_UNKNOWN          0xff
 190
 191 #endif
 192 /* PHY */