1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
14 #ifndef ECORE_INIT_OPS_H
15 #define ECORE_INIT_OPS_H
17 static int ecore_gunzip(struct bnx2x_softc
*sc
, const uint8_t *zbuf
, int len
);
18 static void ecore_write_dmae_phys_len(struct bnx2x_softc
*sc
,
19 ecore_dma_addr_t phys_addr
, uint32_t addr
,
22 static void ecore_init_str_wr(struct bnx2x_softc
*sc
, uint32_t addr
,
23 const uint32_t *data
, uint32_t len
)
27 for (i
= 0; i
< len
; i
++)
28 REG_WR(sc
, addr
+ i
*4, data
[i
]);
31 static void ecore_write_big_buf(struct bnx2x_softc
*sc
, uint32_t addr
, uint32_t len
)
34 ecore_write_dmae_phys_len(sc
, GUNZIP_PHYS(sc
), addr
, len
);
36 else ecore_init_str_wr(sc
, addr
, GUNZIP_BUF(sc
), len
);
39 static void ecore_init_fill(struct bnx2x_softc
*sc
, uint32_t addr
, int fill
,
42 uint32_t buf_len
= (((len
*4) > FW_BUF_SIZE
) ? FW_BUF_SIZE
: (len
*4));
43 uint32_t buf_len32
= buf_len
/4;
46 ECORE_MEMSET(GUNZIP_BUF(sc
), (uint8_t)fill
, buf_len
);
48 for (i
= 0; i
< len
; i
+= buf_len32
) {
49 uint32_t cur_len
= min(buf_len32
, len
- i
);
51 ecore_write_big_buf(sc
, addr
+ i
*4, cur_len
);
55 static void ecore_write_big_buf_wb(struct bnx2x_softc
*sc
, uint32_t addr
, uint32_t len
)
58 ecore_write_dmae_phys_len(sc
, GUNZIP_PHYS(sc
), addr
, len
);
60 else ecore_init_str_wr(sc
, addr
, GUNZIP_BUF(sc
), len
);
63 static void ecore_init_wr_64(struct bnx2x_softc
*sc
, uint32_t addr
,
64 const uint32_t *data
, uint32_t len64
)
66 uint32_t buf_len32
= FW_BUF_SIZE
/4;
67 uint32_t len
= len64
*2;
71 /* 64 bit value is in a blob: first low DWORD, then high DWORD */
72 data64
= HILO_U64((*(data
+ 1)), (*data
));
74 len64
= min((uint32_t)(FW_BUF_SIZE
/8), len64
);
75 for (i
= 0; i
< len64
; i
++) {
76 uint64_t *pdata
= ((uint64_t *)(GUNZIP_BUF(sc
))) + i
;
81 for (i
= 0; i
< len
; i
+= buf_len32
) {
82 uint32_t cur_len
= min(buf_len32
, len
- i
);
84 ecore_write_big_buf_wb(sc
, addr
+ i
*4, cur_len
);
88 /*********************************************************
89 There are different blobs for each PRAM section.
90 In addition, each blob write operation is divided into a few operations
91 in order to decrease the amount of phys. contiguous buffer needed.
92 Thus, when we select a blob the address may be with some offset
93 from the beginning of PRAM section.
94 The same holds for the INT_TABLE sections.
95 **********************************************************/
96 #define IF_IS_INT_TABLE_ADDR(base, addr) \
97 if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
99 #define IF_IS_PRAM_ADDR(base, addr) \
100 if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
102 static const uint8_t *ecore_sel_blob(struct bnx2x_softc
*sc
, uint32_t addr
,
105 IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE
, addr
)
106 data
= INIT_TSEM_INT_TABLE_DATA(sc
);
108 IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE
, addr
)
109 data
= INIT_CSEM_INT_TABLE_DATA(sc
);
111 IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE
, addr
)
112 data
= INIT_USEM_INT_TABLE_DATA(sc
);
114 IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE
, addr
)
115 data
= INIT_XSEM_INT_TABLE_DATA(sc
);
117 IF_IS_PRAM_ADDR(TSEM_REG_PRAM
, addr
)
118 data
= INIT_TSEM_PRAM_DATA(sc
);
120 IF_IS_PRAM_ADDR(CSEM_REG_PRAM
, addr
)
121 data
= INIT_CSEM_PRAM_DATA(sc
);
123 IF_IS_PRAM_ADDR(USEM_REG_PRAM
, addr
)
124 data
= INIT_USEM_PRAM_DATA(sc
);
126 IF_IS_PRAM_ADDR(XSEM_REG_PRAM
, addr
)
127 data
= INIT_XSEM_PRAM_DATA(sc
);
132 static void ecore_init_wr_wb(struct bnx2x_softc
*sc
, uint32_t addr
,
133 const uint32_t *data
, uint32_t len
)
136 VIRT_WR_DMAE_LEN(sc
, data
, addr
, len
, 0);
138 else ecore_init_str_wr(sc
, addr
, data
, len
);
141 static void ecore_wr_64(struct bnx2x_softc
*sc
, uint32_t reg
, uint32_t val_lo
,
144 uint32_t wb_write
[2];
146 wb_write
[0] = val_lo
;
147 wb_write
[1] = val_hi
;
148 REG_WR_DMAE_LEN(sc
, reg
, wb_write
, 2);
151 static void ecore_init_wr_zp(struct bnx2x_softc
*sc
, uint32_t addr
, uint32_t len
,
154 const uint8_t *data
= NULL
;
158 data
= ecore_sel_blob(sc
, addr
, data
) + blob_off
*4;
160 rc
= ecore_gunzip(sc
, data
, len
);
164 /* gunzip_outlen is in dwords */
165 len
= GUNZIP_OUTLEN(sc
);
166 for (i
= 0; i
< len
; i
++)
167 ((uint32_t *)GUNZIP_BUF(sc
))[i
] = (uint32_t)
168 ECORE_CPU_TO_LE32(((uint32_t *)GUNZIP_BUF(sc
))[i
]);
170 ecore_write_big_buf_wb(sc
, addr
, len
);
173 static void ecore_init_block(struct bnx2x_softc
*sc
, uint32_t block
, uint32_t stage
)
176 INIT_OPS_OFFSETS(sc
)[BLOCK_OPS_IDX(block
, stage
,
179 INIT_OPS_OFFSETS(sc
)[BLOCK_OPS_IDX(block
, stage
,
181 const union init_op
*op
;
182 uint32_t op_idx
, op_type
, addr
, len
;
183 const uint32_t *data
, *data_base
;
186 if (op_start
== op_end
)
189 data_base
= INIT_DATA(sc
);
191 for (op_idx
= op_start
; op_idx
< op_end
; op_idx
++) {
193 op
= (const union init_op
*)&(INIT_OPS(sc
)[op_idx
]);
194 /* Get generic data */
195 op_type
= op
->raw
.op
;
196 addr
= op
->raw
.offset
;
197 /* Get data that's used for OP_SW, OP_WB, OP_FW, OP_ZP and
198 * OP_WR64 (we assume that op_arr_write and op_write have the
201 len
= op
->arr_wr
.data_len
;
202 data
= data_base
+ op
->arr_wr
.data_off
;
209 REG_WR(sc
, addr
, op
->write
.val
);
212 ecore_init_str_wr(sc
, addr
, data
, len
);
215 ecore_init_wr_wb(sc
, addr
, data
, len
);
219 ecore_init_fill(sc
, addr
, 0, op
->zero
.len
);
222 ecore_init_wr_zp(sc
, addr
, len
, op
->arr_wr
.data_off
);
225 ecore_init_wr_64(sc
, addr
, data
, len
);
228 /* if any of the flags doesn't match, skip the
231 if ((INIT_MODE_FLAGS(sc
) &
232 op
->if_mode
.mode_bit_map
) !=
233 op
->if_mode
.mode_bit_map
)
234 op_idx
+= op
->if_mode
.cmd_offset
;
237 /* if all the flags don't match, skip the conditional
240 if ((INIT_MODE_FLAGS(sc
) &
241 op
->if_mode
.mode_bit_map
) == 0)
242 op_idx
+= op
->if_mode
.cmd_offset
;
244 /* the following opcodes are unused at the moment. */
250 /* Should never get here! */
258 /****************************************************************************
260 ****************************************************************************/
262 * This code configures the PCI read/write arbiter
263 * which implements a weighted round robin
264 * between the virtual queues in the chip.
266 * The values were derived for each PCI max payload and max request size.
267 * since max payload and max request size are only known at run time,
268 * this is done as a separate init stage.
276 /* configuration for one arbiter queue */
283 /* derived configuration for each read queue for each max request size */
284 static const struct arb_line read_arb_data
[NUM_RD_Q
][MAX_RD_ORD
+ 1] = {
285 /* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
286 { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
287 { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
288 { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
289 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
290 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
291 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
292 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
293 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
294 /* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
295 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
296 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
297 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
298 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
299 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
300 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
301 { {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
302 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
303 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
304 /* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
305 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
306 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
307 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
308 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
309 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
310 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
311 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
312 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
313 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
316 /* derived configuration for each write queue for each max request size */
317 static const struct arb_line write_arb_data
[NUM_WR_Q
][MAX_WR_ORD
+ 1] = {
318 /* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
319 { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
320 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
321 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
322 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
323 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
324 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
325 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
326 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
327 /* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
328 { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
329 { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
330 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
333 /* register addresses for read queues */
334 static const struct arb_line read_arb_addr
[NUM_RD_Q
-1] = {
335 /* 1 */ {PXP2_REG_RQ_BW_RD_L0
, PXP2_REG_RQ_BW_RD_ADD0
,
336 PXP2_REG_RQ_BW_RD_UBOUND0
},
337 {PXP2_REG_PSWRQ_BW_L1
, PXP2_REG_PSWRQ_BW_ADD1
,
338 PXP2_REG_PSWRQ_BW_UB1
},
339 {PXP2_REG_PSWRQ_BW_L2
, PXP2_REG_PSWRQ_BW_ADD2
,
340 PXP2_REG_PSWRQ_BW_UB2
},
341 {PXP2_REG_PSWRQ_BW_L3
, PXP2_REG_PSWRQ_BW_ADD3
,
342 PXP2_REG_PSWRQ_BW_UB3
},
343 {PXP2_REG_RQ_BW_RD_L4
, PXP2_REG_RQ_BW_RD_ADD4
,
344 PXP2_REG_RQ_BW_RD_UBOUND4
},
345 {PXP2_REG_RQ_BW_RD_L5
, PXP2_REG_RQ_BW_RD_ADD5
,
346 PXP2_REG_RQ_BW_RD_UBOUND5
},
347 {PXP2_REG_PSWRQ_BW_L6
, PXP2_REG_PSWRQ_BW_ADD6
,
348 PXP2_REG_PSWRQ_BW_UB6
},
349 {PXP2_REG_PSWRQ_BW_L7
, PXP2_REG_PSWRQ_BW_ADD7
,
350 PXP2_REG_PSWRQ_BW_UB7
},
351 {PXP2_REG_PSWRQ_BW_L8
, PXP2_REG_PSWRQ_BW_ADD8
,
352 PXP2_REG_PSWRQ_BW_UB8
},
353 /* 10 */{PXP2_REG_PSWRQ_BW_L9
, PXP2_REG_PSWRQ_BW_ADD9
,
354 PXP2_REG_PSWRQ_BW_UB9
},
355 {PXP2_REG_PSWRQ_BW_L10
, PXP2_REG_PSWRQ_BW_ADD10
,
356 PXP2_REG_PSWRQ_BW_UB10
},
357 {PXP2_REG_PSWRQ_BW_L11
, PXP2_REG_PSWRQ_BW_ADD11
,
358 PXP2_REG_PSWRQ_BW_UB11
},
359 {PXP2_REG_RQ_BW_RD_L12
, PXP2_REG_RQ_BW_RD_ADD12
,
360 PXP2_REG_RQ_BW_RD_UBOUND12
},
361 {PXP2_REG_RQ_BW_RD_L13
, PXP2_REG_RQ_BW_RD_ADD13
,
362 PXP2_REG_RQ_BW_RD_UBOUND13
},
363 {PXP2_REG_RQ_BW_RD_L14
, PXP2_REG_RQ_BW_RD_ADD14
,
364 PXP2_REG_RQ_BW_RD_UBOUND14
},
365 {PXP2_REG_RQ_BW_RD_L15
, PXP2_REG_RQ_BW_RD_ADD15
,
366 PXP2_REG_RQ_BW_RD_UBOUND15
},
367 {PXP2_REG_RQ_BW_RD_L16
, PXP2_REG_RQ_BW_RD_ADD16
,
368 PXP2_REG_RQ_BW_RD_UBOUND16
},
369 {PXP2_REG_RQ_BW_RD_L17
, PXP2_REG_RQ_BW_RD_ADD17
,
370 PXP2_REG_RQ_BW_RD_UBOUND17
},
371 {PXP2_REG_RQ_BW_RD_L18
, PXP2_REG_RQ_BW_RD_ADD18
,
372 PXP2_REG_RQ_BW_RD_UBOUND18
},
373 /* 20 */{PXP2_REG_RQ_BW_RD_L19
, PXP2_REG_RQ_BW_RD_ADD19
,
374 PXP2_REG_RQ_BW_RD_UBOUND19
},
375 {PXP2_REG_RQ_BW_RD_L20
, PXP2_REG_RQ_BW_RD_ADD20
,
376 PXP2_REG_RQ_BW_RD_UBOUND20
},
377 {PXP2_REG_RQ_BW_RD_L22
, PXP2_REG_RQ_BW_RD_ADD22
,
378 PXP2_REG_RQ_BW_RD_UBOUND22
},
379 {PXP2_REG_RQ_BW_RD_L23
, PXP2_REG_RQ_BW_RD_ADD23
,
380 PXP2_REG_RQ_BW_RD_UBOUND23
},
381 {PXP2_REG_RQ_BW_RD_L24
, PXP2_REG_RQ_BW_RD_ADD24
,
382 PXP2_REG_RQ_BW_RD_UBOUND24
},
383 {PXP2_REG_RQ_BW_RD_L25
, PXP2_REG_RQ_BW_RD_ADD25
,
384 PXP2_REG_RQ_BW_RD_UBOUND25
},
385 {PXP2_REG_RQ_BW_RD_L26
, PXP2_REG_RQ_BW_RD_ADD26
,
386 PXP2_REG_RQ_BW_RD_UBOUND26
},
387 {PXP2_REG_RQ_BW_RD_L27
, PXP2_REG_RQ_BW_RD_ADD27
,
388 PXP2_REG_RQ_BW_RD_UBOUND27
},
389 {PXP2_REG_PSWRQ_BW_L28
, PXP2_REG_PSWRQ_BW_ADD28
,
390 PXP2_REG_PSWRQ_BW_UB28
}
393 /* register addresses for write queues */
394 static const struct arb_line write_arb_addr
[NUM_WR_Q
-1] = {
395 /* 1 */ {PXP2_REG_PSWRQ_BW_L1
, PXP2_REG_PSWRQ_BW_ADD1
,
396 PXP2_REG_PSWRQ_BW_UB1
},
397 {PXP2_REG_PSWRQ_BW_L2
, PXP2_REG_PSWRQ_BW_ADD2
,
398 PXP2_REG_PSWRQ_BW_UB2
},
399 {PXP2_REG_PSWRQ_BW_L3
, PXP2_REG_PSWRQ_BW_ADD3
,
400 PXP2_REG_PSWRQ_BW_UB3
},
401 {PXP2_REG_PSWRQ_BW_L6
, PXP2_REG_PSWRQ_BW_ADD6
,
402 PXP2_REG_PSWRQ_BW_UB6
},
403 {PXP2_REG_PSWRQ_BW_L7
, PXP2_REG_PSWRQ_BW_ADD7
,
404 PXP2_REG_PSWRQ_BW_UB7
},
405 {PXP2_REG_PSWRQ_BW_L8
, PXP2_REG_PSWRQ_BW_ADD8
,
406 PXP2_REG_PSWRQ_BW_UB8
},
407 {PXP2_REG_PSWRQ_BW_L9
, PXP2_REG_PSWRQ_BW_ADD9
,
408 PXP2_REG_PSWRQ_BW_UB9
},
409 {PXP2_REG_PSWRQ_BW_L10
, PXP2_REG_PSWRQ_BW_ADD10
,
410 PXP2_REG_PSWRQ_BW_UB10
},
411 {PXP2_REG_PSWRQ_BW_L11
, PXP2_REG_PSWRQ_BW_ADD11
,
412 PXP2_REG_PSWRQ_BW_UB11
},
413 /* 10 */{PXP2_REG_PSWRQ_BW_L28
, PXP2_REG_PSWRQ_BW_ADD28
,
414 PXP2_REG_PSWRQ_BW_UB28
},
415 {PXP2_REG_RQ_BW_WR_L29
, PXP2_REG_RQ_BW_WR_ADD29
,
416 PXP2_REG_RQ_BW_WR_UBOUND29
},
417 {PXP2_REG_RQ_BW_WR_L30
, PXP2_REG_RQ_BW_WR_ADD30
,
418 PXP2_REG_RQ_BW_WR_UBOUND30
}
421 static void ecore_init_pxp_arb(struct bnx2x_softc
*sc
, int r_order
,
426 if (r_order
> MAX_RD_ORD
) {
427 ECORE_MSG(sc
, "read order of %d order adjusted to %d",
428 r_order
, MAX_RD_ORD
);
429 r_order
= MAX_RD_ORD
;
431 if (w_order
> MAX_WR_ORD
) {
432 ECORE_MSG(sc
, "write order of %d order adjusted to %d",
433 w_order
, MAX_WR_ORD
);
434 w_order
= MAX_WR_ORD
;
436 if (CHIP_REV_IS_FPGA(sc
)) {
437 ECORE_MSG(sc
, "write order adjusted to 1 for FPGA");
440 ECORE_MSG(sc
, "read order %d write order %d", r_order
, w_order
);
442 for (i
= 0; i
< NUM_RD_Q
-1; i
++) {
443 REG_WR(sc
, read_arb_addr
[i
].l
, read_arb_data
[i
][r_order
].l
);
444 REG_WR(sc
, read_arb_addr
[i
].add
,
445 read_arb_data
[i
][r_order
].add
);
446 REG_WR(sc
, read_arb_addr
[i
].ubound
,
447 read_arb_data
[i
][r_order
].ubound
);
450 for (i
= 0; i
< NUM_WR_Q
-1; i
++) {
451 if ((write_arb_addr
[i
].l
== PXP2_REG_RQ_BW_WR_L29
) ||
452 (write_arb_addr
[i
].l
== PXP2_REG_RQ_BW_WR_L30
)) {
454 REG_WR(sc
, write_arb_addr
[i
].l
,
455 write_arb_data
[i
][w_order
].l
);
457 REG_WR(sc
, write_arb_addr
[i
].add
,
458 write_arb_data
[i
][w_order
].add
);
460 REG_WR(sc
, write_arb_addr
[i
].ubound
,
461 write_arb_data
[i
][w_order
].ubound
);
464 val
= REG_RD(sc
, write_arb_addr
[i
].l
);
465 REG_WR(sc
, write_arb_addr
[i
].l
,
466 val
| (write_arb_data
[i
][w_order
].l
<< 10));
468 val
= REG_RD(sc
, write_arb_addr
[i
].add
);
469 REG_WR(sc
, write_arb_addr
[i
].add
,
470 val
| (write_arb_data
[i
][w_order
].add
<< 10));
472 val
= REG_RD(sc
, write_arb_addr
[i
].ubound
);
473 REG_WR(sc
, write_arb_addr
[i
].ubound
,
474 val
| (write_arb_data
[i
][w_order
].ubound
<< 7));
478 val
= write_arb_data
[NUM_WR_Q
-1][w_order
].add
;
479 val
+= write_arb_data
[NUM_WR_Q
-1][w_order
].ubound
<< 10;
480 val
+= write_arb_data
[NUM_WR_Q
-1][w_order
].l
<< 17;
481 REG_WR(sc
, PXP2_REG_PSWRQ_BW_RD
, val
);
483 val
= read_arb_data
[NUM_RD_Q
-1][r_order
].add
;
484 val
+= read_arb_data
[NUM_RD_Q
-1][r_order
].ubound
<< 10;
485 val
+= read_arb_data
[NUM_RD_Q
-1][r_order
].l
<< 17;
486 REG_WR(sc
, PXP2_REG_PSWRQ_BW_WR
, val
);
488 REG_WR(sc
, PXP2_REG_RQ_WR_MBS0
, w_order
);
489 REG_WR(sc
, PXP2_REG_RQ_WR_MBS1
, w_order
);
490 REG_WR(sc
, PXP2_REG_RQ_RD_MBS0
, r_order
);
491 REG_WR(sc
, PXP2_REG_RQ_RD_MBS1
, r_order
);
493 if (CHIP_IS_E1H(sc
) && (r_order
== MAX_RD_ORD
))
494 REG_WR(sc
, PXP2_REG_RQ_PDR_LIMIT
, 0xe00);
497 REG_WR(sc
, PXP2_REG_WR_USDMDP_TH
, (0x4 << w_order
));
498 else if (CHIP_IS_E2(sc
))
499 REG_WR(sc
, PXP2_REG_WR_USDMDP_TH
, (0x8 << w_order
));
501 REG_WR(sc
, PXP2_REG_WR_USDMDP_TH
, (0x18 << w_order
));
503 /* MPS w_order optimal TH presently TH
508 /* DMAE is special */
509 if (!CHIP_IS_E1H(sc
)) {
510 /* E2 can use optimal TH */
512 REG_WR(sc
, PXP2_REG_WR_DMAE_MPS
, val
);
514 val
= ((w_order
== 0) ? 2 : 3);
515 REG_WR(sc
, PXP2_REG_WR_DMAE_MPS
, 2);
518 REG_WR(sc
, PXP2_REG_WR_HC_MPS
, val
);
519 REG_WR(sc
, PXP2_REG_WR_USDM_MPS
, val
);
520 REG_WR(sc
, PXP2_REG_WR_CSDM_MPS
, val
);
521 REG_WR(sc
, PXP2_REG_WR_TSDM_MPS
, val
);
522 REG_WR(sc
, PXP2_REG_WR_XSDM_MPS
, val
);
523 REG_WR(sc
, PXP2_REG_WR_QM_MPS
, val
);
524 REG_WR(sc
, PXP2_REG_WR_TM_MPS
, val
);
525 REG_WR(sc
, PXP2_REG_WR_SRC_MPS
, val
);
526 REG_WR(sc
, PXP2_REG_WR_DBG_MPS
, val
);
527 REG_WR(sc
, PXP2_REG_WR_CDU_MPS
, val
);
529 /* Validate number of tags suppoted by device */
530 #define PCIE_REG_PCIER_TL_HDR_FC_ST 0x2980
531 val
= REG_RD(sc
, PCIE_REG_PCIER_TL_HDR_FC_ST
);
534 REG_WR(sc
, PXP2_REG_PGL_TAGS_LIMIT
, 0x20);
537 /****************************************************************************
539 ****************************************************************************/
541 * This codes hides the low level HW interaction for ILT management and
542 * configuration. The API consists of a shadow ILT table which is set by the
543 * driver and a set of routines to use it to configure the HW.
547 /* ILT HW init operations */
549 /* ILT memory management operations */
550 #define ILT_MEMOP_ALLOC 0
551 #define ILT_MEMOP_FREE 1
553 /* the phys address is shifted right 12 bits and has an added
554 * 1=valid bit added to the 53rd bit
555 * then since this is a wide register(TM)
556 * we split it into two 32 bit writes
558 #define ILT_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
559 #define ILT_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
560 #define ILT_RANGE(f, l) (((l) << 10) | f)
562 static int ecore_ilt_line_mem_op(struct bnx2x_softc
*sc
,
563 struct ilt_line
*line
, uint32_t size
, uint8_t memop
, int cli_num
, int i
)
565 #define ECORE_ILT_NAMESIZE 10
566 char str
[ECORE_ILT_NAMESIZE
];
568 if (memop
== ILT_MEMOP_FREE
) {
569 ECORE_ILT_FREE(line
->page
, line
->page_mapping
, line
->size
);
572 snprintf(str
, ECORE_ILT_NAMESIZE
, "ILT_%d_%d", cli_num
, i
);
573 ECORE_ILT_ZALLOC(line
->page
, &line
->page_mapping
, size
, str
);
581 static int ecore_ilt_client_mem_op(struct bnx2x_softc
*sc
, int cli_num
,
585 struct ecore_ilt
*ilt
= SC_ILT(sc
);
586 struct ilt_client_info
*ilt_cli
= &ilt
->clients
[cli_num
];
588 if (!ilt
|| !ilt
->lines
)
591 if (ilt_cli
->flags
& (ILT_CLIENT_SKIP_INIT
| ILT_CLIENT_SKIP_MEM
))
594 for (i
= ilt_cli
->start
; i
<= ilt_cli
->end
&& !rc
; i
++) {
595 rc
= ecore_ilt_line_mem_op(sc
, &ilt
->lines
[i
],
596 ilt_cli
->page_size
, memop
, cli_num
, i
);
601 static inline int ecore_ilt_mem_op_cnic(struct bnx2x_softc
*sc
, uint8_t memop
)
605 if (CONFIGURE_NIC_MODE(sc
))
606 rc
= ecore_ilt_client_mem_op(sc
, ILT_CLIENT_SRC
, memop
);
608 rc
= ecore_ilt_client_mem_op(sc
, ILT_CLIENT_TM
, memop
);
613 static int ecore_ilt_mem_op(struct bnx2x_softc
*sc
, uint8_t memop
)
615 int rc
= ecore_ilt_client_mem_op(sc
, ILT_CLIENT_CDU
, memop
);
617 rc
= ecore_ilt_client_mem_op(sc
, ILT_CLIENT_QM
, memop
);
618 if (!rc
&& CNIC_SUPPORT(sc
) && !CONFIGURE_NIC_MODE(sc
))
619 rc
= ecore_ilt_client_mem_op(sc
, ILT_CLIENT_SRC
, memop
);
624 static void ecore_ilt_line_wr(struct bnx2x_softc
*sc
, int abs_idx
,
625 ecore_dma_addr_t page_mapping
)
629 reg
= PXP2_REG_RQ_ONCHIP_AT_B0
+ abs_idx
*8;
631 ecore_wr_64(sc
, reg
, ILT_ADDR1(page_mapping
), ILT_ADDR2(page_mapping
));
634 static void ecore_ilt_line_init_op(struct bnx2x_softc
*sc
,
635 struct ecore_ilt
*ilt
, int idx
, uint8_t initop
)
637 ecore_dma_addr_t null_mapping
;
638 int abs_idx
= ilt
->start_line
+ idx
;
642 /* set in the init-value array */
644 ecore_ilt_line_wr(sc
, abs_idx
, ilt
->lines
[idx
].page_mapping
);
648 ecore_ilt_line_wr(sc
, abs_idx
, null_mapping
);
653 static void ecore_ilt_boundry_init_op(struct bnx2x_softc
*sc
,
654 struct ilt_client_info
*ilt_cli
,
657 uint32_t start_reg
= 0;
658 uint32_t end_reg
= 0;
660 /* The boundary is either SET or INIT,
661 CLEAR => SET and for now SET ~~ INIT */
663 /* find the appropriate regs */
664 switch (ilt_cli
->client_num
) {
666 start_reg
= PXP2_REG_RQ_CDU_FIRST_ILT
;
667 end_reg
= PXP2_REG_RQ_CDU_LAST_ILT
;
670 start_reg
= PXP2_REG_RQ_QM_FIRST_ILT
;
671 end_reg
= PXP2_REG_RQ_QM_LAST_ILT
;
674 start_reg
= PXP2_REG_RQ_SRC_FIRST_ILT
;
675 end_reg
= PXP2_REG_RQ_SRC_LAST_ILT
;
678 start_reg
= PXP2_REG_RQ_TM_FIRST_ILT
;
679 end_reg
= PXP2_REG_RQ_TM_LAST_ILT
;
682 REG_WR(sc
, start_reg
, (ilt_start
+ ilt_cli
->start
));
683 REG_WR(sc
, end_reg
, (ilt_start
+ ilt_cli
->end
));
686 static void ecore_ilt_client_init_op_ilt(struct bnx2x_softc
*sc
,
687 struct ecore_ilt
*ilt
,
688 struct ilt_client_info
*ilt_cli
,
693 if (ilt_cli
->flags
& ILT_CLIENT_SKIP_INIT
)
696 for (i
= ilt_cli
->start
; i
<= ilt_cli
->end
; i
++)
697 ecore_ilt_line_init_op(sc
, ilt
, i
, initop
);
699 /* init/clear the ILT boundries */
700 ecore_ilt_boundry_init_op(sc
, ilt_cli
, ilt
->start_line
);
703 static void ecore_ilt_client_init_op(struct bnx2x_softc
*sc
,
704 struct ilt_client_info
*ilt_cli
, uint8_t initop
)
706 struct ecore_ilt
*ilt
= SC_ILT(sc
);
708 ecore_ilt_client_init_op_ilt(sc
, ilt
, ilt_cli
, initop
);
711 static void ecore_ilt_client_id_init_op(struct bnx2x_softc
*sc
,
712 int cli_num
, uint8_t initop
)
714 struct ecore_ilt
*ilt
= SC_ILT(sc
);
715 struct ilt_client_info
*ilt_cli
= &ilt
->clients
[cli_num
];
717 ecore_ilt_client_init_op(sc
, ilt_cli
, initop
);
720 static inline void ecore_ilt_init_op_cnic(struct bnx2x_softc
*sc
, uint8_t initop
)
722 if (CONFIGURE_NIC_MODE(sc
))
723 ecore_ilt_client_id_init_op(sc
, ILT_CLIENT_SRC
, initop
);
724 ecore_ilt_client_id_init_op(sc
, ILT_CLIENT_TM
, initop
);
727 static void ecore_ilt_init_op(struct bnx2x_softc
*sc
, uint8_t initop
)
729 ecore_ilt_client_id_init_op(sc
, ILT_CLIENT_CDU
, initop
);
730 ecore_ilt_client_id_init_op(sc
, ILT_CLIENT_QM
, initop
);
731 if (CNIC_SUPPORT(sc
) && !CONFIGURE_NIC_MODE(sc
))
732 ecore_ilt_client_id_init_op(sc
, ILT_CLIENT_SRC
, initop
);
735 static void ecore_ilt_init_client_psz(struct bnx2x_softc
*sc
, int cli_num
,
736 uint32_t psz_reg
, uint8_t initop
)
738 struct ecore_ilt
*ilt
= SC_ILT(sc
);
739 struct ilt_client_info
*ilt_cli
= &ilt
->clients
[cli_num
];
741 if (ilt_cli
->flags
& ILT_CLIENT_SKIP_INIT
)
746 /* set in the init-value array */
748 REG_WR(sc
, psz_reg
, ILOG2(ilt_cli
->page_size
>> 12));
756 * called during init common stage, ilt clients should be initialized
757 * prioir to calling this function
759 static void ecore_ilt_init_page_size(struct bnx2x_softc
*sc
, uint8_t initop
)
761 ecore_ilt_init_client_psz(sc
, ILT_CLIENT_CDU
,
762 PXP2_REG_RQ_CDU_P_SIZE
, initop
);
763 ecore_ilt_init_client_psz(sc
, ILT_CLIENT_QM
,
764 PXP2_REG_RQ_QM_P_SIZE
, initop
);
765 ecore_ilt_init_client_psz(sc
, ILT_CLIENT_SRC
,
766 PXP2_REG_RQ_SRC_P_SIZE
, initop
);
767 ecore_ilt_init_client_psz(sc
, ILT_CLIENT_TM
,
768 PXP2_REG_RQ_TM_P_SIZE
, initop
);
771 /****************************************************************************
773 ****************************************************************************/
774 #define QM_QUEUES_PER_FUNC 16
775 #define QM_INIT_MIN_CID_COUNT 31
776 #define QM_INIT(cid_cnt) (cid_cnt > QM_INIT_MIN_CID_COUNT)
778 /* called during init port stage */
779 static void ecore_qm_init_cid_count(struct bnx2x_softc
*sc
, int qm_cid_count
,
782 int port
= SC_PORT(sc
);
784 if (QM_INIT(qm_cid_count
)) {
787 /* set in the init-value array */
789 REG_WR(sc
, QM_REG_CONNNUM_0
+ port
*4,
790 qm_cid_count
/16 - 1);
798 static void ecore_qm_set_ptr_table(struct bnx2x_softc
*sc
, int qm_cid_count
,
799 uint32_t base_reg
, uint32_t reg
)
802 uint32_t wb_data
[2] = {0, 0};
803 for (i
= 0; i
< 4 * QM_QUEUES_PER_FUNC
; i
++) {
804 REG_WR(sc
, base_reg
+ i
*4,
805 qm_cid_count
* 4 * (i
% QM_QUEUES_PER_FUNC
));
806 ecore_init_wr_wb(sc
, reg
+ i
*8,
811 /* called during init common stage */
812 static void ecore_qm_init_ptr_table(struct bnx2x_softc
*sc
, int qm_cid_count
,
815 if (!QM_INIT(qm_cid_count
))
820 /* set in the init-value array */
822 ecore_qm_set_ptr_table(sc
, qm_cid_count
,
823 QM_REG_BASEADDR
, QM_REG_PTRTBL
);
825 ecore_qm_set_ptr_table(sc
, qm_cid_count
,
826 QM_REG_BASEADDR_EXT_A
,
827 QM_REG_PTRTBL_EXT_A
);
834 /****************************************************************************
835 * SRC initializations
836 ****************************************************************************/
838 /* called during init func stage */
839 static void ecore_src_init_t2(struct bnx2x_softc
*sc
, struct src_ent
*t2
,
840 ecore_dma_addr_t t2_mapping
, int src_cid_count
)
843 int port
= SC_PORT(sc
);
846 for (i
= 0; i
< src_cid_count
-1; i
++)
847 t2
[i
].next
= (uint64_t)(t2_mapping
+
848 (i
+1)*sizeof(struct src_ent
));
850 /* tell the searcher where the T2 table is */
851 REG_WR(sc
, SRC_REG_COUNTFREE0
+ port
*4, src_cid_count
);
853 ecore_wr_64(sc
, SRC_REG_FIRSTFREE0
+ port
*16,
854 U64_LO(t2_mapping
), U64_HI(t2_mapping
));
856 ecore_wr_64(sc
, SRC_REG_LASTFREE0
+ port
*16,
857 U64_LO((uint64_t)t2_mapping
+
858 (src_cid_count
-1) * sizeof(struct src_ent
)),
859 U64_HI((uint64_t)t2_mapping
+
860 (src_cid_count
-1) * sizeof(struct src_ent
)));
863 #endif /* ECORE_INIT_OPS_H */