2 * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015 QLogic Corporation.
10 * All rights reserved.
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
18 #include "ecore_mfw_req.h"
19 #include "ecore_fw_defs.h"
20 #include "ecore_hsi.h"
21 #include "ecore_reg.h"
23 static elink_status_t
elink_link_reset(struct elink_params
*params
,
24 struct elink_vars
*vars
,
25 uint8_t reset_ext_phy
);
26 static elink_status_t
elink_check_half_open_conn(struct elink_params
*params
,
27 struct elink_vars
*vars
,
29 static elink_status_t
elink_sfp_module_detection(struct elink_phy
*phy
,
30 struct elink_params
*params
);
32 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
33 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
34 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
35 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
36 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
38 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
39 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
40 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
41 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
42 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
43 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
44 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
45 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
46 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
47 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
48 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
49 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
50 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
51 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
52 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
53 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
54 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
56 #define MDIO_REG_BANK_RX0 0x80b0
57 #define MDIO_RX0_RX_STATUS 0x10
58 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
59 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
60 #define MDIO_RX0_RX_EQ_BOOST 0x1c
61 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
62 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
64 #define MDIO_REG_BANK_RX1 0x80c0
65 #define MDIO_RX1_RX_EQ_BOOST 0x1c
66 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
67 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
69 #define MDIO_REG_BANK_RX2 0x80d0
70 #define MDIO_RX2_RX_EQ_BOOST 0x1c
71 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
72 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
74 #define MDIO_REG_BANK_RX3 0x80e0
75 #define MDIO_RX3_RX_EQ_BOOST 0x1c
76 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
77 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
79 #define MDIO_REG_BANK_RX_ALL 0x80f0
80 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
81 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
82 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
84 #define MDIO_REG_BANK_TX0 0x8060
85 #define MDIO_TX0_TX_DRIVER 0x17
86 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
87 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
88 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
89 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
90 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
91 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
92 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
93 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
94 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
96 #define MDIO_REG_BANK_TX1 0x8070
97 #define MDIO_TX1_TX_DRIVER 0x17
98 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
99 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
100 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
101 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
102 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
103 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
104 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
105 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
106 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
108 #define MDIO_REG_BANK_TX2 0x8080
109 #define MDIO_TX2_TX_DRIVER 0x17
110 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
111 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
112 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
113 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
114 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
115 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
116 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
117 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
118 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
120 #define MDIO_REG_BANK_TX3 0x8090
121 #define MDIO_TX3_TX_DRIVER 0x17
122 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
123 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
124 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
125 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
126 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
127 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
128 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
129 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
130 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
132 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
133 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
135 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
136 #define MDIO_BLOCK1_LANE_CTRL0 0x15
137 #define MDIO_BLOCK1_LANE_CTRL1 0x16
138 #define MDIO_BLOCK1_LANE_CTRL2 0x17
139 #define MDIO_BLOCK1_LANE_PRBS 0x19
141 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
142 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
143 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
144 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
145 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
146 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
147 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
148 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
149 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
150 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
152 #define MDIO_REG_BANK_GP_STATUS 0x8120
153 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
154 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
155 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
156 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
157 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
158 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
159 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
160 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
161 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
162 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
163 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
164 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
165 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
166 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
167 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
168 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
169 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
170 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
171 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
172 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
173 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
174 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
175 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
176 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
177 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
178 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
179 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
180 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
181 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
182 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
184 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
185 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
186 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
187 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
188 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
189 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
190 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
192 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
193 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
194 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
195 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
196 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
197 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
198 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
199 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
200 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
201 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
202 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
203 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
204 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
205 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
206 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
207 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
208 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
209 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
210 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
211 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
212 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
213 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
214 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
215 #define MDIO_SERDES_DIGITAL_MISC1 0x18
216 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
217 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
218 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
219 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
220 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
221 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
222 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
223 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
224 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
225 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
226 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
227 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
228 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
229 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
230 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
231 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
232 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
233 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
235 #define MDIO_REG_BANK_OVER_1G 0x8320
236 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
237 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
238 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
239 #define MDIO_OVER_1G_UP1 0x19
240 #define MDIO_OVER_1G_UP1_2_5G 0x0001
241 #define MDIO_OVER_1G_UP1_5G 0x0002
242 #define MDIO_OVER_1G_UP1_6G 0x0004
243 #define MDIO_OVER_1G_UP1_10G 0x0010
244 #define MDIO_OVER_1G_UP1_10GH 0x0008
245 #define MDIO_OVER_1G_UP1_12G 0x0020
246 #define MDIO_OVER_1G_UP1_12_5G 0x0040
247 #define MDIO_OVER_1G_UP1_13G 0x0080
248 #define MDIO_OVER_1G_UP1_15G 0x0100
249 #define MDIO_OVER_1G_UP1_16G 0x0200
250 #define MDIO_OVER_1G_UP2 0x1A
251 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
252 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
253 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
254 #define MDIO_OVER_1G_UP3 0x1B
255 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
256 #define MDIO_OVER_1G_LP_UP1 0x1C
257 #define MDIO_OVER_1G_LP_UP2 0x1D
258 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
259 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
260 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
261 #define MDIO_OVER_1G_LP_UP3 0x1E
263 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
264 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
265 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
266 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
268 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
269 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
270 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
271 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
273 #define MDIO_REG_BANK_CL73_USERB0 0x8370
274 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
275 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
276 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
277 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
278 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
279 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
280 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
281 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
282 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
283 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
284 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
286 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
287 #define MDIO_AER_BLOCK_AER_REG 0x1E
289 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
290 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
291 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
292 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
293 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
294 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
295 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
296 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
297 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
298 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
299 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
300 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
301 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
302 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
303 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
304 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
305 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
306 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
307 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
308 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
309 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
310 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
311 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
312 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
313 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
314 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
315 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
316 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
317 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
318 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
319 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
320 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
321 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
322 Theotherbitsarereservedandshouldbezero*/
323 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
325 #define MDIO_PMA_DEVAD 0x1
327 #define MDIO_PMA_REG_CTRL 0x0
328 #define MDIO_PMA_REG_STATUS 0x1
329 #define MDIO_PMA_REG_10G_CTRL2 0x7
330 #define MDIO_PMA_REG_TX_DISABLE 0x0009
331 #define MDIO_PMA_REG_RX_SD 0xa
333 #define MDIO_PMA_REG_BNX2X_CTRL 0x0096
334 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
335 #define MDIO_PMA_LASI_RXCTRL 0x9000
336 #define MDIO_PMA_LASI_TXCTRL 0x9001
337 #define MDIO_PMA_LASI_CTRL 0x9002
338 #define MDIO_PMA_LASI_RXSTAT 0x9003
339 #define MDIO_PMA_LASI_TXSTAT 0x9004
340 #define MDIO_PMA_LASI_STAT 0x9005
341 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
342 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
343 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
344 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
345 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
346 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
347 #define MDIO_PMA_REG_GEN_CTRL 0xca10
348 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
349 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
350 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
351 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
352 #define MDIO_PMA_REG_ROM_VER1 0xca19
353 #define MDIO_PMA_REG_ROM_VER2 0xca1a
354 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
355 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
356 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
357 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
358 #define MDIO_PMA_REG_LRM_MODE 0xca3f
359 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
360 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
362 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
363 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
364 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
365 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
366 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
367 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
368 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
369 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
370 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
371 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
372 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
373 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
375 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
376 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
377 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
378 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
379 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
380 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
381 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
382 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
383 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
384 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
386 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
387 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
388 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
389 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
390 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
392 #define MDIO_PMA_REG_7101_RESET 0xc000
393 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
394 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
395 #define MDIO_PMA_REG_7101_VER1 0xc026
396 #define MDIO_PMA_REG_7101_VER2 0xc027
398 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
399 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
400 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
401 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
402 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
403 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
404 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
405 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
406 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
407 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
409 #define MDIO_WIS_DEVAD 0x2
411 #define MDIO_WIS_REG_LASI_CNTL 0x9002
412 #define MDIO_WIS_REG_LASI_STATUS 0x9005
414 #define MDIO_PCS_DEVAD 0x3
415 #define MDIO_PCS_REG_STATUS 0x0020
416 #define MDIO_PCS_REG_LASI_STATUS 0x9005
417 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
418 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
419 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
420 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
421 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
422 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
423 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
424 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
425 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
427 #define MDIO_XS_DEVAD 0x4
428 #define MDIO_XS_REG_STATUS 0x0001
429 #define MDIO_XS_PLL_SEQUENCER 0x8000
430 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
432 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
433 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
434 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
435 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
436 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
438 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
440 #define MDIO_AN_DEVAD 0x7
442 #define MDIO_AN_REG_CTRL 0x0000
443 #define MDIO_AN_REG_STATUS 0x0001
444 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
445 #define MDIO_AN_REG_ADV_PAUSE 0x0010
446 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
447 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
448 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
449 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
450 #define MDIO_AN_REG_ADV 0x0011
451 #define MDIO_AN_REG_ADV2 0x0012
452 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
453 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
454 #define MDIO_AN_REG_MASTER_STATUS 0x0021
455 #define MDIO_AN_REG_EEE_ADV 0x003c
456 #define MDIO_AN_REG_LP_EEE_ADV 0x003d
458 #define MDIO_AN_REG_LINK_STATUS 0x8304
459 #define MDIO_AN_REG_CL37_CL73 0x8370
460 #define MDIO_AN_REG_CL37_AN 0xffe0
461 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
462 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
463 #define MDIO_AN_REG_1000T_STATUS 0xffea
465 #define MDIO_AN_REG_8073_2_5G 0x8329
466 #define MDIO_AN_REG_8073_BAM 0x8350
468 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
469 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
470 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
471 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
472 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
473 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
474 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
475 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
476 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
477 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
478 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
479 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
480 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
482 /* BNX2X84823 only */
483 #define MDIO_CTL_DEVAD 0x1e
484 #define MDIO_CTL_REG_84823_MEDIA 0x401a
485 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
486 /* These pins configure the BNX2X84823 interface to MAC after reset. */
487 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
488 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
489 /* These pins configure the BNX2X84823 interface to Line after reset. */
490 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
491 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
492 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
493 /* When this pin is active high during reset, 10GBASE-T core is power
494 * down, When it is active low the 10GBASE-T is power up
496 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
497 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
498 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
499 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
500 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
501 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
502 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
503 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
504 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
505 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
506 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
507 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
509 /* BNX2X84833 only */
510 #define MDIO_84833_TOP_CFG_FW_REV 0x400f
511 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
512 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
513 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
514 #define MDIO_84833_SUPER_ISOLATE 0x8000
515 /* These are mailbox register set used by 84833. */
516 #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
517 #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
518 #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
519 #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
520 #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
521 #define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
522 #define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
523 #define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
524 #define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
525 #define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
526 #define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
527 #define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
528 #define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
529 #define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
530 #define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
531 #define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
532 #define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
533 #define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
535 /* Mailbox command set used by 84833. */
536 #define PHY84833_CMD_SET_PAIR_SWAP 0x8001
537 #define PHY84833_CMD_GET_EEE_MODE 0x8008
538 #define PHY84833_CMD_SET_EEE_MODE 0x8009
539 #define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
540 /* Mailbox status set used by 84833. */
541 #define PHY84833_STATUS_CMD_RECEIVED 0x0001
542 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
543 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
544 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
545 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
546 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
547 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
548 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
549 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
551 /* Warpcore clause 45 addressing */
552 #define MDIO_WC_DEVAD 0x3
553 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
554 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
555 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
556 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
557 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
558 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
559 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
560 #define MDIO_WC_REG_PCS_STATUS2 0x0021
561 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
562 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
563 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
564 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
565 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
566 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
567 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
568 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018
569 #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a
570 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
571 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
572 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
573 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
574 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
575 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
576 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
577 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
578 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
579 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
580 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
581 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
582 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
583 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
584 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
585 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
586 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
587 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
588 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
589 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
590 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
591 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
592 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
593 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
594 #define MDIO_WC_REG_XGXS_STATUS4 0x813c
595 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
596 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
597 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
598 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
599 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
600 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
601 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
602 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
603 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
604 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
605 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
606 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
607 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
608 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
609 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
610 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
611 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
612 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
613 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
614 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
615 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
616 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
617 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
618 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
619 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
620 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
621 #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e
622 #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7)
623 #define MDIO_WC_REG_DSC_SMC 0x8213
624 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
625 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
626 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
627 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
628 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
629 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
630 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
631 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
632 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
633 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
634 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
635 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
636 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
637 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
638 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
639 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
640 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
641 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
642 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
643 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
644 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
645 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
646 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
647 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
648 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
649 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
650 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
651 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
652 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
653 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
654 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
655 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
656 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
657 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
658 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
659 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
660 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
661 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
662 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
663 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
664 #define MDIO_WC_REG_RX66_SCW0 0x83c2
665 #define MDIO_WC_REG_RX66_SCW1 0x83c3
666 #define MDIO_WC_REG_RX66_SCW2 0x83c4
667 #define MDIO_WC_REG_RX66_SCW3 0x83c5
668 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
669 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
670 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
671 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
672 #define MDIO_WC_REG_FX100_CTRL1 0x8400
673 #define MDIO_WC_REG_FX100_CTRL3 0x8402
674 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
675 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
676 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
677 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
678 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
679 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
680 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
681 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
682 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
683 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
684 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
685 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
686 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
687 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
689 #define MDIO_WC_REG_AERBLK_AER 0xffde
690 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
691 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
693 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
694 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
695 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
697 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
699 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
702 #define MDIO_REG_GPHY_MII_STATUS 0x1
703 #define MDIO_REG_GPHY_PHYID_LSB 0x3
704 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
705 #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
706 #define MDIO_REG_GPHY_CL45_REG_READ 0xc000
707 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe
708 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
709 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
710 #define MDIO_REG_GPHY_EXP_ACCESS 0x17
711 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
712 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
713 #define MDIO_REG_GPHY_AUX_STATUS 0x19
714 #define MDIO_REG_INTR_STATUS 0x1a
715 #define MDIO_REG_INTR_MASK 0x1b
716 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
717 #define MDIO_REG_GPHY_SHADOW 0x1c
718 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
719 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
720 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
721 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
722 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
724 typedef elink_status_t(*read_sfp_module_eeprom_func_p
) (struct elink_phy
* phy
,
725 struct elink_params
*
732 /********************************************************/
733 #define ELINK_ETH_HLEN 14
734 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
735 #define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8)
736 #define ELINK_ETH_MIN_PACKET_SIZE 60
737 #define ELINK_ETH_MAX_PACKET_SIZE 1500
738 #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600
739 #define ELINK_MDIO_ACCESS_TIMEOUT 1000
740 #define WC_LANE_MAX 4
741 #define I2C_SWITCH_WIDTH 2
744 #define I2C_WA_RETRY_CNT 3
745 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
746 #define MCPR_IMC_COMMAND_READ_OP 1
747 #define MCPR_IMC_COMMAND_WRITE_OP 2
749 /* LED Blink rate that will achieve ~15.9Hz */
750 #define LED_BLINK_RATE_VAL_E3 354
751 #define LED_BLINK_RATE_VAL_E1X_E2 480
752 /***********************************************************/
753 /* Shortcut definitions */
754 /***********************************************************/
756 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0
758 #define ELINK_NIG_STATUS_EMAC0_MI_INT \
759 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
760 #define ELINK_NIG_STATUS_XGXS0_LINK10G \
761 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
762 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \
763 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
764 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
765 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
766 #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \
767 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
768 #define ELINK_NIG_MASK_MI_INT \
769 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
770 #define ELINK_NIG_MASK_XGXS0_LINK10G \
771 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
772 #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \
773 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
774 #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \
775 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
777 #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \
778 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
779 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
781 #define ELINK_XGXS_RESET_BITS \
782 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
783 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
784 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
785 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
786 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
788 #define ELINK_SERDES_RESET_BITS \
789 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
790 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
791 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
792 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
794 #define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
795 #define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
796 #define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
797 #define ELINK_AUTONEG_PARALLEL \
798 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
799 #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \
800 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
801 #define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
803 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
804 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
805 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
806 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
807 #define ELINK_GP_STATUS_SPEED_MASK \
808 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
809 #define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
810 #define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
811 #define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
812 #define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
813 #define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
814 #define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
815 #define ELINK_GP_STATUS_10G_HIG \
816 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
817 #define ELINK_GP_STATUS_10G_CX4 \
818 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
819 #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
820 #define ELINK_GP_STATUS_10G_KX4 \
821 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
822 #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
823 #define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
824 #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
825 #define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
826 #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
827 #define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
828 #define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
829 #define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
830 #define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
831 #define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
832 #define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
833 #define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
834 #define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
835 #define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
836 #define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
837 #define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
838 #define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
839 #define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
840 #define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
841 #define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
843 #define ELINK_LINK_UPDATE_MASK \
844 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
845 LINK_STATUS_LINK_UP | \
846 LINK_STATUS_PHYSICAL_LINK_FLAG | \
847 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
848 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
849 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
850 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
851 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
852 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
854 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2
855 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7
856 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
857 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
859 #define ELINK_SFP_EEPROM_COMP_CODE_ADDR 0x3
860 #define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
861 #define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
862 #define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
864 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8
865 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
866 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
868 #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40
869 #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
870 #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2
872 #define ELINK_EDC_MODE_LINEAR 0x0022
873 #define ELINK_EDC_MODE_LIMITING 0x0044
874 #define ELINK_EDC_MODE_PASSIVE_DAC 0x0055
875 #define ELINK_EDC_MODE_ACTIVE_DAC 0x0066
878 #define DCBX_INVALID_COS (0xFF)
880 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
881 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
882 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
883 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
884 #define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000)
886 #define ELINK_MAX_PACKET_SIZE (9700)
887 #define MAX_KR_LINK_RETRY 4
889 /**********************************************************/
891 /**********************************************************/
893 #define CL22_WR_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
894 elink_cl45_write(_sc, _phy, \
895 (_phy)->def_md_devad, \
896 (_bank + (_addr & 0xf)), \
899 #define CL22_RD_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
900 elink_cl45_read(_sc, _phy, \
901 (_phy)->def_md_devad, \
902 (_bank + (_addr & 0xf)), \
905 static uint32_t elink_bits_en(struct bnx2x_softc
*sc
, uint32_t reg
, uint32_t bits
)
907 uint32_t val
= REG_RD(sc
, reg
);
910 REG_WR(sc
, reg
, val
);
914 static uint32_t elink_bits_dis(struct bnx2x_softc
*sc
, uint32_t reg
,
917 uint32_t val
= REG_RD(sc
, reg
);
920 REG_WR(sc
, reg
, val
);
925 * elink_check_lfa - This function checks if link reinitialization is required,
926 * or link flap can be avoided.
928 * @params: link parameters
929 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
932 static int elink_check_lfa(struct elink_params
*params
)
934 uint32_t link_status
, cfg_idx
, lfa_mask
, cfg_size
;
935 uint32_t cur_speed_cap_mask
, cur_req_fc_auto_adv
, additional_config
;
936 uint32_t saved_val
, req_val
, eee_status
;
937 struct bnx2x_softc
*sc
= params
->sc
;
940 REG_RD(sc
, params
->lfa_base
+
941 offsetof(struct shmem_lfa
, additional_config
));
943 /* NOTE: must be first condition checked -
944 * to verify DCC bit is cleared in any case!
946 if (additional_config
& NO_LFA_DUE_TO_DCC_MASK
) {
947 PMD_DRV_LOG(DEBUG
, "No LFA due to DCC flap after clp exit");
948 REG_WR(sc
, params
->lfa_base
+
949 offsetof(struct shmem_lfa
, additional_config
),
950 additional_config
& ~NO_LFA_DUE_TO_DCC_MASK
);
951 return LFA_DCC_LFA_DISABLED
;
954 /* Verify that link is up */
955 link_status
= REG_RD(sc
, params
->shmem_base
+
956 offsetof(struct shmem_region
,
957 port_mb
[params
->port
].link_status
));
958 if (!(link_status
& LINK_STATUS_LINK_UP
))
959 return LFA_LINK_DOWN
;
961 /* if loaded after BOOT from SAN, don't flap the link in any case and
962 * rely on link set by preboot driver
964 if (params
->feature_config_flags
& ELINK_FEATURE_CONFIG_BOOT_FROM_SAN
)
967 /* Verify that loopback mode is not set */
968 if (params
->loopback_mode
)
969 return LFA_LOOPBACK_ENABLED
;
971 /* Verify that MFW supports LFA */
972 if (!params
->lfa_base
)
973 return LFA_MFW_IS_TOO_OLD
;
975 if (params
->num_phys
== 3) {
977 lfa_mask
= 0xffffffff;
984 saved_val
= REG_RD(sc
, params
->lfa_base
+
985 offsetof(struct shmem_lfa
, req_duplex
));
986 req_val
= params
->req_duplex
[0] | (params
->req_duplex
[1] << 16);
987 if ((saved_val
& lfa_mask
) != (req_val
& lfa_mask
)) {
988 PMD_DRV_LOG(INFO
, "Duplex mismatch %x vs. %x",
989 (saved_val
& lfa_mask
), (req_val
& lfa_mask
));
990 return LFA_DUPLEX_MISMATCH
;
992 /* Compare Flow Control */
993 saved_val
= REG_RD(sc
, params
->lfa_base
+
994 offsetof(struct shmem_lfa
, req_flow_ctrl
));
995 req_val
= params
->req_flow_ctrl
[0] | (params
->req_flow_ctrl
[1] << 16);
996 if ((saved_val
& lfa_mask
) != (req_val
& lfa_mask
)) {
997 PMD_DRV_LOG(DEBUG
, "Flow control mismatch %x vs. %x",
998 (saved_val
& lfa_mask
), (req_val
& lfa_mask
));
999 return LFA_FLOW_CTRL_MISMATCH
;
1001 /* Compare Link Speed */
1002 saved_val
= REG_RD(sc
, params
->lfa_base
+
1003 offsetof(struct shmem_lfa
, req_line_speed
));
1004 req_val
= params
->req_line_speed
[0] | (params
->req_line_speed
[1] << 16);
1005 if ((saved_val
& lfa_mask
) != (req_val
& lfa_mask
)) {
1006 PMD_DRV_LOG(DEBUG
, "Link speed mismatch %x vs. %x",
1007 (saved_val
& lfa_mask
), (req_val
& lfa_mask
));
1008 return LFA_LINK_SPEED_MISMATCH
;
1011 for (cfg_idx
= 0; cfg_idx
< cfg_size
; cfg_idx
++) {
1012 cur_speed_cap_mask
= REG_RD(sc
, params
->lfa_base
+
1013 offsetof(struct shmem_lfa
,
1014 speed_cap_mask
[cfg_idx
]));
1016 if (cur_speed_cap_mask
!= params
->speed_cap_mask
[cfg_idx
]) {
1017 PMD_DRV_LOG(DEBUG
, "Speed Cap mismatch %x vs. %x",
1019 params
->speed_cap_mask
[cfg_idx
]);
1020 return LFA_SPEED_CAP_MISMATCH
;
1024 cur_req_fc_auto_adv
=
1025 REG_RD(sc
, params
->lfa_base
+
1026 offsetof(struct shmem_lfa
, additional_config
)) &
1027 REQ_FC_AUTO_ADV_MASK
;
1029 if ((uint16_t) cur_req_fc_auto_adv
!= params
->req_fc_auto_adv
) {
1030 PMD_DRV_LOG(DEBUG
, "Flow Ctrl AN mismatch %x vs. %x",
1031 cur_req_fc_auto_adv
, params
->req_fc_auto_adv
);
1032 return LFA_FLOW_CTRL_MISMATCH
;
1035 eee_status
= REG_RD(sc
, params
->shmem2_base
+
1036 offsetof(struct shmem2_region
,
1037 eee_status
[params
->port
]));
1039 if (((eee_status
& SHMEM_EEE_LPI_REQUESTED_BIT
) ^
1040 (params
->eee_mode
& ELINK_EEE_MODE_ENABLE_LPI
)) ||
1041 ((eee_status
& SHMEM_EEE_REQUESTED_BIT
) ^
1042 (params
->eee_mode
& ELINK_EEE_MODE_ADV_LPI
))) {
1043 PMD_DRV_LOG(DEBUG
, "EEE mismatch %x vs. %x", params
->eee_mode
,
1045 return LFA_EEE_MISMATCH
;
1048 /* LFA conditions are met */
1052 /******************************************************************/
1053 /* EPIO/GPIO section */
1054 /******************************************************************/
1055 static void elink_get_epio(struct bnx2x_softc
*sc
, uint32_t epio_pin
,
1058 uint32_t epio_mask
, gp_oenable
;
1061 if (epio_pin
> 31) {
1062 PMD_DRV_LOG(DEBUG
, "Invalid EPIO pin %d to get", epio_pin
);
1066 epio_mask
= 1 << epio_pin
;
1067 /* Set this EPIO to output */
1068 gp_oenable
= REG_RD(sc
, MCP_REG_MCPR_GP_OENABLE
);
1069 REG_WR(sc
, MCP_REG_MCPR_GP_OENABLE
, gp_oenable
& ~epio_mask
);
1071 *en
= (REG_RD(sc
, MCP_REG_MCPR_GP_INPUTS
) & epio_mask
) >> epio_pin
;
1074 static void elink_set_epio(struct bnx2x_softc
*sc
, uint32_t epio_pin
, uint32_t en
)
1076 uint32_t epio_mask
, gp_output
, gp_oenable
;
1079 if (epio_pin
> 31) {
1080 PMD_DRV_LOG(DEBUG
, "Invalid EPIO pin %d to set", epio_pin
);
1083 PMD_DRV_LOG(DEBUG
, "Setting EPIO pin %d to %d", epio_pin
, en
);
1084 epio_mask
= 1 << epio_pin
;
1085 /* Set this EPIO to output */
1086 gp_output
= REG_RD(sc
, MCP_REG_MCPR_GP_OUTPUTS
);
1088 gp_output
|= epio_mask
;
1090 gp_output
&= ~epio_mask
;
1092 REG_WR(sc
, MCP_REG_MCPR_GP_OUTPUTS
, gp_output
);
1094 /* Set the value for this EPIO */
1095 gp_oenable
= REG_RD(sc
, MCP_REG_MCPR_GP_OENABLE
);
1096 REG_WR(sc
, MCP_REG_MCPR_GP_OENABLE
, gp_oenable
| epio_mask
);
1099 static void elink_set_cfg_pin(struct bnx2x_softc
*sc
, uint32_t pin_cfg
,
1102 if (pin_cfg
== PIN_CFG_NA
)
1104 if (pin_cfg
>= PIN_CFG_EPIO0
) {
1105 elink_set_epio(sc
, pin_cfg
- PIN_CFG_EPIO0
, val
);
1107 uint8_t gpio_num
= (pin_cfg
- PIN_CFG_GPIO0_P0
) & 0x3;
1108 uint8_t gpio_port
= (pin_cfg
- PIN_CFG_GPIO0_P0
) >> 2;
1109 elink_cb_gpio_write(sc
, gpio_num
, (uint8_t) val
, gpio_port
);
1113 static uint32_t elink_get_cfg_pin(struct bnx2x_softc
*sc
, uint32_t pin_cfg
,
1116 if (pin_cfg
== PIN_CFG_NA
)
1117 return ELINK_STATUS_ERROR
;
1118 if (pin_cfg
>= PIN_CFG_EPIO0
) {
1119 elink_get_epio(sc
, pin_cfg
- PIN_CFG_EPIO0
, val
);
1121 uint8_t gpio_num
= (pin_cfg
- PIN_CFG_GPIO0_P0
) & 0x3;
1122 uint8_t gpio_port
= (pin_cfg
- PIN_CFG_GPIO0_P0
) >> 2;
1123 *val
= elink_cb_gpio_read(sc
, gpio_num
, gpio_port
);
1125 return ELINK_STATUS_OK
;
1129 /******************************************************************/
1131 /******************************************************************/
1132 static void elink_update_pfc_xmac(struct elink_params
*params
,
1133 struct elink_vars
*vars
)
1135 struct bnx2x_softc
*sc
= params
->sc
;
1137 uint32_t pause_val
, pfc0_val
, pfc1_val
;
1139 /* XMAC base adrr */
1140 xmac_base
= (params
->port
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
1142 /* Initialize pause and pfc registers */
1143 pause_val
= 0x18000;
1144 pfc0_val
= 0xFFFF8000;
1147 /* No PFC support */
1148 if (!(params
->feature_config_flags
& ELINK_FEATURE_CONFIG_PFC_ENABLED
)) {
1150 /* RX flow control - Process pause frame in receive direction
1152 if (vars
->flow_ctrl
& ELINK_FLOW_CTRL_RX
)
1153 pause_val
|= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN
;
1155 /* TX flow control - Send pause packet when buffer is full */
1156 if (vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
)
1157 pause_val
|= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN
;
1158 } else { /* PFC support */
1159 pfc1_val
|= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN
|
1160 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN
|
1161 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN
|
1162 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN
|
1163 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON
;
1164 /* Write pause and PFC registers */
1165 REG_WR(sc
, xmac_base
+ XMAC_REG_PAUSE_CTRL
, pause_val
);
1166 REG_WR(sc
, xmac_base
+ XMAC_REG_PFC_CTRL
, pfc0_val
);
1167 REG_WR(sc
, xmac_base
+ XMAC_REG_PFC_CTRL_HI
, pfc1_val
);
1168 pfc1_val
&= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON
;
1172 /* Write pause and PFC registers */
1173 REG_WR(sc
, xmac_base
+ XMAC_REG_PAUSE_CTRL
, pause_val
);
1174 REG_WR(sc
, xmac_base
+ XMAC_REG_PFC_CTRL
, pfc0_val
);
1175 REG_WR(sc
, xmac_base
+ XMAC_REG_PFC_CTRL_HI
, pfc1_val
);
1177 /* Set MAC address for source TX Pause/PFC frames */
1178 REG_WR(sc
, xmac_base
+ XMAC_REG_CTRL_SA_LO
,
1179 ((params
->mac_addr
[2] << 24) |
1180 (params
->mac_addr
[3] << 16) |
1181 (params
->mac_addr
[4] << 8) | (params
->mac_addr
[5])));
1182 REG_WR(sc
, xmac_base
+ XMAC_REG_CTRL_SA_HI
,
1183 ((params
->mac_addr
[0] << 8) | (params
->mac_addr
[1])));
1188 /******************************************************************/
1189 /* MAC/PBF section */
1190 /******************************************************************/
1191 static void elink_set_mdio_clk(struct bnx2x_softc
*sc
, uint32_t emac_base
)
1193 uint32_t new_mode
, cur_mode
;
1195 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1196 * (a value of 49==0x31) and make sure that the AUTO poll is off
1198 cur_mode
= REG_RD(sc
, emac_base
+ EMAC_REG_EMAC_MDIO_MODE
);
1200 if (USES_WARPCORE(sc
))
1201 clc_cnt
= 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT
;
1203 clc_cnt
= 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT
;
1205 if (((cur_mode
& EMAC_MDIO_MODE_CLOCK_CNT
) == clc_cnt
) &&
1206 (cur_mode
& (EMAC_MDIO_MODE_CLAUSE_45
)))
1209 new_mode
= cur_mode
&
1210 ~(EMAC_MDIO_MODE_AUTO_POLL
| EMAC_MDIO_MODE_CLOCK_CNT
);
1211 new_mode
|= clc_cnt
;
1212 new_mode
|= (EMAC_MDIO_MODE_CLAUSE_45
);
1214 PMD_DRV_LOG(DEBUG
, "Changing emac_mode from 0x%x to 0x%x",
1215 cur_mode
, new_mode
);
1216 REG_WR(sc
, emac_base
+ EMAC_REG_EMAC_MDIO_MODE
, new_mode
);
1220 static void elink_set_mdio_emac_per_phy(struct bnx2x_softc
*sc
,
1221 struct elink_params
*params
)
1224 /* Set mdio clock per phy */
1225 for (phy_index
= ELINK_INT_PHY
; phy_index
< params
->num_phys
;
1227 elink_set_mdio_clk(sc
, params
->phy
[phy_index
].mdio_ctrl
);
1230 static uint8_t elink_is_4_port_mode(struct bnx2x_softc
*sc
)
1232 uint32_t port4mode_ovwr_val
;
1233 /* Check 4-port override enabled */
1234 port4mode_ovwr_val
= REG_RD(sc
, MISC_REG_PORT4MODE_EN_OVWR
);
1235 if (port4mode_ovwr_val
& (1 << 0)) {
1236 /* Return 4-port mode override value */
1237 return (port4mode_ovwr_val
& (1 << 1)) == (1 << 1);
1239 /* Return 4-port mode from input pin */
1240 return (uint8_t) REG_RD(sc
, MISC_REG_PORT4MODE_EN
);
1243 static void elink_emac_init(struct elink_params
*params
)
1245 /* reset and unreset the emac core */
1246 struct bnx2x_softc
*sc
= params
->sc
;
1247 uint8_t port
= params
->port
;
1248 uint32_t emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
1252 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
1253 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
<< port
));
1255 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
1256 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
<< port
));
1258 /* init emac - use read-modify-write */
1259 /* self clear reset */
1260 val
= REG_RD(sc
, emac_base
+ EMAC_REG_EMAC_MODE
);
1261 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_MODE
,
1262 (val
| EMAC_MODE_RESET
));
1266 val
= REG_RD(sc
, emac_base
+ EMAC_REG_EMAC_MODE
);
1267 PMD_DRV_LOG(DEBUG
, "EMAC reset reg is %u", val
);
1269 PMD_DRV_LOG(DEBUG
, "EMAC timeout!");
1273 } while (val
& EMAC_MODE_RESET
);
1275 elink_set_mdio_emac_per_phy(sc
, params
);
1276 /* Set mac address */
1277 val
= ((params
->mac_addr
[0] << 8) | params
->mac_addr
[1]);
1278 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_MAC_MATCH
, val
);
1280 val
= ((params
->mac_addr
[2] << 24) |
1281 (params
->mac_addr
[3] << 16) |
1282 (params
->mac_addr
[4] << 8) | params
->mac_addr
[5]);
1283 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_MAC_MATCH
+ 4, val
);
1286 static void elink_set_xumac_nig(struct elink_params
*params
,
1287 uint16_t tx_pause_en
, uint8_t enable
)
1289 struct bnx2x_softc
*sc
= params
->sc
;
1291 REG_WR(sc
, params
->port
? NIG_REG_P1_MAC_IN_EN
: NIG_REG_P0_MAC_IN_EN
,
1293 REG_WR(sc
, params
->port
? NIG_REG_P1_MAC_OUT_EN
: NIG_REG_P0_MAC_OUT_EN
,
1295 REG_WR(sc
, params
->port
? NIG_REG_P1_MAC_PAUSE_OUT_EN
:
1296 NIG_REG_P0_MAC_PAUSE_OUT_EN
, tx_pause_en
);
1299 static void elink_set_umac_rxtx(struct elink_params
*params
, uint8_t en
)
1301 uint32_t umac_base
= params
->port
? GRCBASE_UMAC1
: GRCBASE_UMAC0
;
1303 struct bnx2x_softc
*sc
= params
->sc
;
1304 if (!(REG_RD(sc
, MISC_REG_RESET_REG_2
) &
1305 (MISC_REGISTERS_RESET_REG_2_UMAC0
<< params
->port
)))
1307 val
= REG_RD(sc
, umac_base
+ UMAC_REG_COMMAND_CONFIG
);
1309 val
|= (UMAC_COMMAND_CONFIG_REG_TX_ENA
|
1310 UMAC_COMMAND_CONFIG_REG_RX_ENA
);
1312 val
&= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA
|
1313 UMAC_COMMAND_CONFIG_REG_RX_ENA
);
1314 /* Disable RX and TX */
1315 REG_WR(sc
, umac_base
+ UMAC_REG_COMMAND_CONFIG
, val
);
1318 static void elink_umac_enable(struct elink_params
*params
,
1319 struct elink_vars
*vars
, uint8_t lb
)
1322 uint32_t umac_base
= params
->port
? GRCBASE_UMAC1
: GRCBASE_UMAC0
;
1323 struct bnx2x_softc
*sc
= params
->sc
;
1325 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
1326 (MISC_REGISTERS_RESET_REG_2_UMAC0
<< params
->port
));
1329 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
1330 (MISC_REGISTERS_RESET_REG_2_UMAC0
<< params
->port
));
1332 PMD_DRV_LOG(DEBUG
, "enabling UMAC");
1334 /* This register opens the gate for the UMAC despite its name */
1335 REG_WR(sc
, NIG_REG_EGRESS_EMAC0_PORT
+ params
->port
* 4, 1);
1337 val
= UMAC_COMMAND_CONFIG_REG_PROMIS_EN
|
1338 UMAC_COMMAND_CONFIG_REG_PAD_EN
|
1339 UMAC_COMMAND_CONFIG_REG_SW_RESET
|
1340 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK
;
1341 switch (vars
->line_speed
) {
1342 case ELINK_SPEED_10
:
1345 case ELINK_SPEED_100
:
1348 case ELINK_SPEED_1000
:
1351 case ELINK_SPEED_2500
:
1355 PMD_DRV_LOG(DEBUG
, "Invalid speed for UMAC %d",
1359 if (!(vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
))
1360 val
|= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE
;
1362 if (!(vars
->flow_ctrl
& ELINK_FLOW_CTRL_RX
))
1363 val
|= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE
;
1365 if (vars
->duplex
== DUPLEX_HALF
)
1366 val
|= UMAC_COMMAND_CONFIG_REG_HD_ENA
;
1368 REG_WR(sc
, umac_base
+ UMAC_REG_COMMAND_CONFIG
, val
);
1371 /* Configure UMAC for EEE */
1372 if (vars
->eee_status
& SHMEM_EEE_ADV_STATUS_MASK
) {
1373 PMD_DRV_LOG(DEBUG
, "configured UMAC for EEE");
1374 REG_WR(sc
, umac_base
+ UMAC_REG_UMAC_EEE_CTRL
,
1375 UMAC_UMAC_EEE_CTRL_REG_EEE_EN
);
1376 REG_WR(sc
, umac_base
+ UMAC_REG_EEE_WAKE_TIMER
, 0x11);
1378 REG_WR(sc
, umac_base
+ UMAC_REG_UMAC_EEE_CTRL
, 0x0);
1381 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1382 REG_WR(sc
, umac_base
+ UMAC_REG_MAC_ADDR0
,
1383 ((params
->mac_addr
[2] << 24) |
1384 (params
->mac_addr
[3] << 16) |
1385 (params
->mac_addr
[4] << 8) | (params
->mac_addr
[5])));
1386 REG_WR(sc
, umac_base
+ UMAC_REG_MAC_ADDR1
,
1387 ((params
->mac_addr
[0] << 8) | (params
->mac_addr
[1])));
1389 /* Enable RX and TX */
1390 val
&= ~UMAC_COMMAND_CONFIG_REG_PAD_EN
;
1391 val
|= UMAC_COMMAND_CONFIG_REG_TX_ENA
| UMAC_COMMAND_CONFIG_REG_RX_ENA
;
1392 REG_WR(sc
, umac_base
+ UMAC_REG_COMMAND_CONFIG
, val
);
1395 /* Remove SW Reset */
1396 val
&= ~UMAC_COMMAND_CONFIG_REG_SW_RESET
;
1398 /* Check loopback mode */
1400 val
|= UMAC_COMMAND_CONFIG_REG_LOOP_ENA
;
1401 REG_WR(sc
, umac_base
+ UMAC_REG_COMMAND_CONFIG
, val
);
1403 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1404 * length used by the MAC receive logic to check frames.
1406 REG_WR(sc
, umac_base
+ UMAC_REG_MAXFR
, 0x2710);
1407 elink_set_xumac_nig(params
,
1408 ((vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
) != 0), 1);
1409 vars
->mac_type
= ELINK_MAC_TYPE_UMAC
;
1413 /* Define the XMAC mode */
1414 static void elink_xmac_init(struct elink_params
*params
, uint32_t max_speed
)
1416 struct bnx2x_softc
*sc
= params
->sc
;
1417 uint32_t is_port4mode
= elink_is_4_port_mode(sc
);
1419 /* In 4-port mode, need to set the mode only once, so if XMAC is
1420 * already out of reset, it means the mode has already been set,
1421 * and it must not* reset the XMAC again, since it controls both
1425 if (((CHIP_NUM(sc
) == CHIP_NUM_57840_4_10
) ||
1426 (CHIP_NUM(sc
) == CHIP_NUM_57840_2_20
) ||
1427 (CHIP_NUM(sc
) == CHIP_NUM_57840_OBS
)) &&
1429 (REG_RD(sc
, MISC_REG_RESET_REG_2
) &
1430 MISC_REGISTERS_RESET_REG_2_XMAC
)) {
1431 PMD_DRV_LOG(DEBUG
, "XMAC already out of reset in 4-port mode");
1436 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
1437 MISC_REGISTERS_RESET_REG_2_XMAC
);
1440 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
1441 MISC_REGISTERS_RESET_REG_2_XMAC
);
1443 PMD_DRV_LOG(DEBUG
, "Init XMAC to 2 ports x 10G per path");
1445 /* Set the number of ports on the system side to up to 2 */
1446 REG_WR(sc
, MISC_REG_XMAC_CORE_PORT_MODE
, 1);
1448 /* Set the number of ports on the Warp Core to 10G */
1449 REG_WR(sc
, MISC_REG_XMAC_PHY_PORT_MODE
, 3);
1451 /* Set the number of ports on the system side to 1 */
1452 REG_WR(sc
, MISC_REG_XMAC_CORE_PORT_MODE
, 0);
1453 if (max_speed
== ELINK_SPEED_10000
) {
1455 "Init XMAC to 10G x 1 port per path");
1456 /* Set the number of ports on the Warp Core to 10G */
1457 REG_WR(sc
, MISC_REG_XMAC_PHY_PORT_MODE
, 3);
1460 "Init XMAC to 20G x 2 ports per path");
1461 /* Set the number of ports on the Warp Core to 20G */
1462 REG_WR(sc
, MISC_REG_XMAC_PHY_PORT_MODE
, 1);
1466 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
1467 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT
);
1470 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
1471 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT
);
1475 static void elink_set_xmac_rxtx(struct elink_params
*params
, uint8_t en
)
1477 uint8_t port
= params
->port
;
1478 struct bnx2x_softc
*sc
= params
->sc
;
1479 uint32_t pfc_ctrl
, xmac_base
= (port
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
1482 if (REG_RD(sc
, MISC_REG_RESET_REG_2
) & MISC_REGISTERS_RESET_REG_2_XMAC
) {
1483 /* Send an indication to change the state in the NIG back to XON
1484 * Clearing this bit enables the next set of this bit to get
1487 pfc_ctrl
= REG_RD(sc
, xmac_base
+ XMAC_REG_PFC_CTRL_HI
);
1488 REG_WR(sc
, xmac_base
+ XMAC_REG_PFC_CTRL_HI
,
1489 (pfc_ctrl
& ~(1 << 1)));
1490 REG_WR(sc
, xmac_base
+ XMAC_REG_PFC_CTRL_HI
,
1491 (pfc_ctrl
| (1 << 1)));
1492 PMD_DRV_LOG(DEBUG
, "Disable XMAC on port %x", port
);
1493 val
= REG_RD(sc
, xmac_base
+ XMAC_REG_CTRL
);
1495 val
|= (XMAC_CTRL_REG_TX_EN
| XMAC_CTRL_REG_RX_EN
);
1497 val
&= ~(XMAC_CTRL_REG_TX_EN
| XMAC_CTRL_REG_RX_EN
);
1498 REG_WR(sc
, xmac_base
+ XMAC_REG_CTRL
, val
);
1502 static elink_status_t
elink_xmac_enable(struct elink_params
*params
,
1503 struct elink_vars
*vars
, uint8_t lb
)
1505 uint32_t val
, xmac_base
;
1506 struct bnx2x_softc
*sc
= params
->sc
;
1507 PMD_DRV_LOG(DEBUG
, "enabling XMAC");
1509 xmac_base
= (params
->port
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
1511 elink_xmac_init(params
, vars
->line_speed
);
1513 /* This register determines on which events the MAC will assert
1514 * error on the i/f to the NIG along w/ EOP.
1517 /* This register tells the NIG whether to send traffic to UMAC
1520 REG_WR(sc
, NIG_REG_EGRESS_EMAC0_PORT
+ params
->port
* 4, 0);
1522 /* When XMAC is in XLGMII mode, disable sending idles for fault
1525 if (!(params
->phy
[ELINK_INT_PHY
].flags
& ELINK_FLAGS_TX_ERROR_CHECK
)) {
1526 REG_WR(sc
, xmac_base
+ XMAC_REG_RX_LSS_CTRL
,
1527 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE
|
1528 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE
));
1529 REG_WR(sc
, xmac_base
+ XMAC_REG_CLEAR_RX_LSS_STATUS
, 0);
1530 REG_WR(sc
, xmac_base
+ XMAC_REG_CLEAR_RX_LSS_STATUS
,
1531 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS
|
1532 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS
);
1534 /* Set Max packet size */
1535 REG_WR(sc
, xmac_base
+ XMAC_REG_RX_MAX_SIZE
, 0x2710);
1537 /* CRC append for Tx packets */
1538 REG_WR(sc
, xmac_base
+ XMAC_REG_TX_CTRL
, 0xC800);
1541 elink_update_pfc_xmac(params
, vars
);
1543 if (vars
->eee_status
& SHMEM_EEE_ADV_STATUS_MASK
) {
1544 PMD_DRV_LOG(DEBUG
, "Setting XMAC for EEE");
1545 REG_WR(sc
, xmac_base
+ XMAC_REG_EEE_TIMERS_HI
, 0x1380008);
1546 REG_WR(sc
, xmac_base
+ XMAC_REG_EEE_CTRL
, 0x1);
1548 REG_WR(sc
, xmac_base
+ XMAC_REG_EEE_CTRL
, 0x0);
1551 /* Enable TX and RX */
1552 val
= XMAC_CTRL_REG_TX_EN
| XMAC_CTRL_REG_RX_EN
;
1554 /* Set MAC in XLGMII mode for dual-mode */
1555 if ((vars
->line_speed
== ELINK_SPEED_20000
) &&
1556 (params
->phy
[ELINK_INT_PHY
].supported
&
1557 ELINK_SUPPORTED_20000baseKR2_Full
))
1558 val
|= XMAC_CTRL_REG_XLGMII_ALIGN_ENB
;
1560 /* Check loopback mode */
1562 val
|= XMAC_CTRL_REG_LINE_LOCAL_LPBK
;
1563 REG_WR(sc
, xmac_base
+ XMAC_REG_CTRL
, val
);
1564 elink_set_xumac_nig(params
,
1565 ((vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
) != 0), 1);
1567 vars
->mac_type
= ELINK_MAC_TYPE_XMAC
;
1569 return ELINK_STATUS_OK
;
1572 static elink_status_t
elink_emac_enable(struct elink_params
*params
,
1573 struct elink_vars
*vars
, uint8_t lb
)
1575 struct bnx2x_softc
*sc
= params
->sc
;
1576 uint8_t port
= params
->port
;
1577 uint32_t emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
1580 PMD_DRV_LOG(DEBUG
, "enabling EMAC");
1583 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
1584 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
1586 /* enable emac and not bmac */
1587 REG_WR(sc
, NIG_REG_EGRESS_EMAC0_PORT
+ port
* 4, 1);
1589 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
1590 uint32_t ser_lane
= ((params
->lane_config
&
1591 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
1592 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
1594 PMD_DRV_LOG(DEBUG
, "XGXS");
1595 /* select the master lanes (out of 0-3) */
1596 REG_WR(sc
, NIG_REG_XGXS_LANE_SEL_P0
+ port
* 4, ser_lane
);
1598 REG_WR(sc
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
* 4, 1);
1600 } else { /* SerDes */
1601 PMD_DRV_LOG(DEBUG
, "SerDes");
1603 REG_WR(sc
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
* 4, 0);
1606 elink_bits_en(sc
, emac_base
+ EMAC_REG_EMAC_RX_MODE
,
1607 EMAC_RX_MODE_RESET
);
1608 elink_bits_en(sc
, emac_base
+ EMAC_REG_EMAC_TX_MODE
,
1609 EMAC_TX_MODE_RESET
);
1611 /* pause enable/disable */
1612 elink_bits_dis(sc
, emac_base
+ EMAC_REG_EMAC_RX_MODE
,
1613 EMAC_RX_MODE_FLOW_EN
);
1615 elink_bits_dis(sc
, emac_base
+ EMAC_REG_EMAC_TX_MODE
,
1616 (EMAC_TX_MODE_EXT_PAUSE_EN
|
1617 EMAC_TX_MODE_FLOW_EN
));
1618 if (!(params
->feature_config_flags
&
1619 ELINK_FEATURE_CONFIG_PFC_ENABLED
)) {
1620 if (vars
->flow_ctrl
& ELINK_FLOW_CTRL_RX
)
1621 elink_bits_en(sc
, emac_base
+
1622 EMAC_REG_EMAC_RX_MODE
,
1623 EMAC_RX_MODE_FLOW_EN
);
1625 if (vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
)
1626 elink_bits_en(sc
, emac_base
+
1627 EMAC_REG_EMAC_TX_MODE
,
1628 (EMAC_TX_MODE_EXT_PAUSE_EN
|
1629 EMAC_TX_MODE_FLOW_EN
));
1631 elink_bits_en(sc
, emac_base
+ EMAC_REG_EMAC_TX_MODE
,
1632 EMAC_TX_MODE_FLOW_EN
);
1634 /* KEEP_VLAN_TAG, promiscuous */
1635 val
= REG_RD(sc
, emac_base
+ EMAC_REG_EMAC_RX_MODE
);
1636 val
|= EMAC_RX_MODE_KEEP_VLAN_TAG
| EMAC_RX_MODE_PROMISCUOUS
;
1638 /* Setting this bit causes MAC control frames (except for pause
1639 * frames) to be passed on for processing. This setting has no
1640 * affect on the operation of the pause frames. This bit effects
1641 * all packets regardless of RX Parser packet sorting logic.
1642 * Turn the PFC off to make sure we are in Xon state before
1645 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_RX_PFC_MODE
, 0);
1646 if (params
->feature_config_flags
& ELINK_FEATURE_CONFIG_PFC_ENABLED
) {
1647 PMD_DRV_LOG(DEBUG
, "PFC is enabled");
1648 /* Enable PFC again */
1649 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_RX_PFC_MODE
,
1650 EMAC_REG_RX_PFC_MODE_RX_EN
|
1651 EMAC_REG_RX_PFC_MODE_TX_EN
|
1652 EMAC_REG_RX_PFC_MODE_PRIORITIES
);
1654 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_RX_PFC_PARAM
,
1656 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT
) |
1658 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT
)));
1659 val
|= EMAC_RX_MODE_KEEP_MAC_CONTROL
;
1661 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_RX_MODE
, val
);
1664 val
= REG_RD(sc
, emac_base
+ EMAC_REG_EMAC_MODE
);
1669 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_MODE
, val
);
1672 REG_WR(sc
, NIG_REG_NIG_EMAC0_EN
+ port
* 4, 1);
1674 /* Enable emac for jumbo packets */
1675 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_RX_MTU_SIZE
,
1676 (EMAC_RX_MTU_SIZE_JUMBO_ENA
|
1677 (ELINK_ETH_MAX_JUMBO_PACKET_SIZE
+
1678 ELINK_ETH_OVREHEAD
)));
1681 REG_WR(sc
, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC
+ port
* 4, 0x1);
1683 /* Disable the NIG in/out to the bmac */
1684 REG_WR(sc
, NIG_REG_BMAC0_IN_EN
+ port
* 4, 0x0);
1685 REG_WR(sc
, NIG_REG_BMAC0_PAUSE_OUT_EN
+ port
* 4, 0x0);
1686 REG_WR(sc
, NIG_REG_BMAC0_OUT_EN
+ port
* 4, 0x0);
1688 /* Enable the NIG in/out to the emac */
1689 REG_WR(sc
, NIG_REG_EMAC0_IN_EN
+ port
* 4, 0x1);
1691 if ((params
->feature_config_flags
&
1692 ELINK_FEATURE_CONFIG_PFC_ENABLED
) ||
1693 (vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
))
1696 REG_WR(sc
, NIG_REG_EMAC0_PAUSE_OUT_EN
+ port
* 4, val
);
1697 REG_WR(sc
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
* 4, 0x1);
1699 REG_WR(sc
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
* 4, 0x0);
1701 vars
->mac_type
= ELINK_MAC_TYPE_EMAC
;
1702 return ELINK_STATUS_OK
;
1705 static void elink_update_pfc_bmac1(struct elink_params
*params
,
1706 struct elink_vars
*vars
)
1708 uint32_t wb_data
[2];
1709 struct bnx2x_softc
*sc
= params
->sc
;
1710 uint32_t bmac_addr
= params
->port
? NIG_REG_INGRESS_BMAC1_MEM
:
1711 NIG_REG_INGRESS_BMAC0_MEM
;
1713 uint32_t val
= 0x14;
1714 if ((!(params
->feature_config_flags
&
1715 ELINK_FEATURE_CONFIG_PFC_ENABLED
)) &&
1716 (vars
->flow_ctrl
& ELINK_FLOW_CTRL_RX
))
1717 /* Enable BigMAC to react on received Pause packets */
1721 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_RX_CONTROL
, wb_data
, 2);
1725 if (!(params
->feature_config_flags
&
1726 ELINK_FEATURE_CONFIG_PFC_ENABLED
) &&
1727 (vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
))
1731 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_TX_CONTROL
, wb_data
, 2);
1734 static void elink_update_pfc_bmac2(struct elink_params
*params
,
1735 struct elink_vars
*vars
, uint8_t is_lb
)
1737 /* Set rx control: Strip CRC and enable BigMAC to relay
1738 * control packets to the system as well
1740 uint32_t wb_data
[2];
1741 struct bnx2x_softc
*sc
= params
->sc
;
1742 uint32_t bmac_addr
= params
->port
? NIG_REG_INGRESS_BMAC1_MEM
:
1743 NIG_REG_INGRESS_BMAC0_MEM
;
1744 uint32_t val
= 0x14;
1746 if ((!(params
->feature_config_flags
&
1747 ELINK_FEATURE_CONFIG_PFC_ENABLED
)) &&
1748 (vars
->flow_ctrl
& ELINK_FLOW_CTRL_RX
))
1749 /* Enable BigMAC to react on received Pause packets */
1753 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_RX_CONTROL
, wb_data
, 2);
1758 if (!(params
->feature_config_flags
&
1759 ELINK_FEATURE_CONFIG_PFC_ENABLED
) &&
1760 (vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
))
1764 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_TX_CONTROL
, wb_data
, 2);
1766 if (params
->feature_config_flags
& ELINK_FEATURE_CONFIG_PFC_ENABLED
) {
1767 PMD_DRV_LOG(DEBUG
, "PFC is enabled");
1768 /* Enable PFC RX & TX & STATS and set 8 COS */
1770 wb_data
[0] |= (1 << 0); /* RX */
1771 wb_data
[0] |= (1 << 1); /* TX */
1772 wb_data
[0] |= (1 << 2); /* Force initial Xon */
1773 wb_data
[0] |= (1 << 3); /* 8 cos */
1774 wb_data
[0] |= (1 << 5); /* STATS */
1776 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_PFC_CONTROL
,
1778 /* Clear the force Xon */
1779 wb_data
[0] &= ~(1 << 2);
1781 PMD_DRV_LOG(DEBUG
, "PFC is disabled");
1782 /* Disable PFC RX & TX & STATS and set 8 COS */
1787 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_PFC_CONTROL
, wb_data
, 2);
1789 /* Set Time (based unit is 512 bit time) between automatic
1790 * re-sending of PP packets amd enable automatic re-send of
1791 * Per-Priroity Packet as long as pp_gen is asserted and
1792 * pp_disable is low.
1795 if (params
->feature_config_flags
& ELINK_FEATURE_CONFIG_PFC_ENABLED
)
1796 val
|= (1 << 16); /* enable automatic re-send */
1800 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_TX_PAUSE_CONTROL
,
1804 val
= 0x3; /* Enable RX and TX */
1806 val
|= 0x4; /* Local loopback */
1807 PMD_DRV_LOG(DEBUG
, "enable bmac loopback");
1809 /* When PFC enabled, Pass pause frames towards the NIG. */
1810 if (params
->feature_config_flags
& ELINK_FEATURE_CONFIG_PFC_ENABLED
)
1811 val
|= ((1 << 6) | (1 << 5));
1815 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_BMAC_CONTROL
, wb_data
, 2);
1818 /******************************************************************************
1820 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
1821 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
1822 ******************************************************************************/
1823 static elink_status_t
elink_pfc_nig_rx_priority_mask(struct bnx2x_softc
*sc
,
1825 uint32_t priority_mask
,
1828 uint32_t nig_reg_rx_priority_mask_add
= 0;
1830 switch (cos_entry
) {
1832 nig_reg_rx_priority_mask_add
= (port
) ?
1833 NIG_REG_P1_RX_COS0_PRIORITY_MASK
:
1834 NIG_REG_P0_RX_COS0_PRIORITY_MASK
;
1837 nig_reg_rx_priority_mask_add
= (port
) ?
1838 NIG_REG_P1_RX_COS1_PRIORITY_MASK
:
1839 NIG_REG_P0_RX_COS1_PRIORITY_MASK
;
1842 nig_reg_rx_priority_mask_add
= (port
) ?
1843 NIG_REG_P1_RX_COS2_PRIORITY_MASK
:
1844 NIG_REG_P0_RX_COS2_PRIORITY_MASK
;
1848 return ELINK_STATUS_ERROR
;
1849 nig_reg_rx_priority_mask_add
= NIG_REG_P0_RX_COS3_PRIORITY_MASK
;
1853 return ELINK_STATUS_ERROR
;
1854 nig_reg_rx_priority_mask_add
= NIG_REG_P0_RX_COS4_PRIORITY_MASK
;
1858 return ELINK_STATUS_ERROR
;
1859 nig_reg_rx_priority_mask_add
= NIG_REG_P0_RX_COS5_PRIORITY_MASK
;
1863 REG_WR(sc
, nig_reg_rx_priority_mask_add
, priority_mask
);
1865 return ELINK_STATUS_OK
;
1868 static void elink_update_mng(struct elink_params
*params
, uint32_t link_status
)
1870 struct bnx2x_softc
*sc
= params
->sc
;
1872 REG_WR(sc
, params
->shmem_base
+
1873 offsetof(struct shmem_region
,
1874 port_mb
[params
->port
].link_status
), link_status
);
1877 static void elink_update_link_attr(struct elink_params
*params
,
1880 struct bnx2x_softc
*sc
= params
->sc
;
1882 if (SHMEM2_HAS(sc
, link_attr_sync
))
1883 REG_WR(sc
, params
->shmem2_base
+
1884 offsetof(struct shmem2_region
,
1885 link_attr_sync
[params
->port
]), link_attr
);
1888 static void elink_update_pfc_nig(struct elink_params
*params
,
1889 struct elink_nig_brb_pfc_port_params
1892 uint32_t xcm_mask
= 0, ppp_enable
= 0, pause_enable
= 0, llfc_out_en
=
1894 uint32_t llfc_enable
= 0, xcm_out_en
= 0, hwpfc_enable
= 0;
1895 uint32_t pkt_priority_to_cos
= 0;
1896 struct bnx2x_softc
*sc
= params
->sc
;
1897 uint8_t port
= params
->port
;
1899 int set_pfc
= params
->feature_config_flags
&
1900 ELINK_FEATURE_CONFIG_PFC_ENABLED
;
1901 PMD_DRV_LOG(DEBUG
, "updating pfc nig parameters");
1903 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
1904 * MAC control frames (that are not pause packets)
1905 * will be forwarded to the XCM.
1907 xcm_mask
= REG_RD(sc
, port
? NIG_REG_LLH1_XCM_MASK
:
1908 NIG_REG_LLH0_XCM_MASK
);
1909 /* NIG params will override non PFC params, since it's possible to
1910 * do transition from PFC to SAFC
1920 xcm_mask
&= ~(port
? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN
:
1921 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN
);
1926 llfc_out_en
= nig_params
->llfc_out_en
;
1927 llfc_enable
= nig_params
->llfc_enable
;
1928 pause_enable
= nig_params
->pause_enable
;
1929 } else /* Default non PFC mode - PAUSE */
1932 xcm_mask
|= (port
? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN
:
1933 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN
);
1938 REG_WR(sc
, port
? NIG_REG_BRB1_PAUSE_IN_EN
:
1939 NIG_REG_BRB0_PAUSE_IN_EN
, pause_enable
);
1940 REG_WR(sc
, port
? NIG_REG_LLFC_OUT_EN_1
:
1941 NIG_REG_LLFC_OUT_EN_0
, llfc_out_en
);
1942 REG_WR(sc
, port
? NIG_REG_LLFC_ENABLE_1
:
1943 NIG_REG_LLFC_ENABLE_0
, llfc_enable
);
1944 REG_WR(sc
, port
? NIG_REG_PAUSE_ENABLE_1
:
1945 NIG_REG_PAUSE_ENABLE_0
, pause_enable
);
1947 REG_WR(sc
, port
? NIG_REG_PPP_ENABLE_1
:
1948 NIG_REG_PPP_ENABLE_0
, ppp_enable
);
1950 REG_WR(sc
, port
? NIG_REG_LLH1_XCM_MASK
:
1951 NIG_REG_LLH0_XCM_MASK
, xcm_mask
);
1953 REG_WR(sc
, port
? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1
:
1954 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0
, 0x7);
1956 /* Output enable for RX_XCM # IF */
1957 REG_WR(sc
, port
? NIG_REG_XCM1_OUT_EN
:
1958 NIG_REG_XCM0_OUT_EN
, xcm_out_en
);
1960 /* HW PFC TX enable */
1961 REG_WR(sc
, port
? NIG_REG_P1_HWPFC_ENABLE
:
1962 NIG_REG_P0_HWPFC_ENABLE
, hwpfc_enable
);
1966 pkt_priority_to_cos
= nig_params
->pkt_priority_to_cos
;
1968 for (i
= 0; i
< nig_params
->num_of_rx_cos_priority_mask
; i
++)
1969 elink_pfc_nig_rx_priority_mask(sc
, i
,
1971 rx_cos_priority_mask
[i
],
1974 REG_WR(sc
, port
? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1
:
1975 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0
,
1976 nig_params
->llfc_high_priority_classes
);
1978 REG_WR(sc
, port
? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1
:
1979 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0
,
1980 nig_params
->llfc_low_priority_classes
);
1982 REG_WR(sc
, port
? NIG_REG_P1_PKT_PRIORITY_TO_COS
:
1983 NIG_REG_P0_PKT_PRIORITY_TO_COS
, pkt_priority_to_cos
);
1986 elink_status_t
elink_update_pfc(struct elink_params
*params
,
1987 struct elink_vars
*vars
,
1988 struct elink_nig_brb_pfc_port_params
1991 /* The PFC and pause are orthogonal to one another, meaning when
1992 * PFC is enabled, the pause are disabled, and when PFC is
1993 * disabled, pause are set according to the pause result.
1996 struct bnx2x_softc
*sc
= params
->sc
;
1997 elink_status_t elink_status
= ELINK_STATUS_OK
;
1998 uint8_t bmac_loopback
= (params
->loopback_mode
== ELINK_LOOPBACK_BMAC
);
2000 if (params
->feature_config_flags
& ELINK_FEATURE_CONFIG_PFC_ENABLED
)
2001 vars
->link_status
|= LINK_STATUS_PFC_ENABLED
;
2003 vars
->link_status
&= ~LINK_STATUS_PFC_ENABLED
;
2005 elink_update_mng(params
, vars
->link_status
);
2007 /* Update NIG params */
2008 elink_update_pfc_nig(params
, pfc_params
);
2011 return elink_status
;
2013 PMD_DRV_LOG(DEBUG
, "About to update PFC in BMAC");
2015 if (CHIP_IS_E3(sc
)) {
2016 if (vars
->mac_type
== ELINK_MAC_TYPE_XMAC
)
2017 elink_update_pfc_xmac(params
, vars
);
2019 val
= REG_RD(sc
, MISC_REG_RESET_REG_2
);
2021 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< params
->port
))
2023 PMD_DRV_LOG(DEBUG
, "About to update PFC in EMAC");
2024 elink_emac_enable(params
, vars
, 0);
2025 return elink_status
;
2028 elink_update_pfc_bmac2(params
, vars
, bmac_loopback
);
2030 elink_update_pfc_bmac1(params
, vars
);
2033 if ((params
->feature_config_flags
&
2034 ELINK_FEATURE_CONFIG_PFC_ENABLED
) ||
2035 (vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
))
2037 REG_WR(sc
, NIG_REG_BMAC0_PAUSE_OUT_EN
+ params
->port
* 4, val
);
2039 return elink_status
;
2042 static elink_status_t
elink_bmac1_enable(struct elink_params
*params
,
2043 struct elink_vars
*vars
, uint8_t is_lb
)
2045 struct bnx2x_softc
*sc
= params
->sc
;
2046 uint8_t port
= params
->port
;
2047 uint32_t bmac_addr
= port
? NIG_REG_INGRESS_BMAC1_MEM
:
2048 NIG_REG_INGRESS_BMAC0_MEM
;
2049 uint32_t wb_data
[2];
2052 PMD_DRV_LOG(DEBUG
, "Enabling BigMAC1");
2057 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_BMAC_XGXS_CONTROL
,
2061 wb_data
[0] = ((params
->mac_addr
[2] << 24) |
2062 (params
->mac_addr
[3] << 16) |
2063 (params
->mac_addr
[4] << 8) | params
->mac_addr
[5]);
2064 wb_data
[1] = ((params
->mac_addr
[0] << 8) | params
->mac_addr
[1]);
2065 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_TX_SOURCE_ADDR
, wb_data
, 2);
2071 PMD_DRV_LOG(DEBUG
, "enable bmac loopback");
2075 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_BMAC_CONTROL
, wb_data
, 2);
2078 wb_data
[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE
+ ELINK_ETH_OVREHEAD
;
2080 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_RX_MAX_SIZE
, wb_data
, 2);
2082 elink_update_pfc_bmac1(params
, vars
);
2085 wb_data
[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE
+ ELINK_ETH_OVREHEAD
;
2087 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_TX_MAX_SIZE
, wb_data
, 2);
2089 /* Set cnt max size */
2090 wb_data
[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE
+ ELINK_ETH_OVREHEAD
;
2092 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_CNT_MAX_SIZE
, wb_data
, 2);
2094 /* Configure SAFC */
2095 wb_data
[0] = 0x1000200;
2097 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_RX_LLFC_MSG_FLDS
,
2100 return ELINK_STATUS_OK
;
2103 static elink_status_t
elink_bmac2_enable(struct elink_params
*params
,
2104 struct elink_vars
*vars
, uint8_t is_lb
)
2106 struct bnx2x_softc
*sc
= params
->sc
;
2107 uint8_t port
= params
->port
;
2108 uint32_t bmac_addr
= port
? NIG_REG_INGRESS_BMAC1_MEM
:
2109 NIG_REG_INGRESS_BMAC0_MEM
;
2110 uint32_t wb_data
[2];
2112 PMD_DRV_LOG(DEBUG
, "Enabling BigMAC2");
2116 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_BMAC_CONTROL
, wb_data
, 2);
2119 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2122 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_BMAC_XGXS_CONTROL
,
2128 wb_data
[0] = ((params
->mac_addr
[2] << 24) |
2129 (params
->mac_addr
[3] << 16) |
2130 (params
->mac_addr
[4] << 8) | params
->mac_addr
[5]);
2131 wb_data
[1] = ((params
->mac_addr
[0] << 8) | params
->mac_addr
[1]);
2132 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_TX_SOURCE_ADDR
,
2137 /* Configure SAFC */
2138 wb_data
[0] = 0x1000200;
2140 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS
,
2145 wb_data
[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE
+ ELINK_ETH_OVREHEAD
;
2147 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_RX_MAX_SIZE
, wb_data
, 2);
2151 wb_data
[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE
+ ELINK_ETH_OVREHEAD
;
2153 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_TX_MAX_SIZE
, wb_data
, 2);
2155 /* Set cnt max size */
2156 wb_data
[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE
+ ELINK_ETH_OVREHEAD
- 2;
2158 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_CNT_MAX_SIZE
, wb_data
, 2);
2160 elink_update_pfc_bmac2(params
, vars
, is_lb
);
2162 return ELINK_STATUS_OK
;
2165 static elink_status_t
elink_bmac_enable(struct elink_params
*params
,
2166 struct elink_vars
*vars
,
2167 uint8_t is_lb
, uint8_t reset_bmac
)
2169 elink_status_t rc
= ELINK_STATUS_OK
;
2170 uint8_t port
= params
->port
;
2171 struct bnx2x_softc
*sc
= params
->sc
;
2173 /* Reset and unreset the BigMac */
2175 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
2176 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
2180 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
2181 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
2183 /* Enable access for bmac registers */
2184 REG_WR(sc
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
* 4, 0x1);
2186 /* Enable BMAC according to BMAC type */
2188 rc
= elink_bmac2_enable(params
, vars
, is_lb
);
2190 rc
= elink_bmac1_enable(params
, vars
, is_lb
);
2191 REG_WR(sc
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
* 4, 0x1);
2192 REG_WR(sc
, NIG_REG_XGXS_LANE_SEL_P0
+ port
* 4, 0x0);
2193 REG_WR(sc
, NIG_REG_EGRESS_EMAC0_PORT
+ port
* 4, 0x0);
2195 if ((params
->feature_config_flags
&
2196 ELINK_FEATURE_CONFIG_PFC_ENABLED
) ||
2197 (vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
))
2199 REG_WR(sc
, NIG_REG_BMAC0_PAUSE_OUT_EN
+ port
* 4, val
);
2200 REG_WR(sc
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
* 4, 0x0);
2201 REG_WR(sc
, NIG_REG_EMAC0_IN_EN
+ port
* 4, 0x0);
2202 REG_WR(sc
, NIG_REG_EMAC0_PAUSE_OUT_EN
+ port
* 4, 0x0);
2203 REG_WR(sc
, NIG_REG_BMAC0_IN_EN
+ port
* 4, 0x1);
2204 REG_WR(sc
, NIG_REG_BMAC0_OUT_EN
+ port
* 4, 0x1);
2206 vars
->mac_type
= ELINK_MAC_TYPE_BMAC
;
2210 static void elink_set_bmac_rx(struct bnx2x_softc
*sc
, uint8_t port
, uint8_t en
)
2212 uint32_t bmac_addr
= port
? NIG_REG_INGRESS_BMAC1_MEM
:
2213 NIG_REG_INGRESS_BMAC0_MEM
;
2214 uint32_t wb_data
[2];
2215 uint32_t nig_bmac_enable
=
2216 REG_RD(sc
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
* 4);
2219 bmac_addr
+= BIGMAC2_REGISTER_BMAC_CONTROL
;
2221 bmac_addr
+= BIGMAC_REGISTER_BMAC_CONTROL
;
2222 /* Only if the bmac is out of reset */
2223 if (REG_RD(sc
, MISC_REG_RESET_REG_2
) &
2224 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
) && nig_bmac_enable
) {
2225 /* Clear Rx Enable bit in BMAC_CONTROL register */
2226 REG_RD_DMAE(sc
, bmac_addr
, wb_data
, 2);
2228 wb_data
[0] |= ELINK_BMAC_CONTROL_RX_ENABLE
;
2230 wb_data
[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE
;
2231 REG_WR_DMAE(sc
, bmac_addr
, wb_data
, 2);
2236 static elink_status_t
elink_pbf_update(struct elink_params
*params
,
2237 uint32_t flow_ctrl
, uint32_t line_speed
)
2239 struct bnx2x_softc
*sc
= params
->sc
;
2240 uint8_t port
= params
->port
;
2241 uint32_t init_crd
, crd
;
2242 uint32_t count
= 1000;
2245 REG_WR(sc
, PBF_REG_DISABLE_NEW_TASK_PROC_P0
+ port
* 4, 0x1);
2247 /* Wait for init credit */
2248 init_crd
= REG_RD(sc
, PBF_REG_P0_INIT_CRD
+ port
* 4);
2249 crd
= REG_RD(sc
, PBF_REG_P0_CREDIT
+ port
* 8);
2250 PMD_DRV_LOG(DEBUG
, "init_crd 0x%x crd 0x%x", init_crd
, crd
);
2252 while ((init_crd
!= crd
) && count
) {
2254 crd
= REG_RD(sc
, PBF_REG_P0_CREDIT
+ port
* 8);
2257 crd
= REG_RD(sc
, PBF_REG_P0_CREDIT
+ port
* 8);
2258 if (init_crd
!= crd
) {
2259 PMD_DRV_LOG(DEBUG
, "BUG! init_crd 0x%x != crd 0x%x",
2261 return ELINK_STATUS_ERROR
;
2264 if (flow_ctrl
& ELINK_FLOW_CTRL_RX
||
2265 line_speed
== ELINK_SPEED_10
||
2266 line_speed
== ELINK_SPEED_100
||
2267 line_speed
== ELINK_SPEED_1000
|| line_speed
== ELINK_SPEED_2500
) {
2268 REG_WR(sc
, PBF_REG_P0_PAUSE_ENABLE
+ port
* 4, 1);
2269 /* Update threshold */
2270 REG_WR(sc
, PBF_REG_P0_ARB_THRSH
+ port
* 4, 0);
2271 /* Update init credit */
2272 init_crd
= 778; /* (800-18-4) */
2275 uint32_t thresh
= (ELINK_ETH_MAX_JUMBO_PACKET_SIZE
+
2276 ELINK_ETH_OVREHEAD
) / 16;
2277 REG_WR(sc
, PBF_REG_P0_PAUSE_ENABLE
+ port
* 4, 0);
2278 /* Update threshold */
2279 REG_WR(sc
, PBF_REG_P0_ARB_THRSH
+ port
* 4, thresh
);
2280 /* Update init credit */
2281 switch (line_speed
) {
2282 case ELINK_SPEED_10000
:
2283 init_crd
= thresh
+ 553 - 22;
2286 PMD_DRV_LOG(DEBUG
, "Invalid line_speed 0x%x",
2288 return ELINK_STATUS_ERROR
;
2291 REG_WR(sc
, PBF_REG_P0_INIT_CRD
+ port
* 4, init_crd
);
2292 PMD_DRV_LOG(DEBUG
, "PBF updated to speed %d credit %d",
2293 line_speed
, init_crd
);
2295 /* Probe the credit changes */
2296 REG_WR(sc
, PBF_REG_INIT_P0
+ port
* 4, 0x1);
2298 REG_WR(sc
, PBF_REG_INIT_P0
+ port
* 4, 0x0);
2301 REG_WR(sc
, PBF_REG_DISABLE_NEW_TASK_PROC_P0
+ port
* 4, 0x0);
2302 return ELINK_STATUS_OK
;
2306 * elink_get_emac_base - retrive emac base address
2308 * @bp: driver handle
2309 * @mdc_mdio_access: access type
2312 * This function selects the MDC/MDIO access (through emac0 or
2313 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2314 * phy has a default access mode, which could also be overridden
2315 * by nvram configuration. This parameter, whether this is the
2316 * default phy configuration, or the nvram overrun
2317 * configuration, is passed here as mdc_mdio_access and selects
2318 * the emac_base for the CL45 read/writes operations
2320 static uint32_t elink_get_emac_base(struct bnx2x_softc
*sc
,
2321 uint32_t mdc_mdio_access
, uint8_t port
)
2323 uint32_t emac_base
= 0;
2324 switch (mdc_mdio_access
) {
2325 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE
:
2327 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0
:
2328 if (REG_RD(sc
, NIG_REG_PORT_SWAP
))
2329 emac_base
= GRCBASE_EMAC1
;
2331 emac_base
= GRCBASE_EMAC0
;
2333 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1
:
2334 if (REG_RD(sc
, NIG_REG_PORT_SWAP
))
2335 emac_base
= GRCBASE_EMAC0
;
2337 emac_base
= GRCBASE_EMAC1
;
2339 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH
:
2340 emac_base
= (port
) ? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
2342 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED
:
2343 emac_base
= (port
) ? GRCBASE_EMAC0
: GRCBASE_EMAC1
;
2352 /******************************************************************/
2353 /* CL22 access functions */
2354 /******************************************************************/
2355 static elink_status_t
elink_cl22_write(struct bnx2x_softc
*sc
,
2356 struct elink_phy
*phy
,
2357 uint16_t reg
, uint16_t val
)
2361 elink_status_t rc
= ELINK_STATUS_OK
;
2362 /* Switch to CL22 */
2363 mode
= REG_RD(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
);
2364 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
,
2365 mode
& ~EMAC_MDIO_MODE_CLAUSE_45
);
2368 tmp
= ((phy
->addr
<< 21) | (reg
<< 16) | val
|
2369 EMAC_MDIO_COMM_COMMAND_WRITE_22
| EMAC_MDIO_COMM_START_BUSY
);
2370 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, tmp
);
2372 for (i
= 0; i
< 50; i
++) {
2375 tmp
= REG_RD(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
);
2376 if (!(tmp
& EMAC_MDIO_COMM_START_BUSY
)) {
2381 if (tmp
& EMAC_MDIO_COMM_START_BUSY
) {
2382 PMD_DRV_LOG(DEBUG
, "write phy register failed");
2383 rc
= ELINK_STATUS_TIMEOUT
;
2385 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
, mode
);
2389 static elink_status_t
elink_cl22_read(struct bnx2x_softc
*sc
,
2390 struct elink_phy
*phy
,
2391 uint16_t reg
, uint16_t * ret_val
)
2395 elink_status_t rc
= ELINK_STATUS_OK
;
2397 /* Switch to CL22 */
2398 mode
= REG_RD(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
);
2399 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
,
2400 mode
& ~EMAC_MDIO_MODE_CLAUSE_45
);
2403 val
= ((phy
->addr
<< 21) | (reg
<< 16) |
2404 EMAC_MDIO_COMM_COMMAND_READ_22
| EMAC_MDIO_COMM_START_BUSY
);
2405 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, val
);
2407 for (i
= 0; i
< 50; i
++) {
2410 val
= REG_RD(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
);
2411 if (!(val
& EMAC_MDIO_COMM_START_BUSY
)) {
2412 *ret_val
= (uint16_t) (val
& EMAC_MDIO_COMM_DATA
);
2417 if (val
& EMAC_MDIO_COMM_START_BUSY
) {
2418 PMD_DRV_LOG(DEBUG
, "read phy register failed");
2421 rc
= ELINK_STATUS_TIMEOUT
;
2423 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
, mode
);
2427 /******************************************************************/
2428 /* CL45 access functions */
2429 /******************************************************************/
2430 static elink_status_t
elink_cl45_read(struct bnx2x_softc
*sc
,
2431 struct elink_phy
*phy
, uint8_t devad
,
2432 uint16_t reg
, uint16_t * ret_val
)
2436 elink_status_t rc
= ELINK_STATUS_OK
;
2437 if (phy
->flags
& ELINK_FLAGS_MDC_MDIO_WA_G
) {
2438 elink_set_mdio_clk(sc
, phy
->mdio_ctrl
);
2441 if (phy
->flags
& ELINK_FLAGS_MDC_MDIO_WA_B0
)
2442 elink_bits_en(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_STATUS
,
2443 EMAC_MDIO_STATUS_10MB
);
2445 val
= ((phy
->addr
<< 21) | (devad
<< 16) | reg
|
2446 EMAC_MDIO_COMM_COMMAND_ADDRESS
| EMAC_MDIO_COMM_START_BUSY
);
2447 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, val
);
2449 for (i
= 0; i
< 50; i
++) {
2452 val
= REG_RD(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
);
2453 if (!(val
& EMAC_MDIO_COMM_START_BUSY
)) {
2458 if (val
& EMAC_MDIO_COMM_START_BUSY
) {
2459 PMD_DRV_LOG(DEBUG
, "read phy register failed");
2460 elink_cb_event_log(sc
, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT
); // "MDC/MDIO access timeout"
2463 rc
= ELINK_STATUS_TIMEOUT
;
2466 val
= ((phy
->addr
<< 21) | (devad
<< 16) |
2467 EMAC_MDIO_COMM_COMMAND_READ_45
|
2468 EMAC_MDIO_COMM_START_BUSY
);
2469 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, val
);
2471 for (i
= 0; i
< 50; i
++) {
2474 val
= REG_RD(sc
, phy
->mdio_ctrl
+
2475 EMAC_REG_EMAC_MDIO_COMM
);
2476 if (!(val
& EMAC_MDIO_COMM_START_BUSY
)) {
2478 (uint16_t) (val
& EMAC_MDIO_COMM_DATA
);
2482 if (val
& EMAC_MDIO_COMM_START_BUSY
) {
2483 PMD_DRV_LOG(DEBUG
, "read phy register failed");
2484 elink_cb_event_log(sc
, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT
); // "MDC/MDIO access timeout"
2487 rc
= ELINK_STATUS_TIMEOUT
;
2490 /* Work around for E3 A0 */
2491 if (phy
->flags
& ELINK_FLAGS_MDC_MDIO_WA
) {
2492 phy
->flags
^= ELINK_FLAGS_DUMMY_READ
;
2493 if (phy
->flags
& ELINK_FLAGS_DUMMY_READ
) {
2495 elink_cl45_read(sc
, phy
, devad
, 0xf, &temp_val
);
2499 if (phy
->flags
& ELINK_FLAGS_MDC_MDIO_WA_B0
)
2500 elink_bits_dis(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_STATUS
,
2501 EMAC_MDIO_STATUS_10MB
);
2505 static elink_status_t
elink_cl45_write(struct bnx2x_softc
*sc
,
2506 struct elink_phy
*phy
, uint8_t devad
,
2507 uint16_t reg
, uint16_t val
)
2511 elink_status_t rc
= ELINK_STATUS_OK
;
2512 if (phy
->flags
& ELINK_FLAGS_MDC_MDIO_WA_G
) {
2513 elink_set_mdio_clk(sc
, phy
->mdio_ctrl
);
2516 if (phy
->flags
& ELINK_FLAGS_MDC_MDIO_WA_B0
)
2517 elink_bits_en(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_STATUS
,
2518 EMAC_MDIO_STATUS_10MB
);
2521 tmp
= ((phy
->addr
<< 21) | (devad
<< 16) | reg
|
2522 EMAC_MDIO_COMM_COMMAND_ADDRESS
| EMAC_MDIO_COMM_START_BUSY
);
2523 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, tmp
);
2525 for (i
= 0; i
< 50; i
++) {
2528 tmp
= REG_RD(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
);
2529 if (!(tmp
& EMAC_MDIO_COMM_START_BUSY
)) {
2534 if (tmp
& EMAC_MDIO_COMM_START_BUSY
) {
2535 PMD_DRV_LOG(DEBUG
, "write phy register failed");
2536 elink_cb_event_log(sc
, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT
); // "MDC/MDIO access timeout"
2538 rc
= ELINK_STATUS_TIMEOUT
;
2541 tmp
= ((phy
->addr
<< 21) | (devad
<< 16) | val
|
2542 EMAC_MDIO_COMM_COMMAND_WRITE_45
|
2543 EMAC_MDIO_COMM_START_BUSY
);
2544 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, tmp
);
2546 for (i
= 0; i
< 50; i
++) {
2549 tmp
= REG_RD(sc
, phy
->mdio_ctrl
+
2550 EMAC_REG_EMAC_MDIO_COMM
);
2551 if (!(tmp
& EMAC_MDIO_COMM_START_BUSY
)) {
2556 if (tmp
& EMAC_MDIO_COMM_START_BUSY
) {
2557 PMD_DRV_LOG(DEBUG
, "write phy register failed");
2558 elink_cb_event_log(sc
, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT
); // "MDC/MDIO access timeout"
2560 rc
= ELINK_STATUS_TIMEOUT
;
2563 /* Work around for E3 A0 */
2564 if (phy
->flags
& ELINK_FLAGS_MDC_MDIO_WA
) {
2565 phy
->flags
^= ELINK_FLAGS_DUMMY_READ
;
2566 if (phy
->flags
& ELINK_FLAGS_DUMMY_READ
) {
2568 elink_cl45_read(sc
, phy
, devad
, 0xf, &temp_val
);
2571 if (phy
->flags
& ELINK_FLAGS_MDC_MDIO_WA_B0
)
2572 elink_bits_dis(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_STATUS
,
2573 EMAC_MDIO_STATUS_10MB
);
2577 /******************************************************************/
2579 /******************************************************************/
2580 static uint8_t elink_eee_has_cap(struct elink_params
*params
)
2582 struct bnx2x_softc
*sc
= params
->sc
;
2584 if (REG_RD(sc
, params
->shmem2_base
) <=
2585 offsetof(struct shmem2_region
, eee_status
[params
->port
]))
2591 static elink_status_t
elink_eee_nvram_to_time(uint32_t nvram_mode
,
2592 uint32_t * idle_timer
)
2594 switch (nvram_mode
) {
2595 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED
:
2596 *idle_timer
= ELINK_EEE_MODE_NVRAM_BALANCED_TIME
;
2598 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE
:
2599 *idle_timer
= ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME
;
2601 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY
:
2602 *idle_timer
= ELINK_EEE_MODE_NVRAM_LATENCY_TIME
;
2609 return ELINK_STATUS_OK
;
2612 static elink_status_t
elink_eee_time_to_nvram(uint32_t idle_timer
,
2613 uint32_t * nvram_mode
)
2615 switch (idle_timer
) {
2616 case ELINK_EEE_MODE_NVRAM_BALANCED_TIME
:
2617 *nvram_mode
= PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED
;
2619 case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME
:
2620 *nvram_mode
= PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE
;
2622 case ELINK_EEE_MODE_NVRAM_LATENCY_TIME
:
2623 *nvram_mode
= PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY
;
2626 *nvram_mode
= PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED
;
2630 return ELINK_STATUS_OK
;
2633 static uint32_t elink_eee_calc_timer(struct elink_params
*params
)
2635 uint32_t eee_mode
, eee_idle
;
2636 struct bnx2x_softc
*sc
= params
->sc
;
2638 if (params
->eee_mode
& ELINK_EEE_MODE_OVERRIDE_NVRAM
) {
2639 if (params
->eee_mode
& ELINK_EEE_MODE_OUTPUT_TIME
) {
2640 /* time value in eee_mode --> used directly */
2641 eee_idle
= params
->eee_mode
& ELINK_EEE_MODE_TIMER_MASK
;
2643 /* hsi value in eee_mode --> time */
2644 if (elink_eee_nvram_to_time(params
->eee_mode
&
2645 ELINK_EEE_MODE_NVRAM_MASK
,
2650 /* hsi values in nvram --> time */
2651 eee_mode
= ((REG_RD(sc
, params
->shmem_base
+
2652 offsetof(struct shmem_region
,
2653 dev_info
.port_feature_config
2655 port
].eee_power_mode
)) &
2656 PORT_FEAT_CFG_EEE_POWER_MODE_MASK
) >>
2657 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT
);
2659 if (elink_eee_nvram_to_time(eee_mode
, &eee_idle
))
2666 static elink_status_t
elink_eee_set_timers(struct elink_params
*params
,
2667 struct elink_vars
*vars
)
2669 uint32_t eee_idle
= 0, eee_mode
;
2670 struct bnx2x_softc
*sc
= params
->sc
;
2672 eee_idle
= elink_eee_calc_timer(params
);
2675 REG_WR(sc
, MISC_REG_CPMU_LP_IDLE_THR_P0
+ (params
->port
<< 2),
2677 } else if ((params
->eee_mode
& ELINK_EEE_MODE_ENABLE_LPI
) &&
2678 (params
->eee_mode
& ELINK_EEE_MODE_OVERRIDE_NVRAM
) &&
2679 (params
->eee_mode
& ELINK_EEE_MODE_OUTPUT_TIME
)) {
2680 PMD_DRV_LOG(DEBUG
, "Error: Tx LPI is enabled with timer 0");
2681 return ELINK_STATUS_ERROR
;
2684 vars
->eee_status
&= ~(SHMEM_EEE_TIMER_MASK
| SHMEM_EEE_TIME_OUTPUT_BIT
);
2685 if (params
->eee_mode
& ELINK_EEE_MODE_OUTPUT_TIME
) {
2686 /* eee_idle in 1u --> eee_status in 16u */
2688 vars
->eee_status
|= (eee_idle
& SHMEM_EEE_TIMER_MASK
) |
2689 SHMEM_EEE_TIME_OUTPUT_BIT
;
2691 if (elink_eee_time_to_nvram(eee_idle
, &eee_mode
))
2692 return ELINK_STATUS_ERROR
;
2693 vars
->eee_status
|= eee_mode
;
2696 return ELINK_STATUS_OK
;
2699 static elink_status_t
elink_eee_initial_config(struct elink_params
*params
,
2700 struct elink_vars
*vars
,
2703 vars
->eee_status
|= ((uint32_t) mode
) << SHMEM_EEE_SUPPORTED_SHIFT
;
2705 /* Propogate params' bits --> vars (for migration exposure) */
2706 if (params
->eee_mode
& ELINK_EEE_MODE_ENABLE_LPI
)
2707 vars
->eee_status
|= SHMEM_EEE_LPI_REQUESTED_BIT
;
2709 vars
->eee_status
&= ~SHMEM_EEE_LPI_REQUESTED_BIT
;
2711 if (params
->eee_mode
& ELINK_EEE_MODE_ADV_LPI
)
2712 vars
->eee_status
|= SHMEM_EEE_REQUESTED_BIT
;
2714 vars
->eee_status
&= ~SHMEM_EEE_REQUESTED_BIT
;
2716 return elink_eee_set_timers(params
, vars
);
2719 static elink_status_t
elink_eee_disable(struct elink_phy
*phy
,
2720 struct elink_params
*params
,
2721 struct elink_vars
*vars
)
2723 struct bnx2x_softc
*sc
= params
->sc
;
2725 /* Make Certain LPI is disabled */
2726 REG_WR(sc
, MISC_REG_CPMU_LP_FW_ENABLE_P0
+ (params
->port
<< 2), 0);
2728 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_EEE_ADV
, 0x0);
2730 vars
->eee_status
&= ~SHMEM_EEE_ADV_STATUS_MASK
;
2732 return ELINK_STATUS_OK
;
2735 static elink_status_t
elink_eee_advertise(struct elink_phy
*phy
,
2736 struct elink_params
*params
,
2737 struct elink_vars
*vars
,
2740 struct bnx2x_softc
*sc
= params
->sc
;
2743 /* Mask events preventing LPI generation */
2744 REG_WR(sc
, MISC_REG_CPMU_LP_MASK_EXT_P0
+ (params
->port
<< 2), 0xfc20);
2746 if (modes
& SHMEM_EEE_10G_ADV
) {
2747 PMD_DRV_LOG(DEBUG
, "Advertise 10GBase-T EEE");
2750 if (modes
& SHMEM_EEE_1G_ADV
) {
2751 PMD_DRV_LOG(DEBUG
, "Advertise 1GBase-T EEE");
2755 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_EEE_ADV
, val
);
2757 vars
->eee_status
&= ~SHMEM_EEE_ADV_STATUS_MASK
;
2758 vars
->eee_status
|= (modes
<< SHMEM_EEE_ADV_STATUS_SHIFT
);
2760 return ELINK_STATUS_OK
;
2763 static void elink_update_mng_eee(struct elink_params
*params
,
2764 uint32_t eee_status
)
2766 struct bnx2x_softc
*sc
= params
->sc
;
2768 if (elink_eee_has_cap(params
))
2769 REG_WR(sc
, params
->shmem2_base
+
2770 offsetof(struct shmem2_region
,
2771 eee_status
[params
->port
]), eee_status
);
2774 static void elink_eee_an_resolve(struct elink_phy
*phy
,
2775 struct elink_params
*params
,
2776 struct elink_vars
*vars
)
2778 struct bnx2x_softc
*sc
= params
->sc
;
2779 uint16_t adv
= 0, lp
= 0;
2780 uint32_t lp_adv
= 0;
2783 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_EEE_ADV
, &adv
);
2784 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_LP_EEE_ADV
, &lp
);
2787 lp_adv
|= SHMEM_EEE_100M_ADV
;
2789 if (vars
->line_speed
== ELINK_SPEED_100
)
2791 PMD_DRV_LOG(DEBUG
, "EEE negotiated - 100M");
2795 lp_adv
|= SHMEM_EEE_1G_ADV
;
2797 if (vars
->line_speed
== ELINK_SPEED_1000
)
2799 PMD_DRV_LOG(DEBUG
, "EEE negotiated - 1G");
2803 lp_adv
|= SHMEM_EEE_10G_ADV
;
2805 if (vars
->line_speed
== ELINK_SPEED_10000
)
2807 PMD_DRV_LOG(DEBUG
, "EEE negotiated - 10G");
2811 vars
->eee_status
&= ~SHMEM_EEE_LP_ADV_STATUS_MASK
;
2812 vars
->eee_status
|= (lp_adv
<< SHMEM_EEE_LP_ADV_STATUS_SHIFT
);
2815 PMD_DRV_LOG(DEBUG
, "EEE is active");
2816 vars
->eee_status
|= SHMEM_EEE_ACTIVE_BIT
;
2820 /******************************************************************/
2821 /* BSC access functions from E3 */
2822 /******************************************************************/
2823 static void elink_bsc_module_sel(struct elink_params
*params
)
2826 uint32_t board_cfg
, sfp_ctrl
;
2827 uint32_t i2c_pins
[I2C_SWITCH_WIDTH
], i2c_val
[I2C_SWITCH_WIDTH
];
2828 struct bnx2x_softc
*sc
= params
->sc
;
2829 uint8_t port
= params
->port
;
2830 /* Read I2C output PINs */
2831 board_cfg
= REG_RD(sc
, params
->shmem_base
+
2832 offsetof(struct shmem_region
,
2833 dev_info
.shared_hw_config
.board
));
2834 i2c_pins
[I2C_BSC0
] = board_cfg
& SHARED_HW_CFG_E3_I2C_MUX0_MASK
;
2835 i2c_pins
[I2C_BSC1
] = (board_cfg
& SHARED_HW_CFG_E3_I2C_MUX1_MASK
) >>
2836 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT
;
2838 /* Read I2C output value */
2839 sfp_ctrl
= REG_RD(sc
, params
->shmem_base
+
2840 offsetof(struct shmem_region
,
2841 dev_info
.port_hw_config
[port
].
2843 i2c_val
[I2C_BSC0
] = (sfp_ctrl
& PORT_HW_CFG_E3_I2C_MUX0_MASK
) > 0;
2844 i2c_val
[I2C_BSC1
] = (sfp_ctrl
& PORT_HW_CFG_E3_I2C_MUX1_MASK
) > 0;
2845 PMD_DRV_LOG(DEBUG
, "Setting BSC switch");
2846 for (idx
= 0; idx
< I2C_SWITCH_WIDTH
; idx
++)
2847 elink_set_cfg_pin(sc
, i2c_pins
[idx
], i2c_val
[idx
]);
2850 static elink_status_t
elink_bsc_read(struct elink_params
*params
,
2851 struct bnx2x_softc
*sc
,
2855 uint8_t xfer_cnt
, uint32_t * data_array
)
2858 elink_status_t rc
= ELINK_STATUS_OK
;
2860 if (xfer_cnt
> 16) {
2861 PMD_DRV_LOG(DEBUG
, "invalid xfer_cnt %d. Max is 16 bytes",
2863 return ELINK_STATUS_ERROR
;
2866 elink_bsc_module_sel(params
);
2868 xfer_cnt
= 16 - lc_addr
;
2870 /* Enable the engine */
2871 val
= REG_RD(sc
, MCP_REG_MCPR_IMC_COMMAND
);
2872 val
|= MCPR_IMC_COMMAND_ENABLE
;
2873 REG_WR(sc
, MCP_REG_MCPR_IMC_COMMAND
, val
);
2875 /* Program slave device ID */
2876 val
= (sl_devid
<< 16) | sl_addr
;
2877 REG_WR(sc
, MCP_REG_MCPR_IMC_SLAVE_CONTROL
, val
);
2879 /* Start xfer with 0 byte to update the address pointer ??? */
2880 val
= (MCPR_IMC_COMMAND_ENABLE
) |
2881 (MCPR_IMC_COMMAND_WRITE_OP
<<
2882 MCPR_IMC_COMMAND_OPERATION_BITSHIFT
) |
2883 (lc_addr
<< MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT
) | (0);
2884 REG_WR(sc
, MCP_REG_MCPR_IMC_COMMAND
, val
);
2886 /* Poll for completion */
2888 val
= REG_RD(sc
, MCP_REG_MCPR_IMC_COMMAND
);
2889 while (((val
>> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT
) & 0x3) != 1) {
2891 val
= REG_RD(sc
, MCP_REG_MCPR_IMC_COMMAND
);
2893 PMD_DRV_LOG(DEBUG
, "wr 0 byte timed out after %d try",
2895 rc
= ELINK_STATUS_TIMEOUT
;
2899 if (rc
== ELINK_STATUS_TIMEOUT
)
2902 /* Start xfer with read op */
2903 val
= (MCPR_IMC_COMMAND_ENABLE
) |
2904 (MCPR_IMC_COMMAND_READ_OP
<<
2905 MCPR_IMC_COMMAND_OPERATION_BITSHIFT
) |
2906 (lc_addr
<< MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT
) |
2908 REG_WR(sc
, MCP_REG_MCPR_IMC_COMMAND
, val
);
2910 /* Poll for completion */
2912 val
= REG_RD(sc
, MCP_REG_MCPR_IMC_COMMAND
);
2913 while (((val
>> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT
) & 0x3) != 1) {
2915 val
= REG_RD(sc
, MCP_REG_MCPR_IMC_COMMAND
);
2917 PMD_DRV_LOG(DEBUG
, "rd op timed out after %d try", i
);
2918 rc
= ELINK_STATUS_TIMEOUT
;
2922 if (rc
== ELINK_STATUS_TIMEOUT
)
2925 for (i
= (lc_addr
>> 2); i
< 4; i
++) {
2926 data_array
[i
] = REG_RD(sc
, (MCP_REG_MCPR_IMC_DATAREG0
+ i
* 4));
2928 data_array
[i
] = ((data_array
[i
] & 0x000000ff) << 24) |
2929 ((data_array
[i
] & 0x0000ff00) << 8) |
2930 ((data_array
[i
] & 0x00ff0000) >> 8) |
2931 ((data_array
[i
] & 0xff000000) >> 24);
2937 static void elink_cl45_read_or_write(struct bnx2x_softc
*sc
,
2938 struct elink_phy
*phy
, uint8_t devad
,
2939 uint16_t reg
, uint16_t or_val
)
2942 elink_cl45_read(sc
, phy
, devad
, reg
, &val
);
2943 elink_cl45_write(sc
, phy
, devad
, reg
, val
| or_val
);
2946 static void elink_cl45_read_and_write(struct bnx2x_softc
*sc
,
2947 struct elink_phy
*phy
,
2948 uint8_t devad
, uint16_t reg
,
2952 elink_cl45_read(sc
, phy
, devad
, reg
, &val
);
2953 elink_cl45_write(sc
, phy
, devad
, reg
, val
& and_val
);
2956 static uint8_t elink_get_warpcore_lane(struct elink_params
*params
)
2959 struct bnx2x_softc
*sc
= params
->sc
;
2960 uint32_t path_swap
, path_swap_ovr
;
2964 port
= params
->port
;
2966 if (elink_is_4_port_mode(sc
)) {
2967 uint32_t port_swap
, port_swap_ovr
;
2969 /* Figure out path swap value */
2970 path_swap_ovr
= REG_RD(sc
, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR
);
2971 if (path_swap_ovr
& 0x1)
2972 path_swap
= (path_swap_ovr
& 0x2);
2974 path_swap
= REG_RD(sc
, MISC_REG_FOUR_PORT_PATH_SWAP
);
2979 /* Figure out port swap value */
2980 port_swap_ovr
= REG_RD(sc
, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR
);
2981 if (port_swap_ovr
& 0x1)
2982 port_swap
= (port_swap_ovr
& 0x2);
2984 port_swap
= REG_RD(sc
, MISC_REG_FOUR_PORT_PORT_SWAP
);
2989 lane
= (port
<< 1) + path
;
2990 } else { /* Two port mode - no port swap */
2992 /* Figure out path swap value */
2993 path_swap_ovr
= REG_RD(sc
, MISC_REG_TWO_PORT_PATH_SWAP_OVWR
);
2994 if (path_swap_ovr
& 0x1) {
2995 path_swap
= (path_swap_ovr
& 0x2);
2997 path_swap
= REG_RD(sc
, MISC_REG_TWO_PORT_PATH_SWAP
);
3007 static void elink_set_aer_mmd(struct elink_params
*params
,
3008 struct elink_phy
*phy
)
3011 uint16_t offset
, aer_val
;
3012 struct bnx2x_softc
*sc
= params
->sc
;
3013 ser_lane
= ((params
->lane_config
&
3014 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
3015 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
3017 offset
= (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) ?
3018 (phy
->addr
+ ser_lane
) : 0;
3020 if (USES_WARPCORE(sc
)) {
3021 aer_val
= elink_get_warpcore_lane(params
);
3022 /* In Dual-lane mode, two lanes are joined together,
3023 * so in order to configure them, the AER broadcast method is
3025 * 0x200 is the broadcast address for lanes 0,1
3026 * 0x201 is the broadcast address for lanes 2,3
3028 if (phy
->flags
& ELINK_FLAGS_WC_DUAL_MODE
)
3029 aer_val
= (aer_val
>> 1) | 0x200;
3030 } else if (CHIP_IS_E2(sc
))
3031 aer_val
= 0x3800 + offset
- 1;
3033 aer_val
= 0x3800 + offset
;
3035 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
3036 MDIO_AER_BLOCK_AER_REG
, aer_val
);
3040 /******************************************************************/
3041 /* Internal phy section */
3042 /******************************************************************/
3044 static void elink_set_serdes_access(struct bnx2x_softc
*sc
, uint8_t port
)
3046 uint32_t emac_base
= (port
) ? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
3049 REG_WR(sc
, NIG_REG_SERDES0_CTRL_MD_ST
+ port
* 0x10, 1);
3050 REG_WR(sc
, emac_base
+ EMAC_REG_EMAC_MDIO_COMM
, 0x245f8000);
3052 REG_WR(sc
, emac_base
+ EMAC_REG_EMAC_MDIO_COMM
, 0x245d000f);
3055 REG_WR(sc
, NIG_REG_SERDES0_CTRL_MD_ST
+ port
* 0x10, 0);
3058 static void elink_serdes_deassert(struct bnx2x_softc
*sc
, uint8_t port
)
3062 PMD_DRV_LOG(DEBUG
, "elink_serdes_deassert");
3064 val
= ELINK_SERDES_RESET_BITS
<< (port
* 16);
3066 /* Reset and unreset the SerDes/XGXS */
3067 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_CLEAR
, val
);
3069 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_SET
, val
);
3071 elink_set_serdes_access(sc
, port
);
3073 REG_WR(sc
, NIG_REG_SERDES0_CTRL_MD_DEVAD
+ port
* 0x10,
3074 ELINK_DEFAULT_PHY_DEV_ADDR
);
3077 static void elink_xgxs_specific_func(struct elink_phy
*phy
,
3078 struct elink_params
*params
,
3081 struct bnx2x_softc
*sc
= params
->sc
;
3083 case ELINK_PHY_INIT
:
3084 /* Set correct devad */
3085 REG_WR(sc
, NIG_REG_XGXS0_CTRL_MD_ST
+ params
->port
* 0x18, 0);
3086 REG_WR(sc
, NIG_REG_XGXS0_CTRL_MD_DEVAD
+ params
->port
* 0x18,
3092 static void elink_xgxs_deassert(struct elink_params
*params
)
3094 struct bnx2x_softc
*sc
= params
->sc
;
3097 PMD_DRV_LOG(DEBUG
, "elink_xgxs_deassert");
3098 port
= params
->port
;
3100 val
= ELINK_XGXS_RESET_BITS
<< (port
* 16);
3102 /* Reset and unreset the SerDes/XGXS */
3103 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_CLEAR
, val
);
3105 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_SET
, val
);
3106 elink_xgxs_specific_func(¶ms
->phy
[ELINK_INT_PHY
], params
,
3110 static void elink_calc_ieee_aneg_adv(struct elink_phy
*phy
,
3111 struct elink_params
*params
,
3114 *ieee_fc
= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX
;
3115 /* Resolve pause mode and advertisement Please refer to Table
3116 * 28B-3 of the 802.3ab-1999 spec
3119 switch (phy
->req_flow_ctrl
) {
3120 case ELINK_FLOW_CTRL_AUTO
:
3121 switch (params
->req_fc_auto_adv
) {
3122 case ELINK_FLOW_CTRL_BOTH
:
3123 *ieee_fc
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
3125 case ELINK_FLOW_CTRL_RX
:
3126 case ELINK_FLOW_CTRL_TX
:
3128 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
;
3134 case ELINK_FLOW_CTRL_TX
:
3135 *ieee_fc
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
;
3138 case ELINK_FLOW_CTRL_RX
:
3139 case ELINK_FLOW_CTRL_BOTH
:
3140 *ieee_fc
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
3143 case ELINK_FLOW_CTRL_NONE
:
3145 *ieee_fc
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE
;
3148 PMD_DRV_LOG(DEBUG
, "ieee_fc = 0x%x", *ieee_fc
);
3151 static void set_phy_vars(struct elink_params
*params
, struct elink_vars
*vars
)
3153 uint8_t actual_phy_idx
, phy_index
, link_cfg_idx
;
3154 uint8_t phy_config_swapped
= params
->multi_phy_config
&
3155 PORT_HW_CFG_PHY_SWAPPED_ENABLED
;
3156 for (phy_index
= ELINK_INT_PHY
; phy_index
< params
->num_phys
;
3158 link_cfg_idx
= ELINK_LINK_CONFIG_IDX(phy_index
);
3159 actual_phy_idx
= phy_index
;
3160 if (phy_config_swapped
) {
3161 if (phy_index
== ELINK_EXT_PHY1
)
3162 actual_phy_idx
= ELINK_EXT_PHY2
;
3163 else if (phy_index
== ELINK_EXT_PHY2
)
3164 actual_phy_idx
= ELINK_EXT_PHY1
;
3166 params
->phy
[actual_phy_idx
].req_flow_ctrl
=
3167 params
->req_flow_ctrl
[link_cfg_idx
];
3169 params
->phy
[actual_phy_idx
].req_line_speed
=
3170 params
->req_line_speed
[link_cfg_idx
];
3172 params
->phy
[actual_phy_idx
].speed_cap_mask
=
3173 params
->speed_cap_mask
[link_cfg_idx
];
3175 params
->phy
[actual_phy_idx
].req_duplex
=
3176 params
->req_duplex
[link_cfg_idx
];
3178 if (params
->req_line_speed
[link_cfg_idx
] ==
3179 ELINK_SPEED_AUTO_NEG
)
3180 vars
->link_status
|= LINK_STATUS_AUTO_NEGOTIATE_ENABLED
;
3182 PMD_DRV_LOG(DEBUG
, "req_flow_ctrl %x, req_line_speed %x,"
3183 " speed_cap_mask %x",
3184 params
->phy
[actual_phy_idx
].req_flow_ctrl
,
3185 params
->phy
[actual_phy_idx
].req_line_speed
,
3186 params
->phy
[actual_phy_idx
].speed_cap_mask
);
3190 static void elink_ext_phy_set_pause(struct elink_params
*params
,
3191 struct elink_phy
*phy
,
3192 struct elink_vars
*vars
)
3195 struct bnx2x_softc
*sc
= params
->sc
;
3196 /* Read modify write pause advertizing */
3197 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV_PAUSE
, &val
);
3199 val
&= ~MDIO_AN_REG_ADV_PAUSE_BOTH
;
3201 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3202 elink_calc_ieee_aneg_adv(phy
, params
, &vars
->ieee_fc
);
3203 if ((vars
->ieee_fc
&
3204 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) ==
3205 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) {
3206 val
|= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC
;
3208 if ((vars
->ieee_fc
&
3209 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) ==
3210 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) {
3211 val
|= MDIO_AN_REG_ADV_PAUSE_PAUSE
;
3213 PMD_DRV_LOG(DEBUG
, "Ext phy AN advertize 0x%x", val
);
3214 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV_PAUSE
, val
);
3217 static void elink_pause_resolve(struct elink_vars
*vars
, uint32_t pause_result
)
3219 switch (pause_result
) { /* ASYM P ASYM P */
3220 case 0xb: /* 1 0 1 1 */
3221 vars
->flow_ctrl
= ELINK_FLOW_CTRL_TX
;
3224 case 0xe: /* 1 1 1 0 */
3225 vars
->flow_ctrl
= ELINK_FLOW_CTRL_RX
;
3228 case 0x5: /* 0 1 0 1 */
3229 case 0x7: /* 0 1 1 1 */
3230 case 0xd: /* 1 1 0 1 */
3231 case 0xf: /* 1 1 1 1 */
3232 vars
->flow_ctrl
= ELINK_FLOW_CTRL_BOTH
;
3238 if (pause_result
& (1 << 0))
3239 vars
->link_status
|= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE
;
3240 if (pause_result
& (1 << 1))
3241 vars
->link_status
|= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE
;
3245 static void elink_ext_phy_update_adv_fc(struct elink_phy
*phy
,
3246 struct elink_params
*params
,
3247 struct elink_vars
*vars
)
3249 uint16_t ld_pause
; /* local */
3250 uint16_t lp_pause
; /* link partner */
3251 uint16_t pause_result
;
3252 struct bnx2x_softc
*sc
= params
->sc
;
3253 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE
) {
3254 elink_cl22_read(sc
, phy
, 0x4, &ld_pause
);
3255 elink_cl22_read(sc
, phy
, 0x5, &lp_pause
);
3256 } else if (CHIP_IS_E3(sc
) && ELINK_SINGLE_MEDIA_DIRECT(params
)) {
3257 uint8_t lane
= elink_get_warpcore_lane(params
);
3258 uint16_t gp_status
, gp_mask
;
3259 elink_cl45_read(sc
, phy
,
3260 MDIO_AN_DEVAD
, MDIO_WC_REG_GP2_STATUS_GP_2_4
,
3262 gp_mask
= (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL
|
3263 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP
) <<
3265 if ((gp_status
& gp_mask
) == gp_mask
) {
3266 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
3267 MDIO_AN_REG_ADV_PAUSE
, &ld_pause
);
3268 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
3269 MDIO_AN_REG_LP_AUTO_NEG
, &lp_pause
);
3271 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
3272 MDIO_AN_REG_CL37_FC_LD
, &ld_pause
);
3273 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
3274 MDIO_AN_REG_CL37_FC_LP
, &lp_pause
);
3275 ld_pause
= ((ld_pause
&
3276 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
)
3278 lp_pause
= ((lp_pause
&
3279 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
)
3283 elink_cl45_read(sc
, phy
,
3285 MDIO_AN_REG_ADV_PAUSE
, &ld_pause
);
3286 elink_cl45_read(sc
, phy
,
3288 MDIO_AN_REG_LP_AUTO_NEG
, &lp_pause
);
3290 pause_result
= (ld_pause
& MDIO_AN_REG_ADV_PAUSE_MASK
) >> 8;
3291 pause_result
|= (lp_pause
& MDIO_AN_REG_ADV_PAUSE_MASK
) >> 10;
3292 PMD_DRV_LOG(DEBUG
, "Ext PHY pause result 0x%x", pause_result
);
3293 elink_pause_resolve(vars
, pause_result
);
3297 static uint8_t elink_ext_phy_resolve_fc(struct elink_phy
*phy
,
3298 struct elink_params
*params
,
3299 struct elink_vars
*vars
)
3302 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
3303 if (phy
->req_flow_ctrl
!= ELINK_FLOW_CTRL_AUTO
) {
3304 /* Update the advertised flow-controled of LD/LP in AN */
3305 if (phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
)
3306 elink_ext_phy_update_adv_fc(phy
, params
, vars
);
3307 /* But set the flow-control result as the requested one */
3308 vars
->flow_ctrl
= phy
->req_flow_ctrl
;
3309 } else if (phy
->req_line_speed
!= ELINK_SPEED_AUTO_NEG
)
3310 vars
->flow_ctrl
= params
->req_fc_auto_adv
;
3311 else if (vars
->link_status
& LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
) {
3313 elink_ext_phy_update_adv_fc(phy
, params
, vars
);
3318 /******************************************************************/
3319 /* Warpcore section */
3320 /******************************************************************/
3321 /* The init_internal_warpcore should mirror the xgxs,
3322 * i.e. reset the lane (if needed), set aer for the
3323 * init configuration, and set/clear SGMII flag. Internal
3324 * phy init is done purely in phy_init stage.
3326 #define WC_TX_DRIVER(post2, idriver, ipre) \
3327 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3328 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3329 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3331 #define WC_TX_FIR(post, main, pre) \
3332 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3333 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3334 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3336 static void elink_warpcore_enable_AN_KR2(struct elink_phy
*phy
,
3337 struct elink_params
*params
,
3338 struct elink_vars
*vars
)
3340 struct bnx2x_softc
*sc
= params
->sc
;
3342 static struct elink_reg_set reg_set
[] = {
3343 /* Step 1 - Program the TX/RX alignment markers */
3344 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_TX_CTRL5
, 0xa157},
3345 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_TX_CTRL7
, 0xcbe2},
3346 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_TX_CTRL6
, 0x7537},
3347 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_TX_CTRL9
, 0xa157},
3348 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_RX_CTRL11
, 0xcbe2},
3349 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_RX_CTRL10
, 0x7537},
3350 /* Step 2 - Configure the NP registers */
3351 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL73_USERB0_CTRL
, 0x000a},
3352 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL73_BAM_CTRL1
, 0x6400},
3353 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL73_BAM_CTRL3
, 0x0620},
3354 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL73_BAM_CODE_FIELD
, 0x0157},
3355 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_OUI1
, 0x6464},
3356 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_OUI2
, 0x3150},
3357 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_OUI3
, 0x3150},
3358 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE
, 0x0157},
3359 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_LD_UD_CODE
, 0x0620}
3361 PMD_DRV_LOG(DEBUG
, "Enabling 20G-KR2");
3363 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3364 MDIO_WC_REG_CL49_USERB0_CTRL
, (3 << 6));
3366 for (i
= 0; i
< ARRAY_SIZE(reg_set
); i
++)
3367 elink_cl45_write(sc
, phy
, reg_set
[i
].devad
, reg_set
[i
].reg
,
3370 /* Start KR2 work-around timer which handles BNX2X8073 link-parner */
3371 vars
->link_attr_sync
|= LINK_ATTR_SYNC_KR2_ENABLE
;
3372 elink_update_link_attr(params
, vars
->link_attr_sync
);
3375 static void elink_disable_kr2(struct elink_params
*params
,
3376 struct elink_vars
*vars
, struct elink_phy
*phy
)
3378 struct bnx2x_softc
*sc
= params
->sc
;
3380 static struct elink_reg_set reg_set
[] = {
3381 /* Step 1 - Program the TX/RX alignment markers */
3382 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_TX_CTRL5
, 0x7690},
3383 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_TX_CTRL7
, 0xe647},
3384 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_TX_CTRL6
, 0xc4f0},
3385 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_TX_CTRL9
, 0x7690},
3386 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_RX_CTRL11
, 0xe647},
3387 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_RX_CTRL10
, 0xc4f0},
3388 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL73_USERB0_CTRL
, 0x000c},
3389 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL73_BAM_CTRL1
, 0x6000},
3390 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL73_BAM_CTRL3
, 0x0000},
3391 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL73_BAM_CODE_FIELD
, 0x0002},
3392 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_OUI1
, 0x0000},
3393 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_OUI2
, 0x0af7},
3394 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_OUI3
, 0x0af7},
3395 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE
, 0x0002},
3396 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_LD_UD_CODE
, 0x0000}
3398 PMD_DRV_LOG(DEBUG
, "Disabling 20G-KR2");
3400 for (i
= 0; i
< ARRAY_SIZE(reg_set
); i
++)
3401 elink_cl45_write(sc
, phy
, reg_set
[i
].devad
, reg_set
[i
].reg
,
3403 vars
->link_attr_sync
&= ~LINK_ATTR_SYNC_KR2_ENABLE
;
3404 elink_update_link_attr(params
, vars
->link_attr_sync
);
3406 vars
->check_kr2_recovery_cnt
= ELINK_CHECK_KR2_RECOVERY_CNT
;
3409 static void elink_warpcore_set_lpi_passthrough(struct elink_phy
*phy
,
3410 struct elink_params
*params
)
3412 struct bnx2x_softc
*sc
= params
->sc
;
3414 PMD_DRV_LOG(DEBUG
, "Configure WC for LPI pass through");
3415 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3416 MDIO_WC_REG_EEE_COMBO_CONTROL0
, 0x7c);
3417 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3418 MDIO_WC_REG_DIGITAL4_MISC5
, 0xc000);
3421 static void elink_warpcore_restart_AN_KR(struct elink_phy
*phy
,
3422 struct elink_params
*params
)
3424 /* Restart autoneg on the leading lane only */
3425 struct bnx2x_softc
*sc
= params
->sc
;
3426 uint16_t lane
= elink_get_warpcore_lane(params
);
3427 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
3428 MDIO_AER_BLOCK_AER_REG
, lane
);
3429 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
,
3430 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x1200);
3433 elink_set_aer_mmd(params
, phy
);
3436 static void elink_warpcore_enable_AN_KR(struct elink_phy
*phy
,
3437 struct elink_params
*params
,
3438 struct elink_vars
*vars
)
3440 uint16_t lane
, i
, cl72_ctrl
, an_adv
= 0;
3441 struct bnx2x_softc
*sc
= params
->sc
;
3442 static struct elink_reg_set reg_set
[] = {
3443 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
, 0x7},
3444 {MDIO_PMA_DEVAD
, MDIO_WC_REG_IEEE0BLK_AUTONEGNP
, 0x0},
3445 {MDIO_WC_DEVAD
, MDIO_WC_REG_RX66_CONTROL
, 0x7415},
3446 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_MISC2
, 0x6190},
3447 /* Disable Autoneg: re-enable it after adv is done. */
3448 {MDIO_AN_DEVAD
, MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0},
3449 {MDIO_PMA_DEVAD
, MDIO_WC_REG_PMD_KR_CONTROL
, 0x2},
3450 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP
, 0},
3452 PMD_DRV_LOG(DEBUG
, "Enable Auto Negotiation for KR");
3453 /* Set to default registers that may be overriden by 10G force */
3454 for (i
= 0; i
< ARRAY_SIZE(reg_set
); i
++)
3455 elink_cl45_write(sc
, phy
, reg_set
[i
].devad
, reg_set
[i
].reg
,
3458 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3459 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL
, &cl72_ctrl
);
3460 cl72_ctrl
&= 0x08ff;
3461 cl72_ctrl
|= 0x3800;
3462 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3463 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL
, cl72_ctrl
);
3465 /* Check adding advertisement for 1G KX */
3466 if (((vars
->line_speed
== ELINK_SPEED_AUTO_NEG
) &&
3467 (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)) ||
3468 (vars
->line_speed
== ELINK_SPEED_1000
)) {
3469 uint16_t addr
= MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
;
3472 /* Enable CL37 1G Parallel Detect */
3473 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
, addr
, 0x1);
3474 PMD_DRV_LOG(DEBUG
, "Advertize 1G");
3476 if (((vars
->line_speed
== ELINK_SPEED_AUTO_NEG
) &&
3477 (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)) ||
3478 (vars
->line_speed
== ELINK_SPEED_10000
)) {
3479 /* Check adding advertisement for 10G KR */
3481 /* Enable 10G Parallel Detect */
3482 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
3483 MDIO_AER_BLOCK_AER_REG
, 0);
3485 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
,
3486 MDIO_WC_REG_PAR_DET_10G_CTRL
, 1);
3487 elink_set_aer_mmd(params
, phy
);
3488 PMD_DRV_LOG(DEBUG
, "Advertize 10G");
3491 /* Set Transmit PMD settings */
3492 lane
= elink_get_warpcore_lane(params
);
3493 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3494 MDIO_WC_REG_TX0_TX_DRIVER
+ 0x10 * lane
,
3495 WC_TX_DRIVER(0x02, 0x06, 0x09));
3496 /* Configure the next lane if dual mode */
3497 if (phy
->flags
& ELINK_FLAGS_WC_DUAL_MODE
)
3498 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3499 MDIO_WC_REG_TX0_TX_DRIVER
+ 0x10 * (lane
+ 1),
3500 WC_TX_DRIVER(0x02, 0x06, 0x09));
3501 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3502 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL
, 0x03f0);
3503 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3504 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL
, 0x03f0);
3506 /* Advertised speeds */
3507 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
,
3508 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1
, an_adv
);
3510 /* Advertised and set FEC (Forward Error Correction) */
3511 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
,
3512 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2
,
3513 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY
|
3514 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ
));
3516 /* Enable CL37 BAM */
3517 if (REG_RD(sc
, params
->shmem_base
+
3518 offsetof(struct shmem_region
,
3519 dev_info
.port_hw_config
[params
->port
].
3521 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED
) {
3522 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3523 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL
,
3525 PMD_DRV_LOG(DEBUG
, "Enable CL37 BAM on KR");
3528 /* Advertise pause */
3529 elink_ext_phy_set_pause(params
, phy
, vars
);
3530 vars
->rx_tx_asic_rst
= MAX_KR_LINK_RETRY
;
3531 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3532 MDIO_WC_REG_DIGITAL5_MISC7
, 0x100);
3534 /* Over 1G - AN local device user page 1 */
3535 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3536 MDIO_WC_REG_DIGITAL3_UP1
, 0x1f);
3538 if (((phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) &&
3539 (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
)) ||
3540 (phy
->req_line_speed
== ELINK_SPEED_20000
)) {
3542 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
3543 MDIO_AER_BLOCK_AER_REG
, lane
);
3545 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3546 MDIO_WC_REG_RX1_PCI_CTRL
+
3547 (0x10 * lane
), (1 << 11));
3549 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3550 MDIO_WC_REG_XGXS_X2_CONTROL3
, 0x7);
3551 elink_set_aer_mmd(params
, phy
);
3553 elink_warpcore_enable_AN_KR2(phy
, params
, vars
);
3555 elink_disable_kr2(params
, vars
, phy
);
3558 /* Enable Autoneg: only on the main lane */
3559 elink_warpcore_restart_AN_KR(phy
, params
);
3562 static void elink_warpcore_set_10G_KR(struct elink_phy
*phy
,
3563 struct elink_params
*params
)
3565 struct bnx2x_softc
*sc
= params
->sc
;
3566 uint16_t val16
, i
, lane
;
3567 static struct elink_reg_set reg_set
[] = {
3568 /* Disable Autoneg */
3569 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
, 0x7},
3570 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL
,
3572 {MDIO_AN_DEVAD
, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1
, 0},
3573 {MDIO_AN_DEVAD
, MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x0},
3574 {MDIO_WC_DEVAD
, MDIO_WC_REG_DIGITAL3_UP1
, 0x1},
3575 {MDIO_WC_DEVAD
, MDIO_WC_REG_DIGITAL5_MISC7
, 0xa},
3576 /* Leave cl72 training enable, needed for KR */
3577 {MDIO_PMA_DEVAD
, MDIO_WC_REG_PMD_KR_CONTROL
, 0x2}
3580 for (i
= 0; i
< ARRAY_SIZE(reg_set
); i
++)
3581 elink_cl45_write(sc
, phy
, reg_set
[i
].devad
, reg_set
[i
].reg
,
3584 lane
= elink_get_warpcore_lane(params
);
3585 /* Global registers */
3586 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
3587 MDIO_AER_BLOCK_AER_REG
, 0);
3588 /* Disable CL36 PCS Tx */
3589 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3590 MDIO_WC_REG_XGXSBLK1_LANECTRL0
, &val16
);
3591 val16
&= ~(0x0011 << lane
);
3592 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3593 MDIO_WC_REG_XGXSBLK1_LANECTRL0
, val16
);
3595 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3596 MDIO_WC_REG_XGXSBLK1_LANECTRL1
, &val16
);
3597 val16
|= (0x0303 << (lane
<< 1));
3598 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3599 MDIO_WC_REG_XGXSBLK1_LANECTRL1
, val16
);
3601 elink_set_aer_mmd(params
, phy
);
3602 /* Set speed via PMA/PMD register */
3603 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
,
3604 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x2040);
3606 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
,
3607 MDIO_WC_REG_IEEE0BLK_AUTONEGNP
, 0xB);
3609 /* Enable encoded forced speed */
3610 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3611 MDIO_WC_REG_SERDESDIGITAL_MISC2
, 0x30);
3613 /* Turn TX scramble payload only the 64/66 scrambler */
3614 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
, MDIO_WC_REG_TX66_CONTROL
, 0x9);
3616 /* Turn RX scramble payload only the 64/66 scrambler */
3617 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3618 MDIO_WC_REG_RX66_CONTROL
, 0xF9);
3620 /* Set and clear loopback to cause a reset to 64/66 decoder */
3621 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3622 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x4000);
3623 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3624 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x0);
3628 static void elink_warpcore_set_10G_XFI(struct elink_phy
*phy
,
3629 struct elink_params
*params
,
3632 struct bnx2x_softc
*sc
= params
->sc
;
3633 uint16_t misc1_val
, tap_val
, tx_driver_val
, lane
, val
;
3634 uint32_t cfg_tap_val
, tx_drv_brdct
, tx_equal
;
3636 /* Hold rxSeqStart */
3637 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3638 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0
, 0x8000);
3640 /* Hold tx_fifo_reset */
3641 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3642 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3
, 0x1);
3644 /* Disable CL73 AN */
3645 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0);
3647 /* Disable 100FX Enable and Auto-Detect */
3648 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
3649 MDIO_WC_REG_FX100_CTRL1
, 0xFFFA);
3651 /* Disable 100FX Idle detect */
3652 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3653 MDIO_WC_REG_FX100_CTRL3
, 0x0080);
3655 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3656 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
3657 MDIO_WC_REG_DIGITAL4_MISC3
, 0xFF7F);
3659 /* Turn off auto-detect & fiber mode */
3660 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
3661 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
,
3664 /* Set filter_force_link, disable_false_link and parallel_detect */
3665 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3666 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
, &val
);
3667 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3668 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
,
3669 ((val
| 0x0006) & 0xFFFE));
3672 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3673 MDIO_WC_REG_SERDESDIGITAL_MISC1
, &misc1_val
);
3675 misc1_val
&= ~(0x1f);
3679 tap_val
= WC_TX_FIR(0x08, 0x37, 0x00);
3680 tx_driver_val
= WC_TX_DRIVER(0x00, 0x02, 0x03);
3682 cfg_tap_val
= REG_RD(sc
, params
->shmem_base
+
3683 offsetof(struct shmem_region
,
3684 dev_info
.port_hw_config
[params
->
3685 port
].sfi_tap_values
));
3687 tx_equal
= cfg_tap_val
& PORT_HW_CFG_TX_EQUALIZATION_MASK
;
3689 tx_drv_brdct
= (cfg_tap_val
&
3690 PORT_HW_CFG_TX_DRV_BROADCAST_MASK
) >>
3691 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT
;
3695 /* TAP values are controlled by nvram, if value there isn't 0 */
3697 tap_val
= (uint16_t) tx_equal
;
3699 tap_val
= WC_TX_FIR(0x0f, 0x2b, 0x02);
3703 WC_TX_DRIVER(0x03, (uint16_t) tx_drv_brdct
, 0x06);
3705 tx_driver_val
= WC_TX_DRIVER(0x03, 0x02, 0x06);
3707 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3708 MDIO_WC_REG_SERDESDIGITAL_MISC1
, misc1_val
);
3710 /* Set Transmit PMD settings */
3711 lane
= elink_get_warpcore_lane(params
);
3712 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3713 MDIO_WC_REG_TX_FIR_TAP
,
3714 tap_val
| MDIO_WC_REG_TX_FIR_TAP_ENABLE
);
3715 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3716 MDIO_WC_REG_TX0_TX_DRIVER
+ 0x10 * lane
,
3719 /* Enable fiber mode, enable and invert sig_det */
3720 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3721 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
, 0xd);
3723 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3724 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3725 MDIO_WC_REG_DIGITAL4_MISC3
, 0x8080);
3727 elink_warpcore_set_lpi_passthrough(phy
, params
);
3729 /* 10G XFI Full Duplex */
3730 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3731 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x100);
3733 /* Release tx_fifo_reset */
3734 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
3735 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3
,
3737 /* Release rxSeqStart */
3738 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
3739 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0
, 0x7FFF);
3742 static void elink_warpcore_set_20G_force_KR2(struct elink_phy
*phy
,
3743 struct elink_params
*params
)
3746 struct bnx2x_softc
*sc
= params
->sc
;
3747 /* Set global registers, so set AER lane to 0 */
3748 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
3749 MDIO_AER_BLOCK_AER_REG
, 0);
3751 /* Disable sequencer */
3752 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
3753 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL
, ~(1 << 13));
3755 elink_set_aer_mmd(params
, phy
);
3757 elink_cl45_read_and_write(sc
, phy
, MDIO_PMA_DEVAD
,
3758 MDIO_WC_REG_PMD_KR_CONTROL
, ~(1 << 1));
3759 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0);
3761 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3762 MDIO_WC_REG_CL73_USERB0_CTRL
, &val
);
3765 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3766 MDIO_WC_REG_CL73_USERB0_CTRL
, val
);
3768 /* Set 20G KR2 force speed */
3769 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3770 MDIO_WC_REG_SERDESDIGITAL_MISC1
, 0x1f);
3772 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3773 MDIO_WC_REG_DIGITAL4_MISC3
, (1 << 7));
3775 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3776 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL
, &val
);
3779 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3780 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL
, val
);
3781 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3782 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP
, 0x835A);
3784 /* Enable sequencer (over lane 0) */
3785 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
3786 MDIO_AER_BLOCK_AER_REG
, 0);
3788 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3789 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL
, (1 << 13));
3791 elink_set_aer_mmd(params
, phy
);
3794 static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc
*sc
,
3795 struct elink_phy
*phy
, uint16_t lane
)
3797 /* Rx0 anaRxControl1G */
3798 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3799 MDIO_WC_REG_RX0_ANARXCONTROL1G
, 0x90);
3801 /* Rx2 anaRxControl1G */
3802 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3803 MDIO_WC_REG_RX2_ANARXCONTROL1G
, 0x90);
3805 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
, MDIO_WC_REG_RX66_SCW0
, 0xE070);
3807 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
, MDIO_WC_REG_RX66_SCW1
, 0xC0D0);
3809 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
, MDIO_WC_REG_RX66_SCW2
, 0xA0B0);
3811 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
, MDIO_WC_REG_RX66_SCW3
, 0x8090);
3813 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3814 MDIO_WC_REG_RX66_SCW0_MASK
, 0xF0F0);
3816 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3817 MDIO_WC_REG_RX66_SCW1_MASK
, 0xF0F0);
3819 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3820 MDIO_WC_REG_RX66_SCW2_MASK
, 0xF0F0);
3822 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3823 MDIO_WC_REG_RX66_SCW3_MASK
, 0xF0F0);
3825 /* Serdes Digital Misc1 */
3826 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3827 MDIO_WC_REG_SERDESDIGITAL_MISC1
, 0x6008);
3829 /* Serdes Digital4 Misc3 */
3830 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3831 MDIO_WC_REG_DIGITAL4_MISC3
, 0x8088);
3833 /* Set Transmit PMD settings */
3834 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3835 MDIO_WC_REG_TX_FIR_TAP
,
3836 (WC_TX_FIR(0x12, 0x2d, 0x00) |
3837 MDIO_WC_REG_TX_FIR_TAP_ENABLE
));
3838 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3839 MDIO_WC_REG_TX0_TX_DRIVER
+ 0x10 * lane
,
3840 WC_TX_DRIVER(0x02, 0x02, 0x02));
3843 static void elink_warpcore_set_sgmii_speed(struct elink_phy
*phy
,
3844 struct elink_params
*params
,
3846 uint8_t always_autoneg
)
3848 struct bnx2x_softc
*sc
= params
->sc
;
3849 uint16_t val16
, digctrl_kx1
, digctrl_kx2
;
3851 /* Clear XFI clock comp in non-10G single lane mode. */
3852 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
3853 MDIO_WC_REG_RX66_CONTROL
, ~(3 << 13));
3855 elink_warpcore_set_lpi_passthrough(phy
, params
);
3857 if (always_autoneg
|| phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) {
3859 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3860 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
,
3862 PMD_DRV_LOG(DEBUG
, "set SGMII AUTONEG");
3864 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3865 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, &val16
);
3867 switch (phy
->req_line_speed
) {
3868 case ELINK_SPEED_10
:
3870 case ELINK_SPEED_100
:
3873 case ELINK_SPEED_1000
:
3878 "Speed not supported: 0x%x",
3879 phy
->req_line_speed
);
3883 if (phy
->req_duplex
== DUPLEX_FULL
)
3886 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3887 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, val16
);
3889 PMD_DRV_LOG(DEBUG
, "set SGMII force speed %d",
3890 phy
->req_line_speed
);
3891 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3892 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, &val16
);
3893 PMD_DRV_LOG(DEBUG
, " (readback) %x", val16
);
3896 /* SGMII Slave mode and disable signal detect */
3897 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3898 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
, &digctrl_kx1
);
3902 digctrl_kx1
&= 0xff4a;
3904 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3905 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
, digctrl_kx1
);
3907 /* Turn off parallel detect */
3908 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3909 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
, &digctrl_kx2
);
3910 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3911 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
,
3912 (digctrl_kx2
& ~(1 << 2)));
3914 /* Re-enable parallel detect */
3915 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3916 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
,
3917 (digctrl_kx2
| (1 << 2)));
3919 /* Enable autodet */
3920 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3921 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
,
3922 (digctrl_kx1
| 0x10));
3925 static void elink_warpcore_reset_lane(struct bnx2x_softc
*sc
,
3926 struct elink_phy
*phy
, uint8_t reset
)
3929 /* Take lane out of reset after configuration is finished */
3930 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3931 MDIO_WC_REG_DIGITAL5_MISC6
, &val
);
3936 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3937 MDIO_WC_REG_DIGITAL5_MISC6
, val
);
3938 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3939 MDIO_WC_REG_DIGITAL5_MISC6
, &val
);
3942 /* Clear SFI/XFI link settings registers */
3943 static void elink_warpcore_clear_regs(struct elink_phy
*phy
,
3944 struct elink_params
*params
,
3947 struct bnx2x_softc
*sc
= params
->sc
;
3949 static struct elink_reg_set wc_regs
[] = {
3950 {MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0},
3951 {MDIO_WC_DEVAD
, MDIO_WC_REG_FX100_CTRL1
, 0x014a},
3952 {MDIO_WC_DEVAD
, MDIO_WC_REG_FX100_CTRL3
, 0x0800},
3953 {MDIO_WC_DEVAD
, MDIO_WC_REG_DIGITAL4_MISC3
, 0x8008},
3954 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
,
3956 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
,
3958 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3
,
3960 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_MISC1
, 0x6000},
3961 {MDIO_WC_DEVAD
, MDIO_WC_REG_TX_FIR_TAP
, 0x0000},
3962 {MDIO_WC_DEVAD
, MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x2040},
3963 {MDIO_WC_DEVAD
, MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, 0x0140}
3965 /* Set XFI clock comp as default. */
3966 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3967 MDIO_WC_REG_RX66_CONTROL
, (3 << 13));
3969 for (i
= 0; i
< ARRAY_SIZE(wc_regs
); i
++)
3970 elink_cl45_write(sc
, phy
, wc_regs
[i
].devad
, wc_regs
[i
].reg
,
3973 lane
= elink_get_warpcore_lane(params
);
3974 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3975 MDIO_WC_REG_TX0_TX_DRIVER
+ 0x10 * lane
, 0x0990);
3979 static elink_status_t
elink_get_mod_abs_int_cfg(struct bnx2x_softc
*sc
,
3980 uint32_t shmem_base
,
3983 uint8_t * gpio_port
)
3988 if (CHIP_IS_E3(sc
)) {
3989 cfg_pin
= (REG_RD(sc
, shmem_base
+
3990 offsetof(struct shmem_region
,
3991 dev_info
.port_hw_config
[port
].
3993 PORT_HW_CFG_E3_MOD_ABS_MASK
) >>
3994 PORT_HW_CFG_E3_MOD_ABS_SHIFT
;
3996 /* Should not happen. This function called upon interrupt
3997 * triggered by GPIO ( since EPIO can only generate interrupts
3999 * So if this function was called and none of the GPIOs was set,
4000 * it means the shit hit the fan.
4002 if ((cfg_pin
< PIN_CFG_GPIO0_P0
) ||
4003 (cfg_pin
> PIN_CFG_GPIO3_P1
)) {
4005 "No cfg pin %x for module detect indication",
4007 return ELINK_STATUS_ERROR
;
4010 *gpio_num
= (cfg_pin
- PIN_CFG_GPIO0_P0
) & 0x3;
4011 *gpio_port
= (cfg_pin
- PIN_CFG_GPIO0_P0
) >> 2;
4013 *gpio_num
= MISC_REGISTERS_GPIO_3
;
4017 return ELINK_STATUS_OK
;
4020 static int elink_is_sfp_module_plugged(struct elink_params
*params
)
4022 struct bnx2x_softc
*sc
= params
->sc
;
4023 uint8_t gpio_num
, gpio_port
;
4025 if (elink_get_mod_abs_int_cfg(sc
,
4026 params
->shmem_base
, params
->port
,
4027 &gpio_num
, &gpio_port
) != ELINK_STATUS_OK
)
4029 gpio_val
= elink_cb_gpio_read(sc
, gpio_num
, gpio_port
);
4031 /* Call the handling function in case module is detected */
4038 static int elink_warpcore_get_sigdet(struct elink_phy
*phy
,
4039 struct elink_params
*params
)
4041 uint16_t gp2_status_reg0
, lane
;
4042 struct bnx2x_softc
*sc
= params
->sc
;
4044 lane
= elink_get_warpcore_lane(params
);
4046 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
, MDIO_WC_REG_GP2_STATUS_GP_2_0
,
4049 return (gp2_status_reg0
>> (8 + lane
)) & 0x1;
4052 static void elink_warpcore_config_runtime(struct elink_phy
*phy
,
4053 struct elink_params
*params
,
4054 struct elink_vars
*vars
)
4056 struct bnx2x_softc
*sc
= params
->sc
;
4057 uint32_t serdes_net_if
;
4058 uint16_t gp_status1
= 0, lnkup
= 0, lnkup_kr
= 0;
4060 vars
->turn_to_run_wc_rt
= vars
->turn_to_run_wc_rt
? 0 : 1;
4062 if (!vars
->turn_to_run_wc_rt
)
4065 if (vars
->rx_tx_asic_rst
) {
4066 uint16_t lane
= elink_get_warpcore_lane(params
);
4067 serdes_net_if
= (REG_RD(sc
, params
->shmem_base
+
4068 offsetof(struct shmem_region
,
4069 dev_info
.port_hw_config
4072 PORT_HW_CFG_NET_SERDES_IF_MASK
);
4074 switch (serdes_net_if
) {
4075 case PORT_HW_CFG_NET_SERDES_IF_KR
:
4076 /* Do we get link yet? */
4077 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
, 0x81d1,
4079 lnkup
= (gp_status1
>> (8 + lane
)) & 0x1; /* 1G */
4081 lnkup_kr
= (gp_status1
>> (12 + lane
)) & 0x1;
4083 if (lnkup_kr
|| lnkup
) {
4084 vars
->rx_tx_asic_rst
= 0;
4086 /* Reset the lane to see if link comes up. */
4087 elink_warpcore_reset_lane(sc
, phy
, 1);
4088 elink_warpcore_reset_lane(sc
, phy
, 0);
4090 /* Restart Autoneg */
4091 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
,
4092 MDIO_WC_REG_IEEE0BLK_MIICNTL
,
4095 vars
->rx_tx_asic_rst
--;
4096 PMD_DRV_LOG(DEBUG
, "0x%x retry left",
4097 vars
->rx_tx_asic_rst
);
4106 /*params->rx_tx_asic_rst */
4109 static void elink_warpcore_config_sfi(struct elink_phy
*phy
,
4110 struct elink_params
*params
)
4112 uint16_t lane
= elink_get_warpcore_lane(params
);
4114 elink_warpcore_clear_regs(phy
, params
, lane
);
4115 if ((params
->req_line_speed
[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY
)] ==
4116 ELINK_SPEED_10000
) &&
4117 (phy
->media_type
!= ELINK_ETH_PHY_SFP_1G_FIBER
)) {
4118 PMD_DRV_LOG(DEBUG
, "Setting 10G SFI");
4119 elink_warpcore_set_10G_XFI(phy
, params
, 0);
4121 PMD_DRV_LOG(DEBUG
, "Setting 1G Fiber");
4122 elink_warpcore_set_sgmii_speed(phy
, params
, 1, 0);
4126 static void elink_sfp_e3_set_transmitter(struct elink_params
*params
,
4127 struct elink_phy
*phy
, uint8_t tx_en
)
4129 struct bnx2x_softc
*sc
= params
->sc
;
4131 uint8_t port
= params
->port
;
4133 cfg_pin
= REG_RD(sc
, params
->shmem_base
+
4134 offsetof(struct shmem_region
,
4135 dev_info
.port_hw_config
[port
].e3_sfp_ctrl
)) &
4136 PORT_HW_CFG_E3_TX_LASER_MASK
;
4137 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4138 PMD_DRV_LOG(DEBUG
, "Setting WC TX to %d", tx_en
);
4140 /* For 20G, the expected pin to be used is 3 pins after the current */
4141 elink_set_cfg_pin(sc
, cfg_pin
, tx_en
^ 1);
4142 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
)
4143 elink_set_cfg_pin(sc
, cfg_pin
+ 3, tx_en
^ 1);
4146 static void elink_warpcore_config_init(struct elink_phy
*phy
,
4147 struct elink_params
*params
,
4148 struct elink_vars
*vars
)
4150 struct bnx2x_softc
*sc
= params
->sc
;
4151 uint32_t serdes_net_if
;
4153 uint16_t lane
= elink_get_warpcore_lane(params
);
4154 serdes_net_if
= (REG_RD(sc
, params
->shmem_base
+
4155 offsetof(struct shmem_region
,
4156 dev_info
.port_hw_config
[params
->port
].
4158 PORT_HW_CFG_NET_SERDES_IF_MASK
);
4160 "Begin Warpcore init, link_speed %d, "
4161 "serdes_net_if = 0x%x", vars
->line_speed
, serdes_net_if
);
4162 elink_set_aer_mmd(params
, phy
);
4163 elink_warpcore_reset_lane(sc
, phy
, 1);
4164 vars
->phy_flags
|= PHY_XGXS_FLAG
;
4165 if ((serdes_net_if
== PORT_HW_CFG_NET_SERDES_IF_SGMII
) ||
4166 (phy
->req_line_speed
&&
4167 ((phy
->req_line_speed
== ELINK_SPEED_100
) ||
4168 (phy
->req_line_speed
== ELINK_SPEED_10
)))) {
4169 vars
->phy_flags
|= PHY_SGMII_FLAG
;
4170 PMD_DRV_LOG(DEBUG
, "Setting SGMII mode");
4171 elink_warpcore_clear_regs(phy
, params
, lane
);
4172 elink_warpcore_set_sgmii_speed(phy
, params
, 0, 1);
4174 switch (serdes_net_if
) {
4175 case PORT_HW_CFG_NET_SERDES_IF_KR
:
4176 /* Enable KR Auto Neg */
4177 if (params
->loopback_mode
!= ELINK_LOOPBACK_EXT
)
4178 elink_warpcore_enable_AN_KR(phy
, params
, vars
);
4180 PMD_DRV_LOG(DEBUG
, "Setting KR 10G-Force");
4181 elink_warpcore_set_10G_KR(phy
, params
);
4185 case PORT_HW_CFG_NET_SERDES_IF_XFI
:
4186 elink_warpcore_clear_regs(phy
, params
, lane
);
4187 if (vars
->line_speed
== ELINK_SPEED_10000
) {
4188 PMD_DRV_LOG(DEBUG
, "Setting 10G XFI");
4189 elink_warpcore_set_10G_XFI(phy
, params
, 1);
4191 if (ELINK_SINGLE_MEDIA_DIRECT(params
)) {
4192 PMD_DRV_LOG(DEBUG
, "1G Fiber");
4195 PMD_DRV_LOG(DEBUG
, "10/100/1G SGMII");
4198 elink_warpcore_set_sgmii_speed(phy
,
4205 case PORT_HW_CFG_NET_SERDES_IF_SFI
:
4206 /* Issue Module detection if module is plugged, or
4207 * enabled transmitter to avoid current leakage in case
4208 * no module is connected
4210 if ((params
->loopback_mode
== ELINK_LOOPBACK_NONE
) ||
4211 (params
->loopback_mode
== ELINK_LOOPBACK_EXT
)) {
4212 if (elink_is_sfp_module_plugged(params
))
4213 elink_sfp_module_detection(phy
, params
);
4215 elink_sfp_e3_set_transmitter(params
,
4219 elink_warpcore_config_sfi(phy
, params
);
4222 case PORT_HW_CFG_NET_SERDES_IF_DXGXS
:
4223 if (vars
->line_speed
!= ELINK_SPEED_20000
) {
4224 PMD_DRV_LOG(DEBUG
, "Speed not supported yet");
4227 PMD_DRV_LOG(DEBUG
, "Setting 20G DXGXS");
4228 elink_warpcore_set_20G_DXGXS(sc
, phy
, lane
);
4229 /* Issue Module detection */
4231 elink_sfp_module_detection(phy
, params
);
4233 case PORT_HW_CFG_NET_SERDES_IF_KR2
:
4234 if (!params
->loopback_mode
) {
4235 elink_warpcore_enable_AN_KR(phy
, params
, vars
);
4237 PMD_DRV_LOG(DEBUG
, "Setting KR 20G-Force");
4238 elink_warpcore_set_20G_force_KR2(phy
, params
);
4243 "Unsupported Serdes Net Interface 0x%x",
4249 /* Take lane out of reset after configuration is finished */
4250 elink_warpcore_reset_lane(sc
, phy
, 0);
4251 PMD_DRV_LOG(DEBUG
, "Exit config init");
4254 static void elink_warpcore_link_reset(struct elink_phy
*phy
,
4255 struct elink_params
*params
)
4257 struct bnx2x_softc
*sc
= params
->sc
;
4258 uint16_t val16
, lane
;
4259 elink_sfp_e3_set_transmitter(params
, phy
, 0);
4260 elink_set_mdio_emac_per_phy(sc
, params
);
4261 elink_set_aer_mmd(params
, phy
);
4262 /* Global register */
4263 elink_warpcore_reset_lane(sc
, phy
, 1);
4265 /* Clear loopback settings (if any) */
4267 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
4268 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, 0xBFFF);
4270 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
4271 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0xfffe);
4273 /* Update those 1-copy registers */
4274 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
4275 MDIO_AER_BLOCK_AER_REG
, 0);
4276 /* Enable 1G MDIO (1-copy) */
4277 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
4278 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL
, ~0x10);
4280 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
4281 MDIO_WC_REG_XGXSBLK1_LANECTRL2
, 0xff00);
4282 lane
= elink_get_warpcore_lane(params
);
4283 /* Disable CL36 PCS Tx */
4284 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
4285 MDIO_WC_REG_XGXSBLK1_LANECTRL0
, &val16
);
4286 val16
|= (0x11 << lane
);
4287 if (phy
->flags
& ELINK_FLAGS_WC_DUAL_MODE
)
4288 val16
|= (0x22 << lane
);
4289 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
4290 MDIO_WC_REG_XGXSBLK1_LANECTRL0
, val16
);
4292 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
4293 MDIO_WC_REG_XGXSBLK1_LANECTRL1
, &val16
);
4294 val16
&= ~(0x0303 << (lane
<< 1));
4295 val16
|= (0x0101 << (lane
<< 1));
4296 if (phy
->flags
& ELINK_FLAGS_WC_DUAL_MODE
) {
4297 val16
&= ~(0x0c0c << (lane
<< 1));
4298 val16
|= (0x0404 << (lane
<< 1));
4301 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
4302 MDIO_WC_REG_XGXSBLK1_LANECTRL1
, val16
);
4304 elink_set_aer_mmd(params
, phy
);
4308 static void elink_set_warpcore_loopback(struct elink_phy
*phy
,
4309 struct elink_params
*params
)
4311 struct bnx2x_softc
*sc
= params
->sc
;
4314 PMD_DRV_LOG(DEBUG
, "Setting Warpcore loopback type %x, speed %d",
4315 params
->loopback_mode
, phy
->req_line_speed
);
4317 if (phy
->req_line_speed
< ELINK_SPEED_10000
||
4318 phy
->supported
& ELINK_SUPPORTED_20000baseKR2_Full
) {
4319 /* 10/100/1000/20G-KR2 */
4321 /* Update those 1-copy registers */
4322 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
4323 MDIO_AER_BLOCK_AER_REG
, 0);
4324 /* Enable 1G MDIO (1-copy) */
4325 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
4326 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL
,
4328 /* Set 1G loopback based on lane (1-copy) */
4329 lane
= elink_get_warpcore_lane(params
);
4330 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
4331 MDIO_WC_REG_XGXSBLK1_LANECTRL2
, &val16
);
4332 val16
|= (1 << lane
);
4333 if (phy
->flags
& ELINK_FLAGS_WC_DUAL_MODE
)
4334 val16
|= (2 << lane
);
4335 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
4336 MDIO_WC_REG_XGXSBLK1_LANECTRL2
, val16
);
4338 /* Switch back to 4-copy registers */
4339 elink_set_aer_mmd(params
, phy
);
4341 /* 10G / 20G-DXGXS */
4342 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
4343 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
,
4345 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
4346 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x1);
4350 static void elink_sync_link(struct elink_params
*params
,
4351 struct elink_vars
*vars
)
4353 struct bnx2x_softc
*sc
= params
->sc
;
4354 uint8_t link_10g_plus
;
4355 if (vars
->link_status
& LINK_STATUS_PHYSICAL_LINK_FLAG
)
4356 vars
->phy_flags
|= PHY_PHYSICAL_LINK_FLAG
;
4357 vars
->link_up
= (vars
->link_status
& LINK_STATUS_LINK_UP
);
4358 if (vars
->link_up
) {
4359 PMD_DRV_LOG(DEBUG
, "phy link up");
4361 vars
->phy_link_up
= 1;
4362 vars
->duplex
= DUPLEX_FULL
;
4363 switch (vars
->link_status
& LINK_STATUS_SPEED_AND_DUPLEX_MASK
) {
4364 case ELINK_LINK_10THD
:
4365 vars
->duplex
= DUPLEX_HALF
;
4367 case ELINK_LINK_10TFD
:
4368 vars
->line_speed
= ELINK_SPEED_10
;
4371 case ELINK_LINK_100TXHD
:
4372 vars
->duplex
= DUPLEX_HALF
;
4374 case ELINK_LINK_100T4
:
4375 case ELINK_LINK_100TXFD
:
4376 vars
->line_speed
= ELINK_SPEED_100
;
4379 case ELINK_LINK_1000THD
:
4380 vars
->duplex
= DUPLEX_HALF
;
4382 case ELINK_LINK_1000TFD
:
4383 vars
->line_speed
= ELINK_SPEED_1000
;
4386 case ELINK_LINK_2500THD
:
4387 vars
->duplex
= DUPLEX_HALF
;
4389 case ELINK_LINK_2500TFD
:
4390 vars
->line_speed
= ELINK_SPEED_2500
;
4393 case ELINK_LINK_10GTFD
:
4394 vars
->line_speed
= ELINK_SPEED_10000
;
4396 case ELINK_LINK_20GTFD
:
4397 vars
->line_speed
= ELINK_SPEED_20000
;
4402 vars
->flow_ctrl
= 0;
4403 if (vars
->link_status
& LINK_STATUS_TX_FLOW_CONTROL_ENABLED
)
4404 vars
->flow_ctrl
|= ELINK_FLOW_CTRL_TX
;
4406 if (vars
->link_status
& LINK_STATUS_RX_FLOW_CONTROL_ENABLED
)
4407 vars
->flow_ctrl
|= ELINK_FLOW_CTRL_RX
;
4409 if (!vars
->flow_ctrl
)
4410 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
4412 if (vars
->line_speed
&&
4413 ((vars
->line_speed
== ELINK_SPEED_10
) ||
4414 (vars
->line_speed
== ELINK_SPEED_100
))) {
4415 vars
->phy_flags
|= PHY_SGMII_FLAG
;
4417 vars
->phy_flags
&= ~PHY_SGMII_FLAG
;
4419 if (vars
->line_speed
&&
4420 USES_WARPCORE(sc
) && (vars
->line_speed
== ELINK_SPEED_1000
))
4421 vars
->phy_flags
|= PHY_SGMII_FLAG
;
4422 /* Anything 10 and over uses the bmac */
4423 link_10g_plus
= (vars
->line_speed
>= ELINK_SPEED_10000
);
4425 if (link_10g_plus
) {
4426 if (USES_WARPCORE(sc
))
4427 vars
->mac_type
= ELINK_MAC_TYPE_XMAC
;
4429 vars
->mac_type
= ELINK_MAC_TYPE_BMAC
;
4431 if (USES_WARPCORE(sc
))
4432 vars
->mac_type
= ELINK_MAC_TYPE_UMAC
;
4434 vars
->mac_type
= ELINK_MAC_TYPE_EMAC
;
4436 } else { /* Link down */
4437 PMD_DRV_LOG(DEBUG
, "phy link down");
4439 vars
->phy_link_up
= 0;
4441 vars
->line_speed
= 0;
4442 vars
->duplex
= DUPLEX_FULL
;
4443 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
4445 /* Indicate no mac active */
4446 vars
->mac_type
= ELINK_MAC_TYPE_NONE
;
4447 if (vars
->link_status
& LINK_STATUS_PHYSICAL_LINK_FLAG
)
4448 vars
->phy_flags
|= PHY_HALF_OPEN_CONN_FLAG
;
4449 if (vars
->link_status
& LINK_STATUS_SFP_TX_FAULT
)
4450 vars
->phy_flags
|= PHY_SFP_TX_FAULT_FLAG
;
4454 void elink_link_status_update(struct elink_params
*params
,
4455 struct elink_vars
*vars
)
4457 struct bnx2x_softc
*sc
= params
->sc
;
4458 uint8_t port
= params
->port
;
4459 uint32_t sync_offset
, media_types
;
4460 /* Update PHY configuration */
4461 set_phy_vars(params
, vars
);
4463 vars
->link_status
= REG_RD(sc
, params
->shmem_base
+
4464 offsetof(struct shmem_region
,
4465 port_mb
[port
].link_status
));
4467 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4468 if (params
->loopback_mode
!= ELINK_LOOPBACK_NONE
&&
4469 params
->loopback_mode
!= ELINK_LOOPBACK_EXT
)
4470 vars
->link_status
|= LINK_STATUS_LINK_UP
;
4472 if (elink_eee_has_cap(params
))
4473 vars
->eee_status
= REG_RD(sc
, params
->shmem2_base
+
4474 offsetof(struct shmem2_region
,
4475 eee_status
[params
->port
]));
4477 vars
->phy_flags
= PHY_XGXS_FLAG
;
4478 elink_sync_link(params
, vars
);
4479 /* Sync media type */
4480 sync_offset
= params
->shmem_base
+
4481 offsetof(struct shmem_region
,
4482 dev_info
.port_hw_config
[port
].media_type
);
4483 media_types
= REG_RD(sc
, sync_offset
);
4485 params
->phy
[ELINK_INT_PHY
].media_type
=
4486 (media_types
& PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK
) >>
4487 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT
;
4488 params
->phy
[ELINK_EXT_PHY1
].media_type
=
4489 (media_types
& PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK
) >>
4490 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT
;
4491 params
->phy
[ELINK_EXT_PHY2
].media_type
=
4492 (media_types
& PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK
) >>
4493 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT
;
4494 PMD_DRV_LOG(DEBUG
, "media_types = 0x%x", media_types
);
4496 /* Sync AEU offset */
4497 sync_offset
= params
->shmem_base
+
4498 offsetof(struct shmem_region
,
4499 dev_info
.port_hw_config
[port
].aeu_int_mask
);
4501 vars
->aeu_int_mask
= REG_RD(sc
, sync_offset
);
4503 /* Sync PFC status */
4504 if (vars
->link_status
& LINK_STATUS_PFC_ENABLED
)
4505 params
->feature_config_flags
|=
4506 ELINK_FEATURE_CONFIG_PFC_ENABLED
;
4508 params
->feature_config_flags
&=
4509 ~ELINK_FEATURE_CONFIG_PFC_ENABLED
;
4511 if (SHMEM2_HAS(sc
, link_attr_sync
))
4512 vars
->link_attr_sync
= SHMEM2_RD(sc
,
4513 link_attr_sync
[params
->port
]);
4515 PMD_DRV_LOG(DEBUG
, "link_status 0x%x phy_link_up %x int_mask 0x%x",
4516 vars
->link_status
, vars
->phy_link_up
, vars
->aeu_int_mask
);
4517 PMD_DRV_LOG(DEBUG
, "line_speed %x duplex %x flow_ctrl 0x%x",
4518 vars
->line_speed
, vars
->duplex
, vars
->flow_ctrl
);
4521 static void elink_set_master_ln(struct elink_params
*params
,
4522 struct elink_phy
*phy
)
4524 struct bnx2x_softc
*sc
= params
->sc
;
4525 uint16_t new_master_ln
, ser_lane
;
4526 ser_lane
= ((params
->lane_config
&
4527 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
4528 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
4530 /* Set the master_ln for AN */
4531 CL22_RD_OVER_CL45(sc
, phy
,
4532 MDIO_REG_BANK_XGXS_BLOCK2
,
4533 MDIO_XGXS_BLOCK2_TEST_MODE_LANE
, &new_master_ln
);
4535 CL22_WR_OVER_CL45(sc
, phy
,
4536 MDIO_REG_BANK_XGXS_BLOCK2
,
4537 MDIO_XGXS_BLOCK2_TEST_MODE_LANE
,
4538 (new_master_ln
| ser_lane
));
4541 static elink_status_t
elink_reset_unicore(struct elink_params
*params
,
4542 struct elink_phy
*phy
,
4545 struct bnx2x_softc
*sc
= params
->sc
;
4546 uint16_t mii_control
;
4548 CL22_RD_OVER_CL45(sc
, phy
,
4549 MDIO_REG_BANK_COMBO_IEEE0
,
4550 MDIO_COMBO_IEEE0_MII_CONTROL
, &mii_control
);
4552 /* Reset the unicore */
4553 CL22_WR_OVER_CL45(sc
, phy
,
4554 MDIO_REG_BANK_COMBO_IEEE0
,
4555 MDIO_COMBO_IEEE0_MII_CONTROL
,
4556 (mii_control
| MDIO_COMBO_IEEO_MII_CONTROL_RESET
));
4558 elink_set_serdes_access(sc
, params
->port
);
4560 /* Wait for the reset to self clear */
4561 for (i
= 0; i
< ELINK_MDIO_ACCESS_TIMEOUT
; i
++) {
4564 /* The reset erased the previous bank value */
4565 CL22_RD_OVER_CL45(sc
, phy
,
4566 MDIO_REG_BANK_COMBO_IEEE0
,
4567 MDIO_COMBO_IEEE0_MII_CONTROL
, &mii_control
);
4569 if (!(mii_control
& MDIO_COMBO_IEEO_MII_CONTROL_RESET
)) {
4571 return ELINK_STATUS_OK
;
4575 elink_cb_event_log(sc
, ELINK_LOG_ID_PHY_UNINITIALIZED
, params
->port
); // "Warning: PHY was not initialized,"
4578 PMD_DRV_LOG(DEBUG
, "BUG! XGXS is still in reset!");
4579 return ELINK_STATUS_ERROR
;
4583 static void elink_set_swap_lanes(struct elink_params
*params
,
4584 struct elink_phy
*phy
)
4586 struct bnx2x_softc
*sc
= params
->sc
;
4587 /* Each two bits represents a lane number:
4588 * No swap is 0123 => 0x1b no need to enable the swap
4590 uint16_t rx_lane_swap
, tx_lane_swap
;
4592 rx_lane_swap
= ((params
->lane_config
&
4593 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK
) >>
4594 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT
);
4595 tx_lane_swap
= ((params
->lane_config
&
4596 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK
) >>
4597 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT
);
4599 if (rx_lane_swap
!= 0x1b) {
4600 CL22_WR_OVER_CL45(sc
, phy
,
4601 MDIO_REG_BANK_XGXS_BLOCK2
,
4602 MDIO_XGXS_BLOCK2_RX_LN_SWAP
,
4604 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE
|
4605 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE
));
4607 CL22_WR_OVER_CL45(sc
, phy
,
4608 MDIO_REG_BANK_XGXS_BLOCK2
,
4609 MDIO_XGXS_BLOCK2_RX_LN_SWAP
, 0);
4612 if (tx_lane_swap
!= 0x1b) {
4613 CL22_WR_OVER_CL45(sc
, phy
,
4614 MDIO_REG_BANK_XGXS_BLOCK2
,
4615 MDIO_XGXS_BLOCK2_TX_LN_SWAP
,
4617 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE
));
4619 CL22_WR_OVER_CL45(sc
, phy
,
4620 MDIO_REG_BANK_XGXS_BLOCK2
,
4621 MDIO_XGXS_BLOCK2_TX_LN_SWAP
, 0);
4625 static void elink_set_parallel_detection(struct elink_phy
*phy
,
4626 struct elink_params
*params
)
4628 struct bnx2x_softc
*sc
= params
->sc
;
4630 CL22_RD_OVER_CL45(sc
, phy
,
4631 MDIO_REG_BANK_SERDES_DIGITAL
,
4632 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2
, &control2
);
4633 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)
4634 control2
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN
;
4636 control2
&= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN
;
4637 PMD_DRV_LOG(DEBUG
, "phy->speed_cap_mask = 0x%x, control2 = 0x%x",
4638 phy
->speed_cap_mask
, control2
);
4639 CL22_WR_OVER_CL45(sc
, phy
,
4640 MDIO_REG_BANK_SERDES_DIGITAL
,
4641 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2
, control2
);
4643 if ((phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) &&
4644 (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)) {
4645 PMD_DRV_LOG(DEBUG
, "XGXS");
4647 CL22_WR_OVER_CL45(sc
, phy
,
4648 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
4649 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK
,
4650 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT
);
4652 CL22_RD_OVER_CL45(sc
, phy
,
4653 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
4654 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL
,
4658 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN
;
4660 CL22_WR_OVER_CL45(sc
, phy
,
4661 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
4662 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL
,
4665 /* Disable parallel detection of HiG */
4666 CL22_WR_OVER_CL45(sc
, phy
,
4667 MDIO_REG_BANK_XGXS_BLOCK2
,
4668 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G
,
4669 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS
|
4670 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS
);
4674 static void elink_set_autoneg(struct elink_phy
*phy
,
4675 struct elink_params
*params
,
4676 struct elink_vars
*vars
, uint8_t enable_cl73
)
4678 struct bnx2x_softc
*sc
= params
->sc
;
4682 CL22_RD_OVER_CL45(sc
, phy
,
4683 MDIO_REG_BANK_COMBO_IEEE0
,
4684 MDIO_COMBO_IEEE0_MII_CONTROL
, ®_val
);
4686 /* CL37 Autoneg Enabled */
4687 if (vars
->line_speed
== ELINK_SPEED_AUTO_NEG
)
4688 reg_val
|= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
;
4689 else /* CL37 Autoneg Disabled */
4690 reg_val
&= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
4691 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN
);
4693 CL22_WR_OVER_CL45(sc
, phy
,
4694 MDIO_REG_BANK_COMBO_IEEE0
,
4695 MDIO_COMBO_IEEE0_MII_CONTROL
, reg_val
);
4697 /* Enable/Disable Autodetection */
4699 CL22_RD_OVER_CL45(sc
, phy
,
4700 MDIO_REG_BANK_SERDES_DIGITAL
,
4701 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
, ®_val
);
4702 reg_val
&= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN
|
4703 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT
);
4704 reg_val
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE
;
4705 if (vars
->line_speed
== ELINK_SPEED_AUTO_NEG
)
4706 reg_val
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET
;
4708 reg_val
&= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET
;
4710 CL22_WR_OVER_CL45(sc
, phy
,
4711 MDIO_REG_BANK_SERDES_DIGITAL
,
4712 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
, reg_val
);
4714 /* Enable TetonII and BAM autoneg */
4715 CL22_RD_OVER_CL45(sc
, phy
,
4716 MDIO_REG_BANK_BAM_NEXT_PAGE
,
4717 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL
, ®_val
);
4718 if (vars
->line_speed
== ELINK_SPEED_AUTO_NEG
) {
4719 /* Enable BAM aneg Mode and TetonII aneg Mode */
4720 reg_val
|= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE
|
4721 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN
);
4723 /* TetonII and BAM Autoneg Disabled */
4724 reg_val
&= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE
|
4725 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN
);
4727 CL22_WR_OVER_CL45(sc
, phy
,
4728 MDIO_REG_BANK_BAM_NEXT_PAGE
,
4729 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL
, reg_val
);
4732 /* Enable Cl73 FSM status bits */
4733 CL22_WR_OVER_CL45(sc
, phy
,
4734 MDIO_REG_BANK_CL73_USERB0
,
4735 MDIO_CL73_USERB0_CL73_UCTRL
, 0xe);
4737 /* Enable BAM Station Manager */
4738 CL22_WR_OVER_CL45(sc
, phy
,
4739 MDIO_REG_BANK_CL73_USERB0
,
4740 MDIO_CL73_USERB0_CL73_BAM_CTRL1
,
4741 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN
|
4742 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN
4744 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN
);
4746 /* Advertise CL73 link speeds */
4747 CL22_RD_OVER_CL45(sc
, phy
,
4748 MDIO_REG_BANK_CL73_IEEEB1
,
4749 MDIO_CL73_IEEEB1_AN_ADV2
, ®_val
);
4750 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
4751 reg_val
|= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4
;
4752 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)
4753 reg_val
|= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX
;
4755 CL22_WR_OVER_CL45(sc
, phy
,
4756 MDIO_REG_BANK_CL73_IEEEB1
,
4757 MDIO_CL73_IEEEB1_AN_ADV2
, reg_val
);
4759 /* CL73 Autoneg Enabled */
4760 reg_val
= MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN
;
4762 } else /* CL73 Autoneg Disabled */
4765 CL22_WR_OVER_CL45(sc
, phy
,
4766 MDIO_REG_BANK_CL73_IEEEB0
,
4767 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
, reg_val
);
4770 /* Program SerDes, forced speed */
4771 static void elink_program_serdes(struct elink_phy
*phy
,
4772 struct elink_params
*params
,
4773 struct elink_vars
*vars
)
4775 struct bnx2x_softc
*sc
= params
->sc
;
4778 /* Program duplex, disable autoneg and sgmii */
4779 CL22_RD_OVER_CL45(sc
, phy
,
4780 MDIO_REG_BANK_COMBO_IEEE0
,
4781 MDIO_COMBO_IEEE0_MII_CONTROL
, ®_val
);
4782 reg_val
&= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
|
4783 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
4784 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK
);
4785 if (phy
->req_duplex
== DUPLEX_FULL
)
4786 reg_val
|= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
;
4787 CL22_WR_OVER_CL45(sc
, phy
,
4788 MDIO_REG_BANK_COMBO_IEEE0
,
4789 MDIO_COMBO_IEEE0_MII_CONTROL
, reg_val
);
4792 * - needed only if the speed is greater than 1G (2.5G or 10G)
4794 CL22_RD_OVER_CL45(sc
, phy
,
4795 MDIO_REG_BANK_SERDES_DIGITAL
,
4796 MDIO_SERDES_DIGITAL_MISC1
, ®_val
);
4797 /* Clearing the speed value before setting the right speed */
4798 PMD_DRV_LOG(DEBUG
, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val
);
4800 reg_val
&= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK
|
4801 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL
);
4803 if (!((vars
->line_speed
== ELINK_SPEED_1000
) ||
4804 (vars
->line_speed
== ELINK_SPEED_100
) ||
4805 (vars
->line_speed
== ELINK_SPEED_10
))) {
4807 reg_val
|= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M
|
4808 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL
);
4809 if (vars
->line_speed
== ELINK_SPEED_10000
)
4811 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4
;
4814 CL22_WR_OVER_CL45(sc
, phy
,
4815 MDIO_REG_BANK_SERDES_DIGITAL
,
4816 MDIO_SERDES_DIGITAL_MISC1
, reg_val
);
4820 static void elink_set_brcm_cl37_advertisement(struct elink_phy
*phy
,
4821 struct elink_params
*params
)
4823 struct bnx2x_softc
*sc
= params
->sc
;
4826 /* Set extended capabilities */
4827 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
)
4828 val
|= MDIO_OVER_1G_UP1_2_5G
;
4829 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
4830 val
|= MDIO_OVER_1G_UP1_10G
;
4831 CL22_WR_OVER_CL45(sc
, phy
,
4832 MDIO_REG_BANK_OVER_1G
, MDIO_OVER_1G_UP1
, val
);
4834 CL22_WR_OVER_CL45(sc
, phy
,
4835 MDIO_REG_BANK_OVER_1G
, MDIO_OVER_1G_UP3
, 0x400);
4838 static void elink_set_ieee_aneg_advertisement(struct elink_phy
*phy
,
4839 struct elink_params
*params
,
4842 struct bnx2x_softc
*sc
= params
->sc
;
4844 /* For AN, we are always publishing full duplex */
4846 CL22_WR_OVER_CL45(sc
, phy
,
4847 MDIO_REG_BANK_COMBO_IEEE0
,
4848 MDIO_COMBO_IEEE0_AUTO_NEG_ADV
, ieee_fc
);
4849 CL22_RD_OVER_CL45(sc
, phy
,
4850 MDIO_REG_BANK_CL73_IEEEB1
,
4851 MDIO_CL73_IEEEB1_AN_ADV1
, &val
);
4852 val
&= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH
;
4853 val
|= ((ieee_fc
<< 3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK
);
4854 CL22_WR_OVER_CL45(sc
, phy
,
4855 MDIO_REG_BANK_CL73_IEEEB1
,
4856 MDIO_CL73_IEEEB1_AN_ADV1
, val
);
4859 static void elink_restart_autoneg(struct elink_phy
*phy
,
4860 struct elink_params
*params
,
4861 uint8_t enable_cl73
)
4863 struct bnx2x_softc
*sc
= params
->sc
;
4864 uint16_t mii_control
;
4866 PMD_DRV_LOG(DEBUG
, "elink_restart_autoneg");
4867 /* Enable and restart BAM/CL37 aneg */
4870 CL22_RD_OVER_CL45(sc
, phy
,
4871 MDIO_REG_BANK_CL73_IEEEB0
,
4872 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
4875 CL22_WR_OVER_CL45(sc
, phy
,
4876 MDIO_REG_BANK_CL73_IEEEB0
,
4877 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
4879 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN
|
4880 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN
));
4883 CL22_RD_OVER_CL45(sc
, phy
,
4884 MDIO_REG_BANK_COMBO_IEEE0
,
4885 MDIO_COMBO_IEEE0_MII_CONTROL
, &mii_control
);
4887 "elink_restart_autoneg mii_control before = 0x%x",
4889 CL22_WR_OVER_CL45(sc
, phy
,
4890 MDIO_REG_BANK_COMBO_IEEE0
,
4891 MDIO_COMBO_IEEE0_MII_CONTROL
,
4893 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
4894 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN
));
4898 static void elink_initialize_sgmii_process(struct elink_phy
*phy
,
4899 struct elink_params
*params
,
4900 struct elink_vars
*vars
)
4902 struct bnx2x_softc
*sc
= params
->sc
;
4905 /* In SGMII mode, the unicore is always slave */
4907 CL22_RD_OVER_CL45(sc
, phy
,
4908 MDIO_REG_BANK_SERDES_DIGITAL
,
4909 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
, &control1
);
4910 control1
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT
;
4911 /* Set sgmii mode (and not fiber) */
4912 control1
&= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE
|
4913 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET
|
4914 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE
);
4915 CL22_WR_OVER_CL45(sc
, phy
,
4916 MDIO_REG_BANK_SERDES_DIGITAL
,
4917 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
, control1
);
4919 /* If forced speed */
4920 if (!(vars
->line_speed
== ELINK_SPEED_AUTO_NEG
)) {
4921 /* Set speed, disable autoneg */
4922 uint16_t mii_control
;
4924 CL22_RD_OVER_CL45(sc
, phy
,
4925 MDIO_REG_BANK_COMBO_IEEE0
,
4926 MDIO_COMBO_IEEE0_MII_CONTROL
, &mii_control
);
4927 mii_control
&= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
4928 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK
|
4929 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
);
4931 switch (vars
->line_speed
) {
4932 case ELINK_SPEED_100
:
4934 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100
;
4936 case ELINK_SPEED_1000
:
4938 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000
;
4940 case ELINK_SPEED_10
:
4941 /* There is nothing to set for 10M */
4944 /* Invalid speed for SGMII */
4945 PMD_DRV_LOG(DEBUG
, "Invalid line_speed 0x%x",
4950 /* Setting the full duplex */
4951 if (phy
->req_duplex
== DUPLEX_FULL
)
4952 mii_control
|= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
;
4953 CL22_WR_OVER_CL45(sc
, phy
,
4954 MDIO_REG_BANK_COMBO_IEEE0
,
4955 MDIO_COMBO_IEEE0_MII_CONTROL
, mii_control
);
4957 } else { /* AN mode */
4958 /* Enable and restart AN */
4959 elink_restart_autoneg(phy
, params
, 0);
4965 static elink_status_t
elink_direct_parallel_detect_used(struct elink_phy
*phy
,
4969 struct bnx2x_softc
*sc
= params
->sc
;
4970 uint16_t pd_10g
, status2_1000x
;
4971 if (phy
->req_line_speed
!= ELINK_SPEED_AUTO_NEG
)
4972 return ELINK_STATUS_OK
;
4973 CL22_RD_OVER_CL45(sc
, phy
,
4974 MDIO_REG_BANK_SERDES_DIGITAL
,
4975 MDIO_SERDES_DIGITAL_A_1000X_STATUS2
, &status2_1000x
);
4976 CL22_RD_OVER_CL45(sc
, phy
,
4977 MDIO_REG_BANK_SERDES_DIGITAL
,
4978 MDIO_SERDES_DIGITAL_A_1000X_STATUS2
, &status2_1000x
);
4979 if (status2_1000x
& MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED
) {
4980 PMD_DRV_LOG(DEBUG
, "1G parallel detect link on port %d",
4982 return ELINK_STATUS_ERROR
;
4985 CL22_RD_OVER_CL45(sc
, phy
,
4986 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
4987 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS
, &pd_10g
);
4989 if (pd_10g
& MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK
) {
4990 PMD_DRV_LOG(DEBUG
, "10G parallel detect link on port %d",
4992 return ELINK_STATUS_ERROR
;
4994 return ELINK_STATUS_OK
;
4997 static void elink_update_adv_fc(struct elink_phy
*phy
,
4998 struct elink_params
*params
,
4999 struct elink_vars
*vars
, uint32_t gp_status
)
5001 uint16_t ld_pause
; /* local driver */
5002 uint16_t lp_pause
; /* link partner */
5003 uint16_t pause_result
;
5004 struct bnx2x_softc
*sc
= params
->sc
;
5006 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE
|
5007 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE
)) ==
5008 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE
|
5009 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE
)) {
5011 CL22_RD_OVER_CL45(sc
, phy
,
5012 MDIO_REG_BANK_CL73_IEEEB1
,
5013 MDIO_CL73_IEEEB1_AN_ADV1
, &ld_pause
);
5014 CL22_RD_OVER_CL45(sc
, phy
,
5015 MDIO_REG_BANK_CL73_IEEEB1
,
5016 MDIO_CL73_IEEEB1_AN_LP_ADV1
, &lp_pause
);
5017 pause_result
= (ld_pause
&
5018 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK
) >> 8;
5019 pause_result
|= (lp_pause
&
5020 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK
) >> 10;
5021 PMD_DRV_LOG(DEBUG
, "pause_result CL73 0x%x", pause_result
);
5023 CL22_RD_OVER_CL45(sc
, phy
,
5024 MDIO_REG_BANK_COMBO_IEEE0
,
5025 MDIO_COMBO_IEEE0_AUTO_NEG_ADV
, &ld_pause
);
5026 CL22_RD_OVER_CL45(sc
, phy
,
5027 MDIO_REG_BANK_COMBO_IEEE0
,
5028 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1
,
5030 pause_result
= (ld_pause
&
5031 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
) >> 5;
5032 pause_result
|= (lp_pause
&
5033 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
) >> 7;
5034 PMD_DRV_LOG(DEBUG
, "pause_result CL37 0x%x", pause_result
);
5036 elink_pause_resolve(vars
, pause_result
);
5040 static void elink_flow_ctrl_resolve(struct elink_phy
*phy
,
5041 struct elink_params
*params
,
5042 struct elink_vars
*vars
, uint32_t gp_status
)
5044 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
5046 /* Resolve from gp_status in case of AN complete and not sgmii */
5047 if (phy
->req_flow_ctrl
!= ELINK_FLOW_CTRL_AUTO
) {
5048 /* Update the advertised flow-controled of LD/LP in AN */
5049 if (phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
)
5050 elink_update_adv_fc(phy
, params
, vars
, gp_status
);
5051 /* But set the flow-control result as the requested one */
5052 vars
->flow_ctrl
= phy
->req_flow_ctrl
;
5053 } else if (phy
->req_line_speed
!= ELINK_SPEED_AUTO_NEG
)
5054 vars
->flow_ctrl
= params
->req_fc_auto_adv
;
5055 else if ((gp_status
& ELINK_MDIO_AN_CL73_OR_37_COMPLETE
) &&
5056 (!(vars
->phy_flags
& PHY_SGMII_FLAG
))) {
5057 if (elink_direct_parallel_detect_used(phy
, params
)) {
5058 vars
->flow_ctrl
= params
->req_fc_auto_adv
;
5061 elink_update_adv_fc(phy
, params
, vars
, gp_status
);
5063 PMD_DRV_LOG(DEBUG
, "flow_ctrl 0x%x", vars
->flow_ctrl
);
5066 static void elink_check_fallback_to_cl37(struct elink_phy
*phy
,
5067 struct elink_params
*params
)
5069 struct bnx2x_softc
*sc
= params
->sc
;
5070 uint16_t rx_status
, ustat_val
, cl37_fsm_received
;
5071 PMD_DRV_LOG(DEBUG
, "elink_check_fallback_to_cl37");
5072 /* Step 1: Make sure signal is detected */
5073 CL22_RD_OVER_CL45(sc
, phy
,
5074 MDIO_REG_BANK_RX0
, MDIO_RX0_RX_STATUS
, &rx_status
);
5075 if ((rx_status
& MDIO_RX0_RX_STATUS_SIGDET
) !=
5076 (MDIO_RX0_RX_STATUS_SIGDET
)) {
5077 PMD_DRV_LOG(DEBUG
, "Signal is not detected. Restoring CL73."
5078 "rx_status(0x80b0) = 0x%x", rx_status
);
5079 CL22_WR_OVER_CL45(sc
, phy
,
5080 MDIO_REG_BANK_CL73_IEEEB0
,
5081 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
5082 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN
);
5085 /* Step 2: Check CL73 state machine */
5086 CL22_RD_OVER_CL45(sc
, phy
,
5087 MDIO_REG_BANK_CL73_USERB0
,
5088 MDIO_CL73_USERB0_CL73_USTAT1
, &ustat_val
);
5090 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK
|
5091 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37
)) !=
5092 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK
|
5093 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37
)) {
5094 PMD_DRV_LOG(DEBUG
, "CL73 state-machine is not stable. "
5095 "ustat_val(0x8371) = 0x%x", ustat_val
);
5098 /* Step 3: Check CL37 Message Pages received to indicate LP
5099 * supports only CL37
5101 CL22_RD_OVER_CL45(sc
, phy
,
5102 MDIO_REG_BANK_REMOTE_PHY
,
5103 MDIO_REMOTE_PHY_MISC_RX_STATUS
, &cl37_fsm_received
);
5104 if ((cl37_fsm_received
&
5105 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG
|
5106 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG
)) !=
5107 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG
|
5108 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG
)) {
5109 PMD_DRV_LOG(DEBUG
, "No CL37 FSM were received. "
5110 "misc_rx_status(0x8330) = 0x%x", cl37_fsm_received
);
5113 /* The combined cl37/cl73 fsm state information indicating that
5114 * we are connected to a device which does not support cl73, but
5115 * does support cl37 BAM. In this case we disable cl73 and
5116 * restart cl37 auto-neg
5120 CL22_WR_OVER_CL45(sc
, phy
,
5121 MDIO_REG_BANK_CL73_IEEEB0
,
5122 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
, 0);
5123 /* Restart CL37 autoneg */
5124 elink_restart_autoneg(phy
, params
, 0);
5125 PMD_DRV_LOG(DEBUG
, "Disabling CL73, and restarting CL37 autoneg");
5128 static void elink_xgxs_an_resolve(struct elink_phy
*phy
,
5129 struct elink_params
*params
,
5130 struct elink_vars
*vars
, uint32_t gp_status
)
5132 if (gp_status
& ELINK_MDIO_AN_CL73_OR_37_COMPLETE
)
5133 vars
->link_status
|= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
5135 if (elink_direct_parallel_detect_used(phy
, params
))
5136 vars
->link_status
|= LINK_STATUS_PARALLEL_DETECTION_USED
;
5139 static elink_status_t
elink_get_link_speed_duplex(struct elink_phy
*phy
,
5140 struct elink_params
*params __rte_unused
,
5141 struct elink_vars
*vars
,
5142 uint16_t is_link_up
,
5143 uint16_t speed_mask
,
5146 if (phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
)
5147 vars
->link_status
|= LINK_STATUS_AUTO_NEGOTIATE_ENABLED
;
5149 PMD_DRV_LOG(DEBUG
, "phy link up");
5151 vars
->phy_link_up
= 1;
5152 vars
->link_status
|= LINK_STATUS_LINK_UP
;
5154 switch (speed_mask
) {
5155 case ELINK_GP_STATUS_10M
:
5156 vars
->line_speed
= ELINK_SPEED_10
;
5157 if (is_duplex
== DUPLEX_FULL
)
5158 vars
->link_status
|= ELINK_LINK_10TFD
;
5160 vars
->link_status
|= ELINK_LINK_10THD
;
5163 case ELINK_GP_STATUS_100M
:
5164 vars
->line_speed
= ELINK_SPEED_100
;
5165 if (is_duplex
== DUPLEX_FULL
)
5166 vars
->link_status
|= ELINK_LINK_100TXFD
;
5168 vars
->link_status
|= ELINK_LINK_100TXHD
;
5171 case ELINK_GP_STATUS_1G
:
5172 case ELINK_GP_STATUS_1G_KX
:
5173 vars
->line_speed
= ELINK_SPEED_1000
;
5174 if (is_duplex
== DUPLEX_FULL
)
5175 vars
->link_status
|= ELINK_LINK_1000TFD
;
5177 vars
->link_status
|= ELINK_LINK_1000THD
;
5180 case ELINK_GP_STATUS_2_5G
:
5181 vars
->line_speed
= ELINK_SPEED_2500
;
5182 if (is_duplex
== DUPLEX_FULL
)
5183 vars
->link_status
|= ELINK_LINK_2500TFD
;
5185 vars
->link_status
|= ELINK_LINK_2500THD
;
5188 case ELINK_GP_STATUS_5G
:
5189 case ELINK_GP_STATUS_6G
:
5191 "link speed unsupported gp_status 0x%x",
5193 return ELINK_STATUS_ERROR
;
5195 case ELINK_GP_STATUS_10G_KX4
:
5196 case ELINK_GP_STATUS_10G_HIG
:
5197 case ELINK_GP_STATUS_10G_CX4
:
5198 case ELINK_GP_STATUS_10G_KR
:
5199 case ELINK_GP_STATUS_10G_SFI
:
5200 case ELINK_GP_STATUS_10G_XFI
:
5201 vars
->line_speed
= ELINK_SPEED_10000
;
5202 vars
->link_status
|= ELINK_LINK_10GTFD
;
5204 case ELINK_GP_STATUS_20G_DXGXS
:
5205 case ELINK_GP_STATUS_20G_KR2
:
5206 vars
->line_speed
= ELINK_SPEED_20000
;
5207 vars
->link_status
|= ELINK_LINK_20GTFD
;
5211 "link speed unsupported gp_status 0x%x",
5213 return ELINK_STATUS_ERROR
;
5215 } else { /* link_down */
5216 PMD_DRV_LOG(DEBUG
, "phy link down");
5218 vars
->phy_link_up
= 0;
5220 vars
->duplex
= DUPLEX_FULL
;
5221 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
5222 vars
->mac_type
= ELINK_MAC_TYPE_NONE
;
5224 PMD_DRV_LOG(DEBUG
, " phy_link_up %x line_speed %d",
5225 vars
->phy_link_up
, vars
->line_speed
);
5226 return ELINK_STATUS_OK
;
5229 static elink_status_t
elink_link_settings_status(struct elink_phy
*phy
,
5230 struct elink_params
*params
,
5231 struct elink_vars
*vars
)
5233 struct bnx2x_softc
*sc
= params
->sc
;
5235 uint16_t gp_status
, duplex
= DUPLEX_HALF
, link_up
= 0, speed_mask
;
5236 elink_status_t rc
= ELINK_STATUS_OK
;
5238 /* Read gp_status */
5239 CL22_RD_OVER_CL45(sc
, phy
,
5240 MDIO_REG_BANK_GP_STATUS
,
5241 MDIO_GP_STATUS_TOP_AN_STATUS1
, &gp_status
);
5242 if (gp_status
& MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS
)
5243 duplex
= DUPLEX_FULL
;
5244 if (gp_status
& MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS
)
5246 speed_mask
= gp_status
& ELINK_GP_STATUS_SPEED_MASK
;
5247 PMD_DRV_LOG(DEBUG
, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x",
5248 gp_status
, link_up
, speed_mask
);
5249 rc
= elink_get_link_speed_duplex(phy
, params
, vars
, link_up
, speed_mask
,
5251 if (rc
== ELINK_STATUS_ERROR
)
5254 if (gp_status
& MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS
) {
5255 if (ELINK_SINGLE_MEDIA_DIRECT(params
)) {
5256 vars
->duplex
= duplex
;
5257 elink_flow_ctrl_resolve(phy
, params
, vars
, gp_status
);
5258 if (phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
)
5259 elink_xgxs_an_resolve(phy
, params
, vars
,
5262 } else { /* Link_down */
5263 if ((phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) &&
5264 ELINK_SINGLE_MEDIA_DIRECT(params
)) {
5265 /* Check signal is detected */
5266 elink_check_fallback_to_cl37(phy
, params
);
5270 /* Read LP advertised speeds */
5271 if (ELINK_SINGLE_MEDIA_DIRECT(params
) &&
5272 (vars
->link_status
& LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
)) {
5275 CL22_RD_OVER_CL45(sc
, phy
, MDIO_REG_BANK_CL73_IEEEB1
,
5276 MDIO_CL73_IEEEB1_AN_LP_ADV2
, &val
);
5278 if (val
& MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX
)
5279 vars
->link_status
|=
5280 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE
;
5281 if (val
& (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4
|
5282 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR
))
5283 vars
->link_status
|=
5284 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
5286 CL22_RD_OVER_CL45(sc
, phy
, MDIO_REG_BANK_OVER_1G
,
5287 MDIO_OVER_1G_LP_UP1
, &val
);
5289 if (val
& MDIO_OVER_1G_UP1_2_5G
)
5290 vars
->link_status
|=
5291 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE
;
5292 if (val
& (MDIO_OVER_1G_UP1_10G
| MDIO_OVER_1G_UP1_10GH
))
5293 vars
->link_status
|=
5294 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
5297 PMD_DRV_LOG(DEBUG
, "duplex %x flow_ctrl 0x%x link_status 0x%x",
5298 vars
->duplex
, vars
->flow_ctrl
, vars
->link_status
);
5302 static elink_status_t
elink_warpcore_read_status(struct elink_phy
*phy
,
5303 struct elink_params
*params
,
5304 struct elink_vars
*vars
)
5306 struct bnx2x_softc
*sc
= params
->sc
;
5308 uint16_t gp_status1
, gp_speed
, link_up
, duplex
= DUPLEX_FULL
;
5309 elink_status_t rc
= ELINK_STATUS_OK
;
5310 lane
= elink_get_warpcore_lane(params
);
5311 /* Read gp_status */
5312 if ((params
->loopback_mode
) && (phy
->flags
& ELINK_FLAGS_WC_DUAL_MODE
)) {
5313 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
5314 MDIO_WC_REG_DIGITAL5_LINK_STATUS
, &link_up
);
5315 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
5316 MDIO_WC_REG_DIGITAL5_LINK_STATUS
, &link_up
);
5318 } else if ((phy
->req_line_speed
> ELINK_SPEED_10000
) &&
5319 (phy
->supported
& ELINK_SUPPORTED_20000baseMLD2_Full
)) {
5320 uint16_t temp_link_up
;
5321 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
, 1, &temp_link_up
);
5322 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
, 1, &link_up
);
5323 PMD_DRV_LOG(DEBUG
, "PCS RX link status = 0x%x-->0x%x",
5324 temp_link_up
, link_up
);
5325 link_up
&= (1 << 2);
5327 elink_ext_phy_resolve_fc(phy
, params
, vars
);
5329 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
5330 MDIO_WC_REG_GP2_STATUS_GP_2_1
, &gp_status1
);
5331 PMD_DRV_LOG(DEBUG
, "0x81d1 = 0x%x", gp_status1
);
5332 /* Check for either KR, 1G, or AN up. */
5333 link_up
= ((gp_status1
>> 8) |
5334 (gp_status1
>> 12) | (gp_status1
)) & (1 << lane
);
5335 if (phy
->supported
& ELINK_SUPPORTED_20000baseKR2_Full
) {
5337 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
5338 MDIO_AN_REG_STATUS
, &an_link
);
5339 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
5340 MDIO_AN_REG_STATUS
, &an_link
);
5341 link_up
|= (an_link
& (1 << 2));
5343 if (link_up
&& ELINK_SINGLE_MEDIA_DIRECT(params
)) {
5344 uint16_t pd
, gp_status4
;
5345 if (phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) {
5346 /* Check Autoneg complete */
5347 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
5348 MDIO_WC_REG_GP2_STATUS_GP_2_4
,
5350 if (gp_status4
& ((1 << 12) << lane
))
5351 vars
->link_status
|=
5352 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
5354 /* Check parallel detect used */
5355 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
5356 MDIO_WC_REG_PAR_DET_10G_STATUS
,
5359 vars
->link_status
|=
5360 LINK_STATUS_PARALLEL_DETECTION_USED
;
5362 elink_ext_phy_resolve_fc(phy
, params
, vars
);
5363 vars
->duplex
= duplex
;
5367 if ((vars
->link_status
& LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
) &&
5368 ELINK_SINGLE_MEDIA_DIRECT(params
)) {
5371 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
5372 MDIO_AN_REG_LP_AUTO_NEG2
, &val
);
5374 if (val
& MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX
)
5375 vars
->link_status
|=
5376 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE
;
5377 if (val
& (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4
|
5378 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR
))
5379 vars
->link_status
|=
5380 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
5382 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
5383 MDIO_WC_REG_DIGITAL3_LP_UP1
, &val
);
5385 if (val
& MDIO_OVER_1G_UP1_2_5G
)
5386 vars
->link_status
|=
5387 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE
;
5388 if (val
& (MDIO_OVER_1G_UP1_10G
| MDIO_OVER_1G_UP1_10GH
))
5389 vars
->link_status
|=
5390 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
5395 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
5396 MDIO_WC_REG_GP2_STATUS_GP_2_2
, &gp_speed
);
5398 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
5399 MDIO_WC_REG_GP2_STATUS_GP_2_3
, &gp_speed
);
5401 PMD_DRV_LOG(DEBUG
, "lane %d gp_speed 0x%x", lane
, gp_speed
);
5403 if ((lane
& 1) == 0)
5406 link_up
= ! !link_up
;
5408 /* Reset the TX FIFO to fix SGMII issue */
5409 rc
= elink_get_link_speed_duplex(phy
, params
, vars
, link_up
, gp_speed
,
5412 /* In case of KR link down, start up the recovering procedure */
5413 if ((!link_up
) && (phy
->media_type
== ELINK_ETH_PHY_KR
) &&
5414 (!(phy
->flags
& ELINK_FLAGS_WC_DUAL_MODE
)))
5415 vars
->rx_tx_asic_rst
= MAX_KR_LINK_RETRY
;
5417 PMD_DRV_LOG(DEBUG
, "duplex %x flow_ctrl 0x%x link_status 0x%x",
5418 vars
->duplex
, vars
->flow_ctrl
, vars
->link_status
);
5422 static void elink_set_gmii_tx_driver(struct elink_params
*params
)
5424 struct bnx2x_softc
*sc
= params
->sc
;
5425 struct elink_phy
*phy
= ¶ms
->phy
[ELINK_INT_PHY
];
5431 CL22_RD_OVER_CL45(sc
, phy
,
5432 MDIO_REG_BANK_OVER_1G
, MDIO_OVER_1G_LP_UP2
, &lp_up2
);
5434 /* Bits [10:7] at lp_up2, positioned at [15:12] */
5435 lp_up2
= (((lp_up2
& MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK
) >>
5436 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT
) <<
5437 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT
);
5442 for (bank
= MDIO_REG_BANK_TX0
; bank
<= MDIO_REG_BANK_TX3
;
5443 bank
+= (MDIO_REG_BANK_TX1
- MDIO_REG_BANK_TX0
)) {
5444 CL22_RD_OVER_CL45(sc
, phy
,
5445 bank
, MDIO_TX0_TX_DRIVER
, &tx_driver
);
5447 /* Replace tx_driver bits [15:12] */
5448 if (lp_up2
!= (tx_driver
& MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK
)) {
5449 tx_driver
&= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK
;
5450 tx_driver
|= lp_up2
;
5451 CL22_WR_OVER_CL45(sc
, phy
,
5452 bank
, MDIO_TX0_TX_DRIVER
, tx_driver
);
5457 static elink_status_t
elink_emac_program(struct elink_params
*params
,
5458 struct elink_vars
*vars
)
5460 struct bnx2x_softc
*sc
= params
->sc
;
5461 uint8_t port
= params
->port
;
5464 PMD_DRV_LOG(DEBUG
, "setting link speed & duplex");
5465 elink_bits_dis(sc
, GRCBASE_EMAC0
+ port
* 0x400 +
5467 (EMAC_MODE_25G_MODE
|
5468 EMAC_MODE_PORT_MII_10M
| EMAC_MODE_HALF_DUPLEX
));
5469 switch (vars
->line_speed
) {
5470 case ELINK_SPEED_10
:
5471 mode
|= EMAC_MODE_PORT_MII_10M
;
5474 case ELINK_SPEED_100
:
5475 mode
|= EMAC_MODE_PORT_MII
;
5478 case ELINK_SPEED_1000
:
5479 mode
|= EMAC_MODE_PORT_GMII
;
5482 case ELINK_SPEED_2500
:
5483 mode
|= (EMAC_MODE_25G_MODE
| EMAC_MODE_PORT_GMII
);
5487 /* 10G not valid for EMAC */
5488 PMD_DRV_LOG(DEBUG
, "Invalid line_speed 0x%x", vars
->line_speed
);
5489 return ELINK_STATUS_ERROR
;
5492 if (vars
->duplex
== DUPLEX_HALF
)
5493 mode
|= EMAC_MODE_HALF_DUPLEX
;
5495 GRCBASE_EMAC0
+ port
* 0x400 + EMAC_REG_EMAC_MODE
, mode
);
5497 elink_set_led(params
, vars
, ELINK_LED_MODE_OPER
, vars
->line_speed
);
5498 return ELINK_STATUS_OK
;
5501 static void elink_set_preemphasis(struct elink_phy
*phy
,
5502 struct elink_params
*params
)
5505 uint16_t bank
, i
= 0;
5506 struct bnx2x_softc
*sc
= params
->sc
;
5508 for (bank
= MDIO_REG_BANK_RX0
, i
= 0; bank
<= MDIO_REG_BANK_RX3
;
5509 bank
+= (MDIO_REG_BANK_RX1
- MDIO_REG_BANK_RX0
), i
++) {
5510 CL22_WR_OVER_CL45(sc
, phy
,
5512 MDIO_RX0_RX_EQ_BOOST
, phy
->rx_preemphasis
[i
]);
5515 for (bank
= MDIO_REG_BANK_TX0
, i
= 0; bank
<= MDIO_REG_BANK_TX3
;
5516 bank
+= (MDIO_REG_BANK_TX1
- MDIO_REG_BANK_TX0
), i
++) {
5517 CL22_WR_OVER_CL45(sc
, phy
,
5519 MDIO_TX0_TX_DRIVER
, phy
->tx_preemphasis
[i
]);
5523 static void elink_xgxs_config_init(struct elink_phy
*phy
,
5524 struct elink_params
*params
,
5525 struct elink_vars
*vars
)
5527 uint8_t enable_cl73
= (ELINK_SINGLE_MEDIA_DIRECT(params
) ||
5528 (params
->loopback_mode
== ELINK_LOOPBACK_XGXS
));
5530 if (!(vars
->phy_flags
& PHY_SGMII_FLAG
)) {
5531 if (ELINK_SINGLE_MEDIA_DIRECT(params
) &&
5532 (params
->feature_config_flags
&
5533 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
))
5534 elink_set_preemphasis(phy
, params
);
5536 /* Forced speed requested? */
5537 if (vars
->line_speed
!= ELINK_SPEED_AUTO_NEG
||
5538 (ELINK_SINGLE_MEDIA_DIRECT(params
) &&
5539 params
->loopback_mode
== ELINK_LOOPBACK_EXT
)) {
5540 PMD_DRV_LOG(DEBUG
, "not SGMII, no AN");
5542 /* Disable autoneg */
5543 elink_set_autoneg(phy
, params
, vars
, 0);
5545 /* Program speed and duplex */
5546 elink_program_serdes(phy
, params
, vars
);
5548 } else { /* AN_mode */
5549 PMD_DRV_LOG(DEBUG
, "not SGMII, AN");
5552 elink_set_brcm_cl37_advertisement(phy
, params
);
5554 /* Program duplex & pause advertisement (for aneg) */
5555 elink_set_ieee_aneg_advertisement(phy
, params
,
5558 /* Enable autoneg */
5559 elink_set_autoneg(phy
, params
, vars
, enable_cl73
);
5561 /* Enable and restart AN */
5562 elink_restart_autoneg(phy
, params
, enable_cl73
);
5565 } else { /* SGMII mode */
5566 PMD_DRV_LOG(DEBUG
, "SGMII");
5568 elink_initialize_sgmii_process(phy
, params
, vars
);
5572 static elink_status_t
elink_prepare_xgxs(struct elink_phy
*phy
,
5573 struct elink_params
*params
,
5574 struct elink_vars
*vars
)
5577 vars
->phy_flags
|= PHY_XGXS_FLAG
;
5578 if ((phy
->req_line_speed
&&
5579 ((phy
->req_line_speed
== ELINK_SPEED_100
) ||
5580 (phy
->req_line_speed
== ELINK_SPEED_10
))) ||
5581 (!phy
->req_line_speed
&&
5582 (phy
->speed_cap_mask
>=
5583 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
) &&
5584 (phy
->speed_cap_mask
<
5585 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)) ||
5586 (phy
->type
== PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD
))
5587 vars
->phy_flags
|= PHY_SGMII_FLAG
;
5589 vars
->phy_flags
&= ~PHY_SGMII_FLAG
;
5591 elink_calc_ieee_aneg_adv(phy
, params
, &vars
->ieee_fc
);
5592 elink_set_aer_mmd(params
, phy
);
5593 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)
5594 elink_set_master_ln(params
, phy
);
5596 rc
= elink_reset_unicore(params
, phy
, 0);
5597 /* Reset the SerDes and wait for reset bit return low */
5598 if (rc
!= ELINK_STATUS_OK
)
5601 elink_set_aer_mmd(params
, phy
);
5602 /* Setting the masterLn_def again after the reset */
5603 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) {
5604 elink_set_master_ln(params
, phy
);
5605 elink_set_swap_lanes(params
, phy
);
5611 static uint16_t elink_wait_reset_complete(struct bnx2x_softc
*sc
,
5612 struct elink_phy
*phy
,
5613 struct elink_params
*params
)
5616 /* Wait for soft reset to get cleared up to 1 sec */
5617 for (cnt
= 0; cnt
< 1000; cnt
++) {
5618 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE
)
5619 elink_cl22_read(sc
, phy
, MDIO_PMA_REG_CTRL
, &ctrl
);
5621 elink_cl45_read(sc
, phy
,
5623 MDIO_PMA_REG_CTRL
, &ctrl
);
5624 if (!(ctrl
& (1 << 15)))
5630 elink_cb_event_log(sc
, ELINK_LOG_ID_PHY_UNINITIALIZED
, params
->port
); // "Warning: PHY was not initialized,"
5633 PMD_DRV_LOG(DEBUG
, "control reg 0x%x (after %d ms)", ctrl
, cnt
);
5637 static void elink_link_int_enable(struct elink_params
*params
)
5639 uint8_t port
= params
->port
;
5641 struct bnx2x_softc
*sc
= params
->sc
;
5643 /* Setting the status to report on link up for either XGXS or SerDes */
5644 if (CHIP_IS_E3(sc
)) {
5645 mask
= ELINK_NIG_MASK_XGXS0_LINK_STATUS
;
5646 if (!(ELINK_SINGLE_MEDIA_DIRECT(params
)))
5647 mask
|= ELINK_NIG_MASK_MI_INT
;
5648 } else if (params
->switch_cfg
== ELINK_SWITCH_CFG_10G
) {
5649 mask
= (ELINK_NIG_MASK_XGXS0_LINK10G
|
5650 ELINK_NIG_MASK_XGXS0_LINK_STATUS
);
5651 PMD_DRV_LOG(DEBUG
, "enabled XGXS interrupt");
5652 if (!(ELINK_SINGLE_MEDIA_DIRECT(params
)) &&
5653 params
->phy
[ELINK_INT_PHY
].type
!=
5654 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
) {
5655 mask
|= ELINK_NIG_MASK_MI_INT
;
5656 PMD_DRV_LOG(DEBUG
, "enabled external phy int");
5659 } else { /* SerDes */
5660 mask
= ELINK_NIG_MASK_SERDES0_LINK_STATUS
;
5661 PMD_DRV_LOG(DEBUG
, "enabled SerDes interrupt");
5662 if (!(ELINK_SINGLE_MEDIA_DIRECT(params
)) &&
5663 params
->phy
[ELINK_INT_PHY
].type
!=
5664 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN
) {
5665 mask
|= ELINK_NIG_MASK_MI_INT
;
5666 PMD_DRV_LOG(DEBUG
, "enabled external phy int");
5669 elink_bits_en(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
* 4, mask
);
5671 PMD_DRV_LOG(DEBUG
, "port %x, is_xgxs %x, int_status 0x%x", port
,
5672 (params
->switch_cfg
== ELINK_SWITCH_CFG_10G
),
5673 REG_RD(sc
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
* 4));
5674 PMD_DRV_LOG(DEBUG
, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x",
5675 REG_RD(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
* 4),
5676 REG_RD(sc
, NIG_REG_EMAC0_STATUS_MISC_MI_INT
+ port
* 0x18),
5678 NIG_REG_SERDES0_STATUS_LINK_STATUS
+ port
* 0x3c));
5679 PMD_DRV_LOG(DEBUG
, " 10G %x, XGXS_LINK %x",
5680 REG_RD(sc
, NIG_REG_XGXS0_STATUS_LINK10G
+ port
* 0x68),
5681 REG_RD(sc
, NIG_REG_XGXS0_STATUS_LINK_STATUS
+ port
* 0x68));
5684 static void elink_rearm_latch_signal(struct bnx2x_softc
*sc
, uint8_t port
,
5687 uint32_t latch_status
= 0;
5689 /* Disable the MI INT ( external phy int ) by writing 1 to the
5690 * status register. Link down indication is high-active-signal,
5691 * so in this case we need to write the status to clear the XOR
5693 /* Read Latched signals */
5694 latch_status
= REG_RD(sc
, NIG_REG_LATCH_STATUS_0
+ port
* 8);
5695 PMD_DRV_LOG(DEBUG
, "latch_status = 0x%x", latch_status
);
5696 /* Handle only those with latched-signal=up. */
5699 NIG_REG_STATUS_INTERRUPT_PORT0
5700 + port
* 4, ELINK_NIG_STATUS_EMAC0_MI_INT
);
5703 NIG_REG_STATUS_INTERRUPT_PORT0
5704 + port
* 4, ELINK_NIG_STATUS_EMAC0_MI_INT
);
5706 if (latch_status
& 1) {
5708 /* For all latched-signal=up : Re-Arm Latch signals */
5709 REG_WR(sc
, NIG_REG_LATCH_STATUS_0
+ port
* 8,
5710 (latch_status
& 0xfffe) | (latch_status
& 1));
5712 /* For all latched-signal=up,Write original_signal to status */
5715 static void elink_link_int_ack(struct elink_params
*params
,
5716 struct elink_vars
*vars
, uint8_t is_10g_plus
)
5718 struct bnx2x_softc
*sc
= params
->sc
;
5719 uint8_t port
= params
->port
;
5721 /* First reset all status we assume only one line will be
5724 elink_bits_dis(sc
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
* 4,
5725 (ELINK_NIG_STATUS_XGXS0_LINK10G
|
5726 ELINK_NIG_STATUS_XGXS0_LINK_STATUS
|
5727 ELINK_NIG_STATUS_SERDES0_LINK_STATUS
));
5728 if (vars
->phy_link_up
) {
5729 if (USES_WARPCORE(sc
))
5730 mask
= ELINK_NIG_STATUS_XGXS0_LINK_STATUS
;
5733 mask
= ELINK_NIG_STATUS_XGXS0_LINK10G
;
5734 else if (params
->switch_cfg
== ELINK_SWITCH_CFG_10G
) {
5735 /* Disable the link interrupt by writing 1 to
5736 * the relevant lane in the status register
5739 ((params
->lane_config
&
5740 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
5741 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
5742 mask
= ((1 << ser_lane
) <<
5743 ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE
);
5745 mask
= ELINK_NIG_STATUS_SERDES0_LINK_STATUS
;
5747 PMD_DRV_LOG(DEBUG
, "Ack link up interrupt with mask 0x%x",
5750 NIG_REG_STATUS_INTERRUPT_PORT0
+ port
* 4, mask
);
5754 static elink_status_t
elink_format_ver(uint32_t num
, uint8_t * str
,
5757 uint8_t *str_ptr
= str
;
5758 uint32_t mask
= 0xf0000000;
5759 uint8_t shift
= 8 * 4;
5761 uint8_t remove_leading_zeros
= 1;
5763 /* Need more than 10chars for this format */
5766 return ELINK_STATUS_ERROR
;
5771 digit
= ((num
& mask
) >> shift
);
5772 if (digit
== 0 && remove_leading_zeros
) {
5775 } else if (digit
< 0xa)
5776 *str_ptr
= digit
+ '0';
5778 *str_ptr
= digit
- 0xa + 'a';
5779 remove_leading_zeros
= 0;
5783 if (shift
== 4 * 4) {
5787 remove_leading_zeros
= 1;
5790 return ELINK_STATUS_OK
;
5793 static elink_status_t
elink_null_format_ver(__rte_unused
uint32_t spirom_ver
,
5794 uint8_t * str
, uint16_t * len
)
5798 return ELINK_STATUS_OK
;
5801 static void elink_set_xgxs_loopback(struct elink_phy
*phy
,
5802 struct elink_params
*params
)
5804 uint8_t port
= params
->port
;
5805 struct bnx2x_softc
*sc
= params
->sc
;
5807 if (phy
->req_line_speed
!= ELINK_SPEED_1000
) {
5808 uint32_t md_devad
= 0;
5810 PMD_DRV_LOG(DEBUG
, "XGXS 10G loopback enable");
5812 if (!CHIP_IS_E3(sc
)) {
5813 /* Change the uni_phy_addr in the nig */
5814 md_devad
= REG_RD(sc
, (NIG_REG_XGXS0_CTRL_MD_DEVAD
+
5817 REG_WR(sc
, NIG_REG_XGXS0_CTRL_MD_DEVAD
+ port
* 0x18,
5821 elink_cl45_write(sc
, phy
,
5823 (MDIO_REG_BANK_AER_BLOCK
+
5824 (MDIO_AER_BLOCK_AER_REG
& 0xf)), 0x2800);
5826 elink_cl45_write(sc
, phy
,
5828 (MDIO_REG_BANK_CL73_IEEEB0
+
5829 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL
& 0xf)),
5832 /* Set aer mmd back */
5833 elink_set_aer_mmd(params
, phy
);
5835 if (!CHIP_IS_E3(sc
)) {
5837 REG_WR(sc
, NIG_REG_XGXS0_CTRL_MD_DEVAD
+ port
* 0x18,
5842 PMD_DRV_LOG(DEBUG
, "XGXS 1G loopback enable");
5843 elink_cl45_read(sc
, phy
, 5,
5844 (MDIO_REG_BANK_COMBO_IEEE0
+
5845 (MDIO_COMBO_IEEE0_MII_CONTROL
& 0xf)),
5847 elink_cl45_write(sc
, phy
, 5,
5848 (MDIO_REG_BANK_COMBO_IEEE0
+
5849 (MDIO_COMBO_IEEE0_MII_CONTROL
& 0xf)),
5851 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK
);
5855 elink_status_t
elink_set_led(struct elink_params
*params
,
5856 struct elink_vars
*vars
, uint8_t mode
,
5859 uint8_t port
= params
->port
;
5860 uint16_t hw_led_mode
= params
->hw_led_mode
;
5861 elink_status_t rc
= ELINK_STATUS_OK
;
5864 uint32_t emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
5865 struct bnx2x_softc
*sc
= params
->sc
;
5866 PMD_DRV_LOG(DEBUG
, "elink_set_led: port %x, mode %d", port
, mode
);
5867 PMD_DRV_LOG(DEBUG
, "speed 0x%x, hw_led_mode 0x%x", speed
, hw_led_mode
);
5869 for (phy_idx
= ELINK_EXT_PHY1
; phy_idx
< ELINK_MAX_PHYS
; phy_idx
++) {
5870 if (params
->phy
[phy_idx
].set_link_led
) {
5871 params
->phy
[phy_idx
].set_link_led(¶ms
->phy
[phy_idx
],
5877 case ELINK_LED_MODE_FRONT_PANEL_OFF
:
5878 case ELINK_LED_MODE_OFF
:
5879 REG_WR(sc
, NIG_REG_LED_10G_P0
+ port
* 4, 0);
5880 REG_WR(sc
, NIG_REG_LED_MODE_P0
+ port
* 4,
5881 SHARED_HW_CFG_LED_MAC1
);
5883 tmp
= elink_cb_reg_read(sc
, emac_base
+ EMAC_REG_EMAC_LED
);
5884 if (params
->phy
[ELINK_EXT_PHY1
].type
==
5885 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE
)
5886 tmp
&= ~(EMAC_LED_1000MB_OVERRIDE
|
5887 EMAC_LED_100MB_OVERRIDE
|
5888 EMAC_LED_10MB_OVERRIDE
);
5890 tmp
|= EMAC_LED_OVERRIDE
;
5892 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_LED
, tmp
);
5895 case ELINK_LED_MODE_OPER
:
5896 /* For all other phys, OPER mode is same as ON, so in case
5897 * link is down, do nothing
5902 case ELINK_LED_MODE_ON
:
5903 if (((params
->phy
[ELINK_EXT_PHY1
].type
==
5904 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727
) ||
5905 (params
->phy
[ELINK_EXT_PHY1
].type
==
5906 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722
)) &&
5907 CHIP_IS_E2(sc
) && params
->num_phys
== 2) {
5908 /* This is a work-around for E2+8727 Configurations */
5909 if (mode
== ELINK_LED_MODE_ON
||
5910 speed
== ELINK_SPEED_10000
) {
5911 REG_WR(sc
, NIG_REG_LED_MODE_P0
+ port
* 4, 0);
5912 REG_WR(sc
, NIG_REG_LED_10G_P0
+ port
* 4, 1);
5915 elink_cb_reg_read(sc
,
5918 elink_cb_reg_write(sc
,
5921 (tmp
| EMAC_LED_OVERRIDE
));
5922 /* Return here without enabling traffic
5923 * LED blink and setting rate in ON mode.
5924 * In oper mode, enabling LED blink
5925 * and setting rate is needed.
5927 if (mode
== ELINK_LED_MODE_ON
)
5930 } else if (ELINK_SINGLE_MEDIA_DIRECT(params
)) {
5931 /* This is a work-around for HW issue found when link
5934 if ((!CHIP_IS_E3(sc
)) ||
5935 (CHIP_IS_E3(sc
) && mode
== ELINK_LED_MODE_ON
))
5936 REG_WR(sc
, NIG_REG_LED_10G_P0
+ port
* 4, 1);
5938 if (CHIP_IS_E1x(sc
) ||
5939 CHIP_IS_E2(sc
) || (mode
== ELINK_LED_MODE_ON
))
5940 REG_WR(sc
, NIG_REG_LED_MODE_P0
+ port
* 4, 0);
5942 REG_WR(sc
, NIG_REG_LED_MODE_P0
+ port
* 4,
5944 } else if ((params
->phy
[ELINK_EXT_PHY1
].type
==
5945 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE
) &&
5946 (mode
== ELINK_LED_MODE_ON
)) {
5947 REG_WR(sc
, NIG_REG_LED_MODE_P0
+ port
* 4, 0);
5949 elink_cb_reg_read(sc
,
5950 emac_base
+ EMAC_REG_EMAC_LED
);
5951 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_LED
,
5952 tmp
| EMAC_LED_OVERRIDE
|
5953 EMAC_LED_1000MB_OVERRIDE
);
5954 /* Break here; otherwise, it'll disable the
5955 * intended override.
5959 uint32_t nig_led_mode
= ((params
->hw_led_mode
<<
5960 SHARED_HW_CFG_LED_MODE_SHIFT
)
5962 SHARED_HW_CFG_LED_EXTPHY2
)
5963 ? (SHARED_HW_CFG_LED_PHY1
>>
5964 SHARED_HW_CFG_LED_MODE_SHIFT
) : hw_led_mode
;
5965 REG_WR(sc
, NIG_REG_LED_MODE_P0
+ port
* 4,
5969 REG_WR(sc
, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
+ port
* 4,
5971 /* Set blinking rate to ~15.9Hz */
5973 REG_WR(sc
, NIG_REG_LED_CONTROL_BLINK_RATE_P0
+ port
* 4,
5974 LED_BLINK_RATE_VAL_E3
);
5976 REG_WR(sc
, NIG_REG_LED_CONTROL_BLINK_RATE_P0
+ port
* 4,
5977 LED_BLINK_RATE_VAL_E1X_E2
);
5978 REG_WR(sc
, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0
+ port
* 4, 1);
5979 tmp
= elink_cb_reg_read(sc
, emac_base
+ EMAC_REG_EMAC_LED
);
5980 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_LED
,
5981 (tmp
& (~EMAC_LED_OVERRIDE
)));
5986 rc
= ELINK_STATUS_ERROR
;
5987 PMD_DRV_LOG(DEBUG
, "elink_set_led: Invalid led mode %d", mode
);
5994 static elink_status_t
elink_link_initialize(struct elink_params
*params
,
5995 struct elink_vars
*vars
)
5997 elink_status_t rc
= ELINK_STATUS_OK
;
5998 uint8_t phy_index
, non_ext_phy
;
5999 struct bnx2x_softc
*sc
= params
->sc
;
6000 /* In case of external phy existence, the line speed would be the
6001 * line speed linked up by the external phy. In case it is direct
6002 * only, then the line_speed during initialization will be
6003 * equal to the req_line_speed
6005 vars
->line_speed
= params
->phy
[ELINK_INT_PHY
].req_line_speed
;
6007 /* Initialize the internal phy in case this is a direct board
6008 * (no external phys), or this board has external phy which requires
6011 if (!USES_WARPCORE(sc
))
6012 elink_prepare_xgxs(¶ms
->phy
[ELINK_INT_PHY
], params
, vars
);
6013 /* init ext phy and enable link state int */
6014 non_ext_phy
= (ELINK_SINGLE_MEDIA_DIRECT(params
) ||
6015 (params
->loopback_mode
== ELINK_LOOPBACK_XGXS
));
6018 (params
->phy
[ELINK_EXT_PHY1
].flags
& ELINK_FLAGS_INIT_XGXS_FIRST
) ||
6019 (params
->loopback_mode
== ELINK_LOOPBACK_EXT_PHY
)) {
6020 struct elink_phy
*phy
= ¶ms
->phy
[ELINK_INT_PHY
];
6021 if (vars
->line_speed
== ELINK_SPEED_AUTO_NEG
&&
6022 (CHIP_IS_E1x(sc
) || CHIP_IS_E2(sc
)))
6023 elink_set_parallel_detection(phy
, params
);
6024 if (params
->phy
[ELINK_INT_PHY
].config_init
)
6025 params
->phy
[ELINK_INT_PHY
].config_init(phy
,
6029 /* Re-read this value in case it was changed inside config_init due to
6030 * limitations of optic module
6032 vars
->line_speed
= params
->phy
[ELINK_INT_PHY
].req_line_speed
;
6034 /* Init external phy */
6036 if (params
->phy
[ELINK_INT_PHY
].supported
&
6037 ELINK_SUPPORTED_FIBRE
)
6038 vars
->link_status
|= LINK_STATUS_SERDES_LINK
;
6040 for (phy_index
= ELINK_EXT_PHY1
; phy_index
< params
->num_phys
;
6042 /* No need to initialize second phy in case of first
6043 * phy only selection. In case of second phy, we do
6044 * need to initialize the first phy, since they are
6047 if (params
->phy
[phy_index
].supported
&
6048 ELINK_SUPPORTED_FIBRE
)
6049 vars
->link_status
|= LINK_STATUS_SERDES_LINK
;
6051 if (phy_index
== ELINK_EXT_PHY2
&&
6052 (elink_phy_selection(params
) ==
6053 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
)) {
6055 "Not initializing second phy");
6058 params
->phy
[phy_index
].config_init(¶ms
->
6063 /* Reset the interrupt indication after phy was initialized */
6064 elink_bits_dis(sc
, NIG_REG_STATUS_INTERRUPT_PORT0
+
6066 (ELINK_NIG_STATUS_XGXS0_LINK10G
|
6067 ELINK_NIG_STATUS_XGXS0_LINK_STATUS
|
6068 ELINK_NIG_STATUS_SERDES0_LINK_STATUS
|
6069 ELINK_NIG_MASK_MI_INT
));
6073 static void elink_int_link_reset(__rte_unused
struct elink_phy
*phy
,
6074 struct elink_params
*params
)
6076 /* Reset the SerDes/XGXS */
6077 REG_WR(params
->sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_CLEAR
,
6078 (0x1ff << (params
->port
* 16)));
6081 static void elink_common_ext_link_reset(__rte_unused
struct elink_phy
*phy
,
6082 struct elink_params
*params
)
6084 struct bnx2x_softc
*sc
= params
->sc
;
6088 gpio_port
= SC_PATH(sc
);
6090 gpio_port
= params
->port
;
6091 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_1
,
6092 MISC_REGISTERS_GPIO_OUTPUT_LOW
, gpio_port
);
6093 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
6094 MISC_REGISTERS_GPIO_OUTPUT_LOW
, gpio_port
);
6095 PMD_DRV_LOG(DEBUG
, "reset external PHY");
6098 static elink_status_t
elink_update_link_down(struct elink_params
*params
,
6099 struct elink_vars
*vars
)
6101 struct bnx2x_softc
*sc
= params
->sc
;
6102 uint8_t port
= params
->port
;
6104 PMD_DRV_LOG(DEBUG
, "Port %x: Link is down", port
);
6105 elink_set_led(params
, vars
, ELINK_LED_MODE_OFF
, 0);
6106 vars
->phy_flags
&= ~PHY_PHYSICAL_LINK_FLAG
;
6107 /* Indicate no mac active */
6108 vars
->mac_type
= ELINK_MAC_TYPE_NONE
;
6110 /* Update shared memory */
6111 vars
->link_status
&= ~ELINK_LINK_UPDATE_MASK
;
6112 vars
->line_speed
= 0;
6113 elink_update_mng(params
, vars
->link_status
);
6115 /* Activate nig drain */
6116 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ port
* 4, 1);
6119 if (!CHIP_IS_E3(sc
))
6120 REG_WR(sc
, NIG_REG_NIG_EMAC0_EN
+ port
* 4, 0);
6123 /* Reset BigMac/Xmac */
6124 if (CHIP_IS_E1x(sc
) || CHIP_IS_E2(sc
))
6125 elink_set_bmac_rx(sc
, params
->port
, 0);
6127 if (CHIP_IS_E3(sc
)) {
6128 /* Prevent LPI Generation by chip */
6129 REG_WR(sc
, MISC_REG_CPMU_LP_FW_ENABLE_P0
+ (params
->port
<< 2),
6131 REG_WR(sc
, MISC_REG_CPMU_LP_MASK_ENT_P0
+ (params
->port
<< 2),
6133 vars
->eee_status
&= ~(SHMEM_EEE_LP_ADV_STATUS_MASK
|
6134 SHMEM_EEE_ACTIVE_BIT
);
6136 elink_update_mng_eee(params
, vars
->eee_status
);
6137 elink_set_xmac_rxtx(params
, 0);
6138 elink_set_umac_rxtx(params
, 0);
6141 return ELINK_STATUS_OK
;
6144 static elink_status_t
elink_update_link_up(struct elink_params
*params
,
6145 struct elink_vars
*vars
,
6148 struct bnx2x_softc
*sc
= params
->sc
;
6149 uint8_t phy_idx
, port
= params
->port
;
6150 elink_status_t rc
= ELINK_STATUS_OK
;
6152 vars
->link_status
|= (LINK_STATUS_LINK_UP
|
6153 LINK_STATUS_PHYSICAL_LINK_FLAG
);
6154 vars
->phy_flags
|= PHY_PHYSICAL_LINK_FLAG
;
6156 if (vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
)
6157 vars
->link_status
|= LINK_STATUS_TX_FLOW_CONTROL_ENABLED
;
6159 if (vars
->flow_ctrl
& ELINK_FLOW_CTRL_RX
)
6160 vars
->link_status
|= LINK_STATUS_RX_FLOW_CONTROL_ENABLED
;
6161 if (USES_WARPCORE(sc
)) {
6163 if (elink_xmac_enable(params
, vars
, 0) ==
6164 ELINK_STATUS_NO_LINK
) {
6165 PMD_DRV_LOG(DEBUG
, "Found errors on XMAC");
6167 vars
->phy_flags
|= PHY_HALF_OPEN_CONN_FLAG
;
6168 vars
->link_status
&= ~LINK_STATUS_LINK_UP
;
6171 elink_umac_enable(params
, vars
, 0);
6172 elink_set_led(params
, vars
,
6173 ELINK_LED_MODE_OPER
, vars
->line_speed
);
6175 if ((vars
->eee_status
& SHMEM_EEE_ACTIVE_BIT
) &&
6176 (vars
->eee_status
& SHMEM_EEE_LPI_REQUESTED_BIT
)) {
6177 PMD_DRV_LOG(DEBUG
, "Enabling LPI assertion");
6178 REG_WR(sc
, MISC_REG_CPMU_LP_FW_ENABLE_P0
+
6179 (params
->port
<< 2), 1);
6180 REG_WR(sc
, MISC_REG_CPMU_LP_DR_ENABLE
, 1);
6181 REG_WR(sc
, MISC_REG_CPMU_LP_MASK_ENT_P0
+
6182 (params
->port
<< 2), 0xfc20);
6185 if ((CHIP_IS_E1x(sc
) || CHIP_IS_E2(sc
))) {
6187 if (elink_bmac_enable(params
, vars
, 0, 1) ==
6188 ELINK_STATUS_NO_LINK
) {
6189 PMD_DRV_LOG(DEBUG
, "Found errors on BMAC");
6191 vars
->phy_flags
|= PHY_HALF_OPEN_CONN_FLAG
;
6192 vars
->link_status
&= ~LINK_STATUS_LINK_UP
;
6195 elink_set_led(params
, vars
,
6196 ELINK_LED_MODE_OPER
, ELINK_SPEED_10000
);
6198 rc
= elink_emac_program(params
, vars
);
6199 elink_emac_enable(params
, vars
, 0);
6202 if ((vars
->link_status
&
6203 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
)
6204 && (!(vars
->phy_flags
& PHY_SGMII_FLAG
)) &&
6205 ELINK_SINGLE_MEDIA_DIRECT(params
))
6206 elink_set_gmii_tx_driver(params
);
6211 if (CHIP_IS_E1x(sc
))
6212 rc
|= elink_pbf_update(params
, vars
->flow_ctrl
,
6216 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ port
* 4, 0);
6218 /* Update shared memory */
6219 elink_update_mng(params
, vars
->link_status
);
6220 elink_update_mng_eee(params
, vars
->eee_status
);
6221 /* Check remote fault */
6222 for (phy_idx
= ELINK_INT_PHY
; phy_idx
< ELINK_MAX_PHYS
; phy_idx
++) {
6223 if (params
->phy
[phy_idx
].flags
& ELINK_FLAGS_TX_ERROR_CHECK
) {
6224 elink_check_half_open_conn(params
, vars
, 0);
6232 /* The elink_link_update function should be called upon link
6234 * Link is considered up as follows:
6235 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6237 * - SINGLE_MEDIA - The link between the 577xx and the external
6238 * phy (XGXS) need to up as well as the external link of the
6240 * - DUAL_MEDIA - The link between the 577xx and the first
6241 * external phy needs to be up, and at least one of the 2
6242 * external phy link must be up.
6244 elink_status_t
elink_link_update(struct elink_params
* params
,
6245 struct elink_vars
* vars
)
6247 struct bnx2x_softc
*sc
= params
->sc
;
6248 struct elink_vars phy_vars
[ELINK_MAX_PHYS
];
6249 uint8_t port
= params
->port
;
6250 uint8_t link_10g_plus
, phy_index
;
6251 uint8_t ext_phy_link_up
= 0, cur_link_up
;
6252 elink_status_t rc
= ELINK_STATUS_OK
;
6253 __rte_unused
uint8_t is_mi_int
= 0;
6254 uint16_t ext_phy_line_speed
= 0, prev_line_speed
= vars
->line_speed
;
6255 uint8_t active_external_phy
= ELINK_INT_PHY
;
6256 vars
->phy_flags
&= ~PHY_HALF_OPEN_CONN_FLAG
;
6257 vars
->link_status
&= ~ELINK_LINK_UPDATE_MASK
;
6258 for (phy_index
= ELINK_INT_PHY
; phy_index
< params
->num_phys
;
6260 phy_vars
[phy_index
].flow_ctrl
= 0;
6261 phy_vars
[phy_index
].link_status
= ETH_LINK_DOWN
;
6262 phy_vars
[phy_index
].line_speed
= 0;
6263 phy_vars
[phy_index
].duplex
= DUPLEX_FULL
;
6264 phy_vars
[phy_index
].phy_link_up
= 0;
6265 phy_vars
[phy_index
].link_up
= 0;
6266 phy_vars
[phy_index
].fault_detected
= 0;
6267 /* different consideration, since vars holds inner state */
6268 phy_vars
[phy_index
].eee_status
= vars
->eee_status
;
6271 if (USES_WARPCORE(sc
))
6272 elink_set_aer_mmd(params
, ¶ms
->phy
[ELINK_INT_PHY
]);
6274 PMD_DRV_LOG(DEBUG
, "port %x, XGXS?%x, int_status 0x%x",
6275 port
, (vars
->phy_flags
& PHY_XGXS_FLAG
),
6276 REG_RD(sc
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
* 4));
6278 is_mi_int
= (uint8_t) (REG_RD(sc
, NIG_REG_EMAC0_STATUS_MISC_MI_INT
+
6280 PMD_DRV_LOG(DEBUG
, "int_mask 0x%x MI_INT %x, SERDES_LINK %x",
6281 REG_RD(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
* 4),
6284 NIG_REG_SERDES0_STATUS_LINK_STATUS
+ port
* 0x3c));
6286 PMD_DRV_LOG(DEBUG
, " 10G %x, XGXS_LINK %x",
6287 REG_RD(sc
, NIG_REG_XGXS0_STATUS_LINK10G
+ port
* 0x68),
6288 REG_RD(sc
, NIG_REG_XGXS0_STATUS_LINK_STATUS
+ port
* 0x68));
6291 if (!CHIP_IS_E3(sc
))
6292 REG_WR(sc
, NIG_REG_NIG_EMAC0_EN
+ port
* 4, 0);
6295 * Check external link change only for external phys, and apply
6296 * priority selection between them in case the link on both phys
6297 * is up. Note that instead of the common vars, a temporary
6298 * vars argument is used since each phy may have different link/
6299 * speed/duplex result
6301 for (phy_index
= ELINK_EXT_PHY1
; phy_index
< params
->num_phys
;
6303 struct elink_phy
*phy
= ¶ms
->phy
[phy_index
];
6304 if (!phy
->read_status
)
6306 /* Read link status and params of this ext phy */
6307 cur_link_up
= phy
->read_status(phy
, params
,
6308 &phy_vars
[phy_index
]);
6310 PMD_DRV_LOG(DEBUG
, "phy in index %d link is up",
6313 PMD_DRV_LOG(DEBUG
, "phy in index %d link is down",
6318 if (!ext_phy_link_up
) {
6319 ext_phy_link_up
= 1;
6320 active_external_phy
= phy_index
;
6322 switch (elink_phy_selection(params
)) {
6323 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT
:
6324 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY
:
6325 /* In this option, the first PHY makes sure to pass the
6326 * traffic through itself only.
6327 * Its not clear how to reset the link on the second phy
6329 active_external_phy
= ELINK_EXT_PHY1
;
6331 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY
:
6332 /* In this option, the first PHY makes sure to pass the
6333 * traffic through the second PHY.
6335 active_external_phy
= ELINK_EXT_PHY2
;
6338 /* Link indication on both PHYs with the following cases
6340 * - FIRST_PHY means that second phy wasn't initialized,
6341 * hence its link is expected to be down
6342 * - SECOND_PHY means that first phy should not be able
6343 * to link up by itself (using configuration)
6344 * - DEFAULT should be overriden during initialiazation
6346 PMD_DRV_LOG(DEBUG
, "Invalid link indication"
6347 "mpc=0x%x. DISABLING LINK !!!",
6348 params
->multi_phy_config
);
6349 ext_phy_link_up
= 0;
6354 prev_line_speed
= vars
->line_speed
;
6356 * Read the status of the internal phy. In case of
6357 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6358 * otherwise this is the link between the 577xx and the first
6361 if (params
->phy
[ELINK_INT_PHY
].read_status
)
6362 params
->phy
[ELINK_INT_PHY
].read_status(¶ms
->
6365 /* The INT_PHY flow control reside in the vars. This include the
6366 * case where the speed or flow control are not set to AUTO.
6367 * Otherwise, the active external phy flow control result is set
6368 * to the vars. The ext_phy_line_speed is needed to check if the
6369 * speed is different between the internal phy and external phy.
6370 * This case may be result of intermediate link speed change.
6372 if (active_external_phy
> ELINK_INT_PHY
) {
6373 vars
->flow_ctrl
= phy_vars
[active_external_phy
].flow_ctrl
;
6374 /* Link speed is taken from the XGXS. AN and FC result from
6377 vars
->link_status
|= phy_vars
[active_external_phy
].link_status
;
6379 /* if active_external_phy is first PHY and link is up - disable
6380 * disable TX on second external PHY
6382 if (active_external_phy
== ELINK_EXT_PHY1
) {
6383 if (params
->phy
[ELINK_EXT_PHY2
].phy_specific_func
) {
6384 PMD_DRV_LOG(DEBUG
, "Disabling TX on EXT_PHY2");
6385 params
->phy
[ELINK_EXT_PHY2
].
6386 phy_specific_func(¶ms
->
6387 phy
[ELINK_EXT_PHY2
],
6388 params
, ELINK_DISABLE_TX
);
6392 ext_phy_line_speed
= phy_vars
[active_external_phy
].line_speed
;
6393 vars
->duplex
= phy_vars
[active_external_phy
].duplex
;
6394 if (params
->phy
[active_external_phy
].supported
&
6395 ELINK_SUPPORTED_FIBRE
)
6396 vars
->link_status
|= LINK_STATUS_SERDES_LINK
;
6398 vars
->link_status
&= ~LINK_STATUS_SERDES_LINK
;
6400 vars
->eee_status
= phy_vars
[active_external_phy
].eee_status
;
6402 PMD_DRV_LOG(DEBUG
, "Active external phy selected: %x",
6403 active_external_phy
);
6406 for (phy_index
= ELINK_EXT_PHY1
; phy_index
< params
->num_phys
;
6408 if (params
->phy
[phy_index
].flags
&
6409 ELINK_FLAGS_REARM_LATCH_SIGNAL
) {
6410 elink_rearm_latch_signal(sc
, port
,
6412 active_external_phy
);
6416 PMD_DRV_LOG(DEBUG
, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6417 " ext_phy_line_speed = %d", vars
->flow_ctrl
,
6418 vars
->link_status
, ext_phy_line_speed
);
6419 /* Upon link speed change set the NIG into drain mode. Comes to
6420 * deals with possible FIFO glitch due to clk change when speed
6421 * is decreased without link down indicator
6424 if (vars
->phy_link_up
) {
6425 if (!(ELINK_SINGLE_MEDIA_DIRECT(params
)) && ext_phy_link_up
&&
6426 (ext_phy_line_speed
!= vars
->line_speed
)) {
6427 PMD_DRV_LOG(DEBUG
, "Internal link speed %d is"
6428 " different than the external"
6429 " link speed %d", vars
->line_speed
,
6430 ext_phy_line_speed
);
6431 vars
->phy_link_up
= 0;
6432 } else if (prev_line_speed
!= vars
->line_speed
) {
6434 NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4,
6440 /* Anything 10 and over uses the bmac */
6441 link_10g_plus
= (vars
->line_speed
>= ELINK_SPEED_10000
);
6443 elink_link_int_ack(params
, vars
, link_10g_plus
);
6445 /* In case external phy link is up, and internal link is down
6446 * (not initialized yet probably after link initialization, it
6447 * needs to be initialized.
6448 * Note that after link down-up as result of cable plug, the xgxs
6449 * link would probably become up again without the need
6452 if (!(ELINK_SINGLE_MEDIA_DIRECT(params
))) {
6453 PMD_DRV_LOG(DEBUG
, "ext_phy_link_up = %d, int_link_up = %d,"
6454 " init_preceding = %d", ext_phy_link_up
,
6456 params
->phy
[ELINK_EXT_PHY1
].flags
&
6457 ELINK_FLAGS_INIT_XGXS_FIRST
);
6458 if (!(params
->phy
[ELINK_EXT_PHY1
].flags
&
6459 ELINK_FLAGS_INIT_XGXS_FIRST
)
6460 && ext_phy_link_up
&& !vars
->phy_link_up
) {
6461 vars
->line_speed
= ext_phy_line_speed
;
6462 if (vars
->line_speed
< ELINK_SPEED_1000
)
6463 vars
->phy_flags
|= PHY_SGMII_FLAG
;
6465 vars
->phy_flags
&= ~PHY_SGMII_FLAG
;
6467 if (params
->phy
[ELINK_INT_PHY
].config_init
)
6468 params
->phy
[ELINK_INT_PHY
].config_init(¶ms
->
6475 /* Link is up only if both local phy and external phy (in case of
6476 * non-direct board) are up and no fault detected on active PHY.
6478 vars
->link_up
= (vars
->phy_link_up
&&
6480 ELINK_SINGLE_MEDIA_DIRECT(params
)) &&
6481 (phy_vars
[active_external_phy
].fault_detected
== 0));
6483 /* Update the PFC configuration in case it was changed */
6484 if (params
->feature_config_flags
& ELINK_FEATURE_CONFIG_PFC_ENABLED
)
6485 vars
->link_status
|= LINK_STATUS_PFC_ENABLED
;
6487 vars
->link_status
&= ~LINK_STATUS_PFC_ENABLED
;
6490 rc
= elink_update_link_up(params
, vars
, link_10g_plus
);
6492 rc
= elink_update_link_down(params
, vars
);
6494 /* Update MCP link status was changed */
6496 feature_config_flags
& ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX
)
6497 elink_cb_fw_command(sc
, DRV_MSG_CODE_LINK_STATUS_CHANGED
, 0);
6502 /*****************************************************************************/
6503 /* External Phy section */
6504 /*****************************************************************************/
6505 static void elink_ext_phy_hw_reset(struct bnx2x_softc
*sc
, uint8_t port
)
6507 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_1
,
6508 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
6510 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_1
,
6511 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, port
);
6514 static void elink_save_spirom_version(struct bnx2x_softc
*sc
,
6515 __rte_unused
uint8_t port
,
6516 uint32_t spirom_ver
, uint32_t ver_addr
)
6518 PMD_DRV_LOG(DEBUG
, "FW version 0x%x:0x%x for port %d",
6519 (uint16_t) (spirom_ver
>> 16), (uint16_t) spirom_ver
, port
);
6522 REG_WR(sc
, ver_addr
, spirom_ver
);
6525 static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc
*sc
,
6526 struct elink_phy
*phy
, uint8_t port
)
6528 uint16_t fw_ver1
, fw_ver2
;
6530 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
,
6531 MDIO_PMA_REG_ROM_VER1
, &fw_ver1
);
6532 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
,
6533 MDIO_PMA_REG_ROM_VER2
, &fw_ver2
);
6534 elink_save_spirom_version(sc
, port
,
6535 (uint32_t) (fw_ver1
<< 16 | fw_ver2
),
6539 static void elink_ext_phy_10G_an_resolve(struct bnx2x_softc
*sc
,
6540 struct elink_phy
*phy
,
6541 struct elink_vars
*vars
)
6544 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_STATUS
, &val
);
6545 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_STATUS
, &val
);
6547 vars
->link_status
|= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
6548 if ((val
& (1 << 0)) == 0)
6549 vars
->link_status
|= LINK_STATUS_PARALLEL_DETECTION_USED
;
6552 /******************************************************************/
6553 /* common BNX2X8073/BNX2X8727 PHY SECTION */
6554 /******************************************************************/
6555 static void elink_8073_resolve_fc(struct elink_phy
*phy
,
6556 struct elink_params
*params
,
6557 struct elink_vars
*vars
)
6559 struct bnx2x_softc
*sc
= params
->sc
;
6560 if (phy
->req_line_speed
== ELINK_SPEED_10
||
6561 phy
->req_line_speed
== ELINK_SPEED_100
) {
6562 vars
->flow_ctrl
= phy
->req_flow_ctrl
;
6566 if (elink_ext_phy_resolve_fc(phy
, params
, vars
) &&
6567 (vars
->flow_ctrl
== ELINK_FLOW_CTRL_NONE
)) {
6568 uint16_t pause_result
;
6569 uint16_t ld_pause
; /* local */
6570 uint16_t lp_pause
; /* link partner */
6571 elink_cl45_read(sc
, phy
,
6573 MDIO_AN_REG_CL37_FC_LD
, &ld_pause
);
6575 elink_cl45_read(sc
, phy
,
6577 MDIO_AN_REG_CL37_FC_LP
, &lp_pause
);
6578 pause_result
= (ld_pause
&
6579 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) >> 5;
6580 pause_result
|= (lp_pause
&
6581 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) >> 7;
6583 elink_pause_resolve(vars
, pause_result
);
6584 PMD_DRV_LOG(DEBUG
, "Ext PHY CL37 pause result 0x%x",
6589 static elink_status_t
elink_8073_8727_external_rom_boot(struct bnx2x_softc
*sc
,
6590 struct elink_phy
*phy
,
6594 uint16_t fw_ver1
= 0, fw_msgout
;
6595 elink_status_t rc
= ELINK_STATUS_OK
;
6597 /* Boot port from external ROM */
6599 elink_cl45_write(sc
, phy
,
6600 MDIO_PMA_DEVAD
, MDIO_PMA_REG_GEN_CTRL
, 0x0001);
6602 /* Ucode reboot and rst */
6603 elink_cl45_write(sc
, phy
,
6604 MDIO_PMA_DEVAD
, MDIO_PMA_REG_GEN_CTRL
, 0x008c);
6606 elink_cl45_write(sc
, phy
,
6607 MDIO_PMA_DEVAD
, MDIO_PMA_REG_MISC_CTRL1
, 0x0001);
6609 /* Reset internal microprocessor */
6610 elink_cl45_write(sc
, phy
,
6612 MDIO_PMA_REG_GEN_CTRL
,
6613 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET
);
6615 /* Release srst bit */
6616 elink_cl45_write(sc
, phy
,
6618 MDIO_PMA_REG_GEN_CTRL
,
6619 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP
);
6621 /* Delay 100ms per the PHY specifications */
6624 /* 8073 sometimes taking longer to download */
6629 "elink_8073_8727_external_rom_boot port %x:"
6630 "Download failed. fw version = 0x%x",
6632 rc
= ELINK_STATUS_ERROR
;
6636 elink_cl45_read(sc
, phy
,
6638 MDIO_PMA_REG_ROM_VER1
, &fw_ver1
);
6639 elink_cl45_read(sc
, phy
,
6641 MDIO_PMA_REG_M8051_MSGOUT_REG
, &fw_msgout
);
6644 } while (fw_ver1
== 0 || fw_ver1
== 0x4321 ||
6645 ((fw_msgout
& 0xff) != 0x03 && (phy
->type
==
6646 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073
)));
6648 /* Clear ser_boot_ctl bit */
6649 elink_cl45_write(sc
, phy
,
6650 MDIO_PMA_DEVAD
, MDIO_PMA_REG_MISC_CTRL1
, 0x0000);
6651 elink_save_bnx2x_spirom_ver(sc
, phy
, port
);
6654 "elink_8073_8727_external_rom_boot port %x:"
6655 "Download complete. fw version = 0x%x", port
, fw_ver1
);
6660 /******************************************************************/
6661 /* BNX2X8073 PHY SECTION */
6662 /******************************************************************/
6663 static elink_status_t
elink_8073_is_snr_needed(struct bnx2x_softc
*sc
,
6664 struct elink_phy
*phy
)
6666 /* This is only required for 8073A1, version 102 only */
6669 /* Read 8073 HW revision */
6670 elink_cl45_read(sc
, phy
,
6671 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8073_CHIP_REV
, &val
);
6674 /* No need to workaround in 8073 A1 */
6675 return ELINK_STATUS_OK
;
6678 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_ROM_VER2
, &val
);
6680 /* SNR should be applied only for version 0x102 */
6682 return ELINK_STATUS_OK
;
6684 return ELINK_STATUS_ERROR
;
6687 static elink_status_t
elink_8073_xaui_wa(struct bnx2x_softc
*sc
,
6688 struct elink_phy
*phy
)
6690 uint16_t val
, cnt
, cnt1
;
6692 elink_cl45_read(sc
, phy
,
6693 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8073_CHIP_REV
, &val
);
6696 /* No need to workaround in 8073 A1 */
6697 return ELINK_STATUS_OK
;
6699 /* XAUI workaround in 8073 A0: */
6701 /* After loading the boot ROM and restarting Autoneg, poll
6705 for (cnt
= 0; cnt
< 1000; cnt
++) {
6706 elink_cl45_read(sc
, phy
,
6708 MDIO_PMA_REG_8073_SPEED_LINK_STATUS
, &val
);
6709 /* If bit [14] = 0 or bit [13] = 0, continue on with
6710 * system initialization (XAUI work-around not required, as
6711 * these bits indicate 2.5G or 1G link up).
6713 if (!(val
& (1 << 14)) || !(val
& (1 << 13))) {
6714 PMD_DRV_LOG(DEBUG
, "XAUI work-around not required");
6715 return ELINK_STATUS_OK
;
6716 } else if (!(val
& (1 << 15))) {
6717 PMD_DRV_LOG(DEBUG
, "bit 15 went off");
6718 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6719 * MSB (bit15) goes to 1 (indicating that the XAUI
6720 * workaround has completed), then continue on with
6721 * system initialization.
6723 for (cnt1
= 0; cnt1
< 1000; cnt1
++) {
6724 elink_cl45_read(sc
, phy
,
6726 MDIO_PMA_REG_8073_XAUI_WA
,
6728 if (val
& (1 << 15)) {
6730 "XAUI workaround has completed");
6731 return ELINK_STATUS_OK
;
6739 PMD_DRV_LOG(DEBUG
, "Warning: XAUI work-around timeout !!!");
6740 return ELINK_STATUS_ERROR
;
6743 static void elink_807x_force_10G(struct bnx2x_softc
*sc
, struct elink_phy
*phy
)
6745 /* Force KR or KX */
6746 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x2040);
6747 elink_cl45_write(sc
, phy
,
6748 MDIO_PMA_DEVAD
, MDIO_PMA_REG_10G_CTRL2
, 0x000b);
6749 elink_cl45_write(sc
, phy
,
6750 MDIO_PMA_DEVAD
, MDIO_PMA_REG_BNX2X_CTRL
, 0x0000);
6751 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x0000);
6754 static void elink_8073_set_pause_cl37(struct elink_params
*params
,
6755 struct elink_phy
*phy
,
6756 struct elink_vars
*vars
)
6759 struct bnx2x_softc
*sc
= params
->sc
;
6760 elink_cl45_read(sc
, phy
,
6761 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LD
, &cl37_val
);
6763 cl37_val
&= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
6764 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6765 elink_calc_ieee_aneg_adv(phy
, params
, &vars
->ieee_fc
);
6766 if ((vars
->ieee_fc
&
6767 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC
) ==
6768 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC
) {
6769 cl37_val
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC
;
6771 if ((vars
->ieee_fc
&
6772 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) ==
6773 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) {
6774 cl37_val
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
;
6776 if ((vars
->ieee_fc
&
6777 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) ==
6778 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) {
6779 cl37_val
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
6781 PMD_DRV_LOG(DEBUG
, "Ext phy AN advertize cl37 0x%x", cl37_val
);
6783 elink_cl45_write(sc
, phy
,
6784 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LD
, cl37_val
);
6788 static void elink_8073_specific_func(struct elink_phy
*phy
,
6789 struct elink_params
*params
,
6792 struct bnx2x_softc
*sc
= params
->sc
;
6794 case ELINK_PHY_INIT
:
6796 elink_cl45_write(sc
, phy
,
6797 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
,
6799 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
,
6805 static elink_status_t
elink_8073_config_init(struct elink_phy
*phy
,
6806 struct elink_params
*params
,
6807 struct elink_vars
*vars
)
6809 struct bnx2x_softc
*sc
= params
->sc
;
6810 uint16_t val
= 0, tmp1
;
6812 PMD_DRV_LOG(DEBUG
, "Init 8073");
6815 gpio_port
= SC_PATH(sc
);
6817 gpio_port
= params
->port
;
6818 /* Restore normal power mode */
6819 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
6820 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, gpio_port
);
6822 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_1
,
6823 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, gpio_port
);
6825 elink_8073_specific_func(phy
, params
, ELINK_PHY_INIT
);
6826 elink_8073_set_pause_cl37(params
, phy
, vars
);
6828 elink_cl45_read(sc
, phy
,
6829 MDIO_PMA_DEVAD
, MDIO_PMA_REG_M8051_MSGOUT_REG
, &tmp1
);
6831 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXSTAT
, &tmp1
);
6833 PMD_DRV_LOG(DEBUG
, "Before rom RX_ALARM(port1): 0x%x", tmp1
);
6835 /* Swap polarity if required - Must be done only in non-1G mode */
6836 if (params
->lane_config
& PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED
) {
6837 /* Configure the 8073 to swap _P and _N of the KR lines */
6838 PMD_DRV_LOG(DEBUG
, "Swapping polarity for the 8073");
6839 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6840 elink_cl45_read(sc
, phy
,
6842 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL
, &val
);
6843 elink_cl45_write(sc
, phy
,
6845 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL
,
6849 /* Enable CL37 BAM */
6850 if (REG_RD(sc
, params
->shmem_base
+
6851 offsetof(struct shmem_region
,
6852 dev_info
.port_hw_config
[params
->port
].
6854 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED
) {
6856 elink_cl45_read(sc
, phy
,
6857 MDIO_AN_DEVAD
, MDIO_AN_REG_8073_BAM
, &val
);
6858 elink_cl45_write(sc
, phy
,
6859 MDIO_AN_DEVAD
, MDIO_AN_REG_8073_BAM
, val
| 1);
6860 PMD_DRV_LOG(DEBUG
, "Enable CL37 BAM on KR");
6862 if (params
->loopback_mode
== ELINK_LOOPBACK_EXT
) {
6863 elink_807x_force_10G(sc
, phy
);
6864 PMD_DRV_LOG(DEBUG
, "Forced speed 10G on 807X");
6865 return ELINK_STATUS_OK
;
6867 elink_cl45_write(sc
, phy
,
6868 MDIO_PMA_DEVAD
, MDIO_PMA_REG_BNX2X_CTRL
, 0x0002);
6870 if (phy
->req_line_speed
!= ELINK_SPEED_AUTO_NEG
) {
6871 if (phy
->req_line_speed
== ELINK_SPEED_10000
) {
6873 } else if (phy
->req_line_speed
== ELINK_SPEED_2500
) {
6875 /* Note that 2.5G works only when used with 1G
6882 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
6885 /* Note that 2.5G works only when used with 1G advertisement */
6886 if (phy
->speed_cap_mask
&
6887 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
|
6888 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
))
6890 PMD_DRV_LOG(DEBUG
, "807x autoneg val = 0x%x", val
);
6893 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV
, val
);
6894 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_8073_2_5G
, &tmp1
);
6896 if (((phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
) &&
6897 (phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
)) ||
6898 (phy
->req_line_speed
== ELINK_SPEED_2500
)) {
6900 /* Allow 2.5G for A1 and above */
6901 elink_cl45_read(sc
, phy
,
6902 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8073_CHIP_REV
,
6904 PMD_DRV_LOG(DEBUG
, "Add 2.5G");
6910 PMD_DRV_LOG(DEBUG
, "Disable 2.5G");
6914 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_8073_2_5G
, tmp1
);
6915 /* Add support for CL37 (passive mode) II */
6917 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LD
, &tmp1
);
6918 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LD
,
6919 (tmp1
| ((phy
->req_duplex
== DUPLEX_FULL
) ?
6922 /* Add support for CL37 (passive mode) III */
6923 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_AN
, 0x1000);
6925 /* The SNR will improve about 2db by changing BW and FEE main
6926 * tap. Rest commands are executed after link is up
6927 * Change FFE main cursor to 5 in EDC register
6929 if (elink_8073_is_snr_needed(sc
, phy
))
6930 elink_cl45_write(sc
, phy
,
6931 MDIO_PMA_DEVAD
, MDIO_PMA_REG_EDC_FFE_MAIN
,
6934 /* Enable FEC (Forware Error Correction) Request in the AN */
6935 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV2
, &tmp1
);
6937 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV2
, tmp1
);
6939 elink_ext_phy_set_pause(params
, phy
, vars
);
6941 /* Restart autoneg */
6943 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x1200);
6944 PMD_DRV_LOG(DEBUG
, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x",
6945 ((val
& (1 << 5)) > 0), ((val
& (1 << 7)) > 0));
6946 return ELINK_STATUS_OK
;
6949 static uint8_t elink_8073_read_status(struct elink_phy
*phy
,
6950 struct elink_params
*params
,
6951 struct elink_vars
*vars
)
6953 struct bnx2x_softc
*sc
= params
->sc
;
6954 uint8_t link_up
= 0;
6955 uint16_t val1
, val2
;
6956 uint16_t link_status
= 0;
6957 uint16_t an1000_status
= 0;
6959 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val1
);
6961 PMD_DRV_LOG(DEBUG
, "8703 LASI status 0x%x", val1
);
6963 /* Clear the interrupt LASI status register */
6964 elink_cl45_read(sc
, phy
, MDIO_PCS_DEVAD
, MDIO_PCS_REG_STATUS
, &val2
);
6965 elink_cl45_read(sc
, phy
, MDIO_PCS_DEVAD
, MDIO_PCS_REG_STATUS
, &val1
);
6966 PMD_DRV_LOG(DEBUG
, "807x PCS status 0x%x->0x%x", val2
, val1
);
6968 elink_cl45_read(sc
, phy
,
6969 MDIO_PMA_DEVAD
, MDIO_PMA_REG_M8051_MSGOUT_REG
, &val1
);
6971 /* Check the LASI */
6972 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXSTAT
, &val2
);
6974 PMD_DRV_LOG(DEBUG
, "KR 0x9003 0x%x", val2
);
6976 /* Check the link status */
6977 elink_cl45_read(sc
, phy
, MDIO_PCS_DEVAD
, MDIO_PCS_REG_STATUS
, &val2
);
6978 PMD_DRV_LOG(DEBUG
, "KR PCS status 0x%x", val2
);
6980 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val2
);
6981 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val1
);
6982 link_up
= ((val1
& 4) == 4);
6983 PMD_DRV_LOG(DEBUG
, "PMA_REG_STATUS=0x%x", val1
);
6985 if (link_up
&& ((phy
->req_line_speed
!= ELINK_SPEED_10000
))) {
6986 if (elink_8073_xaui_wa(sc
, phy
) != 0)
6989 elink_cl45_read(sc
, phy
,
6990 MDIO_AN_DEVAD
, MDIO_AN_REG_LINK_STATUS
, &an1000_status
);
6991 elink_cl45_read(sc
, phy
,
6992 MDIO_AN_DEVAD
, MDIO_AN_REG_LINK_STATUS
, &an1000_status
);
6994 /* Check the link status on 1.1.2 */
6995 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val2
);
6996 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val1
);
6997 PMD_DRV_LOG(DEBUG
, "KR PMA status 0x%x->0x%x,"
6998 "an_link_status=0x%x", val2
, val1
, an1000_status
);
7000 link_up
= (((val1
& 4) == 4) || (an1000_status
& (1 << 1)));
7001 if (link_up
&& elink_8073_is_snr_needed(sc
, phy
)) {
7002 /* The SNR will improve about 2dbby changing the BW and FEE main
7003 * tap. The 1st write to change FFE main tap is set before
7004 * restart AN. Change PLL Bandwidth in EDC register
7006 elink_cl45_write(sc
, phy
,
7007 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PLL_BANDWIDTH
,
7010 /* Change CDR Bandwidth in EDC register */
7011 elink_cl45_write(sc
, phy
,
7012 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CDR_BANDWIDTH
,
7015 elink_cl45_read(sc
, phy
,
7016 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8073_SPEED_LINK_STATUS
,
7019 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7020 if ((link_status
& (1 << 2)) && (!(link_status
& (1 << 15)))) {
7022 vars
->line_speed
= ELINK_SPEED_10000
;
7023 PMD_DRV_LOG(DEBUG
, "port %x: External link up in 10G",
7025 } else if ((link_status
& (1 << 1)) && (!(link_status
& (1 << 14)))) {
7027 vars
->line_speed
= ELINK_SPEED_2500
;
7028 PMD_DRV_LOG(DEBUG
, "port %x: External link up in 2.5G",
7030 } else if ((link_status
& (1 << 0)) && (!(link_status
& (1 << 13)))) {
7032 vars
->line_speed
= ELINK_SPEED_1000
;
7033 PMD_DRV_LOG(DEBUG
, "port %x: External link up in 1G",
7037 PMD_DRV_LOG(DEBUG
, "port %x: External link is down",
7042 /* Swap polarity if required */
7043 if (params
->lane_config
& PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED
) {
7044 /* Configure the 8073 to swap P and N of the KR lines */
7045 elink_cl45_read(sc
, phy
,
7047 MDIO_XS_REG_8073_RX_CTRL_PCIE
, &val1
);
7048 /* Set bit 3 to invert Rx in 1G mode and clear this bit
7049 * when it`s in 10G mode.
7051 if (vars
->line_speed
== ELINK_SPEED_1000
) {
7052 PMD_DRV_LOG(DEBUG
, "Swapping 1G polarity for"
7058 elink_cl45_write(sc
, phy
,
7060 MDIO_XS_REG_8073_RX_CTRL_PCIE
, val1
);
7062 elink_ext_phy_10G_an_resolve(sc
, phy
, vars
);
7063 elink_8073_resolve_fc(phy
, params
, vars
);
7064 vars
->duplex
= DUPLEX_FULL
;
7067 if (vars
->link_status
& LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
) {
7068 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
7069 MDIO_AN_REG_LP_AUTO_NEG2
, &val1
);
7071 if (val1
& (1 << 5))
7072 vars
->link_status
|=
7073 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE
;
7074 if (val1
& (1 << 7))
7075 vars
->link_status
|=
7076 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
7082 static void elink_8073_link_reset(__rte_unused
struct elink_phy
*phy
,
7083 struct elink_params
*params
)
7085 struct bnx2x_softc
*sc
= params
->sc
;
7088 gpio_port
= SC_PATH(sc
);
7090 gpio_port
= params
->port
;
7091 PMD_DRV_LOG(DEBUG
, "Setting 8073 port %d into low power mode",
7093 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
7094 MISC_REGISTERS_GPIO_OUTPUT_LOW
, gpio_port
);
7097 /******************************************************************/
7098 /* BNX2X8705 PHY SECTION */
7099 /******************************************************************/
7100 static elink_status_t
elink_8705_config_init(struct elink_phy
*phy
,
7101 struct elink_params
*params
,
7102 __rte_unused
struct elink_vars
7105 struct bnx2x_softc
*sc
= params
->sc
;
7106 PMD_DRV_LOG(DEBUG
, "init 8705");
7107 /* Restore normal power mode */
7108 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
7109 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, params
->port
);
7111 elink_ext_phy_hw_reset(sc
, params
->port
);
7112 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0xa040);
7113 elink_wait_reset_complete(sc
, phy
, params
);
7115 elink_cl45_write(sc
, phy
,
7116 MDIO_PMA_DEVAD
, MDIO_PMA_REG_MISC_CTRL
, 0x8288);
7117 elink_cl45_write(sc
, phy
,
7118 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PHY_IDENTIFIER
, 0x7fbf);
7119 elink_cl45_write(sc
, phy
,
7120 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CMU_PLL_BYPASS
, 0x0100);
7121 elink_cl45_write(sc
, phy
, MDIO_WIS_DEVAD
, MDIO_WIS_REG_LASI_CNTL
, 0x1);
7122 /* BNX2X8705 doesn't have microcode, hence the 0 */
7123 elink_save_spirom_version(sc
, params
->port
, params
->shmem_base
, 0);
7124 return ELINK_STATUS_OK
;
7127 static uint8_t elink_8705_read_status(struct elink_phy
*phy
,
7128 struct elink_params
*params
,
7129 struct elink_vars
*vars
)
7131 uint8_t link_up
= 0;
7132 uint16_t val1
, rx_sd
;
7133 struct bnx2x_softc
*sc
= params
->sc
;
7134 PMD_DRV_LOG(DEBUG
, "read status 8705");
7135 elink_cl45_read(sc
, phy
,
7136 MDIO_WIS_DEVAD
, MDIO_WIS_REG_LASI_STATUS
, &val1
);
7137 PMD_DRV_LOG(DEBUG
, "8705 LASI status 0x%x", val1
);
7139 elink_cl45_read(sc
, phy
,
7140 MDIO_WIS_DEVAD
, MDIO_WIS_REG_LASI_STATUS
, &val1
);
7141 PMD_DRV_LOG(DEBUG
, "8705 LASI status 0x%x", val1
);
7143 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_RX_SD
, &rx_sd
);
7145 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, 0xc809, &val1
);
7146 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, 0xc809, &val1
);
7148 PMD_DRV_LOG(DEBUG
, "8705 1.c809 val=0x%x", val1
);
7149 link_up
= ((rx_sd
& 0x1) && (val1
& (1 << 9))
7150 && ((val1
& (1 << 8)) == 0));
7152 vars
->line_speed
= ELINK_SPEED_10000
;
7153 elink_ext_phy_resolve_fc(phy
, params
, vars
);
7158 /******************************************************************/
7159 /* SFP+ module Section */
7160 /******************************************************************/
7161 static void elink_set_disable_pmd_transmit(struct elink_params
*params
,
7162 struct elink_phy
*phy
,
7165 struct bnx2x_softc
*sc
= params
->sc
;
7166 /* Disable transmitter only for bootcodes which can enable it afterwards
7170 if (params
->feature_config_flags
&
7171 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED
) {
7172 PMD_DRV_LOG(DEBUG
, "Disabling PMD transmitter");
7174 PMD_DRV_LOG(DEBUG
, "NOT disabling PMD transmitter");
7178 PMD_DRV_LOG(DEBUG
, "Enabling PMD transmitter");
7180 elink_cl45_write(sc
, phy
,
7181 MDIO_PMA_DEVAD
, MDIO_PMA_REG_TX_DISABLE
, pmd_dis
);
7184 static uint8_t elink_get_gpio_port(struct elink_params
*params
)
7187 uint32_t swap_val
, swap_override
;
7188 struct bnx2x_softc
*sc
= params
->sc
;
7189 if (CHIP_IS_E2(sc
)) {
7190 gpio_port
= SC_PATH(sc
);
7192 gpio_port
= params
->port
;
7194 swap_val
= REG_RD(sc
, NIG_REG_PORT_SWAP
);
7195 swap_override
= REG_RD(sc
, NIG_REG_STRAP_OVERRIDE
);
7196 return gpio_port
^ (swap_val
&& swap_override
);
7199 static void elink_sfp_e1e2_set_transmitter(struct elink_params
*params
,
7200 struct elink_phy
*phy
, uint8_t tx_en
)
7203 uint8_t port
= params
->port
;
7204 struct bnx2x_softc
*sc
= params
->sc
;
7205 uint32_t tx_en_mode
;
7207 /* Disable/Enable transmitter ( TX laser of the SFP+ module.) */
7208 tx_en_mode
= REG_RD(sc
, params
->shmem_base
+
7209 offsetof(struct shmem_region
,
7210 dev_info
.port_hw_config
[port
].sfp_ctrl
)) &
7211 PORT_HW_CFG_TX_LASER_MASK
;
7212 PMD_DRV_LOG(DEBUG
, "Setting transmitter tx_en=%x for port %x "
7213 "mode = %x", tx_en
, port
, tx_en_mode
);
7214 switch (tx_en_mode
) {
7215 case PORT_HW_CFG_TX_LASER_MDIO
:
7217 elink_cl45_read(sc
, phy
,
7219 MDIO_PMA_REG_PHY_IDENTIFIER
, &val
);
7226 elink_cl45_write(sc
, phy
,
7228 MDIO_PMA_REG_PHY_IDENTIFIER
, val
);
7230 case PORT_HW_CFG_TX_LASER_GPIO0
:
7231 case PORT_HW_CFG_TX_LASER_GPIO1
:
7232 case PORT_HW_CFG_TX_LASER_GPIO2
:
7233 case PORT_HW_CFG_TX_LASER_GPIO3
:
7236 uint8_t gpio_port
, gpio_mode
;
7238 gpio_mode
= MISC_REGISTERS_GPIO_OUTPUT_HIGH
;
7240 gpio_mode
= MISC_REGISTERS_GPIO_OUTPUT_LOW
;
7242 gpio_pin
= tx_en_mode
- PORT_HW_CFG_TX_LASER_GPIO0
;
7243 gpio_port
= elink_get_gpio_port(params
);
7244 elink_cb_gpio_write(sc
, gpio_pin
, gpio_mode
, gpio_port
);
7248 PMD_DRV_LOG(DEBUG
, "Invalid TX_LASER_MDIO 0x%x", tx_en_mode
);
7253 static void elink_sfp_set_transmitter(struct elink_params
*params
,
7254 struct elink_phy
*phy
, uint8_t tx_en
)
7256 struct bnx2x_softc
*sc
= params
->sc
;
7257 PMD_DRV_LOG(DEBUG
, "Setting SFP+ transmitter to %d", tx_en
);
7259 elink_sfp_e3_set_transmitter(params
, phy
, tx_en
);
7261 elink_sfp_e1e2_set_transmitter(params
, phy
, tx_en
);
7264 static elink_status_t
elink_8726_read_sfp_module_eeprom(struct elink_phy
*phy
,
7271 __rte_unused
uint8_t
7274 struct bnx2x_softc
*sc
= params
->sc
;
7277 if (byte_cnt
> ELINK_SFP_EEPROM_PAGE_SIZE
) {
7278 PMD_DRV_LOG(DEBUG
, "Reading from eeprom is limited to 0xf");
7279 return ELINK_STATUS_ERROR
;
7281 /* Set the read command byte count */
7282 elink_cl45_write(sc
, phy
,
7283 MDIO_PMA_DEVAD
, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT
,
7284 (byte_cnt
| (dev_addr
<< 8)));
7286 /* Set the read command address */
7287 elink_cl45_write(sc
, phy
,
7288 MDIO_PMA_DEVAD
, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR
,
7291 /* Activate read command */
7292 elink_cl45_write(sc
, phy
,
7293 MDIO_PMA_DEVAD
, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
,
7296 /* Wait up to 500us for command complete status */
7297 for (i
= 0; i
< 100; i
++) {
7298 elink_cl45_read(sc
, phy
,
7300 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
7301 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
7302 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
)
7307 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) !=
7308 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
) {
7310 "Got bad status 0x%x when reading from SFP+ EEPROM",
7311 (val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
));
7312 return ELINK_STATUS_ERROR
;
7315 /* Read the buffer */
7316 for (i
= 0; i
< byte_cnt
; i
++) {
7317 elink_cl45_read(sc
, phy
,
7319 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF
+ i
, &val
);
7321 (uint8_t) (val
& MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK
);
7324 for (i
= 0; i
< 100; i
++) {
7325 elink_cl45_read(sc
, phy
,
7327 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
7328 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
7329 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE
)
7330 return ELINK_STATUS_OK
;
7333 return ELINK_STATUS_ERROR
;
7336 static void elink_warpcore_power_module(struct elink_params
*params
,
7340 struct bnx2x_softc
*sc
= params
->sc
;
7342 pin_cfg
= (REG_RD(sc
, params
->shmem_base
+
7343 offsetof(struct shmem_region
,
7344 dev_info
.port_hw_config
[params
->port
].
7345 e3_sfp_ctrl
)) & PORT_HW_CFG_E3_PWR_DIS_MASK
)
7346 >> PORT_HW_CFG_E3_PWR_DIS_SHIFT
;
7348 if (pin_cfg
== PIN_CFG_NA
)
7350 PMD_DRV_LOG(DEBUG
, "Setting SFP+ module power to %d using pin cfg %d",
7352 /* Low ==> corresponding SFP+ module is powered
7353 * high ==> the SFP+ module is powered down
7355 elink_set_cfg_pin(sc
, pin_cfg
, power
^ 1);
7358 static elink_status_t
elink_warpcore_read_sfp_module_eeprom(__rte_unused
struct
7368 elink_status_t rc
= ELINK_STATUS_OK
;
7369 uint8_t i
, j
= 0, cnt
= 0;
7370 uint32_t data_array
[4];
7372 struct bnx2x_softc
*sc
= params
->sc
;
7374 if (byte_cnt
> ELINK_SFP_EEPROM_PAGE_SIZE
) {
7376 "Reading from eeprom is limited to 16 bytes");
7377 return ELINK_STATUS_ERROR
;
7380 /* 4 byte aligned address */
7381 addr32
= addr
& (~0x3);
7383 if ((!is_init
) && (cnt
== I2C_WA_PWR_ITER
)) {
7384 elink_warpcore_power_module(params
, 0);
7385 /* Note that 100us are not enough here */
7387 elink_warpcore_power_module(params
, 1);
7389 rc
= elink_bsc_read(params
, sc
, dev_addr
, addr32
, 0, byte_cnt
,
7391 } while ((rc
!= ELINK_STATUS_OK
) && (++cnt
< I2C_WA_RETRY_CNT
));
7393 if (rc
== ELINK_STATUS_OK
) {
7394 for (i
= (addr
- addr32
); i
< byte_cnt
+ (addr
- addr32
); i
++) {
7395 o_buf
[j
] = *((uint8_t *) data_array
+ i
);
7403 static elink_status_t
elink_8727_read_sfp_module_eeprom(struct elink_phy
*phy
,
7410 __rte_unused
uint8_t
7413 struct bnx2x_softc
*sc
= params
->sc
;
7416 if (byte_cnt
> ELINK_SFP_EEPROM_PAGE_SIZE
) {
7417 PMD_DRV_LOG(DEBUG
, "Reading from eeprom is limited to 0xf");
7418 return ELINK_STATUS_ERROR
;
7421 /* Set 2-wire transfer rate of SFP+ module EEPROM
7422 * to 100Khz since some DACs(direct attached cables) do
7423 * not work at 400Khz.
7425 elink_cl45_write(sc
, phy
,
7427 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR
,
7428 ((dev_addr
<< 8) | 1));
7430 /* Need to read from 1.8000 to clear it */
7431 elink_cl45_read(sc
, phy
,
7432 MDIO_PMA_DEVAD
, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
7434 /* Set the read command byte count */
7435 elink_cl45_write(sc
, phy
,
7437 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT
,
7438 ((byte_cnt
< 2) ? 2 : byte_cnt
));
7440 /* Set the read command address */
7441 elink_cl45_write(sc
, phy
,
7443 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR
, addr
);
7444 /* Set the destination address */
7445 elink_cl45_write(sc
, phy
,
7447 0x8004, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF
);
7449 /* Activate read command */
7450 elink_cl45_write(sc
, phy
,
7452 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, 0x8002);
7453 /* Wait appropriate time for two-wire command to finish before
7454 * polling the status register
7458 /* Wait up to 500us for command complete status */
7459 for (i
= 0; i
< 100; i
++) {
7460 elink_cl45_read(sc
, phy
,
7462 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
7463 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
7464 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
)
7469 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) !=
7470 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
) {
7472 "Got bad status 0x%x when reading from SFP+ EEPROM",
7473 (val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
));
7474 return ELINK_STATUS_TIMEOUT
;
7477 /* Read the buffer */
7478 for (i
= 0; i
< byte_cnt
; i
++) {
7479 elink_cl45_read(sc
, phy
,
7481 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF
+ i
, &val
);
7483 (uint8_t) (val
& MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK
);
7486 for (i
= 0; i
< 100; i
++) {
7487 elink_cl45_read(sc
, phy
,
7489 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
7490 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
7491 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE
)
7492 return ELINK_STATUS_OK
;
7496 return ELINK_STATUS_ERROR
;
7499 static elink_status_t
elink_read_sfp_module_eeprom(struct elink_phy
*phy
,
7500 struct elink_params
*params
,
7506 elink_status_t rc
= ELINK_STATUS_OK
;
7508 uint8_t *user_data
= o_buf
;
7509 read_sfp_module_eeprom_func_p read_func
;
7511 if ((dev_addr
!= 0xa0) && (dev_addr
!= 0xa2)) {
7512 PMD_DRV_LOG(DEBUG
, "invalid dev_addr 0x%x", dev_addr
);
7513 return ELINK_STATUS_ERROR
;
7516 switch (phy
->type
) {
7517 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726
:
7518 read_func
= elink_8726_read_sfp_module_eeprom
;
7520 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727
:
7521 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722
:
7522 read_func
= elink_8727_read_sfp_module_eeprom
;
7524 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
7525 read_func
= elink_warpcore_read_sfp_module_eeprom
;
7528 return ELINK_OP_NOT_SUPPORTED
;
7531 while (!rc
&& (byte_cnt
> 0)) {
7532 xfer_size
= (byte_cnt
> ELINK_SFP_EEPROM_PAGE_SIZE
) ?
7533 ELINK_SFP_EEPROM_PAGE_SIZE
: byte_cnt
;
7534 rc
= read_func(phy
, params
, dev_addr
, addr
, xfer_size
,
7536 byte_cnt
-= xfer_size
;
7537 user_data
+= xfer_size
;
7543 static elink_status_t
elink_get_edc_mode(struct elink_phy
*phy
,
7544 struct elink_params
*params
,
7545 uint16_t * edc_mode
)
7547 struct bnx2x_softc
*sc
= params
->sc
;
7548 uint32_t sync_offset
= 0, phy_idx
, media_types
;
7549 uint8_t gport
, val
[2], check_limiting_mode
= 0;
7550 *edc_mode
= ELINK_EDC_MODE_LIMITING
;
7551 phy
->media_type
= ELINK_ETH_PHY_UNSPECIFIED
;
7552 /* First check for copper cable */
7553 if (elink_read_sfp_module_eeprom(phy
,
7555 ELINK_I2C_DEV_ADDR_A0
,
7556 ELINK_SFP_EEPROM_CON_TYPE_ADDR
,
7557 2, (uint8_t *) val
) != 0) {
7558 PMD_DRV_LOG(DEBUG
, "Failed to read from SFP+ module EEPROM");
7559 return ELINK_STATUS_ERROR
;
7563 case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER
:
7565 uint8_t copper_module_type
;
7566 phy
->media_type
= ELINK_ETH_PHY_DA_TWINAX
;
7567 /* Check if its active cable (includes SFP+ module)
7570 if (elink_read_sfp_module_eeprom(phy
,
7572 ELINK_I2C_DEV_ADDR_A0
,
7573 ELINK_SFP_EEPROM_FC_TX_TECH_ADDR
,
7575 &copper_module_type
) !=
7578 "Failed to read copper-cable-type"
7579 " from SFP+ EEPROM");
7580 return ELINK_STATUS_ERROR
;
7583 if (copper_module_type
&
7584 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE
) {
7586 "Active Copper cable detected");
7588 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)
7589 *edc_mode
= ELINK_EDC_MODE_ACTIVE_DAC
;
7591 check_limiting_mode
= 1;
7592 } else if (copper_module_type
&
7593 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE
)
7596 "Passive Copper cable detected");
7597 *edc_mode
= ELINK_EDC_MODE_PASSIVE_DAC
;
7600 "Unknown copper-cable-type 0x%x !!!",
7601 copper_module_type
);
7602 return ELINK_STATUS_ERROR
;
7606 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC
:
7607 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45
:
7608 check_limiting_mode
= 1;
7609 if ((val
[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK
|
7610 ELINK_SFP_EEPROM_COMP_CODE_LR_MASK
|
7611 ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK
)) == 0) {
7612 PMD_DRV_LOG(DEBUG
, "1G SFP module detected");
7613 gport
= params
->port
;
7614 phy
->media_type
= ELINK_ETH_PHY_SFP_1G_FIBER
;
7615 if (phy
->req_line_speed
!= ELINK_SPEED_1000
) {
7616 phy
->req_line_speed
= ELINK_SPEED_1000
;
7617 if (!CHIP_IS_E1x(sc
)) {
7618 gport
= SC_PATH(sc
) +
7619 (params
->port
<< 1);
7621 elink_cb_event_log(sc
, ELINK_LOG_ID_NON_10G_MODULE
, gport
); //"Warning: Link speed was forced to 1000Mbps."
7622 // " Current SFP module in port %d is not"
7623 // " compliant with 10G Ethernet",
7627 int idx
, cfg_idx
= 0;
7628 PMD_DRV_LOG(DEBUG
, "10G Optic module detected");
7629 for (idx
= ELINK_INT_PHY
; idx
< ELINK_MAX_PHYS
; idx
++) {
7630 if (params
->phy
[idx
].type
== phy
->type
) {
7631 cfg_idx
= ELINK_LINK_CONFIG_IDX(idx
);
7635 phy
->media_type
= ELINK_ETH_PHY_SFPP_10G_FIBER
;
7636 phy
->req_line_speed
= params
->req_line_speed
[cfg_idx
];
7640 PMD_DRV_LOG(DEBUG
, "Unable to determine module type 0x%x !!!",
7642 return ELINK_STATUS_ERROR
;
7644 sync_offset
= params
->shmem_base
+
7645 offsetof(struct shmem_region
,
7646 dev_info
.port_hw_config
[params
->port
].media_type
);
7647 media_types
= REG_RD(sc
, sync_offset
);
7648 /* Update media type for non-PMF sync */
7649 for (phy_idx
= ELINK_INT_PHY
; phy_idx
< ELINK_MAX_PHYS
; phy_idx
++) {
7650 if (&(params
->phy
[phy_idx
]) == phy
) {
7651 media_types
&= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK
<<
7652 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT
*
7656 media_type
& PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK
) <<
7657 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT
* phy_idx
));
7661 REG_WR(sc
, sync_offset
, media_types
);
7662 if (check_limiting_mode
) {
7663 uint8_t options
[ELINK_SFP_EEPROM_OPTIONS_SIZE
];
7664 if (elink_read_sfp_module_eeprom(phy
,
7666 ELINK_I2C_DEV_ADDR_A0
,
7667 ELINK_SFP_EEPROM_OPTIONS_ADDR
,
7668 ELINK_SFP_EEPROM_OPTIONS_SIZE
,
7671 "Failed to read Option field from module EEPROM");
7672 return ELINK_STATUS_ERROR
;
7674 if ((options
[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK
))
7675 *edc_mode
= ELINK_EDC_MODE_LINEAR
;
7677 *edc_mode
= ELINK_EDC_MODE_LIMITING
;
7679 PMD_DRV_LOG(DEBUG
, "EDC mode is set to 0x%x", *edc_mode
);
7680 return ELINK_STATUS_OK
;
7683 /* This function read the relevant field from the module (SFP+), and verify it
7684 * is compliant with this board
7686 static elink_status_t
elink_verify_sfp_module(struct elink_phy
*phy
,
7687 struct elink_params
*params
)
7689 struct bnx2x_softc
*sc
= params
->sc
;
7691 uint32_t fw_resp
, fw_cmd_param
;
7692 char vendor_name
[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE
+ 1];
7693 char vendor_pn
[ELINK_SFP_EEPROM_PART_NO_SIZE
+ 1];
7694 phy
->flags
&= ~ELINK_FLAGS_SFP_NOT_APPROVED
;
7695 val
= REG_RD(sc
, params
->shmem_base
+
7696 offsetof(struct shmem_region
,
7697 dev_info
.port_feature_config
[params
->port
].
7699 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
7700 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT
) {
7701 PMD_DRV_LOG(DEBUG
, "NOT enforcing module verification");
7702 return ELINK_STATUS_OK
;
7705 if (params
->feature_config_flags
&
7706 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY
) {
7707 /* Use specific phy request */
7708 cmd
= DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL
;
7709 } else if (params
->feature_config_flags
&
7710 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY
) {
7711 /* Use first phy request only in case of non-dual media */
7712 if (ELINK_DUAL_MEDIA(params
)) {
7714 "FW does not support OPT MDL verification");
7715 return ELINK_STATUS_ERROR
;
7717 cmd
= DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL
;
7719 /* No support in OPT MDL detection */
7720 PMD_DRV_LOG(DEBUG
, "FW does not support OPT MDL verification");
7721 return ELINK_STATUS_ERROR
;
7724 fw_cmd_param
= ELINK_FW_PARAM_SET(phy
->addr
, phy
->type
, phy
->mdio_ctrl
);
7725 fw_resp
= elink_cb_fw_command(sc
, cmd
, fw_cmd_param
);
7726 if (fw_resp
== FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS
) {
7727 PMD_DRV_LOG(DEBUG
, "Approved module");
7728 return ELINK_STATUS_OK
;
7731 /* Format the warning message */
7732 if (elink_read_sfp_module_eeprom(phy
,
7734 ELINK_I2C_DEV_ADDR_A0
,
7735 ELINK_SFP_EEPROM_VENDOR_NAME_ADDR
,
7736 ELINK_SFP_EEPROM_VENDOR_NAME_SIZE
,
7737 (uint8_t *) vendor_name
))
7738 vendor_name
[0] = '\0';
7740 vendor_name
[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE
] = '\0';
7741 if (elink_read_sfp_module_eeprom(phy
,
7743 ELINK_I2C_DEV_ADDR_A0
,
7744 ELINK_SFP_EEPROM_PART_NO_ADDR
,
7745 ELINK_SFP_EEPROM_PART_NO_SIZE
,
7746 (uint8_t *) vendor_pn
))
7747 vendor_pn
[0] = '\0';
7749 vendor_pn
[ELINK_SFP_EEPROM_PART_NO_SIZE
] = '\0';
7751 elink_cb_event_log(sc
, ELINK_LOG_ID_UNQUAL_IO_MODULE
, params
->port
, vendor_name
, vendor_pn
); // "Warning: Unqualified SFP+ module detected,"
7752 // " Port %d from %s part number %s",
7754 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) !=
7755 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG
)
7756 phy
->flags
|= ELINK_FLAGS_SFP_NOT_APPROVED
;
7757 return ELINK_STATUS_ERROR
;
7760 static elink_status_t
elink_wait_for_sfp_module_initialized(struct elink_phy
7768 /* Initialization time after hot-plug may take up to 300ms for
7769 * some phys type ( e.g. JDSU )
7772 for (timeout
= 0; timeout
< 60; timeout
++) {
7773 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)
7774 rc
= elink_warpcore_read_sfp_module_eeprom(phy
, params
,
7775 ELINK_I2C_DEV_ADDR_A0
,
7779 rc
= elink_read_sfp_module_eeprom(phy
, params
,
7780 ELINK_I2C_DEV_ADDR_A0
,
7784 "SFP+ module initialization took %d ms",
7786 return ELINK_STATUS_OK
;
7790 rc
= elink_read_sfp_module_eeprom(phy
, params
, ELINK_I2C_DEV_ADDR_A0
,
7795 static void elink_8727_power_module(struct bnx2x_softc
*sc
,
7796 struct elink_phy
*phy
, uint8_t is_power_up
)
7798 /* Make sure GPIOs are not using for LED mode */
7800 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
7801 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7803 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7804 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7805 * where the 1st bit is the over-current(only input), and 2nd bit is
7806 * for power( only output )
7808 * In case of NOC feature is disabled and power is up, set GPIO control
7809 * as input to enable listening of over-current indication
7811 if (phy
->flags
& ELINK_FLAGS_NOC
)
7816 /* Set GPIO control to OUTPUT, and set the power bit
7817 * to according to the is_power_up
7821 elink_cl45_write(sc
, phy
,
7822 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_GPIO_CTRL
, val
);
7825 static elink_status_t
elink_8726_set_limiting_mode(struct bnx2x_softc
*sc
,
7826 struct elink_phy
*phy
,
7829 uint16_t cur_limiting_mode
;
7831 elink_cl45_read(sc
, phy
,
7833 MDIO_PMA_REG_ROM_VER2
, &cur_limiting_mode
);
7834 PMD_DRV_LOG(DEBUG
, "Current Limiting mode is 0x%x", cur_limiting_mode
);
7836 if (edc_mode
== ELINK_EDC_MODE_LIMITING
) {
7837 PMD_DRV_LOG(DEBUG
, "Setting LIMITING MODE");
7838 elink_cl45_write(sc
, phy
,
7840 MDIO_PMA_REG_ROM_VER2
,
7841 ELINK_EDC_MODE_LIMITING
);
7842 } else { /* LRM mode ( default ) */
7844 PMD_DRV_LOG(DEBUG
, "Setting LRM MODE");
7846 /* Changing to LRM mode takes quite few seconds. So do it only
7847 * if current mode is limiting (default is LRM)
7849 if (cur_limiting_mode
!= ELINK_EDC_MODE_LIMITING
)
7850 return ELINK_STATUS_OK
;
7852 elink_cl45_write(sc
, phy
,
7853 MDIO_PMA_DEVAD
, MDIO_PMA_REG_LRM_MODE
, 0);
7854 elink_cl45_write(sc
, phy
,
7855 MDIO_PMA_DEVAD
, MDIO_PMA_REG_ROM_VER2
, 0x128);
7856 elink_cl45_write(sc
, phy
,
7858 MDIO_PMA_REG_MISC_CTRL0
, 0x4008);
7859 elink_cl45_write(sc
, phy
,
7860 MDIO_PMA_DEVAD
, MDIO_PMA_REG_LRM_MODE
, 0xaaaa);
7862 return ELINK_STATUS_OK
;
7865 static elink_status_t
elink_8727_set_limiting_mode(struct bnx2x_softc
*sc
,
7866 struct elink_phy
*phy
,
7869 uint16_t phy_identifier
;
7870 uint16_t rom_ver2_val
;
7871 elink_cl45_read(sc
, phy
,
7873 MDIO_PMA_REG_PHY_IDENTIFIER
, &phy_identifier
);
7875 elink_cl45_write(sc
, phy
,
7877 MDIO_PMA_REG_PHY_IDENTIFIER
,
7878 (phy_identifier
& ~(1 << 9)));
7880 elink_cl45_read(sc
, phy
,
7881 MDIO_PMA_DEVAD
, MDIO_PMA_REG_ROM_VER2
, &rom_ver2_val
);
7882 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7883 elink_cl45_write(sc
, phy
,
7885 MDIO_PMA_REG_ROM_VER2
,
7886 (rom_ver2_val
& 0xff00) | (edc_mode
& 0x00ff));
7888 elink_cl45_write(sc
, phy
,
7890 MDIO_PMA_REG_PHY_IDENTIFIER
,
7891 (phy_identifier
| (1 << 9)));
7893 return ELINK_STATUS_OK
;
7896 static void elink_8727_specific_func(struct elink_phy
*phy
,
7897 struct elink_params
*params
,
7900 struct bnx2x_softc
*sc
= params
->sc
;
7903 case ELINK_DISABLE_TX
:
7904 elink_sfp_set_transmitter(params
, phy
, 0);
7906 case ELINK_ENABLE_TX
:
7907 if (!(phy
->flags
& ELINK_FLAGS_SFP_NOT_APPROVED
))
7908 elink_sfp_set_transmitter(params
, phy
, 1);
7910 case ELINK_PHY_INIT
:
7911 elink_cl45_write(sc
, phy
,
7912 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
,
7913 (1 << 2) | (1 << 5));
7914 elink_cl45_write(sc
, phy
,
7915 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_TXCTRL
, 0);
7916 elink_cl45_write(sc
, phy
,
7917 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0x0006);
7918 /* Make MOD_ABS give interrupt on change */
7919 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
,
7920 MDIO_PMA_REG_8727_PCS_OPT_CTRL
, &val
);
7922 if (phy
->flags
& ELINK_FLAGS_NOC
)
7924 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
7925 * status which reflect SFP+ module over-current
7927 if (!(phy
->flags
& ELINK_FLAGS_NOC
))
7928 val
&= 0xff8f; /* Reset bits 4-6 */
7929 elink_cl45_write(sc
, phy
,
7930 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_PCS_OPT_CTRL
,
7934 PMD_DRV_LOG(DEBUG
, "Function 0x%x not supported by 8727",
7940 static void elink_set_e1e2_module_fault_led(struct elink_params
*params
,
7943 struct bnx2x_softc
*sc
= params
->sc
;
7945 uint32_t fault_led_gpio
= REG_RD(sc
, params
->shmem_base
+
7946 offsetof(struct shmem_region
,
7948 port_hw_config
[params
->port
].
7950 PORT_HW_CFG_FAULT_MODULE_LED_MASK
;
7951 switch (fault_led_gpio
) {
7952 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED
:
7954 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0
:
7955 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1
:
7956 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2
:
7957 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3
:
7959 uint8_t gpio_port
= elink_get_gpio_port(params
);
7960 uint16_t gpio_pin
= fault_led_gpio
-
7961 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0
;
7962 PMD_DRV_LOG(DEBUG
, "Set fault module-detected led "
7963 "pin %x port %x mode %x",
7964 gpio_pin
, gpio_port
, gpio_mode
);
7965 elink_cb_gpio_write(sc
, gpio_pin
, gpio_mode
, gpio_port
);
7969 PMD_DRV_LOG(DEBUG
, "Error: Invalid fault led mode 0x%x",
7974 static void elink_set_e3_module_fault_led(struct elink_params
*params
,
7978 uint8_t port
= params
->port
;
7979 struct bnx2x_softc
*sc
= params
->sc
;
7980 pin_cfg
= (REG_RD(sc
, params
->shmem_base
+
7981 offsetof(struct shmem_region
,
7982 dev_info
.port_hw_config
[port
].e3_sfp_ctrl
)) &
7983 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK
) >>
7984 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT
;
7985 PMD_DRV_LOG(DEBUG
, "Setting Fault LED to %d using pin cfg %d",
7986 gpio_mode
, pin_cfg
);
7987 elink_set_cfg_pin(sc
, pin_cfg
, gpio_mode
);
7990 static void elink_set_sfp_module_fault_led(struct elink_params
*params
,
7993 struct bnx2x_softc
*sc
= params
->sc
;
7994 PMD_DRV_LOG(DEBUG
, "Setting SFP+ module fault LED to %d", gpio_mode
);
7995 if (CHIP_IS_E3(sc
)) {
7996 /* Low ==> if SFP+ module is supported otherwise
7997 * High ==> if SFP+ module is not on the approved vendor list
7999 elink_set_e3_module_fault_led(params
, gpio_mode
);
8001 elink_set_e1e2_module_fault_led(params
, gpio_mode
);
8004 static void elink_warpcore_hw_reset(__rte_unused
struct elink_phy
*phy
,
8005 struct elink_params
*params
)
8007 struct bnx2x_softc
*sc
= params
->sc
;
8008 elink_warpcore_power_module(params
, 0);
8009 /* Put Warpcore in low power mode */
8010 REG_WR(sc
, MISC_REG_WC0_RESET
, 0x0c0e);
8012 /* Put LCPLL in low power mode */
8013 REG_WR(sc
, MISC_REG_LCPLL_E40_PWRDWN
, 1);
8014 REG_WR(sc
, MISC_REG_LCPLL_E40_RESETB_ANA
, 0);
8015 REG_WR(sc
, MISC_REG_LCPLL_E40_RESETB_DIG
, 0);
8018 static void elink_power_sfp_module(struct elink_params
*params
,
8019 struct elink_phy
*phy
, uint8_t power
)
8021 PMD_DRV_LOG(DEBUG
, "Setting SFP+ power to %x", power
);
8023 switch (phy
->type
) {
8024 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727
:
8025 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722
:
8026 elink_8727_power_module(params
->sc
, phy
, power
);
8028 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
8029 elink_warpcore_power_module(params
, power
);
8036 static void elink_warpcore_set_limiting_mode(struct elink_params
*params
,
8037 struct elink_phy
*phy
,
8041 uint16_t mode
= MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT
;
8042 struct bnx2x_softc
*sc
= params
->sc
;
8044 uint8_t lane
= elink_get_warpcore_lane(params
);
8045 /* This is a global register which controls all lanes */
8046 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
8047 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE
, &val
);
8048 val
&= ~(0xf << (lane
<< 2));
8051 case ELINK_EDC_MODE_LINEAR
:
8052 case ELINK_EDC_MODE_LIMITING
:
8053 mode
= MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT
;
8055 case ELINK_EDC_MODE_PASSIVE_DAC
:
8056 case ELINK_EDC_MODE_ACTIVE_DAC
:
8057 mode
= MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC
;
8063 val
|= (mode
<< (lane
<< 2));
8064 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
8065 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE
, val
);
8067 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
8068 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE
, &val
);
8070 /* Restart microcode to re-read the new mode */
8071 elink_warpcore_reset_lane(sc
, phy
, 1);
8072 elink_warpcore_reset_lane(sc
, phy
, 0);
8076 static void elink_set_limiting_mode(struct elink_params
*params
,
8077 struct elink_phy
*phy
, uint16_t edc_mode
)
8079 switch (phy
->type
) {
8080 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726
:
8081 elink_8726_set_limiting_mode(params
->sc
, phy
, edc_mode
);
8083 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727
:
8084 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722
:
8085 elink_8727_set_limiting_mode(params
->sc
, phy
, edc_mode
);
8087 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
8088 elink_warpcore_set_limiting_mode(params
, phy
, edc_mode
);
8093 static elink_status_t
elink_sfp_module_detection(struct elink_phy
*phy
,
8094 struct elink_params
*params
)
8096 struct bnx2x_softc
*sc
= params
->sc
;
8098 elink_status_t rc
= ELINK_STATUS_OK
;
8100 uint32_t val
= REG_RD(sc
, params
->shmem_base
+
8101 offsetof(struct shmem_region
,
8102 dev_info
.port_feature_config
[params
->
8105 /* Enabled transmitter by default */
8106 elink_sfp_set_transmitter(params
, phy
, 1);
8107 PMD_DRV_LOG(DEBUG
, "SFP+ module plugged in/out detected on port %d",
8109 /* Power up module */
8110 elink_power_sfp_module(params
, phy
, 1);
8111 if (elink_get_edc_mode(phy
, params
, &edc_mode
) != 0) {
8112 PMD_DRV_LOG(DEBUG
, "Failed to get valid module type");
8113 return ELINK_STATUS_ERROR
;
8114 } else if (elink_verify_sfp_module(phy
, params
) != 0) {
8115 /* Check SFP+ module compatibility */
8116 PMD_DRV_LOG(DEBUG
, "Module verification failed!!");
8117 rc
= ELINK_STATUS_ERROR
;
8118 /* Turn on fault module-detected led */
8119 elink_set_sfp_module_fault_led(params
,
8120 MISC_REGISTERS_GPIO_HIGH
);
8122 /* Check if need to power down the SFP+ module */
8123 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
8124 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN
) {
8125 PMD_DRV_LOG(DEBUG
, "Shutdown SFP+ module!!");
8126 elink_power_sfp_module(params
, phy
, 0);
8130 /* Turn off fault module-detected led */
8131 elink_set_sfp_module_fault_led(params
, MISC_REGISTERS_GPIO_LOW
);
8134 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8135 * is done automatically
8137 elink_set_limiting_mode(params
, phy
, edc_mode
);
8139 /* Disable transmit for this module if the module is not approved, and
8140 * laser needs to be disabled.
8143 ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
8144 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER
))
8145 elink_sfp_set_transmitter(params
, phy
, 0);
8150 void elink_handle_module_detect_int(struct elink_params
*params
)
8152 struct bnx2x_softc
*sc
= params
->sc
;
8153 struct elink_phy
*phy
;
8155 uint8_t gpio_num
, gpio_port
;
8156 if (CHIP_IS_E3(sc
)) {
8157 phy
= ¶ms
->phy
[ELINK_INT_PHY
];
8158 /* Always enable TX laser,will be disabled in case of fault */
8159 elink_sfp_set_transmitter(params
, phy
, 1);
8161 phy
= ¶ms
->phy
[ELINK_EXT_PHY1
];
8163 if (elink_get_mod_abs_int_cfg(sc
, params
->shmem_base
,
8164 params
->port
, &gpio_num
, &gpio_port
) ==
8165 ELINK_STATUS_ERROR
) {
8166 PMD_DRV_LOG(DEBUG
, "Failed to get MOD_ABS interrupt config");
8170 /* Set valid module led off */
8171 elink_set_sfp_module_fault_led(params
, MISC_REGISTERS_GPIO_HIGH
);
8173 /* Get current gpio val reflecting module plugged in / out */
8174 gpio_val
= elink_cb_gpio_read(sc
, gpio_num
, gpio_port
);
8176 /* Call the handling function in case module is detected */
8177 if (gpio_val
== 0) {
8178 elink_set_mdio_emac_per_phy(sc
, params
);
8179 elink_set_aer_mmd(params
, phy
);
8181 elink_power_sfp_module(params
, phy
, 1);
8182 elink_cb_gpio_int_write(sc
, gpio_num
,
8183 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR
,
8185 if (elink_wait_for_sfp_module_initialized(phy
, params
) == 0) {
8186 elink_sfp_module_detection(phy
, params
);
8187 if (CHIP_IS_E3(sc
)) {
8188 uint16_t rx_tx_in_reset
;
8189 /* In case WC is out of reset, reconfigure the
8190 * link speed while taking into account 1G
8191 * module limitation.
8193 elink_cl45_read(sc
, phy
,
8195 MDIO_WC_REG_DIGITAL5_MISC6
,
8197 if ((!rx_tx_in_reset
) &&
8198 (params
->link_flags
&
8199 ELINK_PHY_INITIALIZED
)) {
8200 elink_warpcore_reset_lane(sc
, phy
, 1);
8201 elink_warpcore_config_sfi(phy
, params
);
8202 elink_warpcore_reset_lane(sc
, phy
, 0);
8206 PMD_DRV_LOG(DEBUG
, "SFP+ module is not initialized");
8209 elink_cb_gpio_int_write(sc
, gpio_num
,
8210 MISC_REGISTERS_GPIO_INT_OUTPUT_SET
,
8212 /* Module was plugged out.
8213 * Disable transmit for this module
8215 phy
->media_type
= ELINK_ETH_PHY_NOT_PRESENT
;
8219 /******************************************************************/
8220 /* Used by 8706 and 8727 */
8221 /******************************************************************/
8222 static void elink_sfp_mask_fault(struct bnx2x_softc
*sc
,
8223 struct elink_phy
*phy
,
8224 uint16_t alarm_status_offset
,
8225 uint16_t alarm_ctrl_offset
)
8227 uint16_t alarm_status
, val
;
8228 elink_cl45_read(sc
, phy
,
8229 MDIO_PMA_DEVAD
, alarm_status_offset
, &alarm_status
);
8230 elink_cl45_read(sc
, phy
,
8231 MDIO_PMA_DEVAD
, alarm_status_offset
, &alarm_status
);
8232 /* Mask or enable the fault event. */
8233 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, alarm_ctrl_offset
, &val
);
8234 if (alarm_status
& (1 << 0))
8238 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, alarm_ctrl_offset
, val
);
8241 /******************************************************************/
8242 /* common BNX2X8706/BNX2X8726 PHY SECTION */
8243 /******************************************************************/
8244 static uint8_t elink_8706_8726_read_status(struct elink_phy
*phy
,
8245 struct elink_params
*params
,
8246 struct elink_vars
*vars
)
8248 uint8_t link_up
= 0;
8249 uint16_t val1
, val2
, rx_sd
, pcs_status
;
8250 struct bnx2x_softc
*sc
= params
->sc
;
8251 PMD_DRV_LOG(DEBUG
, "XGXS 8706/8726");
8252 /* Clear RX Alarm */
8253 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXSTAT
, &val2
);
8255 elink_sfp_mask_fault(sc
, phy
, MDIO_PMA_LASI_TXSTAT
,
8256 MDIO_PMA_LASI_TXCTRL
);
8258 /* Clear LASI indication */
8259 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val1
);
8260 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val2
);
8261 PMD_DRV_LOG(DEBUG
, "8706/8726 LASI status 0x%x--> 0x%x", val1
, val2
);
8263 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_RX_SD
, &rx_sd
);
8264 elink_cl45_read(sc
, phy
,
8265 MDIO_PCS_DEVAD
, MDIO_PCS_REG_STATUS
, &pcs_status
);
8266 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_LINK_STATUS
, &val2
);
8267 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_LINK_STATUS
, &val2
);
8269 PMD_DRV_LOG(DEBUG
, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8270 " link_status 0x%x", rx_sd
, pcs_status
, val2
);
8271 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8272 * are set, or if the autoneg bit 1 is set
8274 link_up
= ((rx_sd
& pcs_status
& 0x1) || (val2
& (1 << 1)));
8276 if (val2
& (1 << 1))
8277 vars
->line_speed
= ELINK_SPEED_1000
;
8279 vars
->line_speed
= ELINK_SPEED_10000
;
8280 elink_ext_phy_resolve_fc(phy
, params
, vars
);
8281 vars
->duplex
= DUPLEX_FULL
;
8284 /* Capture 10G link fault. Read twice to clear stale value. */
8285 if (vars
->line_speed
== ELINK_SPEED_10000
) {
8286 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
,
8287 MDIO_PMA_LASI_TXSTAT
, &val1
);
8288 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
,
8289 MDIO_PMA_LASI_TXSTAT
, &val1
);
8290 if (val1
& (1 << 0))
8291 vars
->fault_detected
= 1;
8297 /******************************************************************/
8298 /* BNX2X8706 PHY SECTION */
8299 /******************************************************************/
8300 static uint8_t elink_8706_config_init(struct elink_phy
*phy
,
8301 struct elink_params
*params
,
8302 __rte_unused
struct elink_vars
*vars
)
8304 uint32_t tx_en_mode
;
8305 uint16_t cnt
, val
, tmp1
;
8306 struct bnx2x_softc
*sc
= params
->sc
;
8308 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
8309 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, params
->port
);
8311 elink_ext_phy_hw_reset(sc
, params
->port
);
8312 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0xa040);
8313 elink_wait_reset_complete(sc
, phy
, params
);
8315 /* Wait until fw is loaded */
8316 for (cnt
= 0; cnt
< 100; cnt
++) {
8317 elink_cl45_read(sc
, phy
,
8318 MDIO_PMA_DEVAD
, MDIO_PMA_REG_ROM_VER1
, &val
);
8323 PMD_DRV_LOG(DEBUG
, "XGXS 8706 is initialized after %d ms", cnt
);
8324 if ((params
->feature_config_flags
&
8325 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
)) {
8328 for (i
= 0; i
< 4; i
++) {
8329 reg
= MDIO_XS_8706_REG_BANK_RX0
+
8330 i
* (MDIO_XS_8706_REG_BANK_RX1
-
8331 MDIO_XS_8706_REG_BANK_RX0
);
8332 elink_cl45_read(sc
, phy
, MDIO_XS_DEVAD
, reg
, &val
);
8333 /* Clear first 3 bits of the control */
8335 /* Set control bits according to configuration */
8336 val
|= (phy
->rx_preemphasis
[i
] & 0x7);
8337 PMD_DRV_LOG(DEBUG
, "Setting RX Equalizer to BNX2X8706"
8338 " reg 0x%x <-- val 0x%x", reg
, val
);
8339 elink_cl45_write(sc
, phy
, MDIO_XS_DEVAD
, reg
, val
);
8343 if (phy
->req_line_speed
== ELINK_SPEED_10000
) {
8344 PMD_DRV_LOG(DEBUG
, "XGXS 8706 force 10Gbps");
8346 elink_cl45_write(sc
, phy
,
8348 MDIO_PMA_REG_DIGITAL_CTRL
, 0x400);
8349 elink_cl45_write(sc
, phy
,
8350 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_TXCTRL
, 0);
8351 /* Arm LASI for link and Tx fault. */
8352 elink_cl45_write(sc
, phy
,
8353 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 3);
8355 /* Force 1Gbps using autoneg with 1G advertisement */
8357 /* Allow CL37 through CL73 */
8358 PMD_DRV_LOG(DEBUG
, "XGXS 8706 AutoNeg");
8359 elink_cl45_write(sc
, phy
,
8360 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_CL73
, 0x040c);
8362 /* Enable Full-Duplex advertisement on CL37 */
8363 elink_cl45_write(sc
, phy
,
8364 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LP
, 0x0020);
8365 /* Enable CL37 AN */
8366 elink_cl45_write(sc
, phy
,
8367 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_AN
, 0x1000);
8369 elink_cl45_write(sc
, phy
,
8370 MDIO_AN_DEVAD
, MDIO_AN_REG_ADV
, (1 << 5));
8372 /* Enable clause 73 AN */
8373 elink_cl45_write(sc
, phy
,
8374 MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x1200);
8375 elink_cl45_write(sc
, phy
,
8376 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
, 0x0400);
8377 elink_cl45_write(sc
, phy
,
8378 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0x0004);
8380 elink_save_bnx2x_spirom_ver(sc
, phy
, params
->port
);
8382 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8383 * power mode, if TX Laser is disabled
8386 tx_en_mode
= REG_RD(sc
, params
->shmem_base
+
8387 offsetof(struct shmem_region
,
8388 dev_info
.port_hw_config
[params
->port
].
8390 & PORT_HW_CFG_TX_LASER_MASK
;
8392 if (tx_en_mode
== PORT_HW_CFG_TX_LASER_GPIO0
) {
8393 PMD_DRV_LOG(DEBUG
, "Enabling TXONOFF_PWRDN_DIS");
8394 elink_cl45_read(sc
, phy
,
8395 MDIO_PMA_DEVAD
, MDIO_PMA_REG_DIGITAL_CTRL
,
8398 elink_cl45_write(sc
, phy
,
8399 MDIO_PMA_DEVAD
, MDIO_PMA_REG_DIGITAL_CTRL
,
8403 return ELINK_STATUS_OK
;
8406 static elink_status_t
elink_8706_read_status(struct elink_phy
*phy
,
8407 struct elink_params
*params
,
8408 struct elink_vars
*vars
)
8410 return elink_8706_8726_read_status(phy
, params
, vars
);
8413 /******************************************************************/
8414 /* BNX2X8726 PHY SECTION */
8415 /******************************************************************/
8416 static void elink_8726_config_loopback(struct elink_phy
*phy
,
8417 struct elink_params
*params
)
8419 struct bnx2x_softc
*sc
= params
->sc
;
8420 PMD_DRV_LOG(DEBUG
, "PMA/PMD ext_phy_loopback: 8726");
8421 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x0001);
8424 static void elink_8726_external_rom_boot(struct elink_phy
*phy
,
8425 struct elink_params
*params
)
8427 struct bnx2x_softc
*sc
= params
->sc
;
8428 /* Need to wait 100ms after reset */
8431 /* Micro controller re-boot */
8432 elink_cl45_write(sc
, phy
,
8433 MDIO_PMA_DEVAD
, MDIO_PMA_REG_GEN_CTRL
, 0x018B);
8435 /* Set soft reset */
8436 elink_cl45_write(sc
, phy
,
8438 MDIO_PMA_REG_GEN_CTRL
,
8439 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET
);
8441 elink_cl45_write(sc
, phy
,
8442 MDIO_PMA_DEVAD
, MDIO_PMA_REG_MISC_CTRL1
, 0x0001);
8444 elink_cl45_write(sc
, phy
,
8446 MDIO_PMA_REG_GEN_CTRL
,
8447 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP
);
8449 /* Wait for 150ms for microcode load */
8452 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8453 elink_cl45_write(sc
, phy
,
8454 MDIO_PMA_DEVAD
, MDIO_PMA_REG_MISC_CTRL1
, 0x0000);
8457 elink_save_bnx2x_spirom_ver(sc
, phy
, params
->port
);
8460 static uint8_t elink_8726_read_status(struct elink_phy
*phy
,
8461 struct elink_params
*params
,
8462 struct elink_vars
*vars
)
8464 struct bnx2x_softc
*sc
= params
->sc
;
8466 uint8_t link_up
= elink_8706_8726_read_status(phy
, params
, vars
);
8468 elink_cl45_read(sc
, phy
,
8469 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PHY_IDENTIFIER
,
8471 if (val1
& (1 << 15)) {
8472 PMD_DRV_LOG(DEBUG
, "Tx is disabled");
8474 vars
->line_speed
= 0;
8480 static elink_status_t
elink_8726_config_init(struct elink_phy
*phy
,
8481 struct elink_params
*params
,
8482 struct elink_vars
*vars
)
8484 struct bnx2x_softc
*sc
= params
->sc
;
8485 PMD_DRV_LOG(DEBUG
, "Initializing BNX2X8726");
8487 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 1 << 15);
8488 elink_wait_reset_complete(sc
, phy
, params
);
8490 elink_8726_external_rom_boot(phy
, params
);
8492 /* Need to call module detected on initialization since the module
8493 * detection triggered by actual module insertion might occur before
8494 * driver is loaded, and when driver is loaded, it reset all
8495 * registers, including the transmitter
8497 elink_sfp_module_detection(phy
, params
);
8499 if (phy
->req_line_speed
== ELINK_SPEED_1000
) {
8500 PMD_DRV_LOG(DEBUG
, "Setting 1G force");
8501 elink_cl45_write(sc
, phy
,
8502 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x40);
8503 elink_cl45_write(sc
, phy
,
8504 MDIO_PMA_DEVAD
, MDIO_PMA_REG_10G_CTRL2
, 0xD);
8505 elink_cl45_write(sc
, phy
,
8506 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0x5);
8507 elink_cl45_write(sc
, phy
,
8508 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
, 0x400);
8509 } else if ((phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) &&
8510 (phy
->speed_cap_mask
&
8511 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
) &&
8512 ((phy
->speed_cap_mask
&
8513 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
) !=
8514 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)) {
8515 PMD_DRV_LOG(DEBUG
, "Setting 1G clause37");
8516 /* Set Flow control */
8517 elink_ext_phy_set_pause(params
, phy
, vars
);
8518 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV
, 0x20);
8519 elink_cl45_write(sc
, phy
,
8520 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_CL73
, 0x040c);
8521 elink_cl45_write(sc
, phy
,
8522 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LD
, 0x0020);
8523 elink_cl45_write(sc
, phy
,
8524 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_AN
, 0x1000);
8525 elink_cl45_write(sc
, phy
,
8526 MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x1200);
8527 /* Enable RX-ALARM control to receive interrupt for 1G speed
8530 elink_cl45_write(sc
, phy
,
8531 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0x4);
8532 elink_cl45_write(sc
, phy
,
8533 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
, 0x400);
8535 } else { /* Default 10G. Set only LASI control */
8536 elink_cl45_write(sc
, phy
,
8537 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 1);
8540 /* Set TX PreEmphasis if needed */
8541 if ((params
->feature_config_flags
&
8542 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
)) {
8544 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
8545 phy
->tx_preemphasis
[0], phy
->tx_preemphasis
[1]);
8546 elink_cl45_write(sc
, phy
,
8548 MDIO_PMA_REG_8726_TX_CTRL1
,
8549 phy
->tx_preemphasis
[0]);
8551 elink_cl45_write(sc
, phy
,
8553 MDIO_PMA_REG_8726_TX_CTRL2
,
8554 phy
->tx_preemphasis
[1]);
8557 return ELINK_STATUS_OK
;
8561 static void elink_8726_link_reset(struct elink_phy
*phy
,
8562 struct elink_params
*params
)
8564 struct bnx2x_softc
*sc
= params
->sc
;
8565 PMD_DRV_LOG(DEBUG
, "elink_8726_link_reset port %d", params
->port
);
8566 /* Set serial boot control for external load */
8567 elink_cl45_write(sc
, phy
,
8568 MDIO_PMA_DEVAD
, MDIO_PMA_REG_GEN_CTRL
, 0x0001);
8571 /******************************************************************/
8572 /* BNX2X8727 PHY SECTION */
8573 /******************************************************************/
8575 static void elink_8727_set_link_led(struct elink_phy
*phy
,
8576 struct elink_params
*params
, uint8_t mode
)
8578 struct bnx2x_softc
*sc
= params
->sc
;
8579 uint16_t led_mode_bitmask
= 0;
8580 uint16_t gpio_pins_bitmask
= 0;
8582 /* Only NOC flavor requires to set the LED specifically */
8583 if (!(phy
->flags
& ELINK_FLAGS_NOC
))
8586 case ELINK_LED_MODE_FRONT_PANEL_OFF
:
8587 case ELINK_LED_MODE_OFF
:
8588 led_mode_bitmask
= 0;
8589 gpio_pins_bitmask
= 0x03;
8591 case ELINK_LED_MODE_ON
:
8592 led_mode_bitmask
= 0;
8593 gpio_pins_bitmask
= 0x02;
8595 case ELINK_LED_MODE_OPER
:
8596 led_mode_bitmask
= 0x60;
8597 gpio_pins_bitmask
= 0x11;
8600 elink_cl45_read(sc
, phy
,
8601 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_PCS_OPT_CTRL
, &val
);
8603 val
|= led_mode_bitmask
;
8604 elink_cl45_write(sc
, phy
,
8605 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_PCS_OPT_CTRL
, val
);
8606 elink_cl45_read(sc
, phy
,
8607 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_GPIO_CTRL
, &val
);
8609 val
|= gpio_pins_bitmask
;
8610 elink_cl45_write(sc
, phy
,
8611 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_GPIO_CTRL
, val
);
8614 static void elink_8727_hw_reset(__rte_unused
struct elink_phy
*phy
,
8615 struct elink_params
*params
)
8617 uint32_t swap_val
, swap_override
;
8619 /* The PHY reset is controlled by GPIO 1. Fake the port number
8620 * to cancel the swap done in set_gpio()
8622 struct bnx2x_softc
*sc
= params
->sc
;
8623 swap_val
= REG_RD(sc
, NIG_REG_PORT_SWAP
);
8624 swap_override
= REG_RD(sc
, NIG_REG_STRAP_OVERRIDE
);
8625 port
= (swap_val
&& swap_override
) ^ 1;
8626 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_1
,
8627 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
8630 static void elink_8727_config_speed(struct elink_phy
*phy
,
8631 struct elink_params
*params
)
8633 struct bnx2x_softc
*sc
= params
->sc
;
8635 /* Set option 1G speed */
8636 if ((phy
->req_line_speed
== ELINK_SPEED_1000
) ||
8637 (phy
->media_type
== ELINK_ETH_PHY_SFP_1G_FIBER
)) {
8638 PMD_DRV_LOG(DEBUG
, "Setting 1G force");
8639 elink_cl45_write(sc
, phy
,
8640 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x40);
8641 elink_cl45_write(sc
, phy
,
8642 MDIO_PMA_DEVAD
, MDIO_PMA_REG_10G_CTRL2
, 0xD);
8643 elink_cl45_read(sc
, phy
,
8644 MDIO_PMA_DEVAD
, MDIO_PMA_REG_10G_CTRL2
, &tmp1
);
8645 PMD_DRV_LOG(DEBUG
, "1.7 = 0x%x", tmp1
);
8646 /* Power down the XAUI until link is up in case of dual-media
8649 if (ELINK_DUAL_MEDIA(params
)) {
8650 elink_cl45_read(sc
, phy
,
8652 MDIO_PMA_REG_8727_PCS_GP
, &val
);
8654 elink_cl45_write(sc
, phy
,
8656 MDIO_PMA_REG_8727_PCS_GP
, val
);
8658 } else if ((phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) &&
8659 ((phy
->speed_cap_mask
&
8660 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)) &&
8661 ((phy
->speed_cap_mask
&
8662 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
) !=
8663 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)) {
8665 PMD_DRV_LOG(DEBUG
, "Setting 1G clause37");
8666 elink_cl45_write(sc
, phy
,
8667 MDIO_AN_DEVAD
, MDIO_AN_REG_8727_MISC_CTRL
, 0);
8668 elink_cl45_write(sc
, phy
,
8669 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_AN
, 0x1300);
8671 /* Since the 8727 has only single reset pin, need to set the 10G
8672 * registers although it is default
8674 elink_cl45_write(sc
, phy
,
8675 MDIO_AN_DEVAD
, MDIO_AN_REG_8727_MISC_CTRL
,
8677 elink_cl45_write(sc
, phy
,
8678 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_AN
, 0x0100);
8679 elink_cl45_write(sc
, phy
,
8680 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x2040);
8681 elink_cl45_write(sc
, phy
,
8682 MDIO_PMA_DEVAD
, MDIO_PMA_REG_10G_CTRL2
,
8687 static elink_status_t
elink_8727_config_init(struct elink_phy
*phy
,
8688 struct elink_params
*params
,
8689 __rte_unused
struct elink_vars
8692 uint32_t tx_en_mode
;
8693 uint16_t tmp1
, mod_abs
, tmp2
;
8694 struct bnx2x_softc
*sc
= params
->sc
;
8695 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8697 elink_wait_reset_complete(sc
, phy
, params
);
8699 PMD_DRV_LOG(DEBUG
, "Initializing BNX2X8727");
8701 elink_8727_specific_func(phy
, params
, ELINK_PHY_INIT
);
8702 /* Initially configure MOD_ABS to interrupt when module is
8705 elink_cl45_read(sc
, phy
,
8706 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PHY_IDENTIFIER
, &mod_abs
);
8707 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
8708 * When the EDC is off it locks onto a reference clock and avoids
8711 mod_abs
&= ~(1 << 8);
8712 if (!(phy
->flags
& ELINK_FLAGS_NOC
))
8713 mod_abs
&= ~(1 << 9);
8714 elink_cl45_write(sc
, phy
,
8715 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PHY_IDENTIFIER
, mod_abs
);
8717 /* Enable/Disable PHY transmitter output */
8718 elink_set_disable_pmd_transmit(params
, phy
, 0);
8720 elink_8727_power_module(sc
, phy
, 1);
8722 elink_cl45_read(sc
, phy
,
8723 MDIO_PMA_DEVAD
, MDIO_PMA_REG_M8051_MSGOUT_REG
, &tmp1
);
8725 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXSTAT
, &tmp1
);
8727 elink_8727_config_speed(phy
, params
);
8729 /* Set TX PreEmphasis if needed */
8730 if ((params
->feature_config_flags
&
8731 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
)) {
8732 PMD_DRV_LOG(DEBUG
, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
8733 phy
->tx_preemphasis
[0], phy
->tx_preemphasis
[1]);
8734 elink_cl45_write(sc
, phy
,
8735 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_TX_CTRL1
,
8736 phy
->tx_preemphasis
[0]);
8738 elink_cl45_write(sc
, phy
,
8739 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_TX_CTRL2
,
8740 phy
->tx_preemphasis
[1]);
8743 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8744 * power mode, if TX Laser is disabled
8746 tx_en_mode
= REG_RD(sc
, params
->shmem_base
+
8747 offsetof(struct shmem_region
,
8748 dev_info
.port_hw_config
[params
->port
].
8750 & PORT_HW_CFG_TX_LASER_MASK
;
8752 if (tx_en_mode
== PORT_HW_CFG_TX_LASER_GPIO0
) {
8754 PMD_DRV_LOG(DEBUG
, "Enabling TXONOFF_PWRDN_DIS");
8755 elink_cl45_read(sc
, phy
,
8756 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_OPT_CFG_REG
,
8760 elink_cl45_write(sc
, phy
,
8761 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_OPT_CFG_REG
,
8763 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
,
8764 MDIO_PMA_REG_PHY_IDENTIFIER
, &tmp2
);
8765 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
,
8766 MDIO_PMA_REG_PHY_IDENTIFIER
, (tmp2
& 0x7fff));
8769 return ELINK_STATUS_OK
;
8772 static void elink_8727_handle_mod_abs(struct elink_phy
*phy
,
8773 struct elink_params
*params
)
8775 struct bnx2x_softc
*sc
= params
->sc
;
8776 uint16_t mod_abs
, rx_alarm_status
;
8777 uint32_t val
= REG_RD(sc
, params
->shmem_base
+
8778 offsetof(struct shmem_region
,
8779 dev_info
.port_feature_config
[params
->
8781 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_PHY_IDENTIFIER
,
8783 if (mod_abs
& (1 << 8)) {
8785 /* Module is absent */
8786 PMD_DRV_LOG(DEBUG
, "MOD_ABS indication show module is absent");
8787 phy
->media_type
= ELINK_ETH_PHY_NOT_PRESENT
;
8788 /* 1. Set mod_abs to detect next module
8790 * 2. Set EDC off by setting OPTXLOS signal input to low
8792 * When the EDC is off it locks onto a reference clock and
8793 * avoids becoming 'lost'.
8795 mod_abs
&= ~(1 << 8);
8796 if (!(phy
->flags
& ELINK_FLAGS_NOC
))
8797 mod_abs
&= ~(1 << 9);
8798 elink_cl45_write(sc
, phy
,
8800 MDIO_PMA_REG_PHY_IDENTIFIER
, mod_abs
);
8802 /* Clear RX alarm since it stays up as long as
8803 * the mod_abs wasn't changed
8805 elink_cl45_read(sc
, phy
,
8807 MDIO_PMA_LASI_RXSTAT
, &rx_alarm_status
);
8810 /* Module is present */
8811 PMD_DRV_LOG(DEBUG
, "MOD_ABS indication show module is present");
8812 /* First disable transmitter, and if the module is ok, the
8813 * module_detection will enable it
8814 * 1. Set mod_abs to detect next module absent event ( bit 8)
8815 * 2. Restore the default polarity of the OPRXLOS signal and
8816 * this signal will then correctly indicate the presence or
8817 * absence of the Rx signal. (bit 9)
8819 mod_abs
|= (1 << 8);
8820 if (!(phy
->flags
& ELINK_FLAGS_NOC
))
8821 mod_abs
|= (1 << 9);
8822 elink_cl45_write(sc
, phy
,
8824 MDIO_PMA_REG_PHY_IDENTIFIER
, mod_abs
);
8826 /* Clear RX alarm since it stays up as long as the mod_abs
8827 * wasn't changed. This is need to be done before calling the
8828 * module detection, otherwise it will clear* the link update
8831 elink_cl45_read(sc
, phy
,
8833 MDIO_PMA_LASI_RXSTAT
, &rx_alarm_status
);
8835 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
8836 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER
)
8837 elink_sfp_set_transmitter(params
, phy
, 0);
8839 if (elink_wait_for_sfp_module_initialized(phy
, params
) == 0) {
8840 elink_sfp_module_detection(phy
, params
);
8842 PMD_DRV_LOG(DEBUG
, "SFP+ module is not initialized");
8845 /* Reconfigure link speed based on module type limitations */
8846 elink_8727_config_speed(phy
, params
);
8849 PMD_DRV_LOG(DEBUG
, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status
);
8850 /* No need to check link status in case of module plugged in/out */
8853 static uint8_t elink_8727_read_status(struct elink_phy
*phy
,
8854 struct elink_params
*params
,
8855 struct elink_vars
*vars
)
8857 struct bnx2x_softc
*sc
= params
->sc
;
8858 uint8_t link_up
= 0, oc_port
= params
->port
;
8859 uint16_t link_status
= 0;
8860 uint16_t rx_alarm_status
, lasi_ctrl
, val1
;
8862 /* If PHY is not initialized, do not check link status */
8863 elink_cl45_read(sc
, phy
,
8864 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, &lasi_ctrl
);
8868 /* Check the LASI on Rx */
8869 elink_cl45_read(sc
, phy
,
8870 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXSTAT
, &rx_alarm_status
);
8871 vars
->line_speed
= 0;
8872 PMD_DRV_LOG(DEBUG
, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status
);
8874 elink_sfp_mask_fault(sc
, phy
, MDIO_PMA_LASI_TXSTAT
,
8875 MDIO_PMA_LASI_TXCTRL
);
8877 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val1
);
8879 PMD_DRV_LOG(DEBUG
, "8727 LASI status 0x%x", val1
);
8882 elink_cl45_read(sc
, phy
,
8883 MDIO_PMA_DEVAD
, MDIO_PMA_REG_M8051_MSGOUT_REG
, &val1
);
8885 /* If a module is present and there is need to check
8888 if (!(phy
->flags
& ELINK_FLAGS_NOC
) && !(rx_alarm_status
& (1 << 5))) {
8889 /* Check over-current using 8727 GPIO0 input */
8890 elink_cl45_read(sc
, phy
,
8891 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_GPIO_CTRL
,
8894 if ((val1
& (1 << 8)) == 0) {
8895 if (!CHIP_IS_E1x(sc
))
8896 oc_port
= SC_PATH(sc
) + (params
->port
<< 1);
8898 "8727 Power fault has been detected on port %d",
8900 elink_cb_event_log(sc
, ELINK_LOG_ID_OVER_CURRENT
, oc_port
); //"Error: Power fault on Port %d has "
8901 // "been detected and the power to "
8902 // "that SFP+ module has been removed "
8903 // "to prevent failure of the card. "
8904 // "Please remove the SFP+ module and "
8905 // "restart the system to clear this "
8907 /* Disable all RX_ALARMs except for mod_abs */
8908 elink_cl45_write(sc
, phy
,
8910 MDIO_PMA_LASI_RXCTRL
, (1 << 5));
8912 elink_cl45_read(sc
, phy
,
8914 MDIO_PMA_REG_PHY_IDENTIFIER
, &val1
);
8915 /* Wait for module_absent_event */
8917 elink_cl45_write(sc
, phy
,
8919 MDIO_PMA_REG_PHY_IDENTIFIER
, val1
);
8920 /* Clear RX alarm */
8921 elink_cl45_read(sc
, phy
,
8923 MDIO_PMA_LASI_RXSTAT
, &rx_alarm_status
);
8924 elink_8727_power_module(params
->sc
, phy
, 0);
8929 /* Over current check */
8930 /* When module absent bit is set, check module */
8931 if (rx_alarm_status
& (1 << 5)) {
8932 elink_8727_handle_mod_abs(phy
, params
);
8933 /* Enable all mod_abs and link detection bits */
8934 elink_cl45_write(sc
, phy
,
8935 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
,
8936 ((1 << 5) | (1 << 2)));
8939 if (!(phy
->flags
& ELINK_FLAGS_SFP_NOT_APPROVED
)) {
8940 PMD_DRV_LOG(DEBUG
, "Enabling 8727 TX laser");
8941 elink_sfp_set_transmitter(params
, phy
, 1);
8943 PMD_DRV_LOG(DEBUG
, "Tx is disabled");
8947 elink_cl45_read(sc
, phy
,
8949 MDIO_PMA_REG_8073_SPEED_LINK_STATUS
, &link_status
);
8951 /* Bits 0..2 --> speed detected,
8952 * Bits 13..15--> link is down
8954 if ((link_status
& (1 << 2)) && (!(link_status
& (1 << 15)))) {
8956 vars
->line_speed
= ELINK_SPEED_10000
;
8957 PMD_DRV_LOG(DEBUG
, "port %x: External link up in 10G",
8959 } else if ((link_status
& (1 << 0)) && (!(link_status
& (1 << 13)))) {
8961 vars
->line_speed
= ELINK_SPEED_1000
;
8962 PMD_DRV_LOG(DEBUG
, "port %x: External link up in 1G",
8966 PMD_DRV_LOG(DEBUG
, "port %x: External link is down",
8970 /* Capture 10G link fault. */
8971 if (vars
->line_speed
== ELINK_SPEED_10000
) {
8972 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
,
8973 MDIO_PMA_LASI_TXSTAT
, &val1
);
8975 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
,
8976 MDIO_PMA_LASI_TXSTAT
, &val1
);
8978 if (val1
& (1 << 0)) {
8979 vars
->fault_detected
= 1;
8984 elink_ext_phy_resolve_fc(phy
, params
, vars
);
8985 vars
->duplex
= DUPLEX_FULL
;
8986 PMD_DRV_LOG(DEBUG
, "duplex = 0x%x", vars
->duplex
);
8989 if ((ELINK_DUAL_MEDIA(params
)) &&
8990 (phy
->req_line_speed
== ELINK_SPEED_1000
)) {
8991 elink_cl45_read(sc
, phy
,
8993 MDIO_PMA_REG_8727_PCS_GP
, &val1
);
8994 /* In case of dual-media board and 1G, power up the XAUI side,
8995 * otherwise power it down. For 10G it is done automatically
9001 elink_cl45_write(sc
, phy
,
9003 MDIO_PMA_REG_8727_PCS_GP
, val1
);
9008 static void elink_8727_link_reset(struct elink_phy
*phy
,
9009 struct elink_params
*params
)
9011 struct bnx2x_softc
*sc
= params
->sc
;
9013 /* Enable/Disable PHY transmitter output */
9014 elink_set_disable_pmd_transmit(params
, phy
, 1);
9016 /* Disable Transmitter */
9017 elink_sfp_set_transmitter(params
, phy
, 0);
9019 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0);
9023 /******************************************************************/
9024 /* BNX2X8481/BNX2X84823/BNX2X84833 PHY SECTION */
9025 /******************************************************************/
9026 static void elink_save_848xx_spirom_version(struct elink_phy
*phy
,
9027 struct bnx2x_softc
*sc
, uint8_t port
)
9029 uint16_t val
, fw_ver2
, cnt
, i
;
9030 static struct elink_reg_set reg_set
[] = {
9031 {MDIO_PMA_DEVAD
, 0xA819, 0x0014},
9032 {MDIO_PMA_DEVAD
, 0xA81A, 0xc200},
9033 {MDIO_PMA_DEVAD
, 0xA81B, 0x0000},
9034 {MDIO_PMA_DEVAD
, 0xA81C, 0x0300},
9035 {MDIO_PMA_DEVAD
, 0xA817, 0x0009}
9039 if ((phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) ||
9040 (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
)) {
9041 elink_cl45_read(sc
, phy
, MDIO_CTL_DEVAD
, 0x400f, &fw_ver1
);
9042 elink_save_spirom_version(sc
, port
, fw_ver1
& 0xfff,
9045 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9046 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9047 for (i
= 0; i
< ARRAY_SIZE(reg_set
); i
++)
9048 elink_cl45_write(sc
, phy
, reg_set
[i
].devad
,
9049 reg_set
[i
].reg
, reg_set
[i
].val
);
9051 for (cnt
= 0; cnt
< 100; cnt
++) {
9052 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, 0xA818, &val
);
9058 PMD_DRV_LOG(DEBUG
, "Unable to read 848xx "
9059 "phy fw version(1)");
9060 elink_save_spirom_version(sc
, port
, 0, phy
->ver_addr
);
9064 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9065 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, 0xA819, 0x0000);
9066 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, 0xA81A, 0xc200);
9067 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, 0xA817, 0x000A);
9068 for (cnt
= 0; cnt
< 100; cnt
++) {
9069 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, 0xA818, &val
);
9075 PMD_DRV_LOG(DEBUG
, "Unable to read 848xx phy fw "
9077 elink_save_spirom_version(sc
, port
, 0, phy
->ver_addr
);
9081 /* lower 16 bits of the register SPI_FW_STATUS */
9082 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, 0xA81B, &fw_ver1
);
9083 /* upper 16 bits of register SPI_FW_STATUS */
9084 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, 0xA81C, &fw_ver2
);
9086 elink_save_spirom_version(sc
, port
, (fw_ver2
<< 16) | fw_ver1
,
9092 static void elink_848xx_set_led(struct bnx2x_softc
*sc
, struct elink_phy
*phy
)
9094 uint16_t val
, offset
, i
;
9095 static struct elink_reg_set reg_set
[] = {
9096 {MDIO_PMA_DEVAD
, MDIO_PMA_REG_8481_LED1_MASK
, 0x0080},
9097 {MDIO_PMA_DEVAD
, MDIO_PMA_REG_8481_LED2_MASK
, 0x0018},
9098 {MDIO_PMA_DEVAD
, MDIO_PMA_REG_8481_LED3_MASK
, 0x0006},
9099 {MDIO_PMA_DEVAD
, MDIO_PMA_REG_8481_LED3_BLINK
, 0x0000},
9100 {MDIO_PMA_DEVAD
, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH
,
9101 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ
},
9102 {MDIO_AN_DEVAD
, 0xFFFB, 0xFFFD}
9104 /* PHYC_CTL_LED_CTL */
9105 elink_cl45_read(sc
, phy
,
9106 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8481_LINK_SIGNAL
, &val
);
9110 elink_cl45_write(sc
, phy
,
9111 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8481_LINK_SIGNAL
, val
);
9113 for (i
= 0; i
< ARRAY_SIZE(reg_set
); i
++)
9114 elink_cl45_write(sc
, phy
, reg_set
[i
].devad
, reg_set
[i
].reg
,
9117 if ((phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) ||
9118 (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
))
9119 offset
= MDIO_PMA_REG_84833_CTL_LED_CTL_1
;
9121 offset
= MDIO_PMA_REG_84823_CTL_LED_CTL_1
;
9123 /* stretch_en for LED3 */
9124 elink_cl45_read_or_write(sc
, phy
,
9125 MDIO_PMA_DEVAD
, offset
,
9126 MDIO_PMA_REG_84823_LED3_STRETCH_EN
);
9129 static void elink_848xx_specific_func(struct elink_phy
*phy
,
9130 struct elink_params
*params
,
9133 struct bnx2x_softc
*sc
= params
->sc
;
9135 case ELINK_PHY_INIT
:
9136 if ((phy
->type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) &&
9137 (phy
->type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
)) {
9138 /* Save spirom version */
9139 elink_save_848xx_spirom_version(phy
, sc
, params
->port
);
9141 /* This phy uses the NIG latch mechanism since link indication
9142 * arrives through its LED4 and not via its LASI signal, so we
9143 * get steady signal instead of clear on read
9145 elink_bits_en(sc
, NIG_REG_LATCH_BC_0
+ params
->port
* 4,
9146 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT
);
9148 elink_848xx_set_led(sc
, phy
);
9153 static elink_status_t
elink_848xx_cmn_config_init(struct elink_phy
*phy
,
9154 struct elink_params
*params
,
9155 struct elink_vars
*vars
)
9157 struct bnx2x_softc
*sc
= params
->sc
;
9158 uint16_t autoneg_val
, an_1000_val
, an_10_100_val
;
9160 elink_848xx_specific_func(phy
, params
, ELINK_PHY_INIT
);
9161 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x0000);
9163 /* set 1000 speed advertisement */
9164 elink_cl45_read(sc
, phy
,
9165 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_1000T_CTRL
,
9168 elink_ext_phy_set_pause(params
, phy
, vars
);
9169 elink_cl45_read(sc
, phy
,
9171 MDIO_AN_REG_8481_LEGACY_AN_ADV
, &an_10_100_val
);
9172 elink_cl45_read(sc
, phy
,
9173 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_LEGACY_MII_CTRL
,
9175 /* Disable forced speed */
9177 ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
9178 an_10_100_val
&= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8));
9180 if (((phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) &&
9181 (phy
->speed_cap_mask
&
9182 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)) ||
9183 (phy
->req_line_speed
== ELINK_SPEED_1000
)) {
9184 an_1000_val
|= (1 << 8);
9185 autoneg_val
|= (1 << 9 | 1 << 12);
9186 if (phy
->req_duplex
== DUPLEX_FULL
)
9187 an_1000_val
|= (1 << 9);
9188 PMD_DRV_LOG(DEBUG
, "Advertising 1G");
9190 an_1000_val
&= ~((1 << 8) | (1 << 9));
9192 elink_cl45_write(sc
, phy
,
9193 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_1000T_CTRL
,
9196 /* Set 10/100 speed advertisement */
9197 if (phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) {
9198 if (phy
->speed_cap_mask
&
9199 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
) {
9200 /* Enable autoneg and restart autoneg for legacy speeds
9202 autoneg_val
|= (1 << 9 | 1 << 12);
9203 an_10_100_val
|= (1 << 8);
9204 PMD_DRV_LOG(DEBUG
, "Advertising 100M-FD");
9207 if (phy
->speed_cap_mask
&
9208 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
) {
9209 /* Enable autoneg and restart autoneg for legacy speeds
9211 autoneg_val
|= (1 << 9 | 1 << 12);
9212 an_10_100_val
|= (1 << 7);
9213 PMD_DRV_LOG(DEBUG
, "Advertising 100M-HD");
9216 if ((phy
->speed_cap_mask
&
9217 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
) &&
9218 (phy
->supported
& ELINK_SUPPORTED_10baseT_Full
)) {
9219 an_10_100_val
|= (1 << 6);
9220 autoneg_val
|= (1 << 9 | 1 << 12);
9221 PMD_DRV_LOG(DEBUG
, "Advertising 10M-FD");
9224 if ((phy
->speed_cap_mask
&
9225 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
) &&
9226 (phy
->supported
& ELINK_SUPPORTED_10baseT_Half
)) {
9227 an_10_100_val
|= (1 << 5);
9228 autoneg_val
|= (1 << 9 | 1 << 12);
9229 PMD_DRV_LOG(DEBUG
, "Advertising 10M-HD");
9233 /* Only 10/100 are allowed to work in FORCE mode */
9234 if ((phy
->req_line_speed
== ELINK_SPEED_100
) &&
9236 (ELINK_SUPPORTED_100baseT_Half
| ELINK_SUPPORTED_100baseT_Full
))) {
9237 autoneg_val
|= (1 << 13);
9238 /* Enabled AUTO-MDIX when autoneg is disabled */
9239 elink_cl45_write(sc
, phy
,
9240 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_AUX_CTRL
,
9241 (1 << 15 | 1 << 9 | 7 << 0));
9242 /* The PHY needs this set even for forced link. */
9243 an_10_100_val
|= (1 << 8) | (1 << 7);
9244 PMD_DRV_LOG(DEBUG
, "Setting 100M force");
9246 if ((phy
->req_line_speed
== ELINK_SPEED_10
) &&
9248 (ELINK_SUPPORTED_10baseT_Half
| ELINK_SUPPORTED_10baseT_Full
))) {
9249 /* Enabled AUTO-MDIX when autoneg is disabled */
9250 elink_cl45_write(sc
, phy
,
9251 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_AUX_CTRL
,
9252 (1 << 15 | 1 << 9 | 7 << 0));
9253 PMD_DRV_LOG(DEBUG
, "Setting 10M force");
9256 elink_cl45_write(sc
, phy
,
9257 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_LEGACY_AN_ADV
,
9260 if (phy
->req_duplex
== DUPLEX_FULL
)
9261 autoneg_val
|= (1 << 8);
9263 /* Always write this if this is not 84833/4.
9264 * For 84833/4, write it only when it's a forced speed.
9266 if (((phy
->type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) &&
9267 (phy
->type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
)) ||
9268 ((autoneg_val
& (1 << 12)) == 0))
9269 elink_cl45_write(sc
, phy
,
9271 MDIO_AN_REG_8481_LEGACY_MII_CTRL
, autoneg_val
);
9273 if (((phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) &&
9274 (phy
->speed_cap_mask
&
9275 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)) ||
9276 (phy
->req_line_speed
== ELINK_SPEED_10000
)) {
9277 PMD_DRV_LOG(DEBUG
, "Advertising 10G");
9278 /* Restart autoneg for 10G */
9280 elink_cl45_read_or_write(sc
, phy
,
9282 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL
,
9284 elink_cl45_write(sc
, phy
,
9285 MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x3200);
9287 elink_cl45_write(sc
, phy
,
9289 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL
, 1);
9291 return ELINK_STATUS_OK
;
9294 static elink_status_t
elink_8481_config_init(struct elink_phy
*phy
,
9295 struct elink_params
*params
,
9296 struct elink_vars
*vars
)
9298 struct bnx2x_softc
*sc
= params
->sc
;
9299 /* Restore normal power mode */
9300 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
9301 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, params
->port
);
9304 elink_ext_phy_hw_reset(sc
, params
->port
);
9305 elink_wait_reset_complete(sc
, phy
, params
);
9307 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 1 << 15);
9308 return elink_848xx_cmn_config_init(phy
, params
, vars
);
9311 #define PHY84833_CMDHDLR_WAIT 300
9312 #define PHY84833_CMDHDLR_MAX_ARGS 5
9313 static elink_status_t
elink_84833_cmd_hdlr(struct elink_phy
*phy
,
9314 struct elink_params
*params
,
9315 uint16_t fw_cmd
, uint16_t cmd_args
[],
9320 struct bnx2x_softc
*sc
= params
->sc
;
9321 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9322 elink_cl45_write(sc
, phy
, MDIO_CTL_DEVAD
,
9323 MDIO_84833_CMD_HDLR_STATUS
,
9324 PHY84833_STATUS_CMD_OPEN_OVERRIDE
);
9325 for (idx
= 0; idx
< PHY84833_CMDHDLR_WAIT
; idx
++) {
9326 elink_cl45_read(sc
, phy
, MDIO_CTL_DEVAD
,
9327 MDIO_84833_CMD_HDLR_STATUS
, &val
);
9328 if (val
== PHY84833_STATUS_CMD_OPEN_FOR_CMDS
)
9332 if (idx
>= PHY84833_CMDHDLR_WAIT
) {
9333 PMD_DRV_LOG(DEBUG
, "FW cmd: FW not ready.");
9334 return ELINK_STATUS_ERROR
;
9337 /* Prepare argument(s) and issue command */
9338 for (idx
= 0; idx
< argc
; idx
++) {
9339 elink_cl45_write(sc
, phy
, MDIO_CTL_DEVAD
,
9340 MDIO_84833_CMD_HDLR_DATA1
+ idx
,
9343 elink_cl45_write(sc
, phy
, MDIO_CTL_DEVAD
,
9344 MDIO_84833_CMD_HDLR_COMMAND
, fw_cmd
);
9345 for (idx
= 0; idx
< PHY84833_CMDHDLR_WAIT
; idx
++) {
9346 elink_cl45_read(sc
, phy
, MDIO_CTL_DEVAD
,
9347 MDIO_84833_CMD_HDLR_STATUS
, &val
);
9348 if ((val
== PHY84833_STATUS_CMD_COMPLETE_PASS
) ||
9349 (val
== PHY84833_STATUS_CMD_COMPLETE_ERROR
))
9353 if ((idx
>= PHY84833_CMDHDLR_WAIT
) ||
9354 (val
== PHY84833_STATUS_CMD_COMPLETE_ERROR
)) {
9355 PMD_DRV_LOG(DEBUG
, "FW cmd failed.");
9356 return ELINK_STATUS_ERROR
;
9358 /* Gather returning data */
9359 for (idx
= 0; idx
< argc
; idx
++) {
9360 elink_cl45_read(sc
, phy
, MDIO_CTL_DEVAD
,
9361 MDIO_84833_CMD_HDLR_DATA1
+ idx
,
9364 elink_cl45_write(sc
, phy
, MDIO_CTL_DEVAD
,
9365 MDIO_84833_CMD_HDLR_STATUS
,
9366 PHY84833_STATUS_CMD_CLEAR_COMPLETE
);
9367 return ELINK_STATUS_OK
;
9370 static elink_status_t
elink_84833_pair_swap_cfg(struct elink_phy
*phy
,
9371 struct elink_params
*params
,
9372 __rte_unused
struct elink_vars
9376 uint16_t data
[PHY84833_CMDHDLR_MAX_ARGS
];
9377 elink_status_t status
;
9378 struct bnx2x_softc
*sc
= params
->sc
;
9380 /* Check for configuration. */
9381 pair_swap
= REG_RD(sc
, params
->shmem_base
+
9382 offsetof(struct shmem_region
,
9383 dev_info
.port_hw_config
[params
->port
].
9385 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK
;
9388 return ELINK_STATUS_OK
;
9390 /* Only the second argument is used for this command */
9391 data
[1] = (uint16_t) pair_swap
;
9393 status
= elink_84833_cmd_hdlr(phy
, params
,
9394 PHY84833_CMD_SET_PAIR_SWAP
, data
,
9395 PHY84833_CMDHDLR_MAX_ARGS
);
9396 if (status
== ELINK_STATUS_OK
) {
9397 PMD_DRV_LOG(DEBUG
, "Pairswap OK, val=0x%x", data
[1]);
9403 static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc
*sc
,
9404 uint32_t shmem_base_path
[],
9405 __rte_unused
uint32_t chip_id
)
9407 uint32_t reset_pin
[2];
9409 uint8_t reset_gpios
;
9410 if (CHIP_IS_E3(sc
)) {
9411 /* Assume that these will be GPIOs, not EPIOs. */
9412 for (idx
= 0; idx
< 2; idx
++) {
9413 /* Map config param to register bit. */
9414 reset_pin
[idx
] = REG_RD(sc
, shmem_base_path
[idx
] +
9415 offsetof(struct shmem_region
,
9420 (reset_pin
[idx
] & PORT_HW_CFG_E3_PHY_RESET_MASK
) >>
9421 PORT_HW_CFG_E3_PHY_RESET_SHIFT
;
9422 reset_pin
[idx
] -= PIN_CFG_GPIO0_P0
;
9423 reset_pin
[idx
] = (1 << reset_pin
[idx
]);
9425 reset_gpios
= (uint8_t) (reset_pin
[0] | reset_pin
[1]);
9427 /* E2, look from diff place of shmem. */
9428 for (idx
= 0; idx
< 2; idx
++) {
9429 reset_pin
[idx
] = REG_RD(sc
, shmem_base_path
[idx
] +
9430 offsetof(struct shmem_region
,
9434 reset_pin
[idx
] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK
;
9435 reset_pin
[idx
] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0
;
9436 reset_pin
[idx
] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT
;
9437 reset_pin
[idx
] = (1 << reset_pin
[idx
]);
9439 reset_gpios
= (uint8_t) (reset_pin
[0] | reset_pin
[1]);
9445 static elink_status_t
elink_84833_hw_reset_phy(struct elink_phy
*phy
,
9446 struct elink_params
*params
)
9448 struct bnx2x_softc
*sc
= params
->sc
;
9449 uint8_t reset_gpios
;
9450 uint32_t other_shmem_base_addr
= REG_RD(sc
, params
->shmem2_base
+
9451 offsetof(struct shmem2_region
,
9452 other_shmem_base_addr
));
9454 uint32_t shmem_base_path
[2];
9456 /* Work around for 84833 LED failure inside RESET status */
9457 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
,
9458 MDIO_AN_REG_8481_LEGACY_MII_CTRL
,
9459 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G
);
9460 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
,
9461 MDIO_AN_REG_8481_1G_100T_EXT_CTRL
,
9462 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF
);
9464 shmem_base_path
[0] = params
->shmem_base
;
9465 shmem_base_path
[1] = other_shmem_base_addr
;
9467 reset_gpios
= elink_84833_get_reset_gpios(sc
, shmem_base_path
,
9470 elink_cb_gpio_mult_write(sc
, reset_gpios
,
9471 MISC_REGISTERS_GPIO_OUTPUT_LOW
);
9473 PMD_DRV_LOG(DEBUG
, "84833 hw reset on pin values 0x%x", reset_gpios
);
9475 return ELINK_STATUS_OK
;
9478 static elink_status_t
elink_8483x_disable_eee(struct elink_phy
*phy
,
9479 struct elink_params
*params
,
9480 struct elink_vars
*vars
)
9483 uint16_t cmd_args
= 0;
9485 PMD_DRV_LOG(DEBUG
, "Don't Advertise 10GBase-T EEE");
9487 /* Prevent Phy from working in EEE and advertising it */
9488 rc
= elink_84833_cmd_hdlr(phy
, params
,
9489 PHY84833_CMD_SET_EEE_MODE
, &cmd_args
, 1);
9490 if (rc
!= ELINK_STATUS_OK
) {
9491 PMD_DRV_LOG(DEBUG
, "EEE disable failed.");
9495 return elink_eee_disable(phy
, params
, vars
);
9498 static elink_status_t
elink_8483x_enable_eee(struct elink_phy
*phy
,
9499 struct elink_params
*params
,
9500 struct elink_vars
*vars
)
9503 uint16_t cmd_args
= 1;
9505 rc
= elink_84833_cmd_hdlr(phy
, params
,
9506 PHY84833_CMD_SET_EEE_MODE
, &cmd_args
, 1);
9507 if (rc
!= ELINK_STATUS_OK
) {
9508 PMD_DRV_LOG(DEBUG
, "EEE enable failed.");
9512 return elink_eee_advertise(phy
, params
, vars
, SHMEM_EEE_10G_ADV
);
9515 #define PHY84833_CONSTANT_LATENCY 1193
9516 static elink_status_t
elink_848x3_config_init(struct elink_phy
*phy
,
9517 struct elink_params
*params
,
9518 struct elink_vars
*vars
)
9520 struct bnx2x_softc
*sc
= params
->sc
;
9521 uint8_t port
, initialize
= 1;
9523 uint32_t actual_phy_selection
;
9524 uint16_t cmd_args
[PHY84833_CMDHDLR_MAX_ARGS
];
9525 elink_status_t rc
= ELINK_STATUS_OK
;
9529 if (!(CHIP_IS_E1x(sc
)))
9532 port
= params
->port
;
9534 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823
) {
9535 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_3
,
9536 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, port
);
9539 elink_cl45_write(sc
, phy
,
9540 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x8000);
9543 elink_wait_reset_complete(sc
, phy
, params
);
9545 /* Wait for GPHY to come out of reset */
9547 if ((phy
->type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) &&
9548 (phy
->type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
)) {
9549 /* BNX2X84823 requires that XGXS links up first @ 10G for normal
9553 temp
= vars
->line_speed
;
9554 vars
->line_speed
= ELINK_SPEED_10000
;
9555 elink_set_autoneg(¶ms
->phy
[ELINK_INT_PHY
], params
, vars
, 0);
9556 elink_program_serdes(¶ms
->phy
[ELINK_INT_PHY
], params
, vars
);
9557 vars
->line_speed
= temp
;
9560 elink_cl45_read(sc
, phy
, MDIO_CTL_DEVAD
,
9561 MDIO_CTL_REG_84823_MEDIA
, &val
);
9562 val
&= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK
|
9563 MDIO_CTL_REG_84823_MEDIA_LINE_MASK
|
9564 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN
|
9565 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK
|
9566 MDIO_CTL_REG_84823_MEDIA_FIBER_1G
);
9568 if (CHIP_IS_E3(sc
)) {
9569 val
&= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK
|
9570 MDIO_CTL_REG_84823_MEDIA_LINE_MASK
);
9572 val
|= (MDIO_CTL_REG_84823_CTRL_MAC_XFI
|
9573 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L
);
9576 actual_phy_selection
= elink_phy_selection(params
);
9578 switch (actual_phy_selection
) {
9579 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT
:
9580 /* Do nothing. Essentially this is like the priority copper */
9582 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY
:
9583 val
|= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER
;
9585 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY
:
9586 val
|= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER
;
9588 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
:
9589 /* Do nothing here. The first PHY won't be initialized at all */
9591 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY
:
9592 val
|= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN
;
9596 if (params
->phy
[ELINK_EXT_PHY2
].req_line_speed
== ELINK_SPEED_1000
)
9597 val
|= MDIO_CTL_REG_84823_MEDIA_FIBER_1G
;
9599 elink_cl45_write(sc
, phy
, MDIO_CTL_DEVAD
,
9600 MDIO_CTL_REG_84823_MEDIA
, val
);
9601 PMD_DRV_LOG(DEBUG
, "Multi_phy config = 0x%x, Media control = 0x%x",
9602 params
->multi_phy_config
, val
);
9604 if ((phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) ||
9605 (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
)) {
9606 elink_84833_pair_swap_cfg(phy
, params
, vars
);
9608 /* Keep AutogrEEEn disabled. */
9611 cmd_args
[2] = PHY84833_CONSTANT_LATENCY
+ 1;
9612 cmd_args
[3] = PHY84833_CONSTANT_LATENCY
;
9613 rc
= elink_84833_cmd_hdlr(phy
, params
,
9614 PHY84833_CMD_SET_EEE_MODE
, cmd_args
,
9615 PHY84833_CMDHDLR_MAX_ARGS
);
9616 if (rc
!= ELINK_STATUS_OK
) {
9617 PMD_DRV_LOG(DEBUG
, "Cfg AutogrEEEn failed.");
9621 rc
= elink_848xx_cmn_config_init(phy
, params
, vars
);
9623 elink_save_848xx_spirom_version(phy
, sc
, params
->port
);
9625 /* 84833 PHY has a better feature and doesn't need to support this. */
9626 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823
) {
9627 uint32_t cms_enable
= REG_RD(sc
, params
->shmem_base
+
9628 offsetof(struct shmem_region
,
9630 port_hw_config
[params
->
9633 PORT_HW_CFG_ENABLE_CMS_MASK
;
9635 elink_cl45_read(sc
, phy
, MDIO_CTL_DEVAD
,
9636 MDIO_CTL_REG_84823_USER_CTRL_REG
, &val
);
9638 val
|= MDIO_CTL_REG_84823_USER_CTRL_CMS
;
9640 val
&= ~MDIO_CTL_REG_84823_USER_CTRL_CMS
;
9641 elink_cl45_write(sc
, phy
, MDIO_CTL_DEVAD
,
9642 MDIO_CTL_REG_84823_USER_CTRL_REG
, val
);
9645 elink_cl45_read(sc
, phy
, MDIO_CTL_DEVAD
,
9646 MDIO_84833_TOP_CFG_FW_REV
, &val
);
9648 /* Configure EEE support */
9649 if ((val
>= MDIO_84833_TOP_CFG_FW_EEE
) &&
9650 (val
!= MDIO_84833_TOP_CFG_FW_NO_EEE
) &&
9651 elink_eee_has_cap(params
)) {
9652 rc
= elink_eee_initial_config(params
, vars
, SHMEM_EEE_10G_ADV
);
9653 if (rc
!= ELINK_STATUS_OK
) {
9654 PMD_DRV_LOG(DEBUG
, "Failed to configure EEE timers");
9655 elink_8483x_disable_eee(phy
, params
, vars
);
9659 if ((phy
->req_duplex
== DUPLEX_FULL
) &&
9660 (params
->eee_mode
& ELINK_EEE_MODE_ADV_LPI
) &&
9661 (elink_eee_calc_timer(params
) ||
9662 !(params
->eee_mode
& ELINK_EEE_MODE_ENABLE_LPI
)))
9663 rc
= elink_8483x_enable_eee(phy
, params
, vars
);
9665 rc
= elink_8483x_disable_eee(phy
, params
, vars
);
9666 if (rc
!= ELINK_STATUS_OK
) {
9667 PMD_DRV_LOG(DEBUG
, "Failed to set EEE advertisement");
9671 vars
->eee_status
&= ~SHMEM_EEE_SUPPORTED_MASK
;
9674 if ((phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) ||
9675 (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
)) {
9676 /* Bring PHY out of super isolate mode as the final step. */
9677 elink_cl45_read_and_write(sc
, phy
,
9679 MDIO_84833_TOP_CFG_XGPHY_STRAP1
,
9681 MDIO_84833_SUPER_ISOLATE
);
9686 static uint8_t elink_848xx_read_status(struct elink_phy
*phy
,
9687 struct elink_params
*params
,
9688 struct elink_vars
*vars
)
9690 struct bnx2x_softc
*sc
= params
->sc
;
9691 uint16_t val
, val1
, val2
;
9692 uint8_t link_up
= 0;
9694 /* Check 10G-BaseT link status */
9695 /* Check PMD signal ok */
9696 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, 0xFFFA, &val1
);
9697 elink_cl45_read(sc
, phy
,
9698 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8481_PMD_SIGNAL
, &val2
);
9699 PMD_DRV_LOG(DEBUG
, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2
);
9701 /* Check link 10G */
9702 if (val2
& (1 << 11)) {
9703 vars
->line_speed
= ELINK_SPEED_10000
;
9704 vars
->duplex
= DUPLEX_FULL
;
9706 elink_ext_phy_10G_an_resolve(sc
, phy
, vars
);
9707 } else { /* Check Legacy speed link */
9708 uint16_t legacy_status
, legacy_speed
, mii_ctrl
;
9710 /* Enable expansion register 0x42 (Operation mode status) */
9711 elink_cl45_write(sc
, phy
,
9713 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS
, 0xf42);
9715 /* Get legacy speed operation status */
9716 elink_cl45_read(sc
, phy
,
9718 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW
,
9721 PMD_DRV_LOG(DEBUG
, "Legacy speed status = 0x%x", legacy_status
);
9722 link_up
= ((legacy_status
& (1 << 11)) == (1 << 11));
9723 legacy_speed
= (legacy_status
& (3 << 9));
9724 if (legacy_speed
== (0 << 9))
9725 vars
->line_speed
= ELINK_SPEED_10
;
9726 else if (legacy_speed
== (1 << 9))
9727 vars
->line_speed
= ELINK_SPEED_100
;
9728 else if (legacy_speed
== (2 << 9))
9729 vars
->line_speed
= ELINK_SPEED_1000
;
9730 else { /* Should not happen: Treat as link down */
9731 vars
->line_speed
= 0;
9735 if (params
->feature_config_flags
&
9736 ELINK_FEATURE_CONFIG_IEEE_PHY_TEST
) {
9737 elink_cl45_read(sc
, phy
,
9739 MDIO_AN_REG_8481_LEGACY_MII_CTRL
,
9741 /* For IEEE testing, check for a fake link. */
9742 link_up
|= ((mii_ctrl
& 0x3040) == 0x40);
9746 if (legacy_status
& (1 << 8))
9747 vars
->duplex
= DUPLEX_FULL
;
9749 vars
->duplex
= DUPLEX_HALF
;
9752 "Link is up in %dMbps, is_duplex_full= %d",
9754 (vars
->duplex
== DUPLEX_FULL
));
9755 /* Check legacy speed AN resolution */
9756 elink_cl45_read(sc
, phy
,
9758 MDIO_AN_REG_8481_LEGACY_MII_STATUS
,
9761 vars
->link_status
|=
9762 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
9763 elink_cl45_read(sc
, phy
,
9765 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION
,
9767 if ((val
& (1 << 0)) == 0)
9768 vars
->link_status
|=
9769 LINK_STATUS_PARALLEL_DETECTION_USED
;
9773 PMD_DRV_LOG(DEBUG
, "BNX2X848x3: link speed is %d",
9775 elink_ext_phy_resolve_fc(phy
, params
, vars
);
9777 /* Read LP advertised speeds */
9778 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
9779 MDIO_AN_REG_CL37_FC_LP
, &val
);
9781 vars
->link_status
|=
9782 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE
;
9784 vars
->link_status
|=
9785 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE
;
9787 vars
->link_status
|=
9788 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE
;
9790 vars
->link_status
|=
9791 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE
;
9793 vars
->link_status
|=
9794 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE
;
9796 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
9797 MDIO_AN_REG_1000T_STATUS
, &val
);
9799 if (val
& (1 << 10))
9800 vars
->link_status
|=
9801 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE
;
9802 if (val
& (1 << 11))
9803 vars
->link_status
|=
9804 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE
;
9806 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
9807 MDIO_AN_REG_MASTER_STATUS
, &val
);
9809 if (val
& (1 << 11))
9810 vars
->link_status
|=
9811 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
9813 /* Determine if EEE was negotiated */
9814 if ((phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) ||
9815 (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
))
9816 elink_eee_an_resolve(phy
, params
, vars
);
9822 static elink_status_t
elink_848xx_format_ver(uint32_t raw_ver
, uint8_t * str
,
9825 elink_status_t status
= ELINK_STATUS_OK
;
9826 uint32_t spirom_ver
;
9827 spirom_ver
= ((raw_ver
& 0xF80) >> 7) << 16 | (raw_ver
& 0x7F);
9828 status
= elink_format_ver(spirom_ver
, str
, len
);
9832 static void elink_8481_hw_reset(__rte_unused
struct elink_phy
*phy
,
9833 struct elink_params
*params
)
9835 elink_cb_gpio_write(params
->sc
, MISC_REGISTERS_GPIO_1
,
9836 MISC_REGISTERS_GPIO_OUTPUT_LOW
, 0);
9837 elink_cb_gpio_write(params
->sc
, MISC_REGISTERS_GPIO_1
,
9838 MISC_REGISTERS_GPIO_OUTPUT_LOW
, 1);
9841 static void elink_8481_link_reset(struct elink_phy
*phy
,
9842 struct elink_params
*params
)
9844 elink_cl45_write(params
->sc
, phy
,
9845 MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x0000);
9846 elink_cl45_write(params
->sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 1);
9849 static void elink_848x3_link_reset(struct elink_phy
*phy
,
9850 struct elink_params
*params
)
9852 struct bnx2x_softc
*sc
= params
->sc
;
9856 if (!(CHIP_IS_E1x(sc
)))
9859 port
= params
->port
;
9861 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823
) {
9862 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_3
,
9863 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
9865 elink_cl45_read(sc
, phy
,
9867 MDIO_84833_TOP_CFG_XGPHY_STRAP1
, &val16
);
9868 val16
|= MDIO_84833_SUPER_ISOLATE
;
9869 elink_cl45_write(sc
, phy
,
9871 MDIO_84833_TOP_CFG_XGPHY_STRAP1
, val16
);
9875 static void elink_848xx_set_link_led(struct elink_phy
*phy
,
9876 struct elink_params
*params
, uint8_t mode
)
9878 struct bnx2x_softc
*sc
= params
->sc
;
9880 __rte_unused
uint8_t port
;
9882 if (!(CHIP_IS_E1x(sc
)))
9885 port
= params
->port
;
9888 case ELINK_LED_MODE_OFF
:
9890 PMD_DRV_LOG(DEBUG
, "Port 0x%x: LED MODE OFF", port
);
9892 if ((params
->hw_led_mode
<< SHARED_HW_CFG_LED_MODE_SHIFT
) ==
9893 SHARED_HW_CFG_LED_EXTPHY1
) {
9896 elink_cl45_write(sc
, phy
,
9898 MDIO_PMA_REG_8481_LED1_MASK
, 0x0);
9900 elink_cl45_write(sc
, phy
,
9902 MDIO_PMA_REG_8481_LED2_MASK
, 0x0);
9904 elink_cl45_write(sc
, phy
,
9906 MDIO_PMA_REG_8481_LED3_MASK
, 0x0);
9908 elink_cl45_write(sc
, phy
,
9910 MDIO_PMA_REG_8481_LED5_MASK
, 0x0);
9913 elink_cl45_write(sc
, phy
,
9915 MDIO_PMA_REG_8481_LED1_MASK
, 0x0);
9918 case ELINK_LED_MODE_FRONT_PANEL_OFF
:
9920 PMD_DRV_LOG(DEBUG
, "Port 0x%x: LED MODE FRONT PANEL OFF", port
);
9922 if ((params
->hw_led_mode
<< SHARED_HW_CFG_LED_MODE_SHIFT
) ==
9923 SHARED_HW_CFG_LED_EXTPHY1
) {
9926 elink_cl45_write(sc
, phy
,
9928 MDIO_PMA_REG_8481_LED1_MASK
, 0x0);
9930 elink_cl45_write(sc
, phy
,
9932 MDIO_PMA_REG_8481_LED2_MASK
, 0x0);
9934 elink_cl45_write(sc
, phy
,
9936 MDIO_PMA_REG_8481_LED3_MASK
, 0x0);
9938 elink_cl45_write(sc
, phy
,
9940 MDIO_PMA_REG_8481_LED5_MASK
, 0x20);
9943 elink_cl45_write(sc
, phy
,
9945 MDIO_PMA_REG_8481_LED1_MASK
, 0x0);
9946 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
) {
9947 /* Disable MI_INT interrupt before setting LED4
9948 * source to constant off.
9950 if (REG_RD(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+
9952 ELINK_NIG_MASK_MI_INT
) {
9953 params
->link_flags
|=
9954 ELINK_LINK_FLAGS_INT_DISABLED
;
9957 NIG_REG_MASK_INTERRUPT_PORT0
9959 ELINK_NIG_MASK_MI_INT
);
9961 elink_cl45_write(sc
, phy
,
9963 MDIO_PMA_REG_8481_SIGNAL_MASK
,
9968 case ELINK_LED_MODE_ON
:
9970 PMD_DRV_LOG(DEBUG
, "Port 0x%x: LED MODE ON", port
);
9972 if ((params
->hw_led_mode
<< SHARED_HW_CFG_LED_MODE_SHIFT
) ==
9973 SHARED_HW_CFG_LED_EXTPHY1
) {
9974 /* Set control reg */
9975 elink_cl45_read(sc
, phy
,
9977 MDIO_PMA_REG_8481_LINK_SIGNAL
, &val
);
9981 elink_cl45_write(sc
, phy
,
9983 MDIO_PMA_REG_8481_LINK_SIGNAL
, val
);
9986 elink_cl45_write(sc
, phy
,
9988 MDIO_PMA_REG_8481_LED1_MASK
, 0x0);
9990 elink_cl45_write(sc
, phy
,
9992 MDIO_PMA_REG_8481_LED2_MASK
, 0x20);
9994 elink_cl45_write(sc
, phy
,
9996 MDIO_PMA_REG_8481_LED3_MASK
, 0x20);
9998 elink_cl45_write(sc
, phy
,
10000 MDIO_PMA_REG_8481_LED5_MASK
, 0x0);
10002 elink_cl45_write(sc
, phy
,
10004 MDIO_PMA_REG_8481_LED1_MASK
, 0x20);
10005 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
) {
10006 /* Disable MI_INT interrupt before setting LED4
10007 * source to constant on.
10009 if (REG_RD(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+
10010 params
->port
* 4) &
10011 ELINK_NIG_MASK_MI_INT
) {
10012 params
->link_flags
|=
10013 ELINK_LINK_FLAGS_INT_DISABLED
;
10016 NIG_REG_MASK_INTERRUPT_PORT0
10017 + params
->port
* 4,
10018 ELINK_NIG_MASK_MI_INT
);
10020 elink_cl45_write(sc
, phy
,
10022 MDIO_PMA_REG_8481_SIGNAL_MASK
,
10028 case ELINK_LED_MODE_OPER
:
10030 PMD_DRV_LOG(DEBUG
, "Port 0x%x: LED MODE OPER", port
);
10032 if ((params
->hw_led_mode
<< SHARED_HW_CFG_LED_MODE_SHIFT
) ==
10033 SHARED_HW_CFG_LED_EXTPHY1
) {
10035 /* Set control reg */
10036 elink_cl45_read(sc
, phy
,
10038 MDIO_PMA_REG_8481_LINK_SIGNAL
, &val
);
10041 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK
)
10043 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT
))
10045 PMD_DRV_LOG(DEBUG
, "Setting LINK_SIGNAL");
10046 elink_cl45_write(sc
, phy
,
10048 MDIO_PMA_REG_8481_LINK_SIGNAL
,
10052 /* Set LED masks */
10053 elink_cl45_write(sc
, phy
,
10055 MDIO_PMA_REG_8481_LED1_MASK
, 0x10);
10057 elink_cl45_write(sc
, phy
,
10059 MDIO_PMA_REG_8481_LED2_MASK
, 0x80);
10061 elink_cl45_write(sc
, phy
,
10063 MDIO_PMA_REG_8481_LED3_MASK
, 0x98);
10065 elink_cl45_write(sc
, phy
,
10067 MDIO_PMA_REG_8481_LED5_MASK
, 0x40);
10070 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
10071 * sources are all wired through LED1, rather than only
10072 * 10G in other modes.
10074 val
= ((params
->hw_led_mode
<<
10075 SHARED_HW_CFG_LED_MODE_SHIFT
) ==
10076 SHARED_HW_CFG_LED_EXTPHY2
) ? 0x98 : 0x80;
10078 elink_cl45_write(sc
, phy
,
10080 MDIO_PMA_REG_8481_LED1_MASK
, val
);
10082 /* Tell LED3 to blink on source */
10083 elink_cl45_read(sc
, phy
,
10085 MDIO_PMA_REG_8481_LINK_SIGNAL
, &val
);
10087 val
|= (1 << 6); /* A83B[8:6]= 1 */
10088 elink_cl45_write(sc
, phy
,
10090 MDIO_PMA_REG_8481_LINK_SIGNAL
, val
);
10091 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
) {
10092 /* Restore LED4 source to external link,
10093 * and re-enable interrupts.
10095 elink_cl45_write(sc
, phy
,
10097 MDIO_PMA_REG_8481_SIGNAL_MASK
,
10099 if (params
->link_flags
&
10100 ELINK_LINK_FLAGS_INT_DISABLED
) {
10101 elink_link_int_enable(params
);
10102 params
->link_flags
&=
10103 ~ELINK_LINK_FLAGS_INT_DISABLED
;
10110 /* This is a workaround for E3+84833 until autoneg
10111 * restart is fixed in f/w
10113 if (CHIP_IS_E3(sc
)) {
10114 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
10115 MDIO_WC_REG_GP2_STATUS_GP_2_1
, &val
);
10119 /******************************************************************/
10120 /* 54618SE PHY SECTION */
10121 /******************************************************************/
10122 static void elink_54618se_specific_func(struct elink_phy
*phy
,
10123 struct elink_params
*params
,
10126 struct bnx2x_softc
*sc
= params
->sc
;
10129 case ELINK_PHY_INIT
:
10130 /* Configure LED4: set to INTR (0x6). */
10131 /* Accessing shadow register 0xe. */
10132 elink_cl22_write(sc
, phy
,
10133 MDIO_REG_GPHY_SHADOW
,
10134 MDIO_REG_GPHY_SHADOW_LED_SEL2
);
10135 elink_cl22_read(sc
, phy
, MDIO_REG_GPHY_SHADOW
, &temp
);
10136 temp
&= ~(0xf << 4);
10137 temp
|= (0x6 << 4);
10138 elink_cl22_write(sc
, phy
,
10139 MDIO_REG_GPHY_SHADOW
,
10140 MDIO_REG_GPHY_SHADOW_WR_ENA
| temp
);
10141 /* Configure INTR based on link status change. */
10142 elink_cl22_write(sc
, phy
,
10143 MDIO_REG_INTR_MASK
,
10144 ~MDIO_REG_INTR_MASK_LINK_STATUS
);
10149 static elink_status_t
elink_54618se_config_init(struct elink_phy
*phy
,
10150 struct elink_params
*params
,
10151 struct elink_vars
*vars
)
10153 struct bnx2x_softc
*sc
= params
->sc
;
10155 uint16_t autoneg_val
, an_1000_val
, an_10_100_val
, fc_val
, temp
;
10158 PMD_DRV_LOG(DEBUG
, "54618SE cfg init");
10161 /* This works with E3 only, no need to check the chip
10162 * before determining the port.
10164 port
= params
->port
;
10166 cfg_pin
= (REG_RD(sc
, params
->shmem_base
+
10167 offsetof(struct shmem_region
,
10168 dev_info
.port_hw_config
[port
].
10170 PORT_HW_CFG_E3_PHY_RESET_MASK
) >>
10171 PORT_HW_CFG_E3_PHY_RESET_SHIFT
;
10173 /* Drive pin high to bring the GPHY out of reset. */
10174 elink_set_cfg_pin(sc
, cfg_pin
, 1);
10176 /* wait for GPHY to reset */
10180 elink_cl22_write(sc
, phy
, MDIO_PMA_REG_CTRL
, 0x8000);
10181 elink_wait_reset_complete(sc
, phy
, params
);
10183 /* Wait for GPHY to reset */
10186 elink_54618se_specific_func(phy
, params
, ELINK_PHY_INIT
);
10187 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10188 elink_cl22_write(sc
, phy
,
10189 MDIO_REG_GPHY_SHADOW
,
10190 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED
);
10191 elink_cl22_read(sc
, phy
, MDIO_REG_GPHY_SHADOW
, &temp
);
10192 temp
|= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD
;
10193 elink_cl22_write(sc
, phy
,
10194 MDIO_REG_GPHY_SHADOW
,
10195 MDIO_REG_GPHY_SHADOW_WR_ENA
| temp
);
10198 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10199 elink_calc_ieee_aneg_adv(phy
, params
, &vars
->ieee_fc
);
10201 if ((vars
->ieee_fc
& MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) ==
10202 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
)
10203 fc_val
|= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC
;
10205 if ((vars
->ieee_fc
& MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) ==
10206 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
)
10207 fc_val
|= MDIO_AN_REG_ADV_PAUSE_PAUSE
;
10209 /* Read all advertisement */
10210 elink_cl22_read(sc
, phy
, 0x09, &an_1000_val
);
10212 elink_cl22_read(sc
, phy
, 0x04, &an_10_100_val
);
10214 elink_cl22_read(sc
, phy
, MDIO_PMA_REG_CTRL
, &autoneg_val
);
10216 /* Disable forced speed */
10218 ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
10220 ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 10) |
10223 if (((phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) &&
10224 (phy
->speed_cap_mask
&
10225 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)) ||
10226 (phy
->req_line_speed
== ELINK_SPEED_1000
)) {
10227 an_1000_val
|= (1 << 8);
10228 autoneg_val
|= (1 << 9 | 1 << 12);
10229 if (phy
->req_duplex
== DUPLEX_FULL
)
10230 an_1000_val
|= (1 << 9);
10231 PMD_DRV_LOG(DEBUG
, "Advertising 1G");
10233 an_1000_val
&= ~((1 << 8) | (1 << 9));
10235 elink_cl22_write(sc
, phy
, 0x09, an_1000_val
);
10236 elink_cl22_read(sc
, phy
, 0x09, &an_1000_val
);
10238 /* Advertise 10/100 link speed */
10239 if (phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) {
10240 if (phy
->speed_cap_mask
&
10241 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
) {
10242 an_10_100_val
|= (1 << 5);
10243 autoneg_val
|= (1 << 9 | 1 << 12);
10244 PMD_DRV_LOG(DEBUG
, "Advertising 10M-HD");
10246 if (phy
->speed_cap_mask
&
10247 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
) {
10248 an_10_100_val
|= (1 << 6);
10249 autoneg_val
|= (1 << 9 | 1 << 12);
10250 PMD_DRV_LOG(DEBUG
, "Advertising 10M-FD");
10252 if (phy
->speed_cap_mask
&
10253 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
) {
10254 an_10_100_val
|= (1 << 7);
10255 autoneg_val
|= (1 << 9 | 1 << 12);
10256 PMD_DRV_LOG(DEBUG
, "Advertising 100M-HD");
10258 if (phy
->speed_cap_mask
&
10259 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
) {
10260 an_10_100_val
|= (1 << 8);
10261 autoneg_val
|= (1 << 9 | 1 << 12);
10262 PMD_DRV_LOG(DEBUG
, "Advertising 100M-FD");
10266 /* Only 10/100 are allowed to work in FORCE mode */
10267 if (phy
->req_line_speed
== ELINK_SPEED_100
) {
10268 autoneg_val
|= (1 << 13);
10269 /* Enabled AUTO-MDIX when autoneg is disabled */
10270 elink_cl22_write(sc
, phy
, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
10271 PMD_DRV_LOG(DEBUG
, "Setting 100M force");
10273 if (phy
->req_line_speed
== ELINK_SPEED_10
) {
10274 /* Enabled AUTO-MDIX when autoneg is disabled */
10275 elink_cl22_write(sc
, phy
, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
10276 PMD_DRV_LOG(DEBUG
, "Setting 10M force");
10279 if ((phy
->flags
& ELINK_FLAGS_EEE
) && elink_eee_has_cap(params
)) {
10282 elink_cl22_write(sc
, phy
, MDIO_REG_GPHY_EXP_ACCESS
,
10283 MDIO_REG_GPHY_EXP_ACCESS_TOP
|
10284 MDIO_REG_GPHY_EXP_TOP_2K_BUF
);
10285 elink_cl22_read(sc
, phy
, MDIO_REG_GPHY_EXP_ACCESS_GATE
, &temp
);
10287 elink_cl22_write(sc
, phy
, MDIO_REG_GPHY_EXP_ACCESS_GATE
, temp
);
10289 rc
= elink_eee_initial_config(params
, vars
, SHMEM_EEE_1G_ADV
);
10290 if (rc
!= ELINK_STATUS_OK
) {
10291 PMD_DRV_LOG(DEBUG
, "Failed to configure EEE timers");
10292 elink_eee_disable(phy
, params
, vars
);
10293 } else if ((params
->eee_mode
& ELINK_EEE_MODE_ADV_LPI
) &&
10294 (phy
->req_duplex
== DUPLEX_FULL
) &&
10295 (elink_eee_calc_timer(params
) ||
10296 !(params
->eee_mode
& ELINK_EEE_MODE_ENABLE_LPI
))) {
10297 /* Need to advertise EEE only when requested,
10298 * and either no LPI assertion was requested,
10299 * or it was requested and a valid timer was set.
10300 * Also notice full duplex is required for EEE.
10302 elink_eee_advertise(phy
, params
, vars
,
10305 PMD_DRV_LOG(DEBUG
, "Don't Advertise 1GBase-T EEE");
10306 elink_eee_disable(phy
, params
, vars
);
10309 vars
->eee_status
&= ~SHMEM_EEE_1G_ADV
<<
10310 SHMEM_EEE_SUPPORTED_SHIFT
;
10312 if (phy
->flags
& ELINK_FLAGS_EEE
) {
10313 /* Handle legacy auto-grEEEn */
10314 if (params
->feature_config_flags
&
10315 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED
) {
10317 PMD_DRV_LOG(DEBUG
, "Enabling Auto-GrEEEn");
10320 PMD_DRV_LOG(DEBUG
, "Don't Adv. EEE");
10322 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
,
10323 MDIO_AN_REG_EEE_ADV
, temp
);
10327 elink_cl22_write(sc
, phy
, 0x04, an_10_100_val
| fc_val
);
10329 if (phy
->req_duplex
== DUPLEX_FULL
)
10330 autoneg_val
|= (1 << 8);
10332 elink_cl22_write(sc
, phy
, MDIO_PMA_REG_CTRL
, autoneg_val
);
10334 return ELINK_STATUS_OK
;
10337 static void elink_5461x_set_link_led(struct elink_phy
*phy
,
10338 struct elink_params
*params
, uint8_t mode
)
10340 struct bnx2x_softc
*sc
= params
->sc
;
10343 elink_cl22_write(sc
, phy
,
10344 MDIO_REG_GPHY_SHADOW
, MDIO_REG_GPHY_SHADOW_LED_SEL1
);
10345 elink_cl22_read(sc
, phy
, MDIO_REG_GPHY_SHADOW
, &temp
);
10348 PMD_DRV_LOG(DEBUG
, "54618x set link led (mode=%x)", mode
);
10350 case ELINK_LED_MODE_FRONT_PANEL_OFF
:
10351 case ELINK_LED_MODE_OFF
:
10354 case ELINK_LED_MODE_OPER
:
10357 case ELINK_LED_MODE_ON
:
10363 elink_cl22_write(sc
, phy
,
10364 MDIO_REG_GPHY_SHADOW
,
10365 MDIO_REG_GPHY_SHADOW_WR_ENA
| temp
);
10369 static void elink_54618se_link_reset(struct elink_phy
*phy
,
10370 struct elink_params
*params
)
10372 struct bnx2x_softc
*sc
= params
->sc
;
10376 /* In case of no EPIO routed to reset the GPHY, put it
10377 * in low power mode.
10379 elink_cl22_write(sc
, phy
, MDIO_PMA_REG_CTRL
, 0x800);
10380 /* This works with E3 only, no need to check the chip
10381 * before determining the port.
10383 port
= params
->port
;
10384 cfg_pin
= (REG_RD(sc
, params
->shmem_base
+
10385 offsetof(struct shmem_region
,
10386 dev_info
.port_hw_config
[port
].
10388 PORT_HW_CFG_E3_PHY_RESET_MASK
) >>
10389 PORT_HW_CFG_E3_PHY_RESET_SHIFT
;
10391 /* Drive pin low to put GPHY in reset. */
10392 elink_set_cfg_pin(sc
, cfg_pin
, 0);
10395 static uint8_t elink_54618se_read_status(struct elink_phy
*phy
,
10396 struct elink_params
*params
,
10397 struct elink_vars
*vars
)
10399 struct bnx2x_softc
*sc
= params
->sc
;
10401 uint8_t link_up
= 0;
10402 uint16_t legacy_status
, legacy_speed
;
10404 /* Get speed operation status */
10405 elink_cl22_read(sc
, phy
, MDIO_REG_GPHY_AUX_STATUS
, &legacy_status
);
10406 PMD_DRV_LOG(DEBUG
, "54618SE read_status: 0x%x", legacy_status
);
10408 /* Read status to clear the PHY interrupt. */
10409 elink_cl22_read(sc
, phy
, MDIO_REG_INTR_STATUS
, &val
);
10411 link_up
= ((legacy_status
& (1 << 2)) == (1 << 2));
10414 legacy_speed
= (legacy_status
& (7 << 8));
10415 if (legacy_speed
== (7 << 8)) {
10416 vars
->line_speed
= ELINK_SPEED_1000
;
10417 vars
->duplex
= DUPLEX_FULL
;
10418 } else if (legacy_speed
== (6 << 8)) {
10419 vars
->line_speed
= ELINK_SPEED_1000
;
10420 vars
->duplex
= DUPLEX_HALF
;
10421 } else if (legacy_speed
== (5 << 8)) {
10422 vars
->line_speed
= ELINK_SPEED_100
;
10423 vars
->duplex
= DUPLEX_FULL
;
10425 /* Omitting 100Base-T4 for now */
10426 else if (legacy_speed
== (3 << 8)) {
10427 vars
->line_speed
= ELINK_SPEED_100
;
10428 vars
->duplex
= DUPLEX_HALF
;
10429 } else if (legacy_speed
== (2 << 8)) {
10430 vars
->line_speed
= ELINK_SPEED_10
;
10431 vars
->duplex
= DUPLEX_FULL
;
10432 } else if (legacy_speed
== (1 << 8)) {
10433 vars
->line_speed
= ELINK_SPEED_10
;
10434 vars
->duplex
= DUPLEX_HALF
;
10435 } else /* Should not happen */
10436 vars
->line_speed
= 0;
10439 "Link is up in %dMbps, is_duplex_full= %d",
10440 vars
->line_speed
, (vars
->duplex
== DUPLEX_FULL
));
10442 /* Check legacy speed AN resolution */
10443 elink_cl22_read(sc
, phy
, 0x01, &val
);
10444 if (val
& (1 << 5))
10445 vars
->link_status
|=
10446 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
10447 elink_cl22_read(sc
, phy
, 0x06, &val
);
10448 if ((val
& (1 << 0)) == 0)
10449 vars
->link_status
|=
10450 LINK_STATUS_PARALLEL_DETECTION_USED
;
10452 PMD_DRV_LOG(DEBUG
, "BNX2X54618SE: link speed is %d",
10455 elink_ext_phy_resolve_fc(phy
, params
, vars
);
10457 if (vars
->link_status
& LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
) {
10458 /* Report LP advertised speeds */
10459 elink_cl22_read(sc
, phy
, 0x5, &val
);
10461 if (val
& (1 << 5))
10462 vars
->link_status
|=
10463 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE
;
10464 if (val
& (1 << 6))
10465 vars
->link_status
|=
10466 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE
;
10467 if (val
& (1 << 7))
10468 vars
->link_status
|=
10469 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE
;
10470 if (val
& (1 << 8))
10471 vars
->link_status
|=
10472 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE
;
10473 if (val
& (1 << 9))
10474 vars
->link_status
|=
10475 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE
;
10477 elink_cl22_read(sc
, phy
, 0xa, &val
);
10478 if (val
& (1 << 10))
10479 vars
->link_status
|=
10480 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE
;
10481 if (val
& (1 << 11))
10482 vars
->link_status
|=
10483 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE
;
10485 if ((phy
->flags
& ELINK_FLAGS_EEE
) &&
10486 elink_eee_has_cap(params
))
10487 elink_eee_an_resolve(phy
, params
, vars
);
10493 static void elink_54618se_config_loopback(struct elink_phy
*phy
,
10494 struct elink_params
*params
)
10496 struct bnx2x_softc
*sc
= params
->sc
;
10498 uint32_t umac_base
= params
->port
? GRCBASE_UMAC1
: GRCBASE_UMAC0
;
10500 PMD_DRV_LOG(DEBUG
, "2PMA/PMD ext_phy_loopback: 54618se");
10502 /* Enable master/slave manual mmode and set to master */
10503 /* mii write 9 [bits set 11 12] */
10504 elink_cl22_write(sc
, phy
, 0x09, 3 << 11);
10506 /* forced 1G and disable autoneg */
10507 /* set val [mii read 0] */
10508 /* set val [expr $val & [bits clear 6 12 13]] */
10509 /* set val [expr $val | [bits set 6 8]] */
10510 /* mii write 0 $val */
10511 elink_cl22_read(sc
, phy
, 0x00, &val
);
10512 val
&= ~((1 << 6) | (1 << 12) | (1 << 13));
10513 val
|= (1 << 6) | (1 << 8);
10514 elink_cl22_write(sc
, phy
, 0x00, val
);
10516 /* Set external loopback and Tx using 6dB coding */
10517 /* mii write 0x18 7 */
10518 /* set val [mii read 0x18] */
10519 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10520 elink_cl22_write(sc
, phy
, 0x18, 7);
10521 elink_cl22_read(sc
, phy
, 0x18, &val
);
10522 elink_cl22_write(sc
, phy
, 0x18, val
| (1 << 10) | (1 << 15));
10524 /* This register opens the gate for the UMAC despite its name */
10525 REG_WR(sc
, NIG_REG_EGRESS_EMAC0_PORT
+ params
->port
* 4, 1);
10527 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10528 * length used by the MAC receive logic to check frames.
10530 REG_WR(sc
, umac_base
+ UMAC_REG_MAXFR
, 0x2710);
10533 /******************************************************************/
10534 /* SFX7101 PHY SECTION */
10535 /******************************************************************/
10536 static void elink_7101_config_loopback(struct elink_phy
*phy
,
10537 struct elink_params
*params
)
10539 struct bnx2x_softc
*sc
= params
->sc
;
10540 /* SFX7101_XGXS_TEST1 */
10541 elink_cl45_write(sc
, phy
,
10542 MDIO_XS_DEVAD
, MDIO_XS_SFX7101_XGXS_TEST1
, 0x100);
10545 static elink_status_t
elink_7101_config_init(struct elink_phy
*phy
,
10546 struct elink_params
*params
,
10547 struct elink_vars
*vars
)
10549 uint16_t fw_ver1
, fw_ver2
, val
;
10550 struct bnx2x_softc
*sc
= params
->sc
;
10551 PMD_DRV_LOG(DEBUG
, "Setting the SFX7101 LASI indication");
10553 /* Restore normal power mode */
10554 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
10555 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, params
->port
);
10557 elink_ext_phy_hw_reset(sc
, params
->port
);
10558 elink_wait_reset_complete(sc
, phy
, params
);
10560 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0x1);
10561 PMD_DRV_LOG(DEBUG
, "Setting the SFX7101 LED to blink on traffic");
10562 elink_cl45_write(sc
, phy
,
10563 MDIO_PMA_DEVAD
, MDIO_PMA_REG_7107_LED_CNTL
, (1 << 3));
10565 elink_ext_phy_set_pause(params
, phy
, vars
);
10566 /* Restart autoneg */
10567 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, &val
);
10569 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, val
);
10571 /* Save spirom version */
10572 elink_cl45_read(sc
, phy
,
10573 MDIO_PMA_DEVAD
, MDIO_PMA_REG_7101_VER1
, &fw_ver1
);
10575 elink_cl45_read(sc
, phy
,
10576 MDIO_PMA_DEVAD
, MDIO_PMA_REG_7101_VER2
, &fw_ver2
);
10577 elink_save_spirom_version(sc
, params
->port
,
10578 (uint32_t) (fw_ver1
<< 16 | fw_ver2
),
10580 return ELINK_STATUS_OK
;
10583 static uint8_t elink_7101_read_status(struct elink_phy
*phy
,
10584 struct elink_params
*params
,
10585 struct elink_vars
*vars
)
10587 struct bnx2x_softc
*sc
= params
->sc
;
10589 uint16_t val1
, val2
;
10590 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val2
);
10591 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val1
);
10592 PMD_DRV_LOG(DEBUG
, "10G-base-T LASI status 0x%x->0x%x", val2
, val1
);
10593 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val2
);
10594 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val1
);
10595 PMD_DRV_LOG(DEBUG
, "10G-base-T PMA status 0x%x->0x%x", val2
, val1
);
10596 link_up
= ((val1
& 4) == 4);
10597 /* If link is up print the AN outcome of the SFX7101 PHY */
10599 elink_cl45_read(sc
, phy
,
10600 MDIO_AN_DEVAD
, MDIO_AN_REG_MASTER_STATUS
,
10602 vars
->line_speed
= ELINK_SPEED_10000
;
10603 vars
->duplex
= DUPLEX_FULL
;
10604 PMD_DRV_LOG(DEBUG
, "SFX7101 AN status 0x%x->Master=%x",
10605 val2
, (val2
& (1 << 14)));
10606 elink_ext_phy_10G_an_resolve(sc
, phy
, vars
);
10607 elink_ext_phy_resolve_fc(phy
, params
, vars
);
10609 /* Read LP advertised speeds */
10610 if (val2
& (1 << 11))
10611 vars
->link_status
|=
10612 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
10617 static elink_status_t
elink_7101_format_ver(uint32_t spirom_ver
, uint8_t * str
,
10621 return ELINK_STATUS_ERROR
;
10622 str
[0] = (spirom_ver
& 0xFF);
10623 str
[1] = (spirom_ver
& 0xFF00) >> 8;
10624 str
[2] = (spirom_ver
& 0xFF0000) >> 16;
10625 str
[3] = (spirom_ver
& 0xFF000000) >> 24;
10628 return ELINK_STATUS_OK
;
10631 static void elink_7101_hw_reset(__rte_unused
struct elink_phy
*phy
,
10632 struct elink_params
*params
)
10634 /* Low power mode is controlled by GPIO 2 */
10635 elink_cb_gpio_write(params
->sc
, MISC_REGISTERS_GPIO_2
,
10636 MISC_REGISTERS_GPIO_OUTPUT_LOW
, params
->port
);
10637 /* The PHY reset is controlled by GPIO 1 */
10638 elink_cb_gpio_write(params
->sc
, MISC_REGISTERS_GPIO_1
,
10639 MISC_REGISTERS_GPIO_OUTPUT_LOW
, params
->port
);
10642 static void elink_7101_set_link_led(struct elink_phy
*phy
,
10643 struct elink_params
*params
, uint8_t mode
)
10646 struct bnx2x_softc
*sc
= params
->sc
;
10648 case ELINK_LED_MODE_FRONT_PANEL_OFF
:
10649 case ELINK_LED_MODE_OFF
:
10652 case ELINK_LED_MODE_ON
:
10655 case ELINK_LED_MODE_OPER
:
10659 elink_cl45_write(sc
, phy
,
10660 MDIO_PMA_DEVAD
, MDIO_PMA_REG_7107_LINK_LED_CNTL
, val
);
10663 /******************************************************************/
10664 /* STATIC PHY DECLARATION */
10665 /******************************************************************/
10667 static const struct elink_phy phy_null
= {
10668 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
,
10671 .flags
= ELINK_FLAGS_INIT_XGXS_FIRST
,
10672 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10673 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10676 .media_type
= ELINK_ETH_PHY_NOT_PRESENT
,
10678 .req_flow_ctrl
= 0,
10679 .req_line_speed
= 0,
10680 .speed_cap_mask
= 0,
10683 .config_init
= (config_init_t
) NULL
,
10684 .read_status
= (read_status_t
) NULL
,
10685 .link_reset
= (link_reset_t
) NULL
,
10686 .config_loopback
= (config_loopback_t
) NULL
,
10687 .format_fw_ver
= (format_fw_ver_t
) NULL
,
10688 .hw_reset
= (hw_reset_t
) NULL
,
10689 .set_link_led
= (set_link_led_t
) NULL
,
10690 .phy_specific_func
= (phy_specific_func_t
) NULL
10693 static const struct elink_phy phy_serdes
= {
10694 .type
= PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT
,
10698 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10699 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10701 .supported
= (ELINK_SUPPORTED_10baseT_Half
|
10702 ELINK_SUPPORTED_10baseT_Full
|
10703 ELINK_SUPPORTED_100baseT_Half
|
10704 ELINK_SUPPORTED_100baseT_Full
|
10705 ELINK_SUPPORTED_1000baseT_Full
|
10706 ELINK_SUPPORTED_2500baseX_Full
|
10707 ELINK_SUPPORTED_TP
|
10708 ELINK_SUPPORTED_Autoneg
|
10709 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10710 .media_type
= ELINK_ETH_PHY_BASE_T
,
10712 .req_flow_ctrl
= 0,
10713 .req_line_speed
= 0,
10714 .speed_cap_mask
= 0,
10717 .config_init
= (config_init_t
) elink_xgxs_config_init
,
10718 .read_status
= (read_status_t
) elink_link_settings_status
,
10719 .link_reset
= (link_reset_t
) elink_int_link_reset
,
10720 .config_loopback
= (config_loopback_t
) NULL
,
10721 .format_fw_ver
= (format_fw_ver_t
) NULL
,
10722 .hw_reset
= (hw_reset_t
) NULL
,
10723 .set_link_led
= (set_link_led_t
) NULL
,
10724 .phy_specific_func
= (phy_specific_func_t
) NULL
10727 static const struct elink_phy phy_xgxs
= {
10728 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
,
10732 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10733 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10735 .supported
= (ELINK_SUPPORTED_10baseT_Half
|
10736 ELINK_SUPPORTED_10baseT_Full
|
10737 ELINK_SUPPORTED_100baseT_Half
|
10738 ELINK_SUPPORTED_100baseT_Full
|
10739 ELINK_SUPPORTED_1000baseT_Full
|
10740 ELINK_SUPPORTED_2500baseX_Full
|
10741 ELINK_SUPPORTED_10000baseT_Full
|
10742 ELINK_SUPPORTED_FIBRE
|
10743 ELINK_SUPPORTED_Autoneg
|
10744 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10745 .media_type
= ELINK_ETH_PHY_CX4
,
10747 .req_flow_ctrl
= 0,
10748 .req_line_speed
= 0,
10749 .speed_cap_mask
= 0,
10752 .config_init
= (config_init_t
) elink_xgxs_config_init
,
10753 .read_status
= (read_status_t
) elink_link_settings_status
,
10754 .link_reset
= (link_reset_t
) elink_int_link_reset
,
10755 .config_loopback
= (config_loopback_t
) elink_set_xgxs_loopback
,
10756 .format_fw_ver
= (format_fw_ver_t
) NULL
,
10757 .hw_reset
= (hw_reset_t
) NULL
,
10758 .set_link_led
= (set_link_led_t
) NULL
,
10759 .phy_specific_func
= (phy_specific_func_t
) elink_xgxs_specific_func
10762 static const struct elink_phy phy_warpcore
= {
10763 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
,
10766 .flags
= ELINK_FLAGS_TX_ERROR_CHECK
,
10767 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10768 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10770 .supported
= (ELINK_SUPPORTED_10baseT_Half
|
10771 ELINK_SUPPORTED_10baseT_Full
|
10772 ELINK_SUPPORTED_100baseT_Half
|
10773 ELINK_SUPPORTED_100baseT_Full
|
10774 ELINK_SUPPORTED_1000baseT_Full
|
10775 ELINK_SUPPORTED_10000baseT_Full
|
10776 ELINK_SUPPORTED_20000baseKR2_Full
|
10777 ELINK_SUPPORTED_20000baseMLD2_Full
|
10778 ELINK_SUPPORTED_FIBRE
|
10779 ELINK_SUPPORTED_Autoneg
|
10780 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10781 .media_type
= ELINK_ETH_PHY_UNSPECIFIED
,
10783 .req_flow_ctrl
= 0,
10784 .req_line_speed
= 0,
10785 .speed_cap_mask
= 0,
10786 /* req_duplex = */ 0,
10788 .config_init
= (config_init_t
) elink_warpcore_config_init
,
10789 .read_status
= (read_status_t
) elink_warpcore_read_status
,
10790 .link_reset
= (link_reset_t
) elink_warpcore_link_reset
,
10791 .config_loopback
= (config_loopback_t
) elink_set_warpcore_loopback
,
10792 .format_fw_ver
= (format_fw_ver_t
) NULL
,
10793 .hw_reset
= (hw_reset_t
) elink_warpcore_hw_reset
,
10794 .set_link_led
= (set_link_led_t
) NULL
,
10795 .phy_specific_func
= (phy_specific_func_t
) NULL
10798 static const struct elink_phy phy_7101
= {
10799 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
,
10802 .flags
= ELINK_FLAGS_FAN_FAILURE_DET_REQ
,
10803 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10804 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10806 .supported
= (ELINK_SUPPORTED_10000baseT_Full
|
10807 ELINK_SUPPORTED_TP
|
10808 ELINK_SUPPORTED_Autoneg
|
10809 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10810 .media_type
= ELINK_ETH_PHY_BASE_T
,
10812 .req_flow_ctrl
= 0,
10813 .req_line_speed
= 0,
10814 .speed_cap_mask
= 0,
10817 .config_init
= (config_init_t
) elink_7101_config_init
,
10818 .read_status
= (read_status_t
) elink_7101_read_status
,
10819 .link_reset
= (link_reset_t
) elink_common_ext_link_reset
,
10820 .config_loopback
= (config_loopback_t
) elink_7101_config_loopback
,
10821 .format_fw_ver
= (format_fw_ver_t
) elink_7101_format_ver
,
10822 .hw_reset
= (hw_reset_t
) elink_7101_hw_reset
,
10823 .set_link_led
= (set_link_led_t
) elink_7101_set_link_led
,
10824 .phy_specific_func
= (phy_specific_func_t
) NULL
10827 static const struct elink_phy phy_8073
= {
10828 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073
,
10832 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10833 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10835 .supported
= (ELINK_SUPPORTED_10000baseT_Full
|
10836 ELINK_SUPPORTED_2500baseX_Full
|
10837 ELINK_SUPPORTED_1000baseT_Full
|
10838 ELINK_SUPPORTED_FIBRE
|
10839 ELINK_SUPPORTED_Autoneg
|
10840 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10841 .media_type
= ELINK_ETH_PHY_KR
,
10843 .req_flow_ctrl
= 0,
10844 .req_line_speed
= 0,
10845 .speed_cap_mask
= 0,
10848 .config_init
= (config_init_t
) elink_8073_config_init
,
10849 .read_status
= (read_status_t
) elink_8073_read_status
,
10850 .link_reset
= (link_reset_t
) elink_8073_link_reset
,
10851 .config_loopback
= (config_loopback_t
) NULL
,
10852 .format_fw_ver
= (format_fw_ver_t
) elink_format_ver
,
10853 .hw_reset
= (hw_reset_t
) NULL
,
10854 .set_link_led
= (set_link_led_t
) NULL
,
10855 .phy_specific_func
= (phy_specific_func_t
) elink_8073_specific_func
10858 static const struct elink_phy phy_8705
= {
10859 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705
,
10862 .flags
= ELINK_FLAGS_INIT_XGXS_FIRST
,
10863 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10864 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10866 .supported
= (ELINK_SUPPORTED_10000baseT_Full
|
10867 ELINK_SUPPORTED_FIBRE
|
10868 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10869 .media_type
= ELINK_ETH_PHY_XFP_FIBER
,
10871 .req_flow_ctrl
= 0,
10872 .req_line_speed
= 0,
10873 .speed_cap_mask
= 0,
10876 .config_init
= (config_init_t
) elink_8705_config_init
,
10877 .read_status
= (read_status_t
) elink_8705_read_status
,
10878 .link_reset
= (link_reset_t
) elink_common_ext_link_reset
,
10879 .config_loopback
= (config_loopback_t
) NULL
,
10880 .format_fw_ver
= (format_fw_ver_t
) elink_null_format_ver
,
10881 .hw_reset
= (hw_reset_t
) NULL
,
10882 .set_link_led
= (set_link_led_t
) NULL
,
10883 .phy_specific_func
= (phy_specific_func_t
) NULL
10886 static const struct elink_phy phy_8706
= {
10887 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706
,
10890 .flags
= ELINK_FLAGS_INIT_XGXS_FIRST
,
10891 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10892 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10894 .supported
= (ELINK_SUPPORTED_10000baseT_Full
|
10895 ELINK_SUPPORTED_1000baseT_Full
|
10896 ELINK_SUPPORTED_FIBRE
|
10897 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10898 .media_type
= ELINK_ETH_PHY_SFPP_10G_FIBER
,
10900 .req_flow_ctrl
= 0,
10901 .req_line_speed
= 0,
10902 .speed_cap_mask
= 0,
10905 .config_init
= (config_init_t
) elink_8706_config_init
,
10906 .read_status
= (read_status_t
) elink_8706_read_status
,
10907 .link_reset
= (link_reset_t
) elink_common_ext_link_reset
,
10908 .config_loopback
= (config_loopback_t
) NULL
,
10909 .format_fw_ver
= (format_fw_ver_t
) elink_format_ver
,
10910 .hw_reset
= (hw_reset_t
) NULL
,
10911 .set_link_led
= (set_link_led_t
) NULL
,
10912 .phy_specific_func
= (phy_specific_func_t
) NULL
10915 static const struct elink_phy phy_8726
= {
10916 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726
,
10919 .flags
= (ELINK_FLAGS_INIT_XGXS_FIRST
| ELINK_FLAGS_TX_ERROR_CHECK
),
10920 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10921 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10923 .supported
= (ELINK_SUPPORTED_10000baseT_Full
|
10924 ELINK_SUPPORTED_1000baseT_Full
|
10925 ELINK_SUPPORTED_Autoneg
|
10926 ELINK_SUPPORTED_FIBRE
|
10927 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10928 .media_type
= ELINK_ETH_PHY_NOT_PRESENT
,
10930 .req_flow_ctrl
= 0,
10931 .req_line_speed
= 0,
10932 .speed_cap_mask
= 0,
10935 .config_init
= (config_init_t
) elink_8726_config_init
,
10936 .read_status
= (read_status_t
) elink_8726_read_status
,
10937 .link_reset
= (link_reset_t
) elink_8726_link_reset
,
10938 .config_loopback
= (config_loopback_t
) elink_8726_config_loopback
,
10939 .format_fw_ver
= (format_fw_ver_t
) elink_format_ver
,
10940 .hw_reset
= (hw_reset_t
) NULL
,
10941 .set_link_led
= (set_link_led_t
) NULL
,
10942 .phy_specific_func
= (phy_specific_func_t
) NULL
10945 static const struct elink_phy phy_8727
= {
10946 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727
,
10949 .flags
= (ELINK_FLAGS_FAN_FAILURE_DET_REQ
| ELINK_FLAGS_TX_ERROR_CHECK
),
10950 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10951 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10953 .supported
= (ELINK_SUPPORTED_10000baseT_Full
|
10954 ELINK_SUPPORTED_1000baseT_Full
|
10955 ELINK_SUPPORTED_FIBRE
|
10956 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10957 .media_type
= ELINK_ETH_PHY_NOT_PRESENT
,
10959 .req_flow_ctrl
= 0,
10960 .req_line_speed
= 0,
10961 .speed_cap_mask
= 0,
10964 .config_init
= (config_init_t
) elink_8727_config_init
,
10965 .read_status
= (read_status_t
) elink_8727_read_status
,
10966 .link_reset
= (link_reset_t
) elink_8727_link_reset
,
10967 .config_loopback
= (config_loopback_t
) NULL
,
10968 .format_fw_ver
= (format_fw_ver_t
) elink_format_ver
,
10969 .hw_reset
= (hw_reset_t
) elink_8727_hw_reset
,
10970 .set_link_led
= (set_link_led_t
) elink_8727_set_link_led
,
10971 .phy_specific_func
= (phy_specific_func_t
) elink_8727_specific_func
10974 static const struct elink_phy phy_8481
= {
10975 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481
,
10978 .flags
= ELINK_FLAGS_FAN_FAILURE_DET_REQ
|
10979 ELINK_FLAGS_REARM_LATCH_SIGNAL
,
10980 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10981 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10983 .supported
= (ELINK_SUPPORTED_10baseT_Half
|
10984 ELINK_SUPPORTED_10baseT_Full
|
10985 ELINK_SUPPORTED_100baseT_Half
|
10986 ELINK_SUPPORTED_100baseT_Full
|
10987 ELINK_SUPPORTED_1000baseT_Full
|
10988 ELINK_SUPPORTED_10000baseT_Full
|
10989 ELINK_SUPPORTED_TP
|
10990 ELINK_SUPPORTED_Autoneg
|
10991 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10992 .media_type
= ELINK_ETH_PHY_BASE_T
,
10994 .req_flow_ctrl
= 0,
10995 .req_line_speed
= 0,
10996 .speed_cap_mask
= 0,
10999 .config_init
= (config_init_t
) elink_8481_config_init
,
11000 .read_status
= (read_status_t
) elink_848xx_read_status
,
11001 .link_reset
= (link_reset_t
) elink_8481_link_reset
,
11002 .config_loopback
= (config_loopback_t
) NULL
,
11003 .format_fw_ver
= (format_fw_ver_t
) elink_848xx_format_ver
,
11004 .hw_reset
= (hw_reset_t
) elink_8481_hw_reset
,
11005 .set_link_led
= (set_link_led_t
) elink_848xx_set_link_led
,
11006 .phy_specific_func
= (phy_specific_func_t
) NULL
11009 static const struct elink_phy phy_84823
= {
11010 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823
,
11013 .flags
= (ELINK_FLAGS_FAN_FAILURE_DET_REQ
|
11014 ELINK_FLAGS_REARM_LATCH_SIGNAL
| ELINK_FLAGS_TX_ERROR_CHECK
),
11015 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11016 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11018 .supported
= (ELINK_SUPPORTED_10baseT_Half
|
11019 ELINK_SUPPORTED_10baseT_Full
|
11020 ELINK_SUPPORTED_100baseT_Half
|
11021 ELINK_SUPPORTED_100baseT_Full
|
11022 ELINK_SUPPORTED_1000baseT_Full
|
11023 ELINK_SUPPORTED_10000baseT_Full
|
11024 ELINK_SUPPORTED_TP
|
11025 ELINK_SUPPORTED_Autoneg
|
11026 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
11027 .media_type
= ELINK_ETH_PHY_BASE_T
,
11029 .req_flow_ctrl
= 0,
11030 .req_line_speed
= 0,
11031 .speed_cap_mask
= 0,
11034 .config_init
= (config_init_t
) elink_848x3_config_init
,
11035 .read_status
= (read_status_t
) elink_848xx_read_status
,
11036 .link_reset
= (link_reset_t
) elink_848x3_link_reset
,
11037 .config_loopback
= (config_loopback_t
) NULL
,
11038 .format_fw_ver
= (format_fw_ver_t
) elink_848xx_format_ver
,
11039 .hw_reset
= (hw_reset_t
) NULL
,
11040 .set_link_led
= (set_link_led_t
) elink_848xx_set_link_led
,
11041 .phy_specific_func
= (phy_specific_func_t
) elink_848xx_specific_func
11044 static const struct elink_phy phy_84833
= {
11045 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
,
11048 .flags
= (ELINK_FLAGS_FAN_FAILURE_DET_REQ
|
11049 ELINK_FLAGS_REARM_LATCH_SIGNAL
|
11050 ELINK_FLAGS_TX_ERROR_CHECK
| ELINK_FLAGS_TEMPERATURE
),
11051 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11052 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11054 .supported
= (ELINK_SUPPORTED_100baseT_Half
|
11055 ELINK_SUPPORTED_100baseT_Full
|
11056 ELINK_SUPPORTED_1000baseT_Full
|
11057 ELINK_SUPPORTED_10000baseT_Full
|
11058 ELINK_SUPPORTED_TP
|
11059 ELINK_SUPPORTED_Autoneg
|
11060 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
11061 .media_type
= ELINK_ETH_PHY_BASE_T
,
11063 .req_flow_ctrl
= 0,
11064 .req_line_speed
= 0,
11065 .speed_cap_mask
= 0,
11068 .config_init
= (config_init_t
) elink_848x3_config_init
,
11069 .read_status
= (read_status_t
) elink_848xx_read_status
,
11070 .link_reset
= (link_reset_t
) elink_848x3_link_reset
,
11071 .config_loopback
= (config_loopback_t
) NULL
,
11072 .format_fw_ver
= (format_fw_ver_t
) elink_848xx_format_ver
,
11073 .hw_reset
= (hw_reset_t
) elink_84833_hw_reset_phy
,
11074 .set_link_led
= (set_link_led_t
) elink_848xx_set_link_led
,
11075 .phy_specific_func
= (phy_specific_func_t
) elink_848xx_specific_func
11078 static const struct elink_phy phy_84834
= {
11079 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
,
11082 .flags
= ELINK_FLAGS_FAN_FAILURE_DET_REQ
|
11083 ELINK_FLAGS_REARM_LATCH_SIGNAL
,
11084 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11085 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11087 .supported
= (ELINK_SUPPORTED_100baseT_Half
|
11088 ELINK_SUPPORTED_100baseT_Full
|
11089 ELINK_SUPPORTED_1000baseT_Full
|
11090 ELINK_SUPPORTED_10000baseT_Full
|
11091 ELINK_SUPPORTED_TP
|
11092 ELINK_SUPPORTED_Autoneg
|
11093 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
11094 .media_type
= ELINK_ETH_PHY_BASE_T
,
11096 .req_flow_ctrl
= 0,
11097 .req_line_speed
= 0,
11098 .speed_cap_mask
= 0,
11101 .config_init
= (config_init_t
) elink_848x3_config_init
,
11102 .read_status
= (read_status_t
) elink_848xx_read_status
,
11103 .link_reset
= (link_reset_t
) elink_848x3_link_reset
,
11104 .config_loopback
= (config_loopback_t
) NULL
,
11105 .format_fw_ver
= (format_fw_ver_t
) elink_848xx_format_ver
,
11106 .hw_reset
= (hw_reset_t
) elink_84833_hw_reset_phy
,
11107 .set_link_led
= (set_link_led_t
) elink_848xx_set_link_led
,
11108 .phy_specific_func
= (phy_specific_func_t
) elink_848xx_specific_func
11111 static const struct elink_phy phy_54618se
= {
11112 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE
,
11115 .flags
= ELINK_FLAGS_INIT_XGXS_FIRST
,
11116 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11117 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11119 .supported
= (ELINK_SUPPORTED_10baseT_Half
|
11120 ELINK_SUPPORTED_10baseT_Full
|
11121 ELINK_SUPPORTED_100baseT_Half
|
11122 ELINK_SUPPORTED_100baseT_Full
|
11123 ELINK_SUPPORTED_1000baseT_Full
|
11124 ELINK_SUPPORTED_TP
|
11125 ELINK_SUPPORTED_Autoneg
|
11126 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
11127 .media_type
= ELINK_ETH_PHY_BASE_T
,
11129 .req_flow_ctrl
= 0,
11130 .req_line_speed
= 0,
11131 .speed_cap_mask
= 0,
11132 /* req_duplex = */ 0,
11134 .config_init
= (config_init_t
) elink_54618se_config_init
,
11135 .read_status
= (read_status_t
) elink_54618se_read_status
,
11136 .link_reset
= (link_reset_t
) elink_54618se_link_reset
,
11137 .config_loopback
= (config_loopback_t
) elink_54618se_config_loopback
,
11138 .format_fw_ver
= (format_fw_ver_t
) NULL
,
11139 .hw_reset
= (hw_reset_t
) NULL
,
11140 .set_link_led
= (set_link_led_t
) elink_5461x_set_link_led
,
11141 .phy_specific_func
= (phy_specific_func_t
) elink_54618se_specific_func
11144 /*****************************************************************/
11146 /* Populate the phy according. Main function: elink_populate_phy */
11148 /*****************************************************************/
11150 static void elink_populate_preemphasis(struct bnx2x_softc
*sc
,
11151 uint32_t shmem_base
,
11152 struct elink_phy
*phy
, uint8_t port
,
11155 /* Get the 4 lanes xgxs config rx and tx */
11156 uint32_t rx
= 0, tx
= 0, i
;
11157 for (i
= 0; i
< 2; i
++) {
11158 /* INT_PHY and ELINK_EXT_PHY1 share the same value location in
11159 * the shmem. When num_phys is greater than 1, than this value
11160 * applies only to ELINK_EXT_PHY1
11162 if (phy_index
== ELINK_INT_PHY
|| phy_index
== ELINK_EXT_PHY1
) {
11163 rx
= REG_RD(sc
, shmem_base
+
11164 offsetof(struct shmem_region
,
11165 dev_info
.port_hw_config
[port
].
11166 xgxs_config_rx
[i
<< 1]));
11168 tx
= REG_RD(sc
, shmem_base
+
11169 offsetof(struct shmem_region
,
11170 dev_info
.port_hw_config
[port
].
11171 xgxs_config_tx
[i
<< 1]));
11173 rx
= REG_RD(sc
, shmem_base
+
11174 offsetof(struct shmem_region
,
11175 dev_info
.port_hw_config
[port
].
11176 xgxs_config2_rx
[i
<< 1]));
11178 tx
= REG_RD(sc
, shmem_base
+
11179 offsetof(struct shmem_region
,
11180 dev_info
.port_hw_config
[port
].
11181 xgxs_config2_rx
[i
<< 1]));
11184 phy
->rx_preemphasis
[i
<< 1] = ((rx
>> 16) & 0xffff);
11185 phy
->rx_preemphasis
[(i
<< 1) + 1] = (rx
& 0xffff);
11187 phy
->tx_preemphasis
[i
<< 1] = ((tx
>> 16) & 0xffff);
11188 phy
->tx_preemphasis
[(i
<< 1) + 1] = (tx
& 0xffff);
11192 static uint32_t elink_get_ext_phy_config(struct bnx2x_softc
*sc
,
11193 uint32_t shmem_base
, uint8_t phy_index
,
11196 uint32_t ext_phy_config
= 0;
11197 switch (phy_index
) {
11198 case ELINK_EXT_PHY1
:
11199 ext_phy_config
= REG_RD(sc
, shmem_base
+
11200 offsetof(struct shmem_region
,
11201 dev_info
.port_hw_config
[port
].
11202 external_phy_config
));
11204 case ELINK_EXT_PHY2
:
11205 ext_phy_config
= REG_RD(sc
, shmem_base
+
11206 offsetof(struct shmem_region
,
11207 dev_info
.port_hw_config
[port
].
11208 external_phy_config2
));
11211 PMD_DRV_LOG(DEBUG
, "Invalid phy_index %d", phy_index
);
11212 return ELINK_STATUS_ERROR
;
11215 return ext_phy_config
;
11218 static elink_status_t
elink_populate_int_phy(struct bnx2x_softc
*sc
,
11219 uint32_t shmem_base
, uint8_t port
,
11220 struct elink_phy
*phy
)
11223 __rte_unused
uint32_t chip_id
;
11224 uint32_t switch_cfg
= (REG_RD(sc
, shmem_base
+
11225 offsetof(struct shmem_region
,
11227 port_feature_config
[port
].
11229 PORT_FEATURE_CONNECTED_SWITCH_MASK
);
11231 (REG_RD(sc
, MISC_REG_CHIP_NUM
) << 16) |
11232 ((REG_RD(sc
, MISC_REG_CHIP_REV
) & 0xf) << 12);
11234 PMD_DRV_LOG(DEBUG
, ":chip_id = 0x%x", chip_id
);
11235 if (USES_WARPCORE(sc
)) {
11236 uint32_t serdes_net_if
;
11237 phy_addr
= REG_RD(sc
, MISC_REG_WC0_CTRL_PHY_ADDR
);
11238 *phy
= phy_warpcore
;
11239 if (REG_RD(sc
, MISC_REG_PORT4MODE_EN_OVWR
) == 0x3)
11240 phy
->flags
|= ELINK_FLAGS_4_PORT_MODE
;
11242 phy
->flags
&= ~ELINK_FLAGS_4_PORT_MODE
;
11243 /* Check Dual mode */
11244 serdes_net_if
= (REG_RD(sc
, shmem_base
+
11245 offsetof(struct shmem_region
,
11246 dev_info
.port_hw_config
[port
].
11248 PORT_HW_CFG_NET_SERDES_IF_MASK
);
11249 /* Set the appropriate supported and flags indications per
11250 * interface type of the chip
11252 switch (serdes_net_if
) {
11253 case PORT_HW_CFG_NET_SERDES_IF_SGMII
:
11254 phy
->supported
&= (ELINK_SUPPORTED_10baseT_Half
|
11255 ELINK_SUPPORTED_10baseT_Full
|
11256 ELINK_SUPPORTED_100baseT_Half
|
11257 ELINK_SUPPORTED_100baseT_Full
|
11258 ELINK_SUPPORTED_1000baseT_Full
|
11259 ELINK_SUPPORTED_FIBRE
|
11260 ELINK_SUPPORTED_Autoneg
|
11261 ELINK_SUPPORTED_Pause
|
11262 ELINK_SUPPORTED_Asym_Pause
);
11263 phy
->media_type
= ELINK_ETH_PHY_BASE_T
;
11265 case PORT_HW_CFG_NET_SERDES_IF_XFI
:
11266 phy
->supported
&= (ELINK_SUPPORTED_1000baseT_Full
|
11267 ELINK_SUPPORTED_10000baseT_Full
|
11268 ELINK_SUPPORTED_FIBRE
|
11269 ELINK_SUPPORTED_Pause
|
11270 ELINK_SUPPORTED_Asym_Pause
);
11271 phy
->media_type
= ELINK_ETH_PHY_XFP_FIBER
;
11273 case PORT_HW_CFG_NET_SERDES_IF_SFI
:
11274 phy
->supported
&= (ELINK_SUPPORTED_1000baseT_Full
|
11275 ELINK_SUPPORTED_10000baseT_Full
|
11276 ELINK_SUPPORTED_FIBRE
|
11277 ELINK_SUPPORTED_Pause
|
11278 ELINK_SUPPORTED_Asym_Pause
);
11279 phy
->media_type
= ELINK_ETH_PHY_SFPP_10G_FIBER
;
11281 case PORT_HW_CFG_NET_SERDES_IF_KR
:
11282 phy
->media_type
= ELINK_ETH_PHY_KR
;
11283 phy
->supported
&= (ELINK_SUPPORTED_1000baseT_Full
|
11284 ELINK_SUPPORTED_10000baseT_Full
|
11285 ELINK_SUPPORTED_FIBRE
|
11286 ELINK_SUPPORTED_Autoneg
|
11287 ELINK_SUPPORTED_Pause
|
11288 ELINK_SUPPORTED_Asym_Pause
);
11290 case PORT_HW_CFG_NET_SERDES_IF_DXGXS
:
11291 phy
->media_type
= ELINK_ETH_PHY_KR
;
11292 phy
->flags
|= ELINK_FLAGS_WC_DUAL_MODE
;
11293 phy
->supported
&= (ELINK_SUPPORTED_20000baseMLD2_Full
|
11294 ELINK_SUPPORTED_FIBRE
|
11295 ELINK_SUPPORTED_Pause
|
11296 ELINK_SUPPORTED_Asym_Pause
);
11298 case PORT_HW_CFG_NET_SERDES_IF_KR2
:
11299 phy
->media_type
= ELINK_ETH_PHY_KR
;
11300 phy
->flags
|= ELINK_FLAGS_WC_DUAL_MODE
;
11301 phy
->supported
&= (ELINK_SUPPORTED_20000baseKR2_Full
|
11302 ELINK_SUPPORTED_10000baseT_Full
|
11303 ELINK_SUPPORTED_1000baseT_Full
|
11304 ELINK_SUPPORTED_Autoneg
|
11305 ELINK_SUPPORTED_FIBRE
|
11306 ELINK_SUPPORTED_Pause
|
11307 ELINK_SUPPORTED_Asym_Pause
);
11308 phy
->flags
&= ~ELINK_FLAGS_TX_ERROR_CHECK
;
11311 PMD_DRV_LOG(DEBUG
, "Unknown WC interface type 0x%x",
11316 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11317 * was not set as expected. For B0, ECO will be enabled so there
11318 * won't be an issue there
11320 if (CHIP_REV(sc
) == CHIP_REV_Ax
)
11321 phy
->flags
|= ELINK_FLAGS_MDC_MDIO_WA
;
11323 phy
->flags
|= ELINK_FLAGS_MDC_MDIO_WA_B0
;
11325 switch (switch_cfg
) {
11326 case ELINK_SWITCH_CFG_1G
:
11327 phy_addr
= REG_RD(sc
,
11328 NIG_REG_SERDES0_CTRL_PHY_ADDR
+
11332 case ELINK_SWITCH_CFG_10G
:
11333 phy_addr
= REG_RD(sc
,
11334 NIG_REG_XGXS0_CTRL_PHY_ADDR
+
11339 PMD_DRV_LOG(DEBUG
, "Invalid switch_cfg");
11340 return ELINK_STATUS_ERROR
;
11343 phy
->addr
= (uint8_t) phy_addr
;
11344 phy
->mdio_ctrl
= elink_get_emac_base(sc
,
11345 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH
,
11347 if (CHIP_IS_E2(sc
))
11348 phy
->def_md_devad
= ELINK_E2_DEFAULT_PHY_DEV_ADDR
;
11350 phy
->def_md_devad
= ELINK_DEFAULT_PHY_DEV_ADDR
;
11352 PMD_DRV_LOG(DEBUG
, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x",
11353 port
, phy
->addr
, phy
->mdio_ctrl
);
11355 elink_populate_preemphasis(sc
, shmem_base
, phy
, port
, ELINK_INT_PHY
);
11356 return ELINK_STATUS_OK
;
11359 static elink_status_t
elink_populate_ext_phy(struct bnx2x_softc
*sc
,
11361 uint32_t shmem_base
,
11362 uint32_t shmem2_base
,
11364 struct elink_phy
*phy
)
11366 uint32_t ext_phy_config
, phy_type
, config2
;
11367 uint32_t mdc_mdio_access
= SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH
;
11368 ext_phy_config
= elink_get_ext_phy_config(sc
, shmem_base
,
11370 phy_type
= ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config
);
11371 /* Select the phy type */
11372 switch (phy_type
) {
11373 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073
:
11374 mdc_mdio_access
= SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED
;
11377 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705
:
11380 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706
:
11383 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726
:
11384 mdc_mdio_access
= SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1
;
11387 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC
:
11388 /* BNX2X8727_NOC => BNX2X8727 no over current */
11389 mdc_mdio_access
= SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1
;
11391 phy
->flags
|= ELINK_FLAGS_NOC
;
11393 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722
:
11394 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727
:
11395 mdc_mdio_access
= SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1
;
11398 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481
:
11401 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823
:
11404 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
:
11407 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
:
11410 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616
:
11411 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE
:
11412 *phy
= phy_54618se
;
11413 if (phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE
)
11414 phy
->flags
|= ELINK_FLAGS_EEE
;
11416 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
:
11419 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
:
11421 return ELINK_STATUS_ERROR
;
11424 /* In case external PHY wasn't found */
11425 if ((phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) &&
11426 (phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
))
11427 return ELINK_STATUS_ERROR
;
11428 return ELINK_STATUS_OK
;
11431 phy
->addr
= ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config
);
11432 elink_populate_preemphasis(sc
, shmem_base
, phy
, port
, phy_index
);
11434 /* The shmem address of the phy version is located on different
11435 * structures. In case this structure is too old, do not set
11438 config2
= REG_RD(sc
, shmem_base
+ offsetof(struct shmem_region
,
11439 dev_info
.shared_hw_config
.
11441 if (phy_index
== ELINK_EXT_PHY1
) {
11442 phy
->ver_addr
= shmem_base
+ offsetof(struct shmem_region
,
11444 ext_phy_fw_version
);
11446 /* Check specific mdc mdio settings */
11447 if (config2
& SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK
)
11448 mdc_mdio_access
= config2
&
11449 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK
;
11451 uint32_t size
= REG_RD(sc
, shmem2_base
);
11453 if (size
> offsetof(struct shmem2_region
, ext_phy_fw_version2
)) {
11454 phy
->ver_addr
= shmem2_base
+
11455 offsetof(struct shmem2_region
,
11456 ext_phy_fw_version2
[port
]);
11458 /* Check specific mdc mdio settings */
11459 if (config2
& SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK
)
11460 mdc_mdio_access
= (config2
&
11461 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK
)
11462 >> (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT
-
11463 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT
);
11465 phy
->mdio_ctrl
= elink_get_emac_base(sc
, mdc_mdio_access
, port
);
11467 if (((phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) ||
11468 (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
)) &&
11470 /* Remove 100Mb link supported for BNX2X84833/4 when phy fw
11471 * version lower than or equal to 1.39
11473 uint32_t raw_ver
= REG_RD(sc
, phy
->ver_addr
);
11474 if (((raw_ver
& 0x7F) <= 39) && (((raw_ver
& 0xF80) >> 7) <= 1))
11475 phy
->supported
&= ~(ELINK_SUPPORTED_100baseT_Half
|
11476 ELINK_SUPPORTED_100baseT_Full
);
11479 PMD_DRV_LOG(DEBUG
, "phy_type 0x%x port %d found in index %d",
11480 phy_type
, port
, phy_index
);
11481 PMD_DRV_LOG(DEBUG
, " addr=0x%x, mdio_ctl=0x%x",
11482 phy
->addr
, phy
->mdio_ctrl
);
11483 return ELINK_STATUS_OK
;
11486 static elink_status_t
elink_populate_phy(struct bnx2x_softc
*sc
,
11487 uint8_t phy_index
, uint32_t shmem_base
,
11488 uint32_t shmem2_base
, uint8_t port
,
11489 struct elink_phy
*phy
)
11491 elink_status_t status
= ELINK_STATUS_OK
;
11492 phy
->type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
;
11493 if (phy_index
== ELINK_INT_PHY
)
11494 return elink_populate_int_phy(sc
, shmem_base
, port
, phy
);
11495 status
= elink_populate_ext_phy(sc
, phy_index
, shmem_base
, shmem2_base
,
11500 static void elink_phy_def_cfg(struct elink_params
*params
,
11501 struct elink_phy
*phy
, uint8_t phy_index
)
11503 struct bnx2x_softc
*sc
= params
->sc
;
11504 uint32_t link_config
;
11505 /* Populate the default phy configuration for MF mode */
11506 if (phy_index
== ELINK_EXT_PHY2
) {
11507 link_config
= REG_RD(sc
, params
->shmem_base
+
11508 offsetof(struct shmem_region
,
11509 dev_info
.port_feature_config
11510 [params
->port
].link_config2
));
11511 phy
->speed_cap_mask
=
11513 params
->shmem_base
+ offsetof(struct shmem_region
,
11514 dev_info
.port_hw_config
11516 speed_capability_mask2
));
11518 link_config
= REG_RD(sc
, params
->shmem_base
+
11519 offsetof(struct shmem_region
,
11520 dev_info
.port_feature_config
11521 [params
->port
].link_config
));
11522 phy
->speed_cap_mask
=
11524 params
->shmem_base
+ offsetof(struct shmem_region
,
11525 dev_info
.port_hw_config
11527 speed_capability_mask
));
11531 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x",
11532 phy_index
, link_config
, phy
->speed_cap_mask
);
11534 phy
->req_duplex
= DUPLEX_FULL
;
11535 switch (link_config
& PORT_FEATURE_LINK_SPEED_MASK
) {
11536 case PORT_FEATURE_LINK_SPEED_10M_HALF
:
11537 phy
->req_duplex
= DUPLEX_HALF
;
11539 case PORT_FEATURE_LINK_SPEED_10M_FULL
:
11540 phy
->req_line_speed
= ELINK_SPEED_10
;
11542 case PORT_FEATURE_LINK_SPEED_100M_HALF
:
11543 phy
->req_duplex
= DUPLEX_HALF
;
11545 case PORT_FEATURE_LINK_SPEED_100M_FULL
:
11546 phy
->req_line_speed
= ELINK_SPEED_100
;
11548 case PORT_FEATURE_LINK_SPEED_1G
:
11549 phy
->req_line_speed
= ELINK_SPEED_1000
;
11551 case PORT_FEATURE_LINK_SPEED_2_5G
:
11552 phy
->req_line_speed
= ELINK_SPEED_2500
;
11554 case PORT_FEATURE_LINK_SPEED_10G_CX4
:
11555 phy
->req_line_speed
= ELINK_SPEED_10000
;
11558 phy
->req_line_speed
= ELINK_SPEED_AUTO_NEG
;
11562 switch (link_config
& PORT_FEATURE_FLOW_CONTROL_MASK
) {
11563 case PORT_FEATURE_FLOW_CONTROL_AUTO
:
11564 phy
->req_flow_ctrl
= ELINK_FLOW_CTRL_AUTO
;
11566 case PORT_FEATURE_FLOW_CONTROL_TX
:
11567 phy
->req_flow_ctrl
= ELINK_FLOW_CTRL_TX
;
11569 case PORT_FEATURE_FLOW_CONTROL_RX
:
11570 phy
->req_flow_ctrl
= ELINK_FLOW_CTRL_RX
;
11572 case PORT_FEATURE_FLOW_CONTROL_BOTH
:
11573 phy
->req_flow_ctrl
= ELINK_FLOW_CTRL_BOTH
;
11576 phy
->req_flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
11581 uint32_t elink_phy_selection(struct elink_params
*params
)
11583 uint32_t phy_config_swapped
, prio_cfg
;
11584 uint32_t return_cfg
= PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT
;
11586 phy_config_swapped
= params
->multi_phy_config
&
11587 PORT_HW_CFG_PHY_SWAPPED_ENABLED
;
11589 prio_cfg
= params
->multi_phy_config
& PORT_HW_CFG_PHY_SELECTION_MASK
;
11591 if (phy_config_swapped
) {
11592 switch (prio_cfg
) {
11593 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY
:
11595 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY
;
11597 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY
:
11599 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY
;
11601 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY
:
11602 return_cfg
= PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
;
11604 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
:
11605 return_cfg
= PORT_HW_CFG_PHY_SELECTION_SECOND_PHY
;
11609 return_cfg
= prio_cfg
;
11614 elink_status_t
elink_phy_probe(struct elink_params
* params
)
11616 uint8_t phy_index
, actual_phy_idx
;
11617 uint32_t phy_config_swapped
, sync_offset
, media_types
;
11618 struct bnx2x_softc
*sc
= params
->sc
;
11619 struct elink_phy
*phy
;
11620 params
->num_phys
= 0;
11621 PMD_DRV_LOG(DEBUG
, "Begin phy probe");
11623 phy_config_swapped
= params
->multi_phy_config
&
11624 PORT_HW_CFG_PHY_SWAPPED_ENABLED
;
11626 for (phy_index
= ELINK_INT_PHY
; phy_index
< ELINK_MAX_PHYS
; phy_index
++) {
11627 actual_phy_idx
= phy_index
;
11628 if (phy_config_swapped
) {
11629 if (phy_index
== ELINK_EXT_PHY1
)
11630 actual_phy_idx
= ELINK_EXT_PHY2
;
11631 else if (phy_index
== ELINK_EXT_PHY2
)
11632 actual_phy_idx
= ELINK_EXT_PHY1
;
11634 PMD_DRV_LOG(DEBUG
, "phy_config_swapped %x, phy_index %x,"
11635 " actual_phy_idx %x", phy_config_swapped
,
11636 phy_index
, actual_phy_idx
);
11637 phy
= ¶ms
->phy
[actual_phy_idx
];
11638 if (elink_populate_phy(sc
, phy_index
, params
->shmem_base
,
11639 params
->shmem2_base
, params
->port
,
11640 phy
) != ELINK_STATUS_OK
) {
11641 params
->num_phys
= 0;
11642 PMD_DRV_LOG(DEBUG
, "phy probe failed in phy index %d",
11644 for (phy_index
= ELINK_INT_PHY
;
11645 phy_index
< ELINK_MAX_PHYS
; phy_index
++)
11647 return ELINK_STATUS_ERROR
;
11649 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
)
11652 if (params
->feature_config_flags
&
11653 ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET
)
11654 phy
->flags
&= ~ELINK_FLAGS_TX_ERROR_CHECK
;
11656 if (!(params
->feature_config_flags
&
11657 ELINK_FEATURE_CONFIG_MT_SUPPORT
))
11658 phy
->flags
|= ELINK_FLAGS_MDC_MDIO_WA_G
;
11660 sync_offset
= params
->shmem_base
+
11661 offsetof(struct shmem_region
,
11662 dev_info
.port_hw_config
[params
->port
].media_type
);
11663 media_types
= REG_RD(sc
, sync_offset
);
11665 /* Update media type for non-PMF sync only for the first time
11666 * In case the media type changes afterwards, it will be updated
11667 * using the update_status function
11669 if ((media_types
& (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK
<<
11670 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT
*
11671 actual_phy_idx
))) == 0) {
11672 media_types
|= ((phy
->media_type
&
11673 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK
) <<
11674 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT
*
11677 REG_WR(sc
, sync_offset
, media_types
);
11679 elink_phy_def_cfg(params
, phy
, phy_index
);
11680 params
->num_phys
++;
11683 PMD_DRV_LOG(DEBUG
, "End phy probe. #phys found %x", params
->num_phys
);
11684 return ELINK_STATUS_OK
;
11687 static void elink_init_bmac_loopback(struct elink_params
*params
,
11688 struct elink_vars
*vars
)
11690 struct bnx2x_softc
*sc
= params
->sc
;
11692 vars
->line_speed
= ELINK_SPEED_10000
;
11693 vars
->duplex
= DUPLEX_FULL
;
11694 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
11695 vars
->mac_type
= ELINK_MAC_TYPE_BMAC
;
11697 vars
->phy_flags
= PHY_XGXS_FLAG
;
11699 elink_xgxs_deassert(params
);
11701 /* Set bmac loopback */
11702 elink_bmac_enable(params
, vars
, 1, 1);
11704 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 0);
11707 static void elink_init_emac_loopback(struct elink_params
*params
,
11708 struct elink_vars
*vars
)
11710 struct bnx2x_softc
*sc
= params
->sc
;
11712 vars
->line_speed
= ELINK_SPEED_1000
;
11713 vars
->duplex
= DUPLEX_FULL
;
11714 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
11715 vars
->mac_type
= ELINK_MAC_TYPE_EMAC
;
11717 vars
->phy_flags
= PHY_XGXS_FLAG
;
11719 elink_xgxs_deassert(params
);
11720 /* Set bmac loopback */
11721 elink_emac_enable(params
, vars
, 1);
11722 elink_emac_program(params
, vars
);
11723 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 0);
11726 static void elink_init_xmac_loopback(struct elink_params
*params
,
11727 struct elink_vars
*vars
)
11729 struct bnx2x_softc
*sc
= params
->sc
;
11731 if (!params
->req_line_speed
[0])
11732 vars
->line_speed
= ELINK_SPEED_10000
;
11734 vars
->line_speed
= params
->req_line_speed
[0];
11735 vars
->duplex
= DUPLEX_FULL
;
11736 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
11737 vars
->mac_type
= ELINK_MAC_TYPE_XMAC
;
11738 vars
->phy_flags
= PHY_XGXS_FLAG
;
11739 /* Set WC to loopback mode since link is required to provide clock
11740 * to the XMAC in 20G mode
11742 elink_set_aer_mmd(params
, ¶ms
->phy
[0]);
11743 elink_warpcore_reset_lane(sc
, ¶ms
->phy
[0], 0);
11744 params
->phy
[ELINK_INT_PHY
].config_loopback(¶ms
->phy
[ELINK_INT_PHY
],
11747 elink_xmac_enable(params
, vars
, 1);
11748 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 0);
11751 static void elink_init_umac_loopback(struct elink_params
*params
,
11752 struct elink_vars
*vars
)
11754 struct bnx2x_softc
*sc
= params
->sc
;
11756 vars
->line_speed
= ELINK_SPEED_1000
;
11757 vars
->duplex
= DUPLEX_FULL
;
11758 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
11759 vars
->mac_type
= ELINK_MAC_TYPE_UMAC
;
11760 vars
->phy_flags
= PHY_XGXS_FLAG
;
11761 elink_umac_enable(params
, vars
, 1);
11763 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 0);
11766 static void elink_init_xgxs_loopback(struct elink_params
*params
,
11767 struct elink_vars
*vars
)
11769 struct bnx2x_softc
*sc
= params
->sc
;
11770 struct elink_phy
*int_phy
= ¶ms
->phy
[ELINK_INT_PHY
];
11772 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
11773 vars
->duplex
= DUPLEX_FULL
;
11774 if (params
->req_line_speed
[0] == ELINK_SPEED_1000
)
11775 vars
->line_speed
= ELINK_SPEED_1000
;
11776 else if ((params
->req_line_speed
[0] == ELINK_SPEED_20000
) ||
11777 (int_phy
->flags
& ELINK_FLAGS_WC_DUAL_MODE
))
11778 vars
->line_speed
= ELINK_SPEED_20000
;
11780 vars
->line_speed
= ELINK_SPEED_10000
;
11782 if (!USES_WARPCORE(sc
))
11783 elink_xgxs_deassert(params
);
11784 elink_link_initialize(params
, vars
);
11786 if (params
->req_line_speed
[0] == ELINK_SPEED_1000
) {
11787 if (USES_WARPCORE(sc
))
11788 elink_umac_enable(params
, vars
, 0);
11790 elink_emac_program(params
, vars
);
11791 elink_emac_enable(params
, vars
, 0);
11794 if (USES_WARPCORE(sc
))
11795 elink_xmac_enable(params
, vars
, 0);
11797 elink_bmac_enable(params
, vars
, 0, 1);
11800 if (params
->loopback_mode
== ELINK_LOOPBACK_XGXS
) {
11801 /* Set 10G XGXS loopback */
11802 int_phy
->config_loopback(int_phy
, params
);
11804 /* Set external phy loopback */
11806 for (phy_index
= ELINK_EXT_PHY1
;
11807 phy_index
< params
->num_phys
; phy_index
++)
11808 if (params
->phy
[phy_index
].config_loopback
)
11809 params
->phy
[phy_index
].config_loopback(¶ms
->
11814 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 0);
11816 elink_set_led(params
, vars
, ELINK_LED_MODE_OPER
, vars
->line_speed
);
11819 void elink_set_rx_filter(struct elink_params
*params
, uint8_t en
)
11821 struct bnx2x_softc
*sc
= params
->sc
;
11822 uint8_t val
= en
* 0x1F;
11824 /* Open / close the gate between the NIG and the BRB */
11825 if (!CHIP_IS_E1x(sc
))
11827 REG_WR(sc
, NIG_REG_LLH0_BRB1_DRV_MASK
+ params
->port
* 4, val
);
11829 REG_WR(sc
, NIG_REG_LLH0_BRB1_DRV_MASK_MF
+ params
->port
* 4, en
* 0x3);
11831 REG_WR(sc
, (params
->port
? NIG_REG_LLH1_BRB1_NOT_MCP
:
11832 NIG_REG_LLH0_BRB1_NOT_MCP
), en
);
11835 static elink_status_t
elink_avoid_link_flap(struct elink_params
*params
,
11836 struct elink_vars
*vars
)
11839 uint32_t dont_clear_stat
, lfa_sts
;
11840 struct bnx2x_softc
*sc
= params
->sc
;
11842 /* Sync the link parameters */
11843 elink_link_status_update(params
, vars
);
11846 * The module verification was already done by previous link owner,
11847 * so this call is meant only to get warning message
11850 for (phy_idx
= ELINK_INT_PHY
; phy_idx
< params
->num_phys
; phy_idx
++) {
11851 struct elink_phy
*phy
= ¶ms
->phy
[phy_idx
];
11852 if (phy
->phy_specific_func
) {
11853 PMD_DRV_LOG(DEBUG
, "Calling PHY specific func");
11854 phy
->phy_specific_func(phy
, params
, ELINK_PHY_INIT
);
11856 if ((phy
->media_type
== ELINK_ETH_PHY_SFPP_10G_FIBER
) ||
11857 (phy
->media_type
== ELINK_ETH_PHY_SFP_1G_FIBER
) ||
11858 (phy
->media_type
== ELINK_ETH_PHY_DA_TWINAX
))
11859 elink_verify_sfp_module(phy
, params
);
11861 lfa_sts
= REG_RD(sc
, params
->lfa_base
+
11862 offsetof(struct shmem_lfa
, lfa_sts
));
11864 dont_clear_stat
= lfa_sts
& SHMEM_LFA_DONT_CLEAR_STAT
;
11866 /* Re-enable the NIG/MAC */
11867 if (CHIP_IS_E3(sc
)) {
11868 if (!dont_clear_stat
) {
11869 REG_WR(sc
, GRCBASE_MISC
+
11870 MISC_REGISTERS_RESET_REG_2_CLEAR
,
11871 (MISC_REGISTERS_RESET_REG_2_MSTAT0
<<
11873 REG_WR(sc
, GRCBASE_MISC
+
11874 MISC_REGISTERS_RESET_REG_2_SET
,
11875 (MISC_REGISTERS_RESET_REG_2_MSTAT0
<<
11878 if (vars
->line_speed
< ELINK_SPEED_10000
)
11879 elink_umac_enable(params
, vars
, 0);
11881 elink_xmac_enable(params
, vars
, 0);
11883 if (vars
->line_speed
< ELINK_SPEED_10000
)
11884 elink_emac_enable(params
, vars
, 0);
11886 elink_bmac_enable(params
, vars
, 0, !dont_clear_stat
);
11889 /* Increment LFA count */
11890 lfa_sts
= ((lfa_sts
& ~LINK_FLAP_AVOIDANCE_COUNT_MASK
) |
11891 (((((lfa_sts
& LINK_FLAP_AVOIDANCE_COUNT_MASK
) >>
11892 LINK_FLAP_AVOIDANCE_COUNT_OFFSET
) + 1) & 0xff)
11893 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET
));
11894 /* Clear link flap reason */
11895 lfa_sts
&= ~LFA_LINK_FLAP_REASON_MASK
;
11897 REG_WR(sc
, params
->lfa_base
+
11898 offsetof(struct shmem_lfa
, lfa_sts
), lfa_sts
);
11900 /* Disable NIG DRAIN */
11901 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 0);
11903 /* Enable interrupts */
11904 elink_link_int_enable(params
);
11905 return ELINK_STATUS_OK
;
11908 static void elink_cannot_avoid_link_flap(struct elink_params
*params
,
11909 struct elink_vars
*vars
,
11912 uint32_t lfa_sts
, cfg_idx
, tmp_val
;
11913 struct bnx2x_softc
*sc
= params
->sc
;
11915 elink_link_reset(params
, vars
, 1);
11917 if (!params
->lfa_base
)
11919 /* Store the new link parameters */
11920 REG_WR(sc
, params
->lfa_base
+
11921 offsetof(struct shmem_lfa
, req_duplex
),
11922 params
->req_duplex
[0] | (params
->req_duplex
[1] << 16));
11924 REG_WR(sc
, params
->lfa_base
+
11925 offsetof(struct shmem_lfa
, req_flow_ctrl
),
11926 params
->req_flow_ctrl
[0] | (params
->req_flow_ctrl
[1] << 16));
11928 REG_WR(sc
, params
->lfa_base
+
11929 offsetof(struct shmem_lfa
, req_line_speed
),
11930 params
->req_line_speed
[0] | (params
->req_line_speed
[1] << 16));
11932 for (cfg_idx
= 0; cfg_idx
< SHMEM_LINK_CONFIG_SIZE
; cfg_idx
++) {
11933 REG_WR(sc
, params
->lfa_base
+
11934 offsetof(struct shmem_lfa
,
11935 speed_cap_mask
[cfg_idx
]),
11936 params
->speed_cap_mask
[cfg_idx
]);
11939 tmp_val
= REG_RD(sc
, params
->lfa_base
+
11940 offsetof(struct shmem_lfa
, additional_config
));
11941 tmp_val
&= ~REQ_FC_AUTO_ADV_MASK
;
11942 tmp_val
|= params
->req_fc_auto_adv
;
11944 REG_WR(sc
, params
->lfa_base
+
11945 offsetof(struct shmem_lfa
, additional_config
), tmp_val
);
11947 lfa_sts
= REG_RD(sc
, params
->lfa_base
+
11948 offsetof(struct shmem_lfa
, lfa_sts
));
11950 /* Clear the "Don't Clear Statistics" bit, and set reason */
11951 lfa_sts
&= ~SHMEM_LFA_DONT_CLEAR_STAT
;
11953 /* Set link flap reason */
11954 lfa_sts
&= ~LFA_LINK_FLAP_REASON_MASK
;
11955 lfa_sts
|= ((lfa_status
& LFA_LINK_FLAP_REASON_MASK
) <<
11956 LFA_LINK_FLAP_REASON_OFFSET
);
11958 /* Increment link flap counter */
11959 lfa_sts
= ((lfa_sts
& ~LINK_FLAP_COUNT_MASK
) |
11960 (((((lfa_sts
& LINK_FLAP_COUNT_MASK
) >>
11961 LINK_FLAP_COUNT_OFFSET
) + 1) & 0xff)
11962 << LINK_FLAP_COUNT_OFFSET
));
11963 REG_WR(sc
, params
->lfa_base
+
11964 offsetof(struct shmem_lfa
, lfa_sts
), lfa_sts
);
11965 /* Proceed with regular link initialization */
11968 elink_status_t
elink_phy_init(struct elink_params
*params
,
11969 struct elink_vars
*vars
)
11972 struct bnx2x_softc
*sc
= params
->sc
;
11973 PMD_DRV_LOG(DEBUG
, "Phy Initialization started");
11974 PMD_DRV_LOG(DEBUG
, "(1) req_speed %d, req_flowctrl %d",
11975 params
->req_line_speed
[0], params
->req_flow_ctrl
[0]);
11976 PMD_DRV_LOG(DEBUG
, "(2) req_speed %d, req_flowctrl %d",
11977 params
->req_line_speed
[1], params
->req_flow_ctrl
[1]);
11978 PMD_DRV_LOG(DEBUG
, "req_adv_flow_ctrl 0x%x", params
->req_fc_auto_adv
);
11979 vars
->link_status
= 0;
11980 vars
->phy_link_up
= 0;
11982 vars
->line_speed
= 0;
11983 vars
->duplex
= DUPLEX_FULL
;
11984 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
11985 vars
->mac_type
= ELINK_MAC_TYPE_NONE
;
11986 vars
->phy_flags
= 0;
11987 vars
->check_kr2_recovery_cnt
= 0;
11988 params
->link_flags
= ELINK_PHY_INITIALIZED
;
11989 /* Driver opens NIG-BRB filters */
11990 elink_set_rx_filter(params
, 1);
11991 /* Check if link flap can be avoided */
11992 lfa_status
= elink_check_lfa(params
);
11994 if (lfa_status
== 0) {
11995 PMD_DRV_LOG(DEBUG
, "Link Flap Avoidance in progress");
11996 return elink_avoid_link_flap(params
, vars
);
11999 PMD_DRV_LOG(DEBUG
, "Cannot avoid link flap lfa_sta=0x%x", lfa_status
);
12000 elink_cannot_avoid_link_flap(params
, vars
, lfa_status
);
12002 /* Disable attentions */
12003 elink_bits_dis(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+ params
->port
* 4,
12004 (ELINK_NIG_MASK_XGXS0_LINK_STATUS
|
12005 ELINK_NIG_MASK_XGXS0_LINK10G
|
12006 ELINK_NIG_MASK_SERDES0_LINK_STATUS
|
12007 ELINK_NIG_MASK_MI_INT
));
12009 elink_emac_init(params
);
12011 if (params
->feature_config_flags
& ELINK_FEATURE_CONFIG_PFC_ENABLED
)
12012 vars
->link_status
|= LINK_STATUS_PFC_ENABLED
;
12014 if ((params
->num_phys
== 0) && !CHIP_REV_IS_SLOW(sc
)) {
12015 PMD_DRV_LOG(DEBUG
, "No phy found for initialization !!");
12016 return ELINK_STATUS_ERROR
;
12018 set_phy_vars(params
, vars
);
12020 PMD_DRV_LOG(DEBUG
, "Num of phys on board: %d", params
->num_phys
);
12022 switch (params
->loopback_mode
) {
12023 case ELINK_LOOPBACK_BMAC
:
12024 elink_init_bmac_loopback(params
, vars
);
12026 case ELINK_LOOPBACK_EMAC
:
12027 elink_init_emac_loopback(params
, vars
);
12029 case ELINK_LOOPBACK_XMAC
:
12030 elink_init_xmac_loopback(params
, vars
);
12032 case ELINK_LOOPBACK_UMAC
:
12033 elink_init_umac_loopback(params
, vars
);
12035 case ELINK_LOOPBACK_XGXS
:
12036 case ELINK_LOOPBACK_EXT_PHY
:
12037 elink_init_xgxs_loopback(params
, vars
);
12040 if (!CHIP_IS_E3(sc
)) {
12041 if (params
->switch_cfg
== ELINK_SWITCH_CFG_10G
)
12042 elink_xgxs_deassert(params
);
12044 elink_serdes_deassert(sc
, params
->port
);
12046 elink_link_initialize(params
, vars
);
12048 elink_link_int_enable(params
);
12051 elink_update_mng(params
, vars
->link_status
);
12053 elink_update_mng_eee(params
, vars
->eee_status
);
12054 return ELINK_STATUS_OK
;
12057 static elink_status_t
elink_link_reset(struct elink_params
*params
,
12058 struct elink_vars
*vars
,
12059 uint8_t reset_ext_phy
)
12061 struct bnx2x_softc
*sc
= params
->sc
;
12062 uint8_t phy_index
, port
= params
->port
, clear_latch_ind
= 0;
12063 PMD_DRV_LOG(DEBUG
, "Resetting the link of port %d", port
);
12064 /* Disable attentions */
12065 vars
->link_status
= 0;
12066 elink_update_mng(params
, vars
->link_status
);
12067 vars
->eee_status
&= ~(SHMEM_EEE_LP_ADV_STATUS_MASK
|
12068 SHMEM_EEE_ACTIVE_BIT
);
12069 elink_update_mng_eee(params
, vars
->eee_status
);
12070 elink_bits_dis(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
* 4,
12071 (ELINK_NIG_MASK_XGXS0_LINK_STATUS
|
12072 ELINK_NIG_MASK_XGXS0_LINK10G
|
12073 ELINK_NIG_MASK_SERDES0_LINK_STATUS
|
12074 ELINK_NIG_MASK_MI_INT
));
12076 /* Activate nig drain */
12077 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ port
* 4, 1);
12079 /* Disable nig egress interface */
12080 if (!CHIP_IS_E3(sc
)) {
12081 REG_WR(sc
, NIG_REG_BMAC0_OUT_EN
+ port
* 4, 0);
12082 REG_WR(sc
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
* 4, 0);
12084 if (!CHIP_IS_E3(sc
))
12085 elink_set_bmac_rx(sc
, port
, 0);
12086 if (CHIP_IS_E3(sc
) && !CHIP_REV_IS_FPGA(sc
)) {
12087 elink_set_xmac_rxtx(params
, 0);
12088 elink_set_umac_rxtx(params
, 0);
12091 if (!CHIP_IS_E3(sc
))
12092 REG_WR(sc
, NIG_REG_NIG_EMAC0_EN
+ port
* 4, 0);
12095 /* The PHY reset is controlled by GPIO 1
12096 * Hold it as vars low
12098 /* Clear link led */
12099 elink_set_mdio_emac_per_phy(sc
, params
);
12100 elink_set_led(params
, vars
, ELINK_LED_MODE_OFF
, 0);
12102 if (reset_ext_phy
&& (!CHIP_REV_IS_SLOW(sc
))) {
12103 for (phy_index
= ELINK_EXT_PHY1
; phy_index
< params
->num_phys
;
12105 if (params
->phy
[phy_index
].link_reset
) {
12106 elink_set_aer_mmd(params
,
12107 ¶ms
->phy
[phy_index
]);
12108 params
->phy
[phy_index
].link_reset(¶ms
->
12113 if (params
->phy
[phy_index
].flags
&
12114 ELINK_FLAGS_REARM_LATCH_SIGNAL
)
12115 clear_latch_ind
= 1;
12119 if (clear_latch_ind
) {
12120 /* Clear latching indication */
12121 elink_rearm_latch_signal(sc
, port
, 0);
12122 elink_bits_dis(sc
, NIG_REG_LATCH_BC_0
+ port
* 4,
12123 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT
);
12125 if (params
->phy
[ELINK_INT_PHY
].link_reset
)
12126 params
->phy
[ELINK_INT_PHY
].link_reset(¶ms
->
12131 /* Disable nig ingress interface */
12132 if (!CHIP_IS_E3(sc
)) {
12134 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
12135 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
12136 REG_WR(sc
, NIG_REG_BMAC0_IN_EN
+ port
* 4, 0);
12137 REG_WR(sc
, NIG_REG_EMAC0_IN_EN
+ port
* 4, 0);
12139 uint32_t xmac_base
=
12140 (params
->port
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
12141 elink_set_xumac_nig(params
, 0, 0);
12142 if (REG_RD(sc
, MISC_REG_RESET_REG_2
) &
12143 MISC_REGISTERS_RESET_REG_2_XMAC
)
12144 REG_WR(sc
, xmac_base
+ XMAC_REG_CTRL
,
12145 XMAC_CTRL_REG_SOFT_RESET
);
12148 vars
->phy_flags
= 0;
12149 return ELINK_STATUS_OK
;
12152 elink_status_t
elink_lfa_reset(struct elink_params
* params
,
12153 struct elink_vars
* vars
)
12155 struct bnx2x_softc
*sc
= params
->sc
;
12157 vars
->phy_flags
= 0;
12158 params
->link_flags
&= ~ELINK_PHY_INITIALIZED
;
12159 if (!params
->lfa_base
)
12160 return elink_link_reset(params
, vars
, 1);
12162 * Activate NIG drain so that during this time the device won't send
12163 * anything while it is unable to response.
12165 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 1);
12168 * Close gracefully the gate from BMAC to NIG such that no half packets
12171 if (!CHIP_IS_E3(sc
))
12172 elink_set_bmac_rx(sc
, params
->port
, 0);
12174 if (CHIP_IS_E3(sc
)) {
12175 elink_set_xmac_rxtx(params
, 0);
12176 elink_set_umac_rxtx(params
, 0);
12178 /* Wait 10ms for the pipe to clean up */
12181 /* Clean the NIG-BRB using the network filters in a way that will
12182 * not cut a packet in the middle.
12184 elink_set_rx_filter(params
, 0);
12187 * Re-open the gate between the BMAC and the NIG, after verifying the
12188 * gate to the BRB is closed, otherwise packets may arrive to the
12189 * firmware before driver had initialized it. The target is to achieve
12190 * minimum management protocol down time.
12192 if (!CHIP_IS_E3(sc
))
12193 elink_set_bmac_rx(sc
, params
->port
, 1);
12195 if (CHIP_IS_E3(sc
)) {
12196 elink_set_xmac_rxtx(params
, 1);
12197 elink_set_umac_rxtx(params
, 1);
12199 /* Disable NIG drain */
12200 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 0);
12201 return ELINK_STATUS_OK
;
12204 /****************************************************************************/
12205 /* Common function */
12206 /****************************************************************************/
12207 static elink_status_t
elink_8073_common_init_phy(struct bnx2x_softc
*sc
,
12208 uint32_t shmem_base_path
[],
12209 uint32_t shmem2_base_path
[],
12211 __rte_unused
uint32_t chip_id
)
12213 struct elink_phy phy
[PORT_MAX
];
12214 struct elink_phy
*phy_blk
[PORT_MAX
];
12217 int8_t port_of_path
= 0;
12218 uint32_t swap_val
, swap_override
;
12219 swap_val
= REG_RD(sc
, NIG_REG_PORT_SWAP
);
12220 swap_override
= REG_RD(sc
, NIG_REG_STRAP_OVERRIDE
);
12221 port
^= (swap_val
&& swap_override
);
12222 elink_ext_phy_hw_reset(sc
, port
);
12223 /* PART1 - Reset both phys */
12224 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
12225 uint32_t shmem_base
, shmem2_base
;
12226 /* In E2, same phy is using for port0 of the two paths */
12227 if (CHIP_IS_E1x(sc
)) {
12228 shmem_base
= shmem_base_path
[0];
12229 shmem2_base
= shmem2_base_path
[0];
12230 port_of_path
= port
;
12232 shmem_base
= shmem_base_path
[port
];
12233 shmem2_base
= shmem2_base_path
[port
];
12237 /* Extract the ext phy address for the port */
12238 if (elink_populate_phy(sc
, phy_index
, shmem_base
, shmem2_base
,
12239 port_of_path
, &phy
[port
]) !=
12241 PMD_DRV_LOG(DEBUG
, "populate_phy failed");
12242 return ELINK_STATUS_ERROR
;
12244 /* Disable attentions */
12245 elink_bits_dis(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+
12247 (ELINK_NIG_MASK_XGXS0_LINK_STATUS
|
12248 ELINK_NIG_MASK_XGXS0_LINK10G
|
12249 ELINK_NIG_MASK_SERDES0_LINK_STATUS
|
12250 ELINK_NIG_MASK_MI_INT
));
12252 /* Need to take the phy out of low power mode in order
12253 * to write to access its registers
12255 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
12256 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, port
);
12258 /* Reset the phy */
12259 elink_cl45_write(sc
, &phy
[port
],
12260 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 1 << 15);
12263 /* Add delay of 150ms after reset */
12266 if (phy
[PORT_0
].addr
& 0x1) {
12267 phy_blk
[PORT_0
] = &(phy
[PORT_1
]);
12268 phy_blk
[PORT_1
] = &(phy
[PORT_0
]);
12270 phy_blk
[PORT_0
] = &(phy
[PORT_0
]);
12271 phy_blk
[PORT_1
] = &(phy
[PORT_1
]);
12274 /* PART2 - Download firmware to both phys */
12275 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
12276 if (CHIP_IS_E1x(sc
))
12277 port_of_path
= port
;
12281 PMD_DRV_LOG(DEBUG
, "Loading spirom for phy address 0x%x",
12282 phy_blk
[port
]->addr
);
12283 if (elink_8073_8727_external_rom_boot(sc
, phy_blk
[port
],
12285 return ELINK_STATUS_ERROR
;
12287 /* Only set bit 10 = 1 (Tx power down) */
12288 elink_cl45_read(sc
, phy_blk
[port
],
12290 MDIO_PMA_REG_TX_POWER_DOWN
, &val
);
12292 /* Phase1 of TX_POWER_DOWN reset */
12293 elink_cl45_write(sc
, phy_blk
[port
],
12295 MDIO_PMA_REG_TX_POWER_DOWN
, (val
| 1 << 10));
12298 /* Toggle Transmitter: Power down and then up with 600ms delay
12303 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12304 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
12305 /* Phase2 of POWER_DOWN_RESET */
12306 /* Release bit 10 (Release Tx power down) */
12307 elink_cl45_read(sc
, phy_blk
[port
],
12309 MDIO_PMA_REG_TX_POWER_DOWN
, &val
);
12311 elink_cl45_write(sc
, phy_blk
[port
],
12313 MDIO_PMA_REG_TX_POWER_DOWN
,
12314 (val
& (~(1 << 10))));
12317 /* Read modify write the SPI-ROM version select register */
12318 elink_cl45_read(sc
, phy_blk
[port
],
12320 MDIO_PMA_REG_EDC_FFE_MAIN
, &val
);
12321 elink_cl45_write(sc
, phy_blk
[port
],
12323 MDIO_PMA_REG_EDC_FFE_MAIN
, (val
| (1 << 12)));
12325 /* set GPIO2 back to LOW */
12326 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
12327 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
12329 return ELINK_STATUS_OK
;
12332 static elink_status_t
elink_8726_common_init_phy(struct bnx2x_softc
*sc
,
12333 uint32_t shmem_base_path
[],
12334 uint32_t shmem2_base_path
[],
12336 __rte_unused
uint32_t chip_id
)
12340 struct elink_phy phy
;
12341 /* Use port1 because of the static port-swap */
12342 /* Enable the module detection interrupt */
12343 val
= REG_RD(sc
, MISC_REG_GPIO_EVENT_EN
);
12344 val
|= ((1 << MISC_REGISTERS_GPIO_3
) |
12346 (MISC_REGISTERS_GPIO_3
+ MISC_REGISTERS_GPIO_PORT_SHIFT
)));
12347 REG_WR(sc
, MISC_REG_GPIO_EVENT_EN
, val
);
12349 elink_ext_phy_hw_reset(sc
, 0);
12351 for (port
= 0; port
< PORT_MAX
; port
++) {
12352 uint32_t shmem_base
, shmem2_base
;
12354 /* In E2, same phy is using for port0 of the two paths */
12355 if (CHIP_IS_E1x(sc
)) {
12356 shmem_base
= shmem_base_path
[0];
12357 shmem2_base
= shmem2_base_path
[0];
12359 shmem_base
= shmem_base_path
[port
];
12360 shmem2_base
= shmem2_base_path
[port
];
12362 /* Extract the ext phy address for the port */
12363 if (elink_populate_phy(sc
, phy_index
, shmem_base
, shmem2_base
,
12364 port
, &phy
) != ELINK_STATUS_OK
) {
12365 PMD_DRV_LOG(DEBUG
, "populate phy failed");
12366 return ELINK_STATUS_ERROR
;
12370 elink_cl45_write(sc
, &phy
,
12371 MDIO_PMA_DEVAD
, MDIO_PMA_REG_GEN_CTRL
, 0x0001);
12373 /* Set fault module detected LED on */
12374 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_0
,
12375 MISC_REGISTERS_GPIO_HIGH
, port
);
12378 return ELINK_STATUS_OK
;
12381 static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc
*sc
,
12382 uint32_t shmem_base
, uint8_t * io_gpio
,
12386 uint32_t phy_gpio_reset
= REG_RD(sc
, shmem_base
+
12387 offsetof(struct shmem_region
,
12389 port_hw_config
[PORT_0
].
12391 switch (phy_gpio_reset
) {
12392 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0
:
12396 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0
:
12400 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0
:
12404 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0
:
12408 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1
:
12412 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1
:
12416 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1
:
12420 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1
:
12425 /* Don't override the io_gpio and io_port */
12430 static elink_status_t
elink_8727_common_init_phy(struct bnx2x_softc
*sc
,
12431 uint32_t shmem_base_path
[],
12432 uint32_t shmem2_base_path
[],
12434 __rte_unused
uint32_t chip_id
)
12436 int8_t port
, reset_gpio
;
12437 uint32_t swap_val
, swap_override
;
12438 struct elink_phy phy
[PORT_MAX
];
12439 struct elink_phy
*phy_blk
[PORT_MAX
];
12440 int8_t port_of_path
;
12441 swap_val
= REG_RD(sc
, NIG_REG_PORT_SWAP
);
12442 swap_override
= REG_RD(sc
, NIG_REG_STRAP_OVERRIDE
);
12444 reset_gpio
= MISC_REGISTERS_GPIO_1
;
12447 /* Retrieve the reset gpio/port which control the reset.
12448 * Default is GPIO1, PORT1
12450 elink_get_ext_phy_reset_gpio(sc
, shmem_base_path
[0],
12451 (uint8_t *) & reset_gpio
,
12452 (uint8_t *) & port
);
12454 /* Calculate the port based on port swap */
12455 port
^= (swap_val
&& swap_override
);
12457 /* Initiate PHY reset */
12458 elink_cb_gpio_write(sc
, reset_gpio
, MISC_REGISTERS_GPIO_OUTPUT_LOW
,
12461 elink_cb_gpio_write(sc
, reset_gpio
, MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
12466 /* PART1 - Reset both phys */
12467 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
12468 uint32_t shmem_base
, shmem2_base
;
12470 /* In E2, same phy is using for port0 of the two paths */
12471 if (CHIP_IS_E1x(sc
)) {
12472 shmem_base
= shmem_base_path
[0];
12473 shmem2_base
= shmem2_base_path
[0];
12474 port_of_path
= port
;
12476 shmem_base
= shmem_base_path
[port
];
12477 shmem2_base
= shmem2_base_path
[port
];
12481 /* Extract the ext phy address for the port */
12482 if (elink_populate_phy(sc
, phy_index
, shmem_base
, shmem2_base
,
12483 port_of_path
, &phy
[port
]) !=
12485 PMD_DRV_LOG(DEBUG
, "populate phy failed");
12486 return ELINK_STATUS_ERROR
;
12488 /* disable attentions */
12489 elink_bits_dis(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+
12491 (ELINK_NIG_MASK_XGXS0_LINK_STATUS
|
12492 ELINK_NIG_MASK_XGXS0_LINK10G
|
12493 ELINK_NIG_MASK_SERDES0_LINK_STATUS
|
12494 ELINK_NIG_MASK_MI_INT
));
12496 /* Reset the phy */
12497 elink_cl45_write(sc
, &phy
[port
],
12498 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 1 << 15);
12501 /* Add delay of 150ms after reset */
12503 if (phy
[PORT_0
].addr
& 0x1) {
12504 phy_blk
[PORT_0
] = &(phy
[PORT_1
]);
12505 phy_blk
[PORT_1
] = &(phy
[PORT_0
]);
12507 phy_blk
[PORT_0
] = &(phy
[PORT_0
]);
12508 phy_blk
[PORT_1
] = &(phy
[PORT_1
]);
12510 /* PART2 - Download firmware to both phys */
12511 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
12512 if (CHIP_IS_E1x(sc
))
12513 port_of_path
= port
;
12516 PMD_DRV_LOG(DEBUG
, "Loading spirom for phy address 0x%x",
12517 phy_blk
[port
]->addr
);
12518 if (elink_8073_8727_external_rom_boot(sc
, phy_blk
[port
],
12520 return ELINK_STATUS_ERROR
;
12521 /* Disable PHY transmitter output */
12522 elink_cl45_write(sc
, phy_blk
[port
],
12523 MDIO_PMA_DEVAD
, MDIO_PMA_REG_TX_DISABLE
, 1);
12526 return ELINK_STATUS_OK
;
12529 static elink_status_t
elink_84833_common_init_phy(struct bnx2x_softc
*sc
,
12530 uint32_t shmem_base_path
[],
12531 __rte_unused
uint32_t
12532 shmem2_base_path
[],
12533 __rte_unused
uint8_t
12534 phy_index
, uint32_t chip_id
)
12536 uint8_t reset_gpios
;
12537 reset_gpios
= elink_84833_get_reset_gpios(sc
, shmem_base_path
, chip_id
);
12538 elink_cb_gpio_mult_write(sc
, reset_gpios
,
12539 MISC_REGISTERS_GPIO_OUTPUT_LOW
);
12541 elink_cb_gpio_mult_write(sc
, reset_gpios
,
12542 MISC_REGISTERS_GPIO_OUTPUT_HIGH
);
12543 PMD_DRV_LOG(DEBUG
, "84833 reset pulse on pin values 0x%x", reset_gpios
);
12544 return ELINK_STATUS_OK
;
12547 static elink_status_t
elink_ext_phy_common_init(struct bnx2x_softc
*sc
,
12548 uint32_t shmem_base_path
[],
12549 uint32_t shmem2_base_path
[],
12551 uint32_t ext_phy_type
,
12554 elink_status_t rc
= ELINK_STATUS_OK
;
12556 switch (ext_phy_type
) {
12557 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073
:
12558 rc
= elink_8073_common_init_phy(sc
, shmem_base_path
,
12560 phy_index
, chip_id
);
12562 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722
:
12563 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727
:
12564 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC
:
12565 rc
= elink_8727_common_init_phy(sc
, shmem_base_path
,
12567 phy_index
, chip_id
);
12570 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726
:
12571 /* GPIO1 affects both ports, so there's need to pull
12572 * it for single port alone
12574 rc
= elink_8726_common_init_phy(sc
, shmem_base_path
,
12576 phy_index
, chip_id
);
12578 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
:
12579 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
:
12580 /* GPIO3's are linked, and so both need to be toggled
12581 * to obtain required 2us pulse.
12583 rc
= elink_84833_common_init_phy(sc
, shmem_base_path
,
12585 phy_index
, chip_id
);
12587 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
:
12588 rc
= ELINK_STATUS_ERROR
;
12592 "ext_phy 0x%x common init not required",
12597 if (rc
!= ELINK_STATUS_OK
)
12598 elink_cb_event_log(sc
, ELINK_LOG_ID_PHY_UNINITIALIZED
, 0); // "Warning: PHY was not initialized,"
12604 elink_status_t
elink_common_init_phy(struct bnx2x_softc
* sc
,
12605 uint32_t shmem_base_path
[],
12606 uint32_t shmem2_base_path
[],
12608 __rte_unused
uint8_t one_port_enabled
)
12610 elink_status_t rc
= ELINK_STATUS_OK
;
12611 uint32_t phy_ver
, val
;
12612 uint8_t phy_index
= 0;
12613 uint32_t ext_phy_type
, ext_phy_config
;
12615 elink_set_mdio_clk(sc
, GRCBASE_EMAC0
);
12616 elink_set_mdio_clk(sc
, GRCBASE_EMAC1
);
12617 PMD_DRV_LOG(DEBUG
, "Begin common phy init");
12618 if (CHIP_IS_E3(sc
)) {
12620 val
= REG_RD(sc
, MISC_REG_GEN_PURP_HWG
);
12621 REG_WR(sc
, MISC_REG_GEN_PURP_HWG
, val
| 1);
12623 /* Check if common init was already done */
12624 phy_ver
= REG_RD(sc
, shmem_base_path
[0] +
12625 offsetof(struct shmem_region
,
12626 port_mb
[PORT_0
].ext_phy_fw_version
));
12628 PMD_DRV_LOG(DEBUG
, "Not doing common init; phy ver is 0x%x",
12630 return ELINK_STATUS_OK
;
12633 /* Read the ext_phy_type for arbitrary port(0) */
12634 for (phy_index
= ELINK_EXT_PHY1
; phy_index
< ELINK_MAX_PHYS
;
12636 ext_phy_config
= elink_get_ext_phy_config(sc
,
12637 shmem_base_path
[0],
12639 ext_phy_type
= ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config
);
12640 rc
|= elink_ext_phy_common_init(sc
, shmem_base_path
,
12642 phy_index
, ext_phy_type
,
12648 static void elink_check_over_curr(struct elink_params
*params
,
12649 struct elink_vars
*vars
)
12651 struct bnx2x_softc
*sc
= params
->sc
;
12653 uint8_t port
= params
->port
;
12656 cfg_pin
= (REG_RD(sc
, params
->shmem_base
+
12657 offsetof(struct shmem_region
,
12658 dev_info
.port_hw_config
[port
].
12659 e3_cmn_pin_cfg1
)) &
12660 PORT_HW_CFG_E3_OVER_CURRENT_MASK
) >>
12661 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT
;
12663 /* Ignore check if no external input PIN available */
12664 if (elink_get_cfg_pin(sc
, cfg_pin
, &pin_val
) != ELINK_STATUS_OK
)
12668 if ((vars
->phy_flags
& PHY_OVER_CURRENT_FLAG
) == 0) {
12669 elink_cb_event_log(sc
, ELINK_LOG_ID_OVER_CURRENT
, params
->port
); //"Error: Power fault on Port %d has"
12670 // " been detected and the power to "
12671 // "that SFP+ module has been removed"
12672 // " to prevent failure of the card."
12673 // " Please remove the SFP+ module and"
12674 // " restart the system to clear this"
12676 vars
->phy_flags
|= PHY_OVER_CURRENT_FLAG
;
12677 elink_warpcore_power_module(params
, 0);
12680 vars
->phy_flags
&= ~PHY_OVER_CURRENT_FLAG
;
12683 /* Returns 0 if no change occured since last check; 1 otherwise. */
12684 static uint8_t elink_analyze_link_error(struct elink_params
*params
,
12685 struct elink_vars
*vars
,
12686 uint32_t status
, uint32_t phy_flag
,
12687 uint32_t link_flag
, uint8_t notify
)
12689 struct bnx2x_softc
*sc
= params
->sc
;
12690 /* Compare new value with previous value */
12692 uint32_t old_status
= (vars
->phy_flags
& phy_flag
) ? 1 : 0;
12694 if ((status
^ old_status
) == 0)
12697 /* If values differ */
12698 switch (phy_flag
) {
12699 case PHY_HALF_OPEN_CONN_FLAG
:
12700 PMD_DRV_LOG(DEBUG
, "Analyze Remote Fault");
12702 case PHY_SFP_TX_FAULT_FLAG
:
12703 PMD_DRV_LOG(DEBUG
, "Analyze TX Fault");
12706 PMD_DRV_LOG(DEBUG
, "Analyze UNKNOWN");
12708 PMD_DRV_LOG(DEBUG
, "Link changed:[%x %x]->%x", vars
->link_up
,
12709 old_status
, status
);
12711 /* a. Update shmem->link_status accordingly
12712 * b. Update elink_vars->link_up
12715 vars
->link_status
&= ~LINK_STATUS_LINK_UP
;
12716 vars
->link_status
|= link_flag
;
12718 vars
->phy_flags
|= phy_flag
;
12720 /* activate nig drain */
12721 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 1);
12722 /* Set LED mode to off since the PHY doesn't know about these
12725 led_mode
= ELINK_LED_MODE_OFF
;
12727 vars
->link_status
|= LINK_STATUS_LINK_UP
;
12728 vars
->link_status
&= ~link_flag
;
12730 vars
->phy_flags
&= ~phy_flag
;
12731 led_mode
= ELINK_LED_MODE_OPER
;
12733 /* Clear nig drain */
12734 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 0);
12736 elink_sync_link(params
, vars
);
12737 /* Update the LED according to the link state */
12738 elink_set_led(params
, vars
, led_mode
, ELINK_SPEED_10000
);
12740 /* Update link status in the shared memory */
12741 elink_update_mng(params
, vars
->link_status
);
12743 /* C. Trigger General Attention */
12744 vars
->periodic_flags
|= ELINK_PERIODIC_FLAGS_LINK_EVENT
;
12746 elink_cb_notify_link_changed(sc
);
12751 /******************************************************************************
12753 * This function checks for half opened connection change indication.
12754 * When such change occurs, it calls the elink_analyze_link_error
12755 * to check if Remote Fault is set or cleared. Reception of remote fault
12756 * status message in the MAC indicates that the peer's MAC has detected
12757 * a fault, for example, due to break in the TX side of fiber.
12759 ******************************************************************************/
12760 static elink_status_t
elink_check_half_open_conn(struct elink_params
*params
,
12761 struct elink_vars
*vars
,
12764 struct bnx2x_softc
*sc
= params
->sc
;
12765 uint32_t lss_status
= 0;
12767 /* In case link status is physically up @ 10G do */
12768 if (((vars
->phy_flags
& PHY_PHYSICAL_LINK_FLAG
) == 0) ||
12769 (REG_RD(sc
, NIG_REG_EGRESS_EMAC0_PORT
+ params
->port
* 4)))
12770 return ELINK_STATUS_OK
;
12772 if (CHIP_IS_E3(sc
) &&
12773 (REG_RD(sc
, MISC_REG_RESET_REG_2
) &
12774 (MISC_REGISTERS_RESET_REG_2_XMAC
))) {
12775 /* Check E3 XMAC */
12776 /* Note that link speed cannot be queried here, since it may be
12777 * zero while link is down. In case UMAC is active, LSS will
12778 * simply not be set
12780 mac_base
= (params
->port
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
12782 /* Clear stick bits (Requires rising edge) */
12783 REG_WR(sc
, mac_base
+ XMAC_REG_CLEAR_RX_LSS_STATUS
, 0);
12784 REG_WR(sc
, mac_base
+ XMAC_REG_CLEAR_RX_LSS_STATUS
,
12785 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS
|
12786 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS
);
12787 if (REG_RD(sc
, mac_base
+ XMAC_REG_RX_LSS_STATUS
))
12790 elink_analyze_link_error(params
, vars
, lss_status
,
12791 PHY_HALF_OPEN_CONN_FLAG
,
12792 LINK_STATUS_NONE
, notify
);
12793 } else if (REG_RD(sc
, MISC_REG_RESET_REG_2
) &
12794 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< params
->port
)) {
12795 /* Check E1X / E2 BMAC */
12796 uint32_t lss_status_reg
;
12797 uint32_t wb_data
[2];
12798 mac_base
= params
->port
? NIG_REG_INGRESS_BMAC1_MEM
:
12799 NIG_REG_INGRESS_BMAC0_MEM
;
12800 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
12801 if (CHIP_IS_E2(sc
))
12802 lss_status_reg
= BIGMAC2_REGISTER_RX_LSS_STAT
;
12804 lss_status_reg
= BIGMAC_REGISTER_RX_LSS_STATUS
;
12806 REG_RD_DMAE(sc
, mac_base
+ lss_status_reg
, wb_data
, 2);
12807 lss_status
= (wb_data
[0] > 0);
12809 elink_analyze_link_error(params
, vars
, lss_status
,
12810 PHY_HALF_OPEN_CONN_FLAG
,
12811 LINK_STATUS_NONE
, notify
);
12813 return ELINK_STATUS_OK
;
12816 static void elink_sfp_tx_fault_detection(struct elink_phy
*phy
,
12817 struct elink_params
*params
,
12818 struct elink_vars
*vars
)
12820 struct bnx2x_softc
*sc
= params
->sc
;
12821 uint32_t cfg_pin
, value
= 0;
12822 uint8_t led_change
, port
= params
->port
;
12824 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
12825 cfg_pin
= (REG_RD(sc
, params
->shmem_base
+ offsetof(struct shmem_region
,
12830 PORT_HW_CFG_E3_TX_FAULT_MASK
) >>
12831 PORT_HW_CFG_E3_TX_FAULT_SHIFT
;
12833 if (elink_get_cfg_pin(sc
, cfg_pin
, &value
)) {
12834 PMD_DRV_LOG(DEBUG
, "Failed to read pin 0x%02x", cfg_pin
);
12838 led_change
= elink_analyze_link_error(params
, vars
, value
,
12839 PHY_SFP_TX_FAULT_FLAG
,
12840 LINK_STATUS_SFP_TX_FAULT
, 1);
12843 /* Change TX_Fault led, set link status for further syncs */
12846 if (vars
->phy_flags
& PHY_SFP_TX_FAULT_FLAG
) {
12847 led_mode
= MISC_REGISTERS_GPIO_HIGH
;
12848 vars
->link_status
|= LINK_STATUS_SFP_TX_FAULT
;
12850 led_mode
= MISC_REGISTERS_GPIO_LOW
;
12851 vars
->link_status
&= ~LINK_STATUS_SFP_TX_FAULT
;
12854 /* If module is unapproved, led should be on regardless */
12855 if (!(phy
->flags
& ELINK_FLAGS_SFP_NOT_APPROVED
)) {
12856 PMD_DRV_LOG(DEBUG
, "Change TX_Fault LED: ->%x",
12858 elink_set_e3_module_fault_led(params
, led_mode
);
12863 static void elink_kr2_recovery(struct elink_params
*params
,
12864 struct elink_vars
*vars
, struct elink_phy
*phy
)
12866 PMD_DRV_LOG(DEBUG
, "KR2 recovery");
12868 elink_warpcore_enable_AN_KR2(phy
, params
, vars
);
12869 elink_warpcore_restart_AN_KR(phy
, params
);
12872 static void elink_check_kr2_wa(struct elink_params
*params
,
12873 struct elink_vars
*vars
, struct elink_phy
*phy
)
12875 struct bnx2x_softc
*sc
= params
->sc
;
12876 uint16_t base_page
, next_page
, not_kr2_device
, lane
;
12879 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
12880 * Since some switches tend to reinit the AN process and clear the
12881 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
12882 * and recovered many times
12884 if (vars
->check_kr2_recovery_cnt
> 0) {
12885 vars
->check_kr2_recovery_cnt
--;
12889 sigdet
= elink_warpcore_get_sigdet(phy
, params
);
12891 if (!(vars
->link_attr_sync
& LINK_ATTR_SYNC_KR2_ENABLE
)) {
12892 elink_kr2_recovery(params
, vars
, phy
);
12893 PMD_DRV_LOG(DEBUG
, "No sigdet");
12898 lane
= elink_get_warpcore_lane(params
);
12899 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
12900 MDIO_AER_BLOCK_AER_REG
, lane
);
12901 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
12902 MDIO_AN_REG_LP_AUTO_NEG
, &base_page
);
12903 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
12904 MDIO_AN_REG_LP_AUTO_NEG2
, &next_page
);
12905 elink_set_aer_mmd(params
, phy
);
12907 /* CL73 has not begun yet */
12908 if (base_page
== 0) {
12909 if (!(vars
->link_attr_sync
& LINK_ATTR_SYNC_KR2_ENABLE
)) {
12910 elink_kr2_recovery(params
, vars
, phy
);
12911 PMD_DRV_LOG(DEBUG
, "No BP");
12916 /* In case NP bit is not set in the BasePage, or it is set,
12917 * but only KX is advertised, declare this link partner as non-KR2
12920 not_kr2_device
= (((base_page
& 0x8000) == 0) ||
12921 (((base_page
& 0x8000) &&
12922 ((next_page
& 0xe0) == 0x2))));
12924 /* In case KR2 is already disabled, check if we need to re-enable it */
12925 if (!(vars
->link_attr_sync
& LINK_ATTR_SYNC_KR2_ENABLE
)) {
12926 if (!not_kr2_device
) {
12927 PMD_DRV_LOG(DEBUG
, "BP=0x%x, NP=0x%x", base_page
,
12929 elink_kr2_recovery(params
, vars
, phy
);
12933 /* KR2 is enabled, but not KR2 device */
12934 if (not_kr2_device
) {
12935 /* Disable KR2 on both lanes */
12936 PMD_DRV_LOG(DEBUG
, "BP=0x%x, NP=0x%x", base_page
, next_page
);
12937 elink_disable_kr2(params
, vars
, phy
);
12938 /* Restart AN on leading lane */
12939 elink_warpcore_restart_AN_KR(phy
, params
);
12944 void elink_period_func(struct elink_params
*params
, struct elink_vars
*vars
)
12947 struct bnx2x_softc
*sc
= params
->sc
;
12948 for (phy_idx
= ELINK_INT_PHY
; phy_idx
< ELINK_MAX_PHYS
; phy_idx
++) {
12949 if (params
->phy
[phy_idx
].flags
& ELINK_FLAGS_TX_ERROR_CHECK
) {
12950 elink_set_aer_mmd(params
, ¶ms
->phy
[phy_idx
]);
12951 if (elink_check_half_open_conn(params
, vars
, 1) !=
12953 PMD_DRV_LOG(DEBUG
, "Fault detection failed");
12959 if (CHIP_IS_E3(sc
)) {
12960 struct elink_phy
*phy
= ¶ms
->phy
[ELINK_INT_PHY
];
12961 elink_set_aer_mmd(params
, phy
);
12962 if ((phy
->supported
& ELINK_SUPPORTED_20000baseKR2_Full
) &&
12963 (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
))
12964 elink_check_kr2_wa(params
, vars
, phy
);
12965 elink_check_over_curr(params
, vars
);
12966 if (vars
->rx_tx_asic_rst
)
12967 elink_warpcore_config_runtime(phy
, params
, vars
);
12969 if ((REG_RD(sc
, params
->shmem_base
+
12970 offsetof(struct shmem_region
,
12971 dev_info
.port_hw_config
[params
->port
].
12973 & PORT_HW_CFG_NET_SERDES_IF_MASK
) ==
12974 PORT_HW_CFG_NET_SERDES_IF_SFI
) {
12975 if (elink_is_sfp_module_plugged(params
)) {
12976 elink_sfp_tx_fault_detection(phy
, params
, vars
);
12977 } else if (vars
->link_status
& LINK_STATUS_SFP_TX_FAULT
) {
12978 /* Clean trail, interrupt corrects the leds */
12979 vars
->link_status
&= ~LINK_STATUS_SFP_TX_FAULT
;
12980 vars
->phy_flags
&= ~PHY_SFP_TX_FAULT_FLAG
;
12981 /* Update link status in the shared memory */
12982 elink_update_mng(params
, vars
->link_status
);
12988 uint8_t elink_fan_failure_det_req(struct bnx2x_softc
*sc
,
12989 uint32_t shmem_base
,
12990 uint32_t shmem2_base
, uint8_t port
)
12992 uint8_t phy_index
, fan_failure_det_req
= 0;
12993 struct elink_phy phy
;
12994 for (phy_index
= ELINK_EXT_PHY1
; phy_index
< ELINK_MAX_PHYS
;
12996 if (elink_populate_phy(sc
, phy_index
, shmem_base
, shmem2_base
,
12998 != ELINK_STATUS_OK
) {
12999 PMD_DRV_LOG(DEBUG
, "populate phy failed");
13002 fan_failure_det_req
|= (phy
.flags
&
13003 ELINK_FLAGS_FAN_FAILURE_DET_REQ
);
13005 return fan_failure_det_req
;
13008 void elink_hw_reset_phy(struct elink_params
*params
)
13011 struct bnx2x_softc
*sc
= params
->sc
;
13012 elink_update_mng(params
, 0);
13013 elink_bits_dis(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+ params
->port
* 4,
13014 (ELINK_NIG_MASK_XGXS0_LINK_STATUS
|
13015 ELINK_NIG_MASK_XGXS0_LINK10G
|
13016 ELINK_NIG_MASK_SERDES0_LINK_STATUS
|
13017 ELINK_NIG_MASK_MI_INT
));
13019 for (phy_index
= ELINK_INT_PHY
; phy_index
< ELINK_MAX_PHYS
; phy_index
++) {
13020 if (params
->phy
[phy_index
].hw_reset
) {
13021 params
->phy
[phy_index
].hw_reset(¶ms
->phy
[phy_index
],
13023 params
->phy
[phy_index
] = phy_null
;
13028 void elink_init_mod_abs_int(struct bnx2x_softc
*sc
, struct elink_vars
*vars
,
13029 __rte_unused
uint32_t chip_id
, uint32_t shmem_base
,
13030 uint32_t shmem2_base
, uint8_t port
)
13032 uint8_t gpio_num
= 0xff, gpio_port
= 0xff, phy_index
;
13034 uint32_t offset
, aeu_mask
, swap_val
, swap_override
, sync_offset
;
13035 if (CHIP_IS_E3(sc
)) {
13036 if (elink_get_mod_abs_int_cfg(sc
,
13040 &gpio_port
) != ELINK_STATUS_OK
)
13043 struct elink_phy phy
;
13044 for (phy_index
= ELINK_EXT_PHY1
; phy_index
< ELINK_MAX_PHYS
;
13046 if (elink_populate_phy(sc
, phy_index
, shmem_base
,
13047 shmem2_base
, port
, &phy
)
13048 != ELINK_STATUS_OK
) {
13049 PMD_DRV_LOG(DEBUG
, "populate phy failed");
13052 if (phy
.type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726
) {
13053 gpio_num
= MISC_REGISTERS_GPIO_3
;
13060 if (gpio_num
== 0xff)
13063 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13064 elink_cb_gpio_write(sc
, gpio_num
, MISC_REGISTERS_GPIO_INPUT_HI_Z
,
13067 swap_val
= REG_RD(sc
, NIG_REG_PORT_SWAP
);
13068 swap_override
= REG_RD(sc
, NIG_REG_STRAP_OVERRIDE
);
13069 gpio_port
^= (swap_val
&& swap_override
);
13071 vars
->aeu_int_mask
= AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0
<<
13072 (gpio_num
+ (gpio_port
<< 2));
13074 sync_offset
= shmem_base
+
13075 offsetof(struct shmem_region
,
13076 dev_info
.port_hw_config
[port
].aeu_int_mask
);
13077 REG_WR(sc
, sync_offset
, vars
->aeu_int_mask
);
13079 PMD_DRV_LOG(DEBUG
, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x",
13080 gpio_num
, gpio_port
, vars
->aeu_int_mask
);
13083 offset
= MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
;
13085 offset
= MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
;
13087 /* Open appropriate AEU for interrupts */
13088 aeu_mask
= REG_RD(sc
, offset
);
13089 aeu_mask
|= vars
->aeu_int_mask
;
13090 REG_WR(sc
, offset
, aeu_mask
);
13092 /* Enable the GPIO to trigger interrupt */
13093 val
= REG_RD(sc
, MISC_REG_GPIO_EVENT_EN
);
13094 val
|= 1 << (gpio_num
+ (gpio_port
<< 2));
13095 REG_WR(sc
, MISC_REG_GPIO_EVENT_EN
, val
);