]> git.proxmox.com Git - ceph.git/blob - ceph/src/seastar/dpdk/drivers/net/bnxt/bnxt_ethdev.c
projects / ceph.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
update sources to ceph Nautilus 14.2.1
[ceph.git] / ceph / src / seastar / dpdk / drivers / net / bnxt / bnxt_ethdev.c
1 /*-
2 * BSD LICENSE
3 *
4 * Copyright(c) Broadcom Limited.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <inttypes.h>
35 #include <stdbool.h>
36
37 #include <rte_dev.h>
38 #include <rte_ethdev.h>
39 #include <rte_ethdev_pci.h>
40 #include <rte_malloc.h>
41 #include <rte_cycles.h>
42
43 #include "bnxt.h"
44 #include "bnxt_cpr.h"
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
47 #include "bnxt_irq.h"
48 #include "bnxt_ring.h"
49 #include "bnxt_rxq.h"
50 #include "bnxt_rxr.h"
51 #include "bnxt_stats.h"
52 #include "bnxt_txq.h"
53 #include "bnxt_txr.h"
54 #include "bnxt_vnic.h"
55 #include "hsi_struct_def_dpdk.h"
56
57 #define DRV_MODULE_NAME "bnxt"
58 static const char bnxt_version[] =
59 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
60
61 #define PCI_VENDOR_ID_BROADCOM 0x14E4
62
63 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
64 #define BROADCOM_DEV_ID_57414_VF 0x16c1
65 #define BROADCOM_DEV_ID_57301 0x16c8
66 #define BROADCOM_DEV_ID_57302 0x16c9
67 #define BROADCOM_DEV_ID_57304_PF 0x16ca
68 #define BROADCOM_DEV_ID_57304_VF 0x16cb
69 #define BROADCOM_DEV_ID_57417_MF 0x16cc
70 #define BROADCOM_DEV_ID_NS2 0x16cd
71 #define BROADCOM_DEV_ID_57311 0x16ce
72 #define BROADCOM_DEV_ID_57312 0x16cf
73 #define BROADCOM_DEV_ID_57402 0x16d0
74 #define BROADCOM_DEV_ID_57404 0x16d1
75 #define BROADCOM_DEV_ID_57406_PF 0x16d2
76 #define BROADCOM_DEV_ID_57406_VF 0x16d3
77 #define BROADCOM_DEV_ID_57402_MF 0x16d4
78 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
79 #define BROADCOM_DEV_ID_57412 0x16d6
80 #define BROADCOM_DEV_ID_57414 0x16d7
81 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
82 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
83 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
84 #define BROADCOM_DEV_ID_57412_MF 0x16de
85 #define BROADCOM_DEV_ID_57314 0x16df
86 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
87 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
88 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
89 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
90 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
91 #define BROADCOM_DEV_ID_57404_MF 0x16e7
92 #define BROADCOM_DEV_ID_57406_MF 0x16e8
93 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
94 #define BROADCOM_DEV_ID_57407_MF 0x16ea
95 #define BROADCOM_DEV_ID_57414_MF 0x16ec
96 #define BROADCOM_DEV_ID_57416_MF 0x16ee
97
98 static const struct rte_pci_id bnxt_pci_id_map[] = {
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
133 { .vendor_id = 0, /* sentinel */ },
134 };
135
136 #define BNXT_ETH_RSS_SUPPORT ( \
137 ETH_RSS_IPV4 | \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
140 ETH_RSS_IPV6 | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
143
144 /***********************/
145
146 /*
147 * High level utility functions
148 */
149
150 static void bnxt_free_mem(struct bnxt *bp)
151 {
152 bnxt_free_filter_mem(bp);
153 bnxt_free_vnic_attributes(bp);
154 bnxt_free_vnic_mem(bp);
155
156 bnxt_free_stats(bp);
157 bnxt_free_tx_rings(bp);
158 bnxt_free_rx_rings(bp);
159 bnxt_free_def_cp_ring(bp);
160 }
161
162 static int bnxt_alloc_mem(struct bnxt *bp)
163 {
164 int rc;
165
166 /* Default completion ring */
167 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
168 if (rc)
169 goto alloc_mem_err;
170
171 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
172 bp->def_cp_ring, "def_cp");
173 if (rc)
174 goto alloc_mem_err;
175
176 rc = bnxt_alloc_vnic_mem(bp);
177 if (rc)
178 goto alloc_mem_err;
179
180 rc = bnxt_alloc_vnic_attributes(bp);
181 if (rc)
182 goto alloc_mem_err;
183
184 rc = bnxt_alloc_filter_mem(bp);
185 if (rc)
186 goto alloc_mem_err;
187
188 return 0;
189
190 alloc_mem_err:
191 bnxt_free_mem(bp);
192 return rc;
193 }
194
195 static int bnxt_init_chip(struct bnxt *bp)
196 {
197 unsigned int i, rss_idx, fw_idx;
198 struct rte_eth_link new;
199 int rc;
200
201 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
202 if (rc) {
203 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
204 goto err_out;
205 }
206
207 rc = bnxt_alloc_hwrm_rings(bp);
208 if (rc) {
209 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
210 goto err_out;
211 }
212
213 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
214 if (rc) {
215 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
216 goto err_out;
217 }
218
219 rc = bnxt_mq_rx_configure(bp);
220 if (rc) {
221 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
222 goto err_out;
223 }
224
225 /* VNIC configuration */
226 for (i = 0; i < bp->nr_vnics; i++) {
227 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
228
229 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
230 if (rc) {
231 RTE_LOG(ERR, PMD, "HWRM vnic alloc failure rc: %x\n",
232 rc);
233 goto err_out;
234 }
235
236 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
237 if (rc) {
238 RTE_LOG(ERR, PMD,
239 "HWRM vnic ctx alloc failure rc: %x\n", rc);
240 goto err_out;
241 }
242
243 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
244 if (rc) {
245 RTE_LOG(ERR, PMD, "HWRM vnic cfg failure rc: %x\n", rc);
246 goto err_out;
247 }
248
249 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
250 if (rc) {
251 RTE_LOG(ERR, PMD, "HWRM vnic filter failure rc: %x\n",
252 rc);
253 goto err_out;
254 }
255 if (vnic->rss_table && vnic->hash_type) {
256 /*
257 * Fill the RSS hash & redirection table with
258 * ring group ids for all VNICs
259 */
260 for (rss_idx = 0, fw_idx = 0;
261 rss_idx < HW_HASH_INDEX_SIZE;
262 rss_idx++, fw_idx++) {
263 if (vnic->fw_grp_ids[fw_idx] ==
264 INVALID_HW_RING_ID)
265 fw_idx = 0;
266 vnic->rss_table[rss_idx] =
267 vnic->fw_grp_ids[fw_idx];
268 }
269 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
270 if (rc) {
271 RTE_LOG(ERR, PMD,
272 "HWRM vnic set RSS failure rc: %x\n",
273 rc);
274 goto err_out;
275 }
276 }
277 }
278 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]);
279 if (rc) {
280 RTE_LOG(ERR, PMD,
281 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
282 goto err_out;
283 }
284
285 rc = bnxt_get_hwrm_link_config(bp, &new);
286 if (rc) {
287 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
288 goto err_out;
289 }
290
291 if (!bp->link_info.link_up) {
292 rc = bnxt_set_hwrm_link_config(bp, true);
293 if (rc) {
294 RTE_LOG(ERR, PMD,
295 "HWRM link config failure rc: %x\n", rc);
296 goto err_out;
297 }
298 }
299
300 return 0;
301
302 err_out:
303 bnxt_free_all_hwrm_resources(bp);
304
305 return rc;
306 }
307
308 static int bnxt_shutdown_nic(struct bnxt *bp)
309 {
310 bnxt_free_all_hwrm_resources(bp);
311 bnxt_free_all_filters(bp);
312 bnxt_free_all_vnics(bp);
313 return 0;
314 }
315
316 static int bnxt_init_nic(struct bnxt *bp)
317 {
318 int rc;
319
320 bnxt_init_ring_grps(bp);
321 bnxt_init_vnics(bp);
322 bnxt_init_filters(bp);
323
324 rc = bnxt_init_chip(bp);
325 if (rc)
326 return rc;
327
328 return 0;
329 }
330
331 /*
332 * Device configuration and status function
333 */
334
335 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
336 struct rte_eth_dev_info *dev_info)
337 {
338 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
339 uint16_t max_vnics, i, j, vpool, vrxq;
340
341 dev_info->pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
342
343 /* MAC Specifics */
344 dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
345 dev_info->max_hash_mac_addrs = 0;
346
347 /* PF/VF specifics */
348 if (BNXT_PF(bp)) {
349 dev_info->max_rx_queues = bp->pf.max_rx_rings;
350 dev_info->max_tx_queues = bp->pf.max_tx_rings;
351 dev_info->max_vfs = bp->pf.active_vfs;
352 dev_info->reta_size = bp->pf.max_rsscos_ctx;
353 max_vnics = bp->pf.max_vnics;
354 } else {
355 dev_info->max_rx_queues = bp->vf.max_rx_rings;
356 dev_info->max_tx_queues = bp->vf.max_tx_rings;
357 dev_info->reta_size = bp->vf.max_rsscos_ctx;
358 max_vnics = bp->vf.max_vnics;
359 }
360
361 /* Fast path specifics */
362 dev_info->min_rx_bufsize = 1;
363 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
364 + VLAN_TAG_SIZE;
365 dev_info->rx_offload_capa = 0;
366 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
367 DEV_TX_OFFLOAD_TCP_CKSUM |
368 DEV_TX_OFFLOAD_UDP_CKSUM |
369 DEV_TX_OFFLOAD_TCP_TSO;
370
371 /* *INDENT-OFF* */
372 dev_info->default_rxconf = (struct rte_eth_rxconf) {
373 .rx_thresh = {
374 .pthresh = 8,
375 .hthresh = 8,
376 .wthresh = 0,
377 },
378 .rx_free_thresh = 32,
379 .rx_drop_en = 0,
380 };
381
382 dev_info->default_txconf = (struct rte_eth_txconf) {
383 .tx_thresh = {
384 .pthresh = 32,
385 .hthresh = 0,
386 .wthresh = 0,
387 },
388 .tx_free_thresh = 32,
389 .tx_rs_thresh = 32,
390 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
391 ETH_TXQ_FLAGS_NOOFFLOADS,
392 };
393 eth_dev->data->dev_conf.intr_conf.lsc = 1;
394
395 /* *INDENT-ON* */
396
397 /*
398 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
399 * need further investigation.
400 */
401
402 /* VMDq resources */
403 vpool = 64; /* ETH_64_POOLS */
404 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
405 for (i = 0; i < 4; vpool >>= 1, i++) {
406 if (max_vnics > vpool) {
407 for (j = 0; j < 5; vrxq >>= 1, j++) {
408 if (dev_info->max_rx_queues > vrxq) {
409 if (vpool > vrxq)
410 vpool = vrxq;
411 goto found;
412 }
413 }
414 /* Not enough resources to support VMDq */
415 break;
416 }
417 }
418 /* Not enough resources to support VMDq */
419 vpool = 0;
420 vrxq = 0;
421 found:
422 dev_info->max_vmdq_pools = vpool;
423 dev_info->vmdq_queue_num = vrxq;
424
425 dev_info->vmdq_pool_base = 0;
426 dev_info->vmdq_queue_base = 0;
427 }
428
429 /* Configure the device based on the configuration provided */
430 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
431 {
432 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
433
434 bp->rx_queues = (void *)eth_dev->data->rx_queues;
435 bp->tx_queues = (void *)eth_dev->data->tx_queues;
436
437 /* Inherit new configurations */
438 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
439 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
440 bp->rx_cp_nr_rings = bp->rx_nr_rings;
441 bp->tx_cp_nr_rings = bp->tx_nr_rings;
442
443 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
444 eth_dev->data->mtu =
445 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
446 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
447 return 0;
448 }
449
450 static inline int
451 rte_bnxt_atomic_write_link_status(struct rte_eth_dev *eth_dev,
452 struct rte_eth_link *link)
453 {
454 struct rte_eth_link *dst = &eth_dev->data->dev_link;
455 struct rte_eth_link *src = link;
456
457 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
458 *(uint64_t *)src) == 0)
459 return 1;
460
461 return 0;
462 }
463
464 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
465 {
466 struct rte_eth_link *link = &eth_dev->data->dev_link;
467
468 if (link->link_status)
469 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
470 (uint8_t)(eth_dev->data->port_id),
471 (uint32_t)link->link_speed,
472 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
473 ("full-duplex") : ("half-duplex\n"));
474 else
475 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
476 (uint8_t)(eth_dev->data->port_id));
477 }
478
479 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
480 {
481 bnxt_print_link_info(eth_dev);
482 return 0;
483 }
484
485 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
486 {
487 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
488 int rc;
489
490 bp->dev_stopped = 0;
491 rc = bnxt_hwrm_func_reset(bp);
492 if (rc) {
493 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
494 rc = -1;
495 goto error;
496 }
497
498 rc = bnxt_setup_int(bp);
499 if (rc)
500 goto error;
501
502 rc = bnxt_alloc_mem(bp);
503 if (rc)
504 goto error;
505
506 rc = bnxt_request_int(bp);
507 if (rc)
508 goto error;
509
510 rc = bnxt_init_nic(bp);
511 if (rc)
512 goto error;
513
514 bnxt_enable_int(bp);
515
516 bnxt_link_update_op(eth_dev, 0);
517 return 0;
518
519 error:
520 bnxt_shutdown_nic(bp);
521 bnxt_disable_int(bp);
522 bnxt_free_int(bp);
523 bnxt_free_tx_mbufs(bp);
524 bnxt_free_rx_mbufs(bp);
525 bnxt_free_mem(bp);
526 return rc;
527 }
528
529 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
530 {
531 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
532
533 eth_dev->data->dev_link.link_status = 1;
534 bnxt_set_hwrm_link_config(bp, true);
535 return 0;
536 }
537
538 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
539 {
540 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
541
542 eth_dev->data->dev_link.link_status = 0;
543 bnxt_set_hwrm_link_config(bp, false);
544 return 0;
545 }
546
547 /* Unload the driver, release resources */
548 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
549 {
550 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
551
552 if (bp->eth_dev->data->dev_started) {
553 /* TBD: STOP HW queues DMA */
554 eth_dev->data->dev_link.link_status = 0;
555 }
556 bnxt_set_hwrm_link_config(bp, false);
557 bnxt_disable_int(bp);
558 bnxt_free_int(bp);
559 bnxt_shutdown_nic(bp);
560 bp->dev_stopped = 1;
561 }
562
563 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
564 {
565 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
566
567 if (bp->dev_stopped == 0)
568 bnxt_dev_stop_op(eth_dev);
569
570 bnxt_free_tx_mbufs(bp);
571 bnxt_free_rx_mbufs(bp);
572 bnxt_free_mem(bp);
573 if (eth_dev->data->mac_addrs != NULL) {
574 rte_free(eth_dev->data->mac_addrs);
575 eth_dev->data->mac_addrs = NULL;
576 }
577 if (bp->grp_info != NULL) {
578 rte_free(bp->grp_info);
579 bp->grp_info = NULL;
580 }
581 }
582
583 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
584 uint32_t index)
585 {
586 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
587 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
588 struct bnxt_vnic_info *vnic;
589 struct bnxt_filter_info *filter, *temp_filter;
590 int i;
591
592 /*
593 * Loop through all VNICs from the specified filter flow pools to
594 * remove the corresponding MAC addr filter
595 */
596 for (i = 0; i < MAX_FF_POOLS; i++) {
597 if (!(pool_mask & (1ULL << i)))
598 continue;
599
600 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
601 filter = STAILQ_FIRST(&vnic->filter);
602 while (filter) {
603 temp_filter = STAILQ_NEXT(filter, next);
604 if (filter->mac_index == index) {
605 STAILQ_REMOVE(&vnic->filter, filter,
606 bnxt_filter_info, next);
607 bnxt_hwrm_clear_filter(bp, filter);
608 filter->mac_index = INVALID_MAC_INDEX;
609 memset(&filter->l2_addr, 0,
610 ETHER_ADDR_LEN);
611 STAILQ_INSERT_TAIL(
612 &bp->free_filter_list,
613 filter, next);
614 }
615 filter = temp_filter;
616 }
617 }
618 }
619 }
620
621 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
622 struct ether_addr *mac_addr,
623 uint32_t index, uint32_t pool)
624 {
625 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
626 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
627 struct bnxt_filter_info *filter;
628
629 if (BNXT_VF(bp)) {
630 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
631 return -ENOTSUP;
632 }
633
634 if (!vnic) {
635 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
636 return -EINVAL;
637 }
638 /* Attach requested MAC address to the new l2_filter */
639 STAILQ_FOREACH(filter, &vnic->filter, next) {
640 if (filter->mac_index == index) {
641 RTE_LOG(ERR, PMD,
642 "MAC addr already existed for pool %d\n", pool);
643 return -EINVAL;
644 }
645 }
646 filter = bnxt_alloc_filter(bp);
647 if (!filter) {
648 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
649 return -ENODEV;
650 }
651 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
652 filter->mac_index = index;
653 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
654 return bnxt_hwrm_set_filter(bp, vnic, filter);
655 }
656
657 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
658 {
659 int rc = 0;
660 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
661 struct rte_eth_link new;
662 unsigned int cnt = BNXT_LINK_WAIT_CNT;
663
664 memset(&new, 0, sizeof(new));
665 do {
666 /* Retrieve link info from hardware */
667 rc = bnxt_get_hwrm_link_config(bp, &new);
668 if (rc) {
669 new.link_speed = ETH_LINK_SPEED_100M;
670 new.link_duplex = ETH_LINK_FULL_DUPLEX;
671 RTE_LOG(ERR, PMD,
672 "Failed to retrieve link rc = 0x%x!", rc);
673 goto out;
674 }
675 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
676
677 if (!wait_to_complete)
678 break;
679 } while (!new.link_status && cnt--);
680
681 out:
682 /* Timed out or success */
683 if (new.link_status != eth_dev->data->dev_link.link_status ||
684 new.link_speed != eth_dev->data->dev_link.link_speed) {
685 rte_bnxt_atomic_write_link_status(eth_dev, &new);
686 bnxt_print_link_info(eth_dev);
687 }
688
689 return rc;
690 }
691
692 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
693 {
694 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
695 struct bnxt_vnic_info *vnic;
696
697 if (bp->vnic_info == NULL)
698 return;
699
700 vnic = &bp->vnic_info[0];
701
702 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
703 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
704 }
705
706 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
707 {
708 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
709 struct bnxt_vnic_info *vnic;
710
711 if (bp->vnic_info == NULL)
712 return;
713
714 vnic = &bp->vnic_info[0];
715
716 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
717 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
718 }
719
720 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
721 {
722 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
723 struct bnxt_vnic_info *vnic;
724
725 if (bp->vnic_info == NULL)
726 return;
727
728 vnic = &bp->vnic_info[0];
729
730 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
731 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
732 }
733
734 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
735 {
736 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
737 struct bnxt_vnic_info *vnic;
738
739 if (bp->vnic_info == NULL)
740 return;
741
742 vnic = &bp->vnic_info[0];
743
744 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
745 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
746 }
747
748 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
749 struct rte_eth_rss_reta_entry64 *reta_conf,
750 uint16_t reta_size)
751 {
752 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
753 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
754 struct bnxt_vnic_info *vnic;
755 int i;
756
757 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
758 return -EINVAL;
759
760 if (reta_size != HW_HASH_INDEX_SIZE) {
761 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
762 "(%d) must equal the size supported by the hardware "
763 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
764 return -EINVAL;
765 }
766 /* Update the RSS VNIC(s) */
767 for (i = 0; i < MAX_FF_POOLS; i++) {
768 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
769 memcpy(vnic->rss_table, reta_conf, reta_size);
770
771 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
772 }
773 }
774 return 0;
775 }
776
777 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
778 struct rte_eth_rss_reta_entry64 *reta_conf,
779 uint16_t reta_size)
780 {
781 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
782 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
783 struct rte_intr_handle *intr_handle
784 = &bp->pdev->intr_handle;
785
786 /* Retrieve from the default VNIC */
787 if (!vnic)
788 return -EINVAL;
789 if (!vnic->rss_table)
790 return -EINVAL;
791
792 if (reta_size != HW_HASH_INDEX_SIZE) {
793 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
794 "(%d) must equal the size supported by the hardware "
795 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
796 return -EINVAL;
797 }
798 /* EW - need to revisit here copying from u64 to u16 */
799 memcpy(reta_conf, vnic->rss_table, reta_size);
800
801 if (rte_intr_allow_others(intr_handle)) {
802 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
803 bnxt_dev_lsc_intr_setup(eth_dev);
804 }
805
806 return 0;
807 }
808
809 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
810 struct rte_eth_rss_conf *rss_conf)
811 {
812 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
813 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
814 struct bnxt_vnic_info *vnic;
815 uint16_t hash_type = 0;
816 int i;
817
818 /*
819 * If RSS enablement were different than dev_configure,
820 * then return -EINVAL
821 */
822 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
823 if (!rss_conf->rss_hf)
824 return -EINVAL;
825 } else {
826 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
827 return -EINVAL;
828 }
829 if (rss_conf->rss_hf & ETH_RSS_IPV4)
830 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
831 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
832 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
833 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
834 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
835 if (rss_conf->rss_hf & ETH_RSS_IPV6)
836 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
837 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
838 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
839 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
840 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
841
842 /* Update the RSS VNIC(s) */
843 for (i = 0; i < MAX_FF_POOLS; i++) {
844 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
845 vnic->hash_type = hash_type;
846
847 /*
848 * Use the supplied key if the key length is
849 * acceptable and the rss_key is not NULL
850 */
851 if (rss_conf->rss_key &&
852 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
853 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
854 rss_conf->rss_key_len);
855
856 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
857 }
858 }
859 return 0;
860 }
861
862 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
863 struct rte_eth_rss_conf *rss_conf)
864 {
865 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
866 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
867 int len;
868 uint32_t hash_types;
869
870 /* RSS configuration is the same for all VNICs */
871 if (vnic && vnic->rss_hash_key) {
872 if (rss_conf->rss_key) {
873 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
874 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
875 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
876 }
877
878 hash_types = vnic->hash_type;
879 rss_conf->rss_hf = 0;
880 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
881 rss_conf->rss_hf |= ETH_RSS_IPV4;
882 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
883 }
884 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
885 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
886 hash_types &=
887 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
888 }
889 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
890 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
891 hash_types &=
892 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
893 }
894 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
895 rss_conf->rss_hf |= ETH_RSS_IPV6;
896 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
897 }
898 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
899 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
900 hash_types &=
901 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
902 }
903 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
904 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
905 hash_types &=
906 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
907 }
908 if (hash_types) {
909 RTE_LOG(ERR, PMD,
910 "Unknwon RSS config from firmware (%08x), RSS disabled",
911 vnic->hash_type);
912 return -ENOTSUP;
913 }
914 } else {
915 rss_conf->rss_hf = 0;
916 }
917 return 0;
918 }
919
920 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
921 struct rte_eth_fc_conf *fc_conf __rte_unused)
922 {
923 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
924 struct rte_eth_link link_info;
925 int rc;
926
927 rc = bnxt_get_hwrm_link_config(bp, &link_info);
928 if (rc)
929 return rc;
930
931 memset(fc_conf, 0, sizeof(*fc_conf));
932 if (bp->link_info.auto_pause)
933 fc_conf->autoneg = 1;
934 switch (bp->link_info.pause) {
935 case 0:
936 fc_conf->mode = RTE_FC_NONE;
937 break;
938 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
939 fc_conf->mode = RTE_FC_TX_PAUSE;
940 break;
941 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
942 fc_conf->mode = RTE_FC_RX_PAUSE;
943 break;
944 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
945 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
946 fc_conf->mode = RTE_FC_FULL;
947 break;
948 }
949 return 0;
950 }
951
952 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
953 struct rte_eth_fc_conf *fc_conf)
954 {
955 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
956
957 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
958 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
959 return -ENOTSUP;
960 }
961
962 switch (fc_conf->mode) {
963 case RTE_FC_NONE:
964 bp->link_info.auto_pause = 0;
965 bp->link_info.force_pause = 0;
966 break;
967 case RTE_FC_RX_PAUSE:
968 if (fc_conf->autoneg) {
969 bp->link_info.auto_pause =
970 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
971 bp->link_info.force_pause = 0;
972 } else {
973 bp->link_info.auto_pause = 0;
974 bp->link_info.force_pause =
975 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
976 }
977 break;
978 case RTE_FC_TX_PAUSE:
979 if (fc_conf->autoneg) {
980 bp->link_info.auto_pause =
981 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
982 bp->link_info.force_pause = 0;
983 } else {
984 bp->link_info.auto_pause = 0;
985 bp->link_info.force_pause =
986 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
987 }
988 break;
989 case RTE_FC_FULL:
990 if (fc_conf->autoneg) {
991 bp->link_info.auto_pause =
992 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
993 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
994 bp->link_info.force_pause = 0;
995 } else {
996 bp->link_info.auto_pause = 0;
997 bp->link_info.force_pause =
998 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
999 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1000 }
1001 break;
1002 }
1003 return bnxt_set_hwrm_link_config(bp, true);
1004 }
1005
1006 /*
1007 * Initialization
1008 */
1009
1010 static const struct eth_dev_ops bnxt_dev_ops = {
1011 .dev_infos_get = bnxt_dev_info_get_op,
1012 .dev_close = bnxt_dev_close_op,
1013 .dev_configure = bnxt_dev_configure_op,
1014 .dev_start = bnxt_dev_start_op,
1015 .dev_stop = bnxt_dev_stop_op,
1016 .dev_set_link_up = bnxt_dev_set_link_up_op,
1017 .dev_set_link_down = bnxt_dev_set_link_down_op,
1018 .stats_get = bnxt_stats_get_op,
1019 .stats_reset = bnxt_stats_reset_op,
1020 .rx_queue_setup = bnxt_rx_queue_setup_op,
1021 .rx_queue_release = bnxt_rx_queue_release_op,
1022 .tx_queue_setup = bnxt_tx_queue_setup_op,
1023 .tx_queue_release = bnxt_tx_queue_release_op,
1024 .reta_update = bnxt_reta_update_op,
1025 .reta_query = bnxt_reta_query_op,
1026 .rss_hash_update = bnxt_rss_hash_update_op,
1027 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
1028 .link_update = bnxt_link_update_op,
1029 .promiscuous_enable = bnxt_promiscuous_enable_op,
1030 .promiscuous_disable = bnxt_promiscuous_disable_op,
1031 .allmulticast_enable = bnxt_allmulticast_enable_op,
1032 .allmulticast_disable = bnxt_allmulticast_disable_op,
1033 .mac_addr_add = bnxt_mac_addr_add_op,
1034 .mac_addr_remove = bnxt_mac_addr_remove_op,
1035 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
1036 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
1037 };
1038
1039 static bool bnxt_vf_pciid(uint16_t id)
1040 {
1041 if (id == BROADCOM_DEV_ID_57304_VF ||
1042 id == BROADCOM_DEV_ID_57406_VF ||
1043 id == BROADCOM_DEV_ID_5731X_VF ||
1044 id == BROADCOM_DEV_ID_5741X_VF)
1045 return true;
1046 return false;
1047 }
1048
1049 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
1050 {
1051 struct bnxt *bp = eth_dev->data->dev_private;
1052 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1053 int rc;
1054
1055 /* enable device (incl. PCI PM wakeup), and bus-mastering */
1056 if (!pci_dev->mem_resource[0].addr) {
1057 RTE_LOG(ERR, PMD,
1058 "Cannot find PCI device base address, aborting\n");
1059 rc = -ENODEV;
1060 goto init_err_disable;
1061 }
1062
1063 bp->eth_dev = eth_dev;
1064 bp->pdev = pci_dev;
1065
1066 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
1067 if (!bp->bar0) {
1068 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
1069 rc = -ENOMEM;
1070 goto init_err_release;
1071 }
1072 return 0;
1073
1074 init_err_release:
1075 if (bp->bar0)
1076 bp->bar0 = NULL;
1077
1078 init_err_disable:
1079
1080 return rc;
1081 }
1082
1083 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
1084
1085 static int
1086 bnxt_dev_init(struct rte_eth_dev *eth_dev)
1087 {
1088 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1089 static int version_printed;
1090 struct bnxt *bp;
1091 int rc;
1092
1093 if (version_printed++ == 0)
1094 RTE_LOG(INFO, PMD, "%s", bnxt_version);
1095
1096 rte_eth_copy_pci_info(eth_dev, pci_dev);
1097 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1098
1099 bp = eth_dev->data->dev_private;
1100
1101 if (bnxt_vf_pciid(pci_dev->id.device_id))
1102 bp->flags |= BNXT_FLAG_VF;
1103
1104 rc = bnxt_init_board(eth_dev);
1105 if (rc) {
1106 RTE_LOG(ERR, PMD,
1107 "Board initialization failed rc: %x\n", rc);
1108 goto error;
1109 }
1110 eth_dev->dev_ops = &bnxt_dev_ops;
1111 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
1112 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
1113
1114 rc = bnxt_alloc_hwrm_resources(bp);
1115 if (rc) {
1116 RTE_LOG(ERR, PMD,
1117 "hwrm resource allocation failure rc: %x\n", rc);
1118 goto error_free;
1119 }
1120 rc = bnxt_hwrm_ver_get(bp);
1121 if (rc)
1122 goto error_free;
1123 bnxt_hwrm_queue_qportcfg(bp);
1124
1125 bnxt_hwrm_func_qcfg(bp);
1126
1127 /* Get the MAX capabilities for this function */
1128 rc = bnxt_hwrm_func_qcaps(bp);
1129 if (rc) {
1130 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
1131 goto error_free;
1132 }
1133 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
1134 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
1135 if (eth_dev->data->mac_addrs == NULL) {
1136 RTE_LOG(ERR, PMD,
1137 "Failed to alloc %u bytes needed to store MAC addr tbl",
1138 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
1139 rc = -ENOMEM;
1140 goto error_free;
1141 }
1142 /* Copy the permanent MAC from the qcap response address now. */
1143 if (BNXT_PF(bp))
1144 memcpy(bp->mac_addr, bp->pf.mac_addr, sizeof(bp->mac_addr));
1145 else
1146 memcpy(bp->mac_addr, bp->vf.mac_addr, sizeof(bp->mac_addr));
1147 memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1148 bp->grp_info = rte_zmalloc("bnxt_grp_info",
1149 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
1150 if (!bp->grp_info) {
1151 RTE_LOG(ERR, PMD,
1152 "Failed to alloc %zu bytes needed to store group info table\n",
1153 sizeof(*bp->grp_info) * bp->max_ring_grps);
1154 rc = -ENOMEM;
1155 goto error_free;
1156 }
1157
1158 rc = bnxt_hwrm_func_driver_register(bp, 0,
1159 bp->pf.vf_req_fwd);
1160 if (rc) {
1161 RTE_LOG(ERR, PMD,
1162 "Failed to register driver");
1163 rc = -EBUSY;
1164 goto error_free;
1165 }
1166
1167 RTE_LOG(INFO, PMD,
1168 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
1169 pci_dev->mem_resource[0].phys_addr,
1170 pci_dev->mem_resource[0].addr);
1171
1172 bp->dev_stopped = 0;
1173
1174 return 0;
1175
1176 error_free:
1177 bnxt_dev_uninit(eth_dev);
1178 error:
1179 return rc;
1180 }
1181
1182 static int
1183 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
1184 struct bnxt *bp = eth_dev->data->dev_private;
1185 int rc;
1186
1187 if (eth_dev->data->mac_addrs != NULL) {
1188 rte_free(eth_dev->data->mac_addrs);
1189 eth_dev->data->mac_addrs = NULL;
1190 }
1191 if (bp->grp_info != NULL) {
1192 rte_free(bp->grp_info);
1193 bp->grp_info = NULL;
1194 }
1195 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
1196 bnxt_free_hwrm_resources(bp);
1197 if (bp->dev_stopped == 0)
1198 bnxt_dev_close_op(eth_dev);
1199 eth_dev->dev_ops = NULL;
1200 eth_dev->rx_pkt_burst = NULL;
1201 eth_dev->tx_pkt_burst = NULL;
1202
1203 return rc;
1204 }
1205
1206 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1207 struct rte_pci_device *pci_dev)
1208 {
1209 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
1210 bnxt_dev_init);
1211 }
1212
1213 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
1214 {
1215 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
1216 }
1217
1218 static struct rte_pci_driver bnxt_rte_pmd = {
1219 .id_table = bnxt_pci_id_map,
1220 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
1221 RTE_PCI_DRV_INTR_LSC,
1222 .probe = bnxt_pci_probe,
1223 .remove = bnxt_pci_remove,
1224 };
1225
1226 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
1227 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
1228 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio");
Ceph