ceph/src/seastar/dpdk/drivers/net/e1000/base/e1000_82542.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /*
  35  * 82542 Gigabit Ethernet Controller
  36  */
  37
  38 #include "e1000_api.h"
  39
  40 STATIC s32  e1000_init_phy_params_82542(struct e1000_hw *hw);
  41 STATIC s32  e1000_init_nvm_params_82542(struct e1000_hw *hw);
  42 STATIC s32  e1000_init_mac_params_82542(struct e1000_hw *hw);
  43 STATIC s32  e1000_get_bus_info_82542(struct e1000_hw *hw);
  44 STATIC s32  e1000_reset_hw_82542(struct e1000_hw *hw);
  45 STATIC s32  e1000_init_hw_82542(struct e1000_hw *hw);
  46 STATIC s32  e1000_setup_link_82542(struct e1000_hw *hw);
  47 STATIC s32  e1000_led_on_82542(struct e1000_hw *hw);
  48 STATIC s32  e1000_led_off_82542(struct e1000_hw *hw);
  49 STATIC int  e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);
  50 STATIC void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);
  51 STATIC s32  e1000_read_mac_addr_82542(struct e1000_hw *hw);
  52
  53 /**
  54  *  e1000_init_phy_params_82542 - Init PHY func ptrs.
  55  *  @hw: pointer to the HW structure
  56  **/
  57 STATIC s32 e1000_init_phy_params_82542(struct e1000_hw *hw)
  58 {
  59         struct e1000_phy_info *phy = &hw->phy;
  60         s32 ret_val = E1000_SUCCESS;
  61
  62         DEBUGFUNC("e1000_init_phy_params_82542");
  63
  64         phy->type = e1000_phy_none;
  65
  66         return ret_val;
  67 }
  68
  69 /**
  70  *  e1000_init_nvm_params_82542 - Init NVM func ptrs.
  71  *  @hw: pointer to the HW structure
  72  **/
  73 STATIC s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)
  74 {
  75         struct e1000_nvm_info *nvm = &hw->nvm;
  76
  77         DEBUGFUNC("e1000_init_nvm_params_82542");
  78
  79         nvm->address_bits       =  6;
  80         nvm->delay_usec         = 50;
  81         nvm->opcode_bits        =  3;
  82         nvm->type               = e1000_nvm_eeprom_microwire;
  83         nvm->word_size          = 64;
  84
  85         /* Function Pointers */
  86         nvm->ops.read           = e1000_read_nvm_microwire;
  87         nvm->ops.release        = e1000_stop_nvm;
  88         nvm->ops.write          = e1000_write_nvm_microwire;
  89         nvm->ops.update         = e1000_update_nvm_checksum_generic;
  90         nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
  91
  92         return E1000_SUCCESS;
  93 }
  94
  95 /**
  96  *  e1000_init_mac_params_82542 - Init MAC func ptrs.
  97  *  @hw: pointer to the HW structure
  98  **/
  99 STATIC s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
 100 {
 101         struct e1000_mac_info *mac = &hw->mac;
 102
 103         DEBUGFUNC("e1000_init_mac_params_82542");
 104
 105         /* Set media type */
 106         hw->phy.media_type = e1000_media_type_fiber;
 107
 108         /* Set mta register count */
 109         mac->mta_reg_count = 128;
 110         /* Set rar entry count */
 111         mac->rar_entry_count = E1000_RAR_ENTRIES;
 112
 113         /* Function pointers */
 114
 115         /* bus type/speed/width */
 116         mac->ops.get_bus_info = e1000_get_bus_info_82542;
 117         /* function id */
 118         mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
 119         /* reset */
 120         mac->ops.reset_hw = e1000_reset_hw_82542;
 121         /* hw initialization */
 122         mac->ops.init_hw = e1000_init_hw_82542;
 123         /* link setup */
 124         mac->ops.setup_link = e1000_setup_link_82542;
 125         /* phy/fiber/serdes setup */
 126         mac->ops.setup_physical_interface =
 127                                         e1000_setup_fiber_serdes_link_generic;
 128         /* check for link */
 129         mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 130         /* multicast address update */
 131         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 132         /* writing VFTA */
 133         mac->ops.write_vfta = e1000_write_vfta_generic;
 134         /* clearing VFTA */
 135         mac->ops.clear_vfta = e1000_clear_vfta_generic;
 136         /* read mac address */
 137         mac->ops.read_mac_addr = e1000_read_mac_addr_82542;
 138         /* set RAR */
 139         mac->ops.rar_set = e1000_rar_set_82542;
 140         /* turn on/off LED */
 141         mac->ops.led_on = e1000_led_on_82542;
 142         mac->ops.led_off = e1000_led_off_82542;
 143         /* clear hardware counters */
 144         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542;
 145         /* link info */
 146         mac->ops.get_link_up_info =
 147                                 e1000_get_speed_and_duplex_fiber_serdes_generic;
 148
 149         return E1000_SUCCESS;
 150 }
 151
 152 /**
 153  *  e1000_init_function_pointers_82542 - Init func ptrs.
 154  *  @hw: pointer to the HW structure
 155  *
 156  *  Called to initialize all function pointers and parameters.
 157  **/
 158 void e1000_init_function_pointers_82542(struct e1000_hw *hw)
 159 {
 160         DEBUGFUNC("e1000_init_function_pointers_82542");
 161
 162         hw->mac.ops.init_params = e1000_init_mac_params_82542;
 163         hw->nvm.ops.init_params = e1000_init_nvm_params_82542;
 164         hw->phy.ops.init_params = e1000_init_phy_params_82542;
 165 }
 166
 167 /**
 168  *  e1000_get_bus_info_82542 - Obtain bus information for adapter
 169  *  @hw: pointer to the HW structure
 170  *
 171  *  This will obtain information about the HW bus for which the
 172  *  adapter is attached and stores it in the hw structure.
 173  **/
 174 STATIC s32 e1000_get_bus_info_82542(struct e1000_hw *hw)
 175 {
 176         DEBUGFUNC("e1000_get_bus_info_82542");
 177
 178         hw->bus.type = e1000_bus_type_pci;
 179         hw->bus.speed = e1000_bus_speed_unknown;
 180         hw->bus.width = e1000_bus_width_unknown;
 181
 182         return E1000_SUCCESS;
 183 }
 184
 185 /**
 186  *  e1000_reset_hw_82542 - Reset hardware
 187  *  @hw: pointer to the HW structure
 188  *
 189  *  This resets the hardware into a known state.
 190  **/
 191 STATIC s32 e1000_reset_hw_82542(struct e1000_hw *hw)
 192 {
 193         struct e1000_bus_info *bus = &hw->bus;
 194         s32 ret_val = E1000_SUCCESS;
 195         u32 ctrl;
 196
 197         DEBUGFUNC("e1000_reset_hw_82542");
 198
 199         if (hw->revision_id == E1000_REVISION_2) {
 200                 DEBUGOUT("Disabling MWI on 82542 rev 2\n");
 201                 e1000_pci_clear_mwi(hw);
 202         }
 203
 204         DEBUGOUT("Masking off all interrupts\n");
 205         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 206
 207         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 208         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 209         E1000_WRITE_FLUSH(hw);
 210
 211         /*
 212          * Delay to allow any outstanding PCI transactions to complete before
 213          * resetting the device
 214          */
 215         msec_delay(10);
 216
 217         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 218
 219         DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n");
 220         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 221
 222         hw->nvm.ops.reload(hw);
 223         msec_delay(2);
 224
 225         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 226         E1000_READ_REG(hw, E1000_ICR);
 227
 228         if (hw->revision_id == E1000_REVISION_2) {
 229                 if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
 230                         e1000_pci_set_mwi(hw);
 231         }
 232
 233         return ret_val;
 234 }
 235
 236 /**
 237  *  e1000_init_hw_82542 - Initialize hardware
 238  *  @hw: pointer to the HW structure
 239  *
 240  *  This inits the hardware readying it for operation.
 241  **/
 242 STATIC s32 e1000_init_hw_82542(struct e1000_hw *hw)
 243 {
 244         struct e1000_mac_info *mac = &hw->mac;
 245         struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542;
 246         s32 ret_val = E1000_SUCCESS;
 247         u32 ctrl;
 248         u16 i;
 249
 250         DEBUGFUNC("e1000_init_hw_82542");
 251
 252         /* Disabling VLAN filtering */
 253         E1000_WRITE_REG(hw, E1000_VET, 0);
 254         mac->ops.clear_vfta(hw);
 255
 256         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
 257         if (hw->revision_id == E1000_REVISION_2) {
 258                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
 259                 e1000_pci_clear_mwi(hw);
 260                 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
 261                 E1000_WRITE_FLUSH(hw);
 262                 msec_delay(5);
 263         }
 264
 265         /* Setup the receive address. */
 266         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
 267
 268         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
 269         if (hw->revision_id == E1000_REVISION_2) {
 270                 E1000_WRITE_REG(hw, E1000_RCTL, 0);
 271                 E1000_WRITE_FLUSH(hw);
 272                 msec_delay(1);
 273                 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
 274                         e1000_pci_set_mwi(hw);
 275         }
 276
 277         /* Zero out the Multicast HASH table */
 278         DEBUGOUT("Zeroing the MTA\n");
 279         for (i = 0; i < mac->mta_reg_count; i++)
 280                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 281
 282         /*
 283          * Set the PCI priority bit correctly in the CTRL register.  This
 284          * determines if the adapter gives priority to receives, or if it
 285          * gives equal priority to transmits and receives.
 286          */
 287         if (dev_spec->dma_fairness) {
 288                 ctrl = E1000_READ_REG(hw, E1000_CTRL);
 289                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
 290         }
 291
 292         /* Setup link and flow control */
 293         ret_val = e1000_setup_link_82542(hw);
 294
 295         /*
 296          * Clear all of the statistics registers (clear on read).  It is
 297          * important that we do this after we have tried to establish link
 298          * because the symbol error count will increment wildly if there
 299          * is no link.
 300          */
 301         e1000_clear_hw_cntrs_82542(hw);
 302
 303         return ret_val;
 304 }
 305
 306 /**
 307  *  e1000_setup_link_82542 - Setup flow control and link settings
 308  *  @hw: pointer to the HW structure
 309  *
 310  *  Determines which flow control settings to use, then configures flow
 311  *  control.  Calls the appropriate media-specific link configuration
 312  *  function.  Assuming the adapter has a valid link partner, a valid link
 313  *  should be established.  Assumes the hardware has previously been reset
 314  *  and the transmitter and receiver are not enabled.
 315  **/
 316 STATIC s32 e1000_setup_link_82542(struct e1000_hw *hw)
 317 {
 318         struct e1000_mac_info *mac = &hw->mac;
 319         s32 ret_val;
 320
 321         DEBUGFUNC("e1000_setup_link_82542");
 322
 323         ret_val = e1000_set_default_fc_generic(hw);
 324         if (ret_val)
 325                 goto out;
 326
 327         hw->fc.requested_mode &= ~e1000_fc_tx_pause;
 328
 329         if (mac->report_tx_early)
 330                 hw->fc.requested_mode &= ~e1000_fc_rx_pause;
 331
 332         /*
 333          * Save off the requested flow control mode for use later.  Depending
 334          * on the link partner's capabilities, we may or may not use this mode.
 335          */
 336         hw->fc.current_mode = hw->fc.requested_mode;
 337
 338         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
 339                   hw->fc.current_mode);
 340
 341         /* Call the necessary subroutine to configure the link. */
 342         ret_val = mac->ops.setup_physical_interface(hw);
 343         if (ret_val)
 344                 goto out;
 345
 346         /*
 347          * Initialize the flow control address, type, and PAUSE timer
 348          * registers to their default values.  This is done even if flow
 349          * control is disabled, because it does not hurt anything to
 350          * initialize these registers.
 351          */
 352         DEBUGOUT("Initializing Flow Control address, type and timer regs\n");
 353
 354         E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
 355         E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
 356         E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
 357
 358         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
 359
 360         ret_val = e1000_set_fc_watermarks_generic(hw);
 361
 362 out:
 363         return ret_val;
 364 }
 365
 366 /**
 367  *  e1000_led_on_82542 - Turn on SW controllable LED
 368  *  @hw: pointer to the HW structure
 369  *
 370  *  Turns the SW defined LED on.
 371  **/
 372 STATIC s32 e1000_led_on_82542(struct e1000_hw *hw)
 373 {
 374         u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
 375
 376         DEBUGFUNC("e1000_led_on_82542");
 377
 378         ctrl |= E1000_CTRL_SWDPIN0;
 379         ctrl |= E1000_CTRL_SWDPIO0;
 380         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 381
 382         return E1000_SUCCESS;
 383 }
 384
 385 /**
 386  *  e1000_led_off_82542 - Turn off SW controllable LED
 387  *  @hw: pointer to the HW structure
 388  *
 389  *  Turns the SW defined LED off.
 390  **/
 391 STATIC s32 e1000_led_off_82542(struct e1000_hw *hw)
 392 {
 393         u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
 394
 395         DEBUGFUNC("e1000_led_off_82542");
 396
 397         ctrl &= ~E1000_CTRL_SWDPIN0;
 398         ctrl |= E1000_CTRL_SWDPIO0;
 399         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 400
 401         return E1000_SUCCESS;
 402 }
 403
 404 /**
 405  *  e1000_rar_set_82542 - Set receive address register
 406  *  @hw: pointer to the HW structure
 407  *  @addr: pointer to the receive address
 408  *  @index: receive address array register
 409  *
 410  *  Sets the receive address array register at index to the address passed
 411  *  in by addr.
 412  **/
 413 STATIC int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
 414 {
 415         u32 rar_low, rar_high;
 416
 417         DEBUGFUNC("e1000_rar_set_82542");
 418
 419         /*
 420          * HW expects these in little endian so we reverse the byte order
 421          * from network order (big endian) to little endian
 422          */
 423         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
 424                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 425
 426         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
 427
 428         /* If MAC address zero, no need to set the AV bit */
 429         if (rar_low || rar_high)
 430                 rar_high |= E1000_RAH_AV;
 431
 432         E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
 433         E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
 434
 435         return E1000_SUCCESS;
 436 }
 437
 438 /**
 439  *  e1000_translate_register_82542 - Translate the proper register offset
 440  *  @reg: e1000 register to be read
 441  *
 442  *  Registers in 82542 are located in different offsets than other adapters
 443  *  even though they function in the same manner.  This function takes in
 444  *  the name of the register to read and returns the correct offset for
 445  *  82542 silicon.
 446  **/
 447 u32 e1000_translate_register_82542(u32 reg)
 448 {
 449         /*
 450          * Some of the 82542 registers are located at different
 451          * offsets than they are in newer adapters.
 452          * Despite the difference in location, the registers
 453          * function in the same manner.
 454          */
 455         switch (reg) {
 456         case E1000_RA:
 457                 reg = 0x00040;
 458                 break;
 459         case E1000_RDTR:
 460                 reg = 0x00108;
 461                 break;
 462         case E1000_RDBAL(0):
 463                 reg = 0x00110;
 464                 break;
 465         case E1000_RDBAH(0):
 466                 reg = 0x00114;
 467                 break;
 468         case E1000_RDLEN(0):
 469                 reg = 0x00118;
 470                 break;
 471         case E1000_RDH(0):
 472                 reg = 0x00120;
 473                 break;
 474         case E1000_RDT(0):
 475                 reg = 0x00128;
 476                 break;
 477         case E1000_RDBAL(1):
 478                 reg = 0x00138;
 479                 break;
 480         case E1000_RDBAH(1):
 481                 reg = 0x0013C;
 482                 break;
 483         case E1000_RDLEN(1):
 484                 reg = 0x00140;
 485                 break;
 486         case E1000_RDH(1):
 487                 reg = 0x00148;
 488                 break;
 489         case E1000_RDT(1):
 490                 reg = 0x00150;
 491                 break;
 492         case E1000_FCRTH:
 493                 reg = 0x00160;
 494                 break;
 495         case E1000_FCRTL:
 496                 reg = 0x00168;
 497                 break;
 498         case E1000_MTA:
 499                 reg = 0x00200;
 500                 break;
 501         case E1000_TDBAL(0):
 502                 reg = 0x00420;
 503                 break;
 504         case E1000_TDBAH(0):
 505                 reg = 0x00424;
 506                 break;
 507         case E1000_TDLEN(0):
 508                 reg = 0x00428;
 509                 break;
 510         case E1000_TDH(0):
 511                 reg = 0x00430;
 512                 break;
 513         case E1000_TDT(0):
 514                 reg = 0x00438;
 515                 break;
 516         case E1000_TIDV:
 517                 reg = 0x00440;
 518                 break;
 519         case E1000_VFTA:
 520                 reg = 0x00600;
 521                 break;
 522         case E1000_TDFH:
 523                 reg = 0x08010;
 524                 break;
 525         case E1000_TDFT:
 526                 reg = 0x08018;
 527                 break;
 528         default:
 529                 break;
 530         }
 531
 532         return reg;
 533 }
 534
 535 /**
 536  *  e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters
 537  *  @hw: pointer to the HW structure
 538  *
 539  *  Clears the hardware counters by reading the counter registers.
 540  **/
 541 STATIC void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
 542 {
 543         DEBUGFUNC("e1000_clear_hw_cntrs_82542");
 544
 545         e1000_clear_hw_cntrs_base_generic(hw);
 546
 547         E1000_READ_REG(hw, E1000_PRC64);
 548         E1000_READ_REG(hw, E1000_PRC127);
 549         E1000_READ_REG(hw, E1000_PRC255);
 550         E1000_READ_REG(hw, E1000_PRC511);
 551         E1000_READ_REG(hw, E1000_PRC1023);
 552         E1000_READ_REG(hw, E1000_PRC1522);
 553         E1000_READ_REG(hw, E1000_PTC64);
 554         E1000_READ_REG(hw, E1000_PTC127);
 555         E1000_READ_REG(hw, E1000_PTC255);
 556         E1000_READ_REG(hw, E1000_PTC511);
 557         E1000_READ_REG(hw, E1000_PTC1023);
 558         E1000_READ_REG(hw, E1000_PTC1522);
 559 }
 560
 561 /**
 562  *  e1000_read_mac_addr_82542 - Read device MAC address
 563  *  @hw: pointer to the HW structure
 564  *
 565  *  Reads the device MAC address from the EEPROM and stores the value.
 566  **/
 567 s32 e1000_read_mac_addr_82542(struct e1000_hw *hw)
 568 {
 569         s32  ret_val = E1000_SUCCESS;
 570         u16 offset, nvm_data, i;
 571
 572         DEBUGFUNC("e1000_read_mac_addr");
 573
 574         for (i = 0; i < ETH_ADDR_LEN; i += 2) {
 575                 offset = i >> 1;
 576                 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
 577                 if (ret_val) {
 578                         DEBUGOUT("NVM Read Error\n");
 579                         goto out;
 580                 }
 581                 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
 582                 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
 583         }
 584
 585         for (i = 0; i < ETH_ADDR_LEN; i++)
 586                 hw->mac.addr[i] = hw->mac.perm_addr[i];
 587
 588 out:
 589         return ret_val;
 590 }