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[ceph.git] / ceph / src / seastar / dpdk / drivers / net / e1000 / em_ethdev.c
1 /*-
2 * BSD LICENSE
3 *
4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/queue.h>
35 #include <stdio.h>
36 #include <errno.h>
37 #include <stdint.h>
38 #include <stdarg.h>
39
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
43 #include <rte_log.h>
44 #include <rte_debug.h>
45 #include <rte_pci.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memory.h>
50 #include <rte_memzone.h>
51 #include <rte_eal.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
54 #include <rte_dev.h>
55
56 #include "e1000_logs.h"
57 #include "base/e1000_api.h"
58 #include "e1000_ethdev.h"
59
60 #define EM_EIAC 0x000DC
61
62 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
63
64
65 static int eth_em_configure(struct rte_eth_dev *dev);
66 static int eth_em_start(struct rte_eth_dev *dev);
67 static void eth_em_stop(struct rte_eth_dev *dev);
68 static void eth_em_close(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
70 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
72 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
73 static int eth_em_link_update(struct rte_eth_dev *dev,
74 int wait_to_complete);
75 static void eth_em_stats_get(struct rte_eth_dev *dev,
76 struct rte_eth_stats *rte_stats);
77 static void eth_em_stats_reset(struct rte_eth_dev *dev);
78 static void eth_em_infos_get(struct rte_eth_dev *dev,
79 struct rte_eth_dev_info *dev_info);
80 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
81 struct rte_eth_fc_conf *fc_conf);
82 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
83 struct rte_eth_fc_conf *fc_conf);
84 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
85 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
86 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
87 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
88 struct rte_intr_handle *handle);
89 static void eth_em_interrupt_handler(void *param);
90
91 static int em_hw_init(struct e1000_hw *hw);
92 static int em_hardware_init(struct e1000_hw *hw);
93 static void em_hw_control_acquire(struct e1000_hw *hw);
94 static void em_hw_control_release(struct e1000_hw *hw);
95 static void em_init_manageability(struct e1000_hw *hw);
96 static void em_release_manageability(struct e1000_hw *hw);
97
98 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
99
100 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
101 uint16_t vlan_id, int on);
102 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
103 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
105 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
106 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
107
108 /*
109 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
110 uint16_t vlan_id, int on);
111 */
112
113 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
114 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
115 static void em_lsc_intr_disable(struct e1000_hw *hw);
116 static void em_rxq_intr_enable(struct e1000_hw *hw);
117 static void em_rxq_intr_disable(struct e1000_hw *hw);
118
119 static int eth_em_led_on(struct rte_eth_dev *dev);
120 static int eth_em_led_off(struct rte_eth_dev *dev);
121
122 static int em_get_rx_buffer_size(struct e1000_hw *hw);
123 static int eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
124 uint32_t index, uint32_t pool);
125 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
126
127 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
128 struct ether_addr *mc_addr_set,
129 uint32_t nb_mc_addr);
130
131 #define EM_FC_PAUSE_TIME 0x0680
132 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
133 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
134
135 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
136
137 /*
138 * The set of PCI devices this driver supports
139 */
140 static const struct rte_pci_id pci_id_em_map[] = {
141 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
142 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
143 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
144 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
145 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
146 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
147 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
148 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
149 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
150 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
151 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
152 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
153 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
154 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
155 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
156 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
157 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
158 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
159 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
160 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
161 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
162 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
163 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
164 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
165 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
166 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
167 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
168 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
169 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
170 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
171 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
172 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
173 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
174 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
175 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
176 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
177 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
178 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
179 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
180 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
181 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
182 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
183 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
184 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
185 { .vendor_id = 0, /* sentinel */ },
186 };
187
188 static const struct eth_dev_ops eth_em_ops = {
189 .dev_configure = eth_em_configure,
190 .dev_start = eth_em_start,
191 .dev_stop = eth_em_stop,
192 .dev_close = eth_em_close,
193 .promiscuous_enable = eth_em_promiscuous_enable,
194 .promiscuous_disable = eth_em_promiscuous_disable,
195 .allmulticast_enable = eth_em_allmulticast_enable,
196 .allmulticast_disable = eth_em_allmulticast_disable,
197 .link_update = eth_em_link_update,
198 .stats_get = eth_em_stats_get,
199 .stats_reset = eth_em_stats_reset,
200 .dev_infos_get = eth_em_infos_get,
201 .mtu_set = eth_em_mtu_set,
202 .vlan_filter_set = eth_em_vlan_filter_set,
203 .vlan_offload_set = eth_em_vlan_offload_set,
204 .rx_queue_setup = eth_em_rx_queue_setup,
205 .rx_queue_release = eth_em_rx_queue_release,
206 .rx_queue_count = eth_em_rx_queue_count,
207 .rx_descriptor_done = eth_em_rx_descriptor_done,
208 .rx_descriptor_status = eth_em_rx_descriptor_status,
209 .tx_descriptor_status = eth_em_tx_descriptor_status,
210 .tx_queue_setup = eth_em_tx_queue_setup,
211 .tx_queue_release = eth_em_tx_queue_release,
212 .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
213 .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
214 .dev_led_on = eth_em_led_on,
215 .dev_led_off = eth_em_led_off,
216 .flow_ctrl_get = eth_em_flow_ctrl_get,
217 .flow_ctrl_set = eth_em_flow_ctrl_set,
218 .mac_addr_add = eth_em_rar_set,
219 .mac_addr_remove = eth_em_rar_clear,
220 .set_mc_addr_list = eth_em_set_mc_addr_list,
221 .rxq_info_get = em_rxq_info_get,
222 .txq_info_get = em_txq_info_get,
223 };
224
225 /**
226 * Atomically reads the link status information from global
227 * structure rte_eth_dev.
228 *
229 * @param dev
230 * - Pointer to the structure rte_eth_dev to read from.
231 * - Pointer to the buffer to be saved with the link status.
232 *
233 * @return
234 * - On success, zero.
235 * - On failure, negative value.
236 */
237 static inline int
238 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
239 struct rte_eth_link *link)
240 {
241 struct rte_eth_link *dst = link;
242 struct rte_eth_link *src = &(dev->data->dev_link);
243
244 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
245 *(uint64_t *)src) == 0)
246 return -1;
247
248 return 0;
249 }
250
251 /**
252 * Atomically writes the link status information into global
253 * structure rte_eth_dev.
254 *
255 * @param dev
256 * - Pointer to the structure rte_eth_dev to read from.
257 * - Pointer to the buffer to be saved with the link status.
258 *
259 * @return
260 * - On success, zero.
261 * - On failure, negative value.
262 */
263 static inline int
264 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
265 struct rte_eth_link *link)
266 {
267 struct rte_eth_link *dst = &(dev->data->dev_link);
268 struct rte_eth_link *src = link;
269
270 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
271 *(uint64_t *)src) == 0)
272 return -1;
273
274 return 0;
275 }
276
277 /**
278 * eth_em_dev_is_ich8 - Check for ICH8 device
279 * @hw: pointer to the HW structure
280 *
281 * return TRUE for ICH8, otherwise FALSE
282 **/
283 static bool
284 eth_em_dev_is_ich8(struct e1000_hw *hw)
285 {
286 DEBUGFUNC("eth_em_dev_is_ich8");
287
288 switch (hw->device_id) {
289 case E1000_DEV_ID_PCH_LPT_I217_LM:
290 case E1000_DEV_ID_PCH_LPT_I217_V:
291 case E1000_DEV_ID_PCH_LPTLP_I218_LM:
292 case E1000_DEV_ID_PCH_LPTLP_I218_V:
293 case E1000_DEV_ID_PCH_I218_V2:
294 case E1000_DEV_ID_PCH_I218_LM2:
295 case E1000_DEV_ID_PCH_I218_V3:
296 case E1000_DEV_ID_PCH_I218_LM3:
297 case E1000_DEV_ID_PCH_SPT_I219_LM:
298 case E1000_DEV_ID_PCH_SPT_I219_V:
299 case E1000_DEV_ID_PCH_SPT_I219_LM2:
300 case E1000_DEV_ID_PCH_SPT_I219_V2:
301 case E1000_DEV_ID_PCH_LBG_I219_LM3:
302 case E1000_DEV_ID_PCH_SPT_I219_LM4:
303 case E1000_DEV_ID_PCH_SPT_I219_V4:
304 case E1000_DEV_ID_PCH_SPT_I219_LM5:
305 case E1000_DEV_ID_PCH_SPT_I219_V5:
306 case E1000_DEV_ID_PCH_CNP_I219_LM6:
307 case E1000_DEV_ID_PCH_CNP_I219_V6:
308 case E1000_DEV_ID_PCH_CNP_I219_LM7:
309 case E1000_DEV_ID_PCH_CNP_I219_V7:
310 return 1;
311 default:
312 return 0;
313 }
314 }
315
316 static int
317 eth_em_dev_init(struct rte_eth_dev *eth_dev)
318 {
319 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
320 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
321 struct e1000_adapter *adapter =
322 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
323 struct e1000_hw *hw =
324 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
325 struct e1000_vfta * shadow_vfta =
326 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
327
328 eth_dev->dev_ops = &eth_em_ops;
329 eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
330 eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
331 eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
332
333 /* for secondary processes, we don't initialise any further as primary
334 * has already done this work. Only check we don't need a different
335 * RX function */
336 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
337 if (eth_dev->data->scattered_rx)
338 eth_dev->rx_pkt_burst =
339 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
340 return 0;
341 }
342
343 rte_eth_copy_pci_info(eth_dev, pci_dev);
344 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
345
346 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
347 hw->device_id = pci_dev->id.device_id;
348 adapter->stopped = 0;
349
350 /* For ICH8 support we'll need to map the flash memory BAR */
351 if (eth_em_dev_is_ich8(hw))
352 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
353
354 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
355 em_hw_init(hw) != 0) {
356 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
357 "failed to init HW",
358 eth_dev->data->port_id, pci_dev->id.vendor_id,
359 pci_dev->id.device_id);
360 return -ENODEV;
361 }
362
363 /* Allocate memory for storing MAC addresses */
364 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
365 hw->mac.rar_entry_count, 0);
366 if (eth_dev->data->mac_addrs == NULL) {
367 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
368 "store MAC addresses",
369 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
370 return -ENOMEM;
371 }
372
373 /* Copy the permanent MAC address */
374 ether_addr_copy((struct ether_addr *) hw->mac.addr,
375 eth_dev->data->mac_addrs);
376
377 /* initialize the vfta */
378 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
379
380 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
381 eth_dev->data->port_id, pci_dev->id.vendor_id,
382 pci_dev->id.device_id);
383
384 rte_intr_callback_register(intr_handle,
385 eth_em_interrupt_handler, eth_dev);
386
387 return 0;
388 }
389
390 static int
391 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
392 {
393 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
394 struct e1000_adapter *adapter =
395 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
396 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
397
398 PMD_INIT_FUNC_TRACE();
399
400 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
401 return -EPERM;
402
403 if (adapter->stopped == 0)
404 eth_em_close(eth_dev);
405
406 eth_dev->dev_ops = NULL;
407 eth_dev->rx_pkt_burst = NULL;
408 eth_dev->tx_pkt_burst = NULL;
409
410 rte_free(eth_dev->data->mac_addrs);
411 eth_dev->data->mac_addrs = NULL;
412
413 /* disable uio intr before callback unregister */
414 rte_intr_disable(intr_handle);
415 rte_intr_callback_unregister(intr_handle,
416 eth_em_interrupt_handler, eth_dev);
417
418 return 0;
419 }
420
421 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
422 struct rte_pci_device *pci_dev)
423 {
424 return rte_eth_dev_pci_generic_probe(pci_dev,
425 sizeof(struct e1000_adapter), eth_em_dev_init);
426 }
427
428 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
429 {
430 return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
431 }
432
433 static struct rte_pci_driver rte_em_pmd = {
434 .id_table = pci_id_em_map,
435 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
436 .probe = eth_em_pci_probe,
437 .remove = eth_em_pci_remove,
438 };
439
440 static int
441 em_hw_init(struct e1000_hw *hw)
442 {
443 int diag;
444
445 diag = hw->mac.ops.init_params(hw);
446 if (diag != 0) {
447 PMD_INIT_LOG(ERR, "MAC Initialization Error");
448 return diag;
449 }
450 diag = hw->nvm.ops.init_params(hw);
451 if (diag != 0) {
452 PMD_INIT_LOG(ERR, "NVM Initialization Error");
453 return diag;
454 }
455 diag = hw->phy.ops.init_params(hw);
456 if (diag != 0) {
457 PMD_INIT_LOG(ERR, "PHY Initialization Error");
458 return diag;
459 }
460 (void) e1000_get_bus_info(hw);
461
462 hw->mac.autoneg = 1;
463 hw->phy.autoneg_wait_to_complete = 0;
464 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
465
466 e1000_init_script_state_82541(hw, TRUE);
467 e1000_set_tbi_compatibility_82543(hw, TRUE);
468
469 /* Copper options */
470 if (hw->phy.media_type == e1000_media_type_copper) {
471 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
472 hw->phy.disable_polarity_correction = 0;
473 hw->phy.ms_type = e1000_ms_hw_default;
474 }
475
476 /*
477 * Start from a known state, this is important in reading the nvm
478 * and mac from that.
479 */
480 e1000_reset_hw(hw);
481
482 /* Make sure we have a good EEPROM before we read from it */
483 if (e1000_validate_nvm_checksum(hw) < 0) {
484 /*
485 * Some PCI-E parts fail the first check due to
486 * the link being in sleep state, call it again,
487 * if it fails a second time its a real issue.
488 */
489 diag = e1000_validate_nvm_checksum(hw);
490 if (diag < 0) {
491 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
492 goto error;
493 }
494 }
495
496 /* Read the permanent MAC address out of the EEPROM */
497 diag = e1000_read_mac_addr(hw);
498 if (diag != 0) {
499 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
500 goto error;
501 }
502
503 /* Now initialize the hardware */
504 diag = em_hardware_init(hw);
505 if (diag != 0) {
506 PMD_INIT_LOG(ERR, "Hardware initialization failed");
507 goto error;
508 }
509
510 hw->mac.get_link_status = 1;
511
512 /* Indicate SOL/IDER usage */
513 diag = e1000_check_reset_block(hw);
514 if (diag < 0) {
515 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
516 "SOL/IDER session");
517 }
518 return 0;
519
520 error:
521 em_hw_control_release(hw);
522 return diag;
523 }
524
525 static int
526 eth_em_configure(struct rte_eth_dev *dev)
527 {
528 struct e1000_interrupt *intr =
529 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
530
531 PMD_INIT_FUNC_TRACE();
532 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
533 PMD_INIT_FUNC_TRACE();
534
535 return 0;
536 }
537
538 static void
539 em_set_pba(struct e1000_hw *hw)
540 {
541 uint32_t pba;
542
543 /*
544 * Packet Buffer Allocation (PBA)
545 * Writing PBA sets the receive portion of the buffer
546 * the remainder is used for the transmit buffer.
547 * Devices before the 82547 had a Packet Buffer of 64K.
548 * After the 82547 the buffer was reduced to 40K.
549 */
550 switch (hw->mac.type) {
551 case e1000_82547:
552 case e1000_82547_rev_2:
553 /* 82547: Total Packet Buffer is 40K */
554 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
555 break;
556 case e1000_82571:
557 case e1000_82572:
558 case e1000_80003es2lan:
559 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
560 break;
561 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
562 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
563 break;
564 case e1000_82574:
565 case e1000_82583:
566 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
567 break;
568 case e1000_ich8lan:
569 pba = E1000_PBA_8K;
570 break;
571 case e1000_ich9lan:
572 case e1000_ich10lan:
573 pba = E1000_PBA_10K;
574 break;
575 case e1000_pchlan:
576 case e1000_pch2lan:
577 case e1000_pch_lpt:
578 case e1000_pch_spt:
579 case e1000_pch_cnp:
580 pba = E1000_PBA_26K;
581 break;
582 default:
583 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
584 }
585
586 E1000_WRITE_REG(hw, E1000_PBA, pba);
587 }
588
589 static int
590 eth_em_start(struct rte_eth_dev *dev)
591 {
592 struct e1000_adapter *adapter =
593 E1000_DEV_PRIVATE(dev->data->dev_private);
594 struct e1000_hw *hw =
595 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
596 struct rte_pci_device *pci_dev =
597 E1000_DEV_TO_PCI(dev);
598 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
599 int ret, mask;
600 uint32_t intr_vector = 0;
601 uint32_t *speeds;
602 int num_speeds;
603 bool autoneg;
604
605 PMD_INIT_FUNC_TRACE();
606
607 eth_em_stop(dev);
608
609 e1000_power_up_phy(hw);
610
611 /* Set default PBA value */
612 em_set_pba(hw);
613
614 /* Put the address into the Receive Address Array */
615 e1000_rar_set(hw, hw->mac.addr, 0);
616
617 /*
618 * With the 82571 adapter, RAR[0] may be overwritten
619 * when the other port is reset, we make a duplicate
620 * in RAR[14] for that eventuality, this assures
621 * the interface continues to function.
622 */
623 if (hw->mac.type == e1000_82571) {
624 e1000_set_laa_state_82571(hw, TRUE);
625 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
626 }
627
628 /* Initialize the hardware */
629 if (em_hardware_init(hw)) {
630 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
631 return -EIO;
632 }
633
634 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
635
636 /* Configure for OS presence */
637 em_init_manageability(hw);
638
639 if (dev->data->dev_conf.intr_conf.rxq != 0) {
640 intr_vector = dev->data->nb_rx_queues;
641 if (rte_intr_efd_enable(intr_handle, intr_vector))
642 return -1;
643 }
644
645 if (rte_intr_dp_is_en(intr_handle)) {
646 intr_handle->intr_vec =
647 rte_zmalloc("intr_vec",
648 dev->data->nb_rx_queues * sizeof(int), 0);
649 if (intr_handle->intr_vec == NULL) {
650 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
651 " intr_vec", dev->data->nb_rx_queues);
652 return -ENOMEM;
653 }
654
655 /* enable rx interrupt */
656 em_rxq_intr_enable(hw);
657 }
658
659 eth_em_tx_init(dev);
660
661 ret = eth_em_rx_init(dev);
662 if (ret) {
663 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
664 em_dev_clear_queues(dev);
665 return ret;
666 }
667
668 e1000_clear_hw_cntrs_base_generic(hw);
669
670 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
671 ETH_VLAN_EXTEND_MASK;
672 eth_em_vlan_offload_set(dev, mask);
673
674 /* Set Interrupt Throttling Rate to maximum allowed value. */
675 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
676
677 /* Setup link speed and duplex */
678 speeds = &dev->data->dev_conf.link_speeds;
679 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
680 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
681 hw->mac.autoneg = 1;
682 } else {
683 num_speeds = 0;
684 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
685
686 /* Reset */
687 hw->phy.autoneg_advertised = 0;
688
689 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
690 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
691 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
692 num_speeds = -1;
693 goto error_invalid_config;
694 }
695 if (*speeds & ETH_LINK_SPEED_10M_HD) {
696 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
697 num_speeds++;
698 }
699 if (*speeds & ETH_LINK_SPEED_10M) {
700 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
701 num_speeds++;
702 }
703 if (*speeds & ETH_LINK_SPEED_100M_HD) {
704 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
705 num_speeds++;
706 }
707 if (*speeds & ETH_LINK_SPEED_100M) {
708 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
709 num_speeds++;
710 }
711 if (*speeds & ETH_LINK_SPEED_1G) {
712 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
713 num_speeds++;
714 }
715 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
716 goto error_invalid_config;
717
718 /* Set/reset the mac.autoneg based on the link speed,
719 * fixed or not
720 */
721 if (!autoneg) {
722 hw->mac.autoneg = 0;
723 hw->mac.forced_speed_duplex =
724 hw->phy.autoneg_advertised;
725 } else {
726 hw->mac.autoneg = 1;
727 }
728 }
729
730 e1000_setup_link(hw);
731
732 if (rte_intr_allow_others(intr_handle)) {
733 /* check if lsc interrupt is enabled */
734 if (dev->data->dev_conf.intr_conf.lsc != 0) {
735 ret = eth_em_interrupt_setup(dev);
736 if (ret) {
737 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
738 em_dev_clear_queues(dev);
739 return ret;
740 }
741 }
742 } else {
743 rte_intr_callback_unregister(intr_handle,
744 eth_em_interrupt_handler,
745 (void *)dev);
746 if (dev->data->dev_conf.intr_conf.lsc != 0)
747 PMD_INIT_LOG(INFO, "lsc won't enable because of"
748 " no intr multiplexn");
749 }
750 /* check if rxq interrupt is enabled */
751 if (dev->data->dev_conf.intr_conf.rxq != 0)
752 eth_em_rxq_interrupt_setup(dev);
753
754 rte_intr_enable(intr_handle);
755
756 adapter->stopped = 0;
757
758 PMD_INIT_LOG(DEBUG, "<<");
759
760 return 0;
761
762 error_invalid_config:
763 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
764 dev->data->dev_conf.link_speeds, dev->data->port_id);
765 em_dev_clear_queues(dev);
766 return -EINVAL;
767 }
768
769 /*********************************************************************
770 *
771 * This routine disables all traffic on the adapter by issuing a
772 * global reset on the MAC.
773 *
774 **********************************************************************/
775 static void
776 eth_em_stop(struct rte_eth_dev *dev)
777 {
778 struct rte_eth_link link;
779 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
780 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
781 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
782
783 em_rxq_intr_disable(hw);
784 em_lsc_intr_disable(hw);
785
786 e1000_reset_hw(hw);
787 if (hw->mac.type >= e1000_82544)
788 E1000_WRITE_REG(hw, E1000_WUC, 0);
789
790 /* Power down the phy. Needed to make the link go down */
791 e1000_power_down_phy(hw);
792
793 em_dev_clear_queues(dev);
794
795 /* clear the recorded link status */
796 memset(&link, 0, sizeof(link));
797 rte_em_dev_atomic_write_link_status(dev, &link);
798
799 if (!rte_intr_allow_others(intr_handle))
800 /* resume to the default handler */
801 rte_intr_callback_register(intr_handle,
802 eth_em_interrupt_handler,
803 (void *)dev);
804
805 /* Clean datapath event and queue/vec mapping */
806 rte_intr_efd_disable(intr_handle);
807 if (intr_handle->intr_vec != NULL) {
808 rte_free(intr_handle->intr_vec);
809 intr_handle->intr_vec = NULL;
810 }
811 }
812
813 static void
814 eth_em_close(struct rte_eth_dev *dev)
815 {
816 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
817 struct e1000_adapter *adapter =
818 E1000_DEV_PRIVATE(dev->data->dev_private);
819
820 eth_em_stop(dev);
821 adapter->stopped = 1;
822 em_dev_free_queues(dev);
823 e1000_phy_hw_reset(hw);
824 em_release_manageability(hw);
825 em_hw_control_release(hw);
826 }
827
828 static int
829 em_get_rx_buffer_size(struct e1000_hw *hw)
830 {
831 uint32_t rx_buf_size;
832
833 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
834 return rx_buf_size;
835 }
836
837 /*********************************************************************
838 *
839 * Initialize the hardware
840 *
841 **********************************************************************/
842 static int
843 em_hardware_init(struct e1000_hw *hw)
844 {
845 uint32_t rx_buf_size;
846 int diag;
847
848 /* Issue a global reset */
849 e1000_reset_hw(hw);
850
851 /* Let the firmware know the OS is in control */
852 em_hw_control_acquire(hw);
853
854 /*
855 * These parameters control the automatic generation (Tx) and
856 * response (Rx) to Ethernet PAUSE frames.
857 * - High water mark should allow for at least two standard size (1518)
858 * frames to be received after sending an XOFF.
859 * - Low water mark works best when it is very near the high water mark.
860 * This allows the receiver to restart by sending XON when it has
861 * drained a bit. Here we use an arbitrary value of 1500 which will
862 * restart after one full frame is pulled from the buffer. There
863 * could be several smaller frames in the buffer and if so they will
864 * not trigger the XON until their total number reduces the buffer
865 * by 1500.
866 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
867 */
868 rx_buf_size = em_get_rx_buffer_size(hw);
869
870 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
871 hw->fc.low_water = hw->fc.high_water - 1500;
872
873 if (hw->mac.type == e1000_80003es2lan)
874 hw->fc.pause_time = UINT16_MAX;
875 else
876 hw->fc.pause_time = EM_FC_PAUSE_TIME;
877
878 hw->fc.send_xon = 1;
879
880 /* Set Flow control, use the tunable location if sane */
881 if (em_fc_setting <= e1000_fc_full)
882 hw->fc.requested_mode = em_fc_setting;
883 else
884 hw->fc.requested_mode = e1000_fc_none;
885
886 /* Workaround: no TX flow ctrl for PCH */
887 if (hw->mac.type == e1000_pchlan)
888 hw->fc.requested_mode = e1000_fc_rx_pause;
889
890 /* Override - settings for PCH2LAN, ya its magic :) */
891 if (hw->mac.type == e1000_pch2lan) {
892 hw->fc.high_water = 0x5C20;
893 hw->fc.low_water = 0x5048;
894 hw->fc.pause_time = 0x0650;
895 hw->fc.refresh_time = 0x0400;
896 } else if (hw->mac.type == e1000_pch_lpt ||
897 hw->mac.type == e1000_pch_spt ||
898 hw->mac.type == e1000_pch_cnp) {
899 hw->fc.requested_mode = e1000_fc_full;
900 }
901
902 diag = e1000_init_hw(hw);
903 if (diag < 0)
904 return diag;
905 e1000_check_for_link(hw);
906 return 0;
907 }
908
909 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
910 static void
911 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
912 {
913 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
914 struct e1000_hw_stats *stats =
915 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
916 int pause_frames;
917
918 if(hw->phy.media_type == e1000_media_type_copper ||
919 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
920 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
921 stats->sec += E1000_READ_REG(hw, E1000_SEC);
922 }
923
924 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
925 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
926 stats->scc += E1000_READ_REG(hw, E1000_SCC);
927 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
928
929 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
930 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
931 stats->colc += E1000_READ_REG(hw, E1000_COLC);
932 stats->dc += E1000_READ_REG(hw, E1000_DC);
933 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
934 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
935 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
936
937 /*
938 * For watchdog management we need to know if we have been
939 * paused during the last interval, so capture that here.
940 */
941 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
942 stats->xoffrxc += pause_frames;
943 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
944 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
945 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
946 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
947 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
948 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
949 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
950 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
951 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
952 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
953 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
954 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
955
956 /*
957 * For the 64-bit byte counters the low dword must be read first.
958 * Both registers clear on the read of the high dword.
959 */
960
961 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
962 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
963 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
964 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
965
966 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
967 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
968 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
969 stats->roc += E1000_READ_REG(hw, E1000_ROC);
970 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
971
972 stats->tor += E1000_READ_REG(hw, E1000_TORH);
973 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
974
975 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
976 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
977 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
978 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
979 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
980 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
981 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
982 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
983 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
984 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
985
986 /* Interrupt Counts */
987
988 if (hw->mac.type >= e1000_82571) {
989 stats->iac += E1000_READ_REG(hw, E1000_IAC);
990 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
991 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
992 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
993 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
994 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
995 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
996 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
997 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
998 }
999
1000 if (hw->mac.type >= e1000_82543) {
1001 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1002 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1003 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1004 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1005 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1006 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1007 }
1008
1009 if (rte_stats == NULL)
1010 return;
1011
1012 /* Rx Errors */
1013 rte_stats->imissed = stats->mpc;
1014 rte_stats->ierrors = stats->crcerrs +
1015 stats->rlec + stats->ruc + stats->roc +
1016 stats->rxerrc + stats->algnerrc + stats->cexterr;
1017
1018 /* Tx Errors */
1019 rte_stats->oerrors = stats->ecol + stats->latecol;
1020
1021 rte_stats->ipackets = stats->gprc;
1022 rte_stats->opackets = stats->gptc;
1023 rte_stats->ibytes = stats->gorc;
1024 rte_stats->obytes = stats->gotc;
1025 }
1026
1027 static void
1028 eth_em_stats_reset(struct rte_eth_dev *dev)
1029 {
1030 struct e1000_hw_stats *hw_stats =
1031 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1032
1033 /* HW registers are cleared on read */
1034 eth_em_stats_get(dev, NULL);
1035
1036 /* Reset software totals */
1037 memset(hw_stats, 0, sizeof(*hw_stats));
1038 }
1039
1040 static int
1041 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1042 {
1043 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1044 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1045 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1046
1047 em_rxq_intr_enable(hw);
1048 rte_intr_enable(intr_handle);
1049
1050 return 0;
1051 }
1052
1053 static int
1054 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1055 {
1056 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1057
1058 em_rxq_intr_disable(hw);
1059
1060 return 0;
1061 }
1062
1063 static uint32_t
1064 em_get_max_pktlen(const struct e1000_hw *hw)
1065 {
1066 switch (hw->mac.type) {
1067 case e1000_82571:
1068 case e1000_82572:
1069 case e1000_ich9lan:
1070 case e1000_ich10lan:
1071 case e1000_pch2lan:
1072 case e1000_pch_lpt:
1073 case e1000_pch_spt:
1074 case e1000_pch_cnp:
1075 case e1000_82574:
1076 case e1000_80003es2lan: /* 9K Jumbo Frame size */
1077 case e1000_82583:
1078 return 0x2412;
1079 case e1000_pchlan:
1080 return 0x1000;
1081 /* Adapters that do not support jumbo frames */
1082 case e1000_ich8lan:
1083 return ETHER_MAX_LEN;
1084 default:
1085 return MAX_JUMBO_FRAME_SIZE;
1086 }
1087 }
1088
1089 static void
1090 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1091 {
1092 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1093
1094 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1095 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1096 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1097 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1098 dev_info->rx_offload_capa =
1099 DEV_RX_OFFLOAD_VLAN_STRIP |
1100 DEV_RX_OFFLOAD_IPV4_CKSUM |
1101 DEV_RX_OFFLOAD_UDP_CKSUM |
1102 DEV_RX_OFFLOAD_TCP_CKSUM;
1103 dev_info->tx_offload_capa =
1104 DEV_TX_OFFLOAD_VLAN_INSERT |
1105 DEV_TX_OFFLOAD_IPV4_CKSUM |
1106 DEV_TX_OFFLOAD_UDP_CKSUM |
1107 DEV_TX_OFFLOAD_TCP_CKSUM;
1108
1109 /*
1110 * Starting with 631xESB hw supports 2 TX/RX queues per port.
1111 * Unfortunatelly, all these nics have just one TX context.
1112 * So we have few choises for TX:
1113 * - Use just one TX queue.
1114 * - Allow cksum offload only for one TX queue.
1115 * - Don't allow TX cksum offload at all.
1116 * For now, option #1 was chosen.
1117 * To use second RX queue we have to use extended RX descriptor
1118 * (Multiple Receive Queues are mutually exclusive with UDP
1119 * fragmentation and are not supported when a legacy receive
1120 * descriptor format is used).
1121 * Which means separate RX routinies - as legacy nics (82540, 82545)
1122 * don't support extended RXD.
1123 * To avoid it we support just one RX queue for now (no RSS).
1124 */
1125
1126 dev_info->max_rx_queues = 1;
1127 dev_info->max_tx_queues = 1;
1128
1129 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1130 .nb_max = E1000_MAX_RING_DESC,
1131 .nb_min = E1000_MIN_RING_DESC,
1132 .nb_align = EM_RXD_ALIGN,
1133 };
1134
1135 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1136 .nb_max = E1000_MAX_RING_DESC,
1137 .nb_min = E1000_MIN_RING_DESC,
1138 .nb_align = EM_TXD_ALIGN,
1139 .nb_seg_max = EM_TX_MAX_SEG,
1140 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1141 };
1142
1143 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1144 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1145 ETH_LINK_SPEED_1G;
1146 }
1147
1148 /* return 0 means link status changed, -1 means not changed */
1149 static int
1150 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1151 {
1152 struct e1000_hw *hw =
1153 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1154 struct rte_eth_link link, old;
1155 int link_check, count;
1156
1157 link_check = 0;
1158 hw->mac.get_link_status = 1;
1159
1160 /* possible wait-to-complete in up to 9 seconds */
1161 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1162 /* Read the real link status */
1163 switch (hw->phy.media_type) {
1164 case e1000_media_type_copper:
1165 /* Do the work to read phy */
1166 e1000_check_for_link(hw);
1167 link_check = !hw->mac.get_link_status;
1168 break;
1169
1170 case e1000_media_type_fiber:
1171 e1000_check_for_link(hw);
1172 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1173 E1000_STATUS_LU);
1174 break;
1175
1176 case e1000_media_type_internal_serdes:
1177 e1000_check_for_link(hw);
1178 link_check = hw->mac.serdes_has_link;
1179 break;
1180
1181 default:
1182 break;
1183 }
1184 if (link_check || wait_to_complete == 0)
1185 break;
1186 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1187 }
1188 memset(&link, 0, sizeof(link));
1189 rte_em_dev_atomic_read_link_status(dev, &link);
1190 old = link;
1191
1192 /* Now we check if a transition has happened */
1193 if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1194 uint16_t duplex, speed;
1195 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1196 link.link_duplex = (duplex == FULL_DUPLEX) ?
1197 ETH_LINK_FULL_DUPLEX :
1198 ETH_LINK_HALF_DUPLEX;
1199 link.link_speed = speed;
1200 link.link_status = ETH_LINK_UP;
1201 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1202 ETH_LINK_SPEED_FIXED);
1203 } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1204 link.link_speed = 0;
1205 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1206 link.link_status = ETH_LINK_DOWN;
1207 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1208 }
1209 rte_em_dev_atomic_write_link_status(dev, &link);
1210
1211 /* not changed */
1212 if (old.link_status == link.link_status)
1213 return -1;
1214
1215 /* changed */
1216 return 0;
1217 }
1218
1219 /*
1220 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1221 * For ASF and Pass Through versions of f/w this means
1222 * that the driver is loaded. For AMT version type f/w
1223 * this means that the network i/f is open.
1224 */
1225 static void
1226 em_hw_control_acquire(struct e1000_hw *hw)
1227 {
1228 uint32_t ctrl_ext, swsm;
1229
1230 /* Let firmware know the driver has taken over */
1231 if (hw->mac.type == e1000_82573) {
1232 swsm = E1000_READ_REG(hw, E1000_SWSM);
1233 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1234
1235 } else {
1236 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1237 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1238 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1239 }
1240 }
1241
1242 /*
1243 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1244 * For ASF and Pass Through versions of f/w this means that the
1245 * driver is no longer loaded. For AMT versions of the
1246 * f/w this means that the network i/f is closed.
1247 */
1248 static void
1249 em_hw_control_release(struct e1000_hw *hw)
1250 {
1251 uint32_t ctrl_ext, swsm;
1252
1253 /* Let firmware taken over control of h/w */
1254 if (hw->mac.type == e1000_82573) {
1255 swsm = E1000_READ_REG(hw, E1000_SWSM);
1256 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1257 } else {
1258 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1259 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1260 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1261 }
1262 }
1263
1264 /*
1265 * Bit of a misnomer, what this really means is
1266 * to enable OS management of the system... aka
1267 * to disable special hardware management features.
1268 */
1269 static void
1270 em_init_manageability(struct e1000_hw *hw)
1271 {
1272 if (e1000_enable_mng_pass_thru(hw)) {
1273 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1274 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1275
1276 /* disable hardware interception of ARP */
1277 manc &= ~(E1000_MANC_ARP_EN);
1278
1279 /* enable receiving management packets to the host */
1280 manc |= E1000_MANC_EN_MNG2HOST;
1281 manc2h |= 1 << 5; /* Mng Port 623 */
1282 manc2h |= 1 << 6; /* Mng Port 664 */
1283 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1284 E1000_WRITE_REG(hw, E1000_MANC, manc);
1285 }
1286 }
1287
1288 /*
1289 * Give control back to hardware management
1290 * controller if there is one.
1291 */
1292 static void
1293 em_release_manageability(struct e1000_hw *hw)
1294 {
1295 uint32_t manc;
1296
1297 if (e1000_enable_mng_pass_thru(hw)) {
1298 manc = E1000_READ_REG(hw, E1000_MANC);
1299
1300 /* re-enable hardware interception of ARP */
1301 manc |= E1000_MANC_ARP_EN;
1302 manc &= ~E1000_MANC_EN_MNG2HOST;
1303
1304 E1000_WRITE_REG(hw, E1000_MANC, manc);
1305 }
1306 }
1307
1308 static void
1309 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1310 {
1311 struct e1000_hw *hw =
1312 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1313 uint32_t rctl;
1314
1315 rctl = E1000_READ_REG(hw, E1000_RCTL);
1316 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1317 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1318 }
1319
1320 static void
1321 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1322 {
1323 struct e1000_hw *hw =
1324 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1325 uint32_t rctl;
1326
1327 rctl = E1000_READ_REG(hw, E1000_RCTL);
1328 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1329 if (dev->data->all_multicast == 1)
1330 rctl |= E1000_RCTL_MPE;
1331 else
1332 rctl &= (~E1000_RCTL_MPE);
1333 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1334 }
1335
1336 static void
1337 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1338 {
1339 struct e1000_hw *hw =
1340 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1341 uint32_t rctl;
1342
1343 rctl = E1000_READ_REG(hw, E1000_RCTL);
1344 rctl |= E1000_RCTL_MPE;
1345 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1346 }
1347
1348 static void
1349 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1350 {
1351 struct e1000_hw *hw =
1352 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1353 uint32_t rctl;
1354
1355 if (dev->data->promiscuous == 1)
1356 return; /* must remain in all_multicast mode */
1357 rctl = E1000_READ_REG(hw, E1000_RCTL);
1358 rctl &= (~E1000_RCTL_MPE);
1359 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1360 }
1361
1362 static int
1363 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1364 {
1365 struct e1000_hw *hw =
1366 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1367 struct e1000_vfta * shadow_vfta =
1368 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1369 uint32_t vfta;
1370 uint32_t vid_idx;
1371 uint32_t vid_bit;
1372
1373 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1374 E1000_VFTA_ENTRY_MASK);
1375 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1376 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1377 if (on)
1378 vfta |= vid_bit;
1379 else
1380 vfta &= ~vid_bit;
1381 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1382
1383 /* update local VFTA copy */
1384 shadow_vfta->vfta[vid_idx] = vfta;
1385
1386 return 0;
1387 }
1388
1389 static void
1390 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1391 {
1392 struct e1000_hw *hw =
1393 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1394 uint32_t reg;
1395
1396 /* Filter Table Disable */
1397 reg = E1000_READ_REG(hw, E1000_RCTL);
1398 reg &= ~E1000_RCTL_CFIEN;
1399 reg &= ~E1000_RCTL_VFE;
1400 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1401 }
1402
1403 static void
1404 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1405 {
1406 struct e1000_hw *hw =
1407 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1408 struct e1000_vfta * shadow_vfta =
1409 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1410 uint32_t reg;
1411 int i;
1412
1413 /* Filter Table Enable, CFI not used for packet acceptance */
1414 reg = E1000_READ_REG(hw, E1000_RCTL);
1415 reg &= ~E1000_RCTL_CFIEN;
1416 reg |= E1000_RCTL_VFE;
1417 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1418
1419 /* restore vfta from local copy */
1420 for (i = 0; i < IGB_VFTA_SIZE; i++)
1421 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1422 }
1423
1424 static void
1425 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1426 {
1427 struct e1000_hw *hw =
1428 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1429 uint32_t reg;
1430
1431 /* VLAN Mode Disable */
1432 reg = E1000_READ_REG(hw, E1000_CTRL);
1433 reg &= ~E1000_CTRL_VME;
1434 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1435
1436 }
1437
1438 static void
1439 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1440 {
1441 struct e1000_hw *hw =
1442 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1443 uint32_t reg;
1444
1445 /* VLAN Mode Enable */
1446 reg = E1000_READ_REG(hw, E1000_CTRL);
1447 reg |= E1000_CTRL_VME;
1448 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1449 }
1450
1451 static void
1452 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1453 {
1454 if(mask & ETH_VLAN_STRIP_MASK){
1455 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1456 em_vlan_hw_strip_enable(dev);
1457 else
1458 em_vlan_hw_strip_disable(dev);
1459 }
1460
1461 if(mask & ETH_VLAN_FILTER_MASK){
1462 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1463 em_vlan_hw_filter_enable(dev);
1464 else
1465 em_vlan_hw_filter_disable(dev);
1466 }
1467 }
1468
1469 /*
1470 * It enables the interrupt mask and then enable the interrupt.
1471 *
1472 * @param dev
1473 * Pointer to struct rte_eth_dev.
1474 *
1475 * @return
1476 * - On success, zero.
1477 * - On failure, a negative value.
1478 */
1479 static int
1480 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1481 {
1482 uint32_t regval;
1483 struct e1000_hw *hw =
1484 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1485
1486 /* clear interrupt */
1487 E1000_READ_REG(hw, E1000_ICR);
1488 regval = E1000_READ_REG(hw, E1000_IMS);
1489 E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1490 return 0;
1491 }
1492
1493 /*
1494 * It clears the interrupt causes and enables the interrupt.
1495 * It will be called once only during nic initialized.
1496 *
1497 * @param dev
1498 * Pointer to struct rte_eth_dev.
1499 *
1500 * @return
1501 * - On success, zero.
1502 * - On failure, a negative value.
1503 */
1504 static int
1505 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1506 {
1507 struct e1000_hw *hw =
1508 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1509
1510 E1000_READ_REG(hw, E1000_ICR);
1511 em_rxq_intr_enable(hw);
1512 return 0;
1513 }
1514
1515 /*
1516 * It enable receive packet interrupt.
1517 * @param hw
1518 * Pointer to struct e1000_hw
1519 *
1520 * @return
1521 */
1522 static void
1523 em_rxq_intr_enable(struct e1000_hw *hw)
1524 {
1525 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1526 E1000_WRITE_FLUSH(hw);
1527 }
1528
1529 /*
1530 * It disabled lsc interrupt.
1531 * @param hw
1532 * Pointer to struct e1000_hw
1533 *
1534 * @return
1535 */
1536 static void
1537 em_lsc_intr_disable(struct e1000_hw *hw)
1538 {
1539 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1540 E1000_WRITE_FLUSH(hw);
1541 }
1542
1543 /*
1544 * It disabled receive packet interrupt.
1545 * @param hw
1546 * Pointer to struct e1000_hw
1547 *
1548 * @return
1549 */
1550 static void
1551 em_rxq_intr_disable(struct e1000_hw *hw)
1552 {
1553 E1000_READ_REG(hw, E1000_ICR);
1554 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1555 E1000_WRITE_FLUSH(hw);
1556 }
1557
1558 /*
1559 * It reads ICR and gets interrupt causes, check it and set a bit flag
1560 * to update link status.
1561 *
1562 * @param dev
1563 * Pointer to struct rte_eth_dev.
1564 *
1565 * @return
1566 * - On success, zero.
1567 * - On failure, a negative value.
1568 */
1569 static int
1570 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1571 {
1572 uint32_t icr;
1573 struct e1000_hw *hw =
1574 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1575 struct e1000_interrupt *intr =
1576 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1577
1578 /* read-on-clear nic registers here */
1579 icr = E1000_READ_REG(hw, E1000_ICR);
1580 if (icr & E1000_ICR_LSC) {
1581 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1582 }
1583
1584 return 0;
1585 }
1586
1587 /*
1588 * It executes link_update after knowing an interrupt is prsent.
1589 *
1590 * @param dev
1591 * Pointer to struct rte_eth_dev.
1592 *
1593 * @return
1594 * - On success, zero.
1595 * - On failure, a negative value.
1596 */
1597 static int
1598 eth_em_interrupt_action(struct rte_eth_dev *dev,
1599 struct rte_intr_handle *intr_handle)
1600 {
1601 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1602 struct e1000_hw *hw =
1603 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1604 struct e1000_interrupt *intr =
1605 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1606 uint32_t tctl, rctl;
1607 struct rte_eth_link link;
1608 int ret;
1609
1610 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1611 return -1;
1612
1613 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1614 rte_intr_enable(intr_handle);
1615
1616 /* set get_link_status to check register later */
1617 hw->mac.get_link_status = 1;
1618 ret = eth_em_link_update(dev, 0);
1619
1620 /* check if link has changed */
1621 if (ret < 0)
1622 return 0;
1623
1624 memset(&link, 0, sizeof(link));
1625 rte_em_dev_atomic_read_link_status(dev, &link);
1626 if (link.link_status) {
1627 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1628 dev->data->port_id, (unsigned)link.link_speed,
1629 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1630 "full-duplex" : "half-duplex");
1631 } else {
1632 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1633 }
1634 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1635 pci_dev->addr.domain, pci_dev->addr.bus,
1636 pci_dev->addr.devid, pci_dev->addr.function);
1637
1638 tctl = E1000_READ_REG(hw, E1000_TCTL);
1639 rctl = E1000_READ_REG(hw, E1000_RCTL);
1640 if (link.link_status) {
1641 /* enable Tx/Rx */
1642 tctl |= E1000_TCTL_EN;
1643 rctl |= E1000_RCTL_EN;
1644 } else {
1645 /* disable Tx/Rx */
1646 tctl &= ~E1000_TCTL_EN;
1647 rctl &= ~E1000_RCTL_EN;
1648 }
1649 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1650 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1651 E1000_WRITE_FLUSH(hw);
1652
1653 return 0;
1654 }
1655
1656 /**
1657 * Interrupt handler which shall be registered at first.
1658 *
1659 * @param handle
1660 * Pointer to interrupt handle.
1661 * @param param
1662 * The address of parameter (struct rte_eth_dev *) regsitered before.
1663 *
1664 * @return
1665 * void
1666 */
1667 static void
1668 eth_em_interrupt_handler(void *param)
1669 {
1670 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1671
1672 eth_em_interrupt_get_status(dev);
1673 eth_em_interrupt_action(dev, dev->intr_handle);
1674 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1675 }
1676
1677 static int
1678 eth_em_led_on(struct rte_eth_dev *dev)
1679 {
1680 struct e1000_hw *hw;
1681
1682 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1683 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1684 }
1685
1686 static int
1687 eth_em_led_off(struct rte_eth_dev *dev)
1688 {
1689 struct e1000_hw *hw;
1690
1691 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1692 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1693 }
1694
1695 static int
1696 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1697 {
1698 struct e1000_hw *hw;
1699 uint32_t ctrl;
1700 int tx_pause;
1701 int rx_pause;
1702
1703 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704 fc_conf->pause_time = hw->fc.pause_time;
1705 fc_conf->high_water = hw->fc.high_water;
1706 fc_conf->low_water = hw->fc.low_water;
1707 fc_conf->send_xon = hw->fc.send_xon;
1708 fc_conf->autoneg = hw->mac.autoneg;
1709
1710 /*
1711 * Return rx_pause and tx_pause status according to actual setting of
1712 * the TFCE and RFCE bits in the CTRL register.
1713 */
1714 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1715 if (ctrl & E1000_CTRL_TFCE)
1716 tx_pause = 1;
1717 else
1718 tx_pause = 0;
1719
1720 if (ctrl & E1000_CTRL_RFCE)
1721 rx_pause = 1;
1722 else
1723 rx_pause = 0;
1724
1725 if (rx_pause && tx_pause)
1726 fc_conf->mode = RTE_FC_FULL;
1727 else if (rx_pause)
1728 fc_conf->mode = RTE_FC_RX_PAUSE;
1729 else if (tx_pause)
1730 fc_conf->mode = RTE_FC_TX_PAUSE;
1731 else
1732 fc_conf->mode = RTE_FC_NONE;
1733
1734 return 0;
1735 }
1736
1737 static int
1738 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1739 {
1740 struct e1000_hw *hw;
1741 int err;
1742 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1743 e1000_fc_none,
1744 e1000_fc_rx_pause,
1745 e1000_fc_tx_pause,
1746 e1000_fc_full
1747 };
1748 uint32_t rx_buf_size;
1749 uint32_t max_high_water;
1750 uint32_t rctl;
1751
1752 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1753 if (fc_conf->autoneg != hw->mac.autoneg)
1754 return -ENOTSUP;
1755 rx_buf_size = em_get_rx_buffer_size(hw);
1756 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1757
1758 /* At least reserve one Ethernet frame for watermark */
1759 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1760 if ((fc_conf->high_water > max_high_water) ||
1761 (fc_conf->high_water < fc_conf->low_water)) {
1762 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1763 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1764 return -EINVAL;
1765 }
1766
1767 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1768 hw->fc.pause_time = fc_conf->pause_time;
1769 hw->fc.high_water = fc_conf->high_water;
1770 hw->fc.low_water = fc_conf->low_water;
1771 hw->fc.send_xon = fc_conf->send_xon;
1772
1773 err = e1000_setup_link_generic(hw);
1774 if (err == E1000_SUCCESS) {
1775
1776 /* check if we want to forward MAC frames - driver doesn't have native
1777 * capability to do that, so we'll write the registers ourselves */
1778
1779 rctl = E1000_READ_REG(hw, E1000_RCTL);
1780
1781 /* set or clear MFLCN.PMCF bit depending on configuration */
1782 if (fc_conf->mac_ctrl_frame_fwd != 0)
1783 rctl |= E1000_RCTL_PMCF;
1784 else
1785 rctl &= ~E1000_RCTL_PMCF;
1786
1787 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1788 E1000_WRITE_FLUSH(hw);
1789
1790 return 0;
1791 }
1792
1793 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1794 return -EIO;
1795 }
1796
1797 static int
1798 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1799 uint32_t index, __rte_unused uint32_t pool)
1800 {
1801 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1802
1803 return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1804 }
1805
1806 static void
1807 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1808 {
1809 uint8_t addr[ETHER_ADDR_LEN];
1810 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1811
1812 memset(addr, 0, sizeof(addr));
1813
1814 e1000_rar_set(hw, addr, index);
1815 }
1816
1817 static int
1818 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1819 {
1820 struct rte_eth_dev_info dev_info;
1821 struct e1000_hw *hw;
1822 uint32_t frame_size;
1823 uint32_t rctl;
1824
1825 eth_em_infos_get(dev, &dev_info);
1826 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1827
1828 /* check that mtu is within the allowed range */
1829 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1830 return -EINVAL;
1831
1832 /* refuse mtu that requires the support of scattered packets when this
1833 * feature has not been enabled before. */
1834 if (!dev->data->scattered_rx &&
1835 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1836 return -EINVAL;
1837
1838 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1839 rctl = E1000_READ_REG(hw, E1000_RCTL);
1840
1841 /* switch to jumbo mode if needed */
1842 if (frame_size > ETHER_MAX_LEN) {
1843 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1844 rctl |= E1000_RCTL_LPE;
1845 } else {
1846 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1847 rctl &= ~E1000_RCTL_LPE;
1848 }
1849 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1850
1851 /* update max frame size */
1852 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1853 return 0;
1854 }
1855
1856 static int
1857 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1858 struct ether_addr *mc_addr_set,
1859 uint32_t nb_mc_addr)
1860 {
1861 struct e1000_hw *hw;
1862
1863 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1864 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1865 return 0;
1866 }
1867
1868 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1869 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1870 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio");
Ceph