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[ceph.git] / ceph / src / seastar / dpdk / drivers / net / e1000 / igb_ethdev.c
1 /*-
2 * BSD LICENSE
3 *
4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/queue.h>
35 #include <stdio.h>
36 #include <errno.h>
37 #include <stdint.h>
38 #include <stdarg.h>
39
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
43 #include <rte_log.h>
44 #include <rte_debug.h>
45 #include <rte_pci.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memory.h>
50 #include <rte_memzone.h>
51 #include <rte_eal.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
54 #include <rte_dev.h>
55
56 #include "e1000_logs.h"
57 #include "base/e1000_api.h"
58 #include "e1000_ethdev.h"
59 #include "igb_regs.h"
60
61 /*
62 * Default values for port configuration
63 */
64 #define IGB_DEFAULT_RX_FREE_THRESH 32
65
66 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
67 #define IGB_DEFAULT_RX_HTHRESH 8
68 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
69
70 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
71 #define IGB_DEFAULT_TX_HTHRESH 1
72 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
73
74 #define IGB_HKEY_MAX_INDEX 10
75
76 /* Bit shift and mask */
77 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
78 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
79 #define IGB_8_BIT_WIDTH CHAR_BIT
80 #define IGB_8_BIT_MASK UINT8_MAX
81
82 /* Additional timesync values. */
83 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
84 #define E1000_ETQF_FILTER_1588 3
85 #define IGB_82576_TSYNC_SHIFT 16
86 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
87 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
89
90 #define E1000_VTIVAR_MISC 0x01740
91 #define E1000_VTIVAR_MISC_MASK 0xFF
92 #define E1000_VTIVAR_VALID 0x80
93 #define E1000_VTIVAR_MISC_MAILBOX 0
94 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
95
96 /* External VLAN Enable bit mask */
97 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
98
99 /* External VLAN Ether Type bit mask and shift */
100 #define E1000_VET_VET_EXT 0xFFFF0000
101 #define E1000_VET_VET_EXT_SHIFT 16
102
103 static int eth_igb_configure(struct rte_eth_dev *dev);
104 static int eth_igb_start(struct rte_eth_dev *dev);
105 static void eth_igb_stop(struct rte_eth_dev *dev);
106 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
107 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
108 static void eth_igb_close(struct rte_eth_dev *dev);
109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
113 static int eth_igb_link_update(struct rte_eth_dev *dev,
114 int wait_to_complete);
115 static void eth_igb_stats_get(struct rte_eth_dev *dev,
116 struct rte_eth_stats *rte_stats);
117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
118 struct rte_eth_xstat *xstats, unsigned n);
119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
120 const uint64_t *ids,
121 uint64_t *values, unsigned int n);
122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
123 struct rte_eth_xstat_name *xstats_names,
124 unsigned int size);
125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
126 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
127 unsigned int limit);
128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
131 char *fw_version, size_t fw_size);
132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
133 struct rte_eth_dev_info *dev_info);
134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
136 struct rte_eth_dev_info *dev_info);
137 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
138 struct rte_eth_fc_conf *fc_conf);
139 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
140 struct rte_eth_fc_conf *fc_conf);
141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
145 struct rte_intr_handle *handle);
146 static void eth_igb_interrupt_handler(void *param);
147 static int igb_hardware_init(struct e1000_hw *hw);
148 static void igb_hw_control_acquire(struct e1000_hw *hw);
149 static void igb_hw_control_release(struct e1000_hw *hw);
150 static void igb_init_manageability(struct e1000_hw *hw);
151 static void igb_release_manageability(struct e1000_hw *hw);
152
153 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
154
155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
156 uint16_t vlan_id, int on);
157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
158 enum rte_vlan_type vlan_type,
159 uint16_t tpid_id);
160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
161
162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
168
169 static int eth_igb_led_on(struct rte_eth_dev *dev);
170 static int eth_igb_led_off(struct rte_eth_dev *dev);
171
172 static void igb_intr_disable(struct e1000_hw *hw);
173 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
175 struct ether_addr *mac_addr,
176 uint32_t index, uint32_t pool);
177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
179 struct ether_addr *addr);
180
181 static void igbvf_intr_disable(struct e1000_hw *hw);
182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
183 static int igbvf_dev_start(struct rte_eth_dev *dev);
184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
185 static void igbvf_dev_close(struct rte_eth_dev *dev);
186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
190 static int eth_igbvf_link_update(struct e1000_hw *hw);
191 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
192 struct rte_eth_stats *rte_stats);
193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
194 struct rte_eth_xstat *xstats, unsigned n);
195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
196 struct rte_eth_xstat_name *xstats_names,
197 unsigned limit);
198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
200 uint16_t vlan_id, int on);
201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
204 struct ether_addr *addr);
205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
206 static int igbvf_get_regs(struct rte_eth_dev *dev,
207 struct rte_dev_reg_info *regs);
208
209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
210 struct rte_eth_rss_reta_entry64 *reta_conf,
211 uint16_t reta_size);
212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
213 struct rte_eth_rss_reta_entry64 *reta_conf,
214 uint16_t reta_size);
215
216 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
217 struct rte_eth_syn_filter *filter,
218 bool add);
219 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
220 struct rte_eth_syn_filter *filter);
221 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
222 enum rte_filter_op filter_op,
223 void *arg);
224 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
225 struct rte_eth_ntuple_filter *ntuple_filter);
226 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
227 struct rte_eth_ntuple_filter *ntuple_filter);
228 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
229 struct rte_eth_flex_filter *filter,
230 bool add);
231 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
232 struct rte_eth_flex_filter *filter);
233 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
234 enum rte_filter_op filter_op,
235 void *arg);
236 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
237 struct rte_eth_ntuple_filter *ntuple_filter);
238 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
239 struct rte_eth_ntuple_filter *ntuple_filter);
240 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
241 struct rte_eth_ntuple_filter *filter,
242 bool add);
243 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
244 struct rte_eth_ntuple_filter *filter);
245 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
246 enum rte_filter_op filter_op,
247 void *arg);
248 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
249 struct rte_eth_ethertype_filter *filter,
250 bool add);
251 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
252 enum rte_filter_op filter_op,
253 void *arg);
254 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
255 struct rte_eth_ethertype_filter *filter);
256 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
257 enum rte_filter_type filter_type,
258 enum rte_filter_op filter_op,
259 void *arg);
260 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
261 static int eth_igb_get_regs(struct rte_eth_dev *dev,
262 struct rte_dev_reg_info *regs);
263 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
264 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
265 struct rte_dev_eeprom_info *eeprom);
266 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
267 struct rte_dev_eeprom_info *eeprom);
268 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
269 struct ether_addr *mc_addr_set,
270 uint32_t nb_mc_addr);
271 static int igb_timesync_enable(struct rte_eth_dev *dev);
272 static int igb_timesync_disable(struct rte_eth_dev *dev);
273 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
274 struct timespec *timestamp,
275 uint32_t flags);
276 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
277 struct timespec *timestamp);
278 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
279 static int igb_timesync_read_time(struct rte_eth_dev *dev,
280 struct timespec *timestamp);
281 static int igb_timesync_write_time(struct rte_eth_dev *dev,
282 const struct timespec *timestamp);
283 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
284 uint16_t queue_id);
285 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
286 uint16_t queue_id);
287 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
288 uint8_t queue, uint8_t msix_vector);
289 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
290 uint8_t index, uint8_t offset);
291 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
292 static void eth_igbvf_interrupt_handler(void *param);
293 static void igbvf_mbx_process(struct rte_eth_dev *dev);
294
295 /*
296 * Define VF Stats MACRO for Non "cleared on read" register
297 */
298 #define UPDATE_VF_STAT(reg, last, cur) \
299 { \
300 u32 latest = E1000_READ_REG(hw, reg); \
301 cur += (latest - last) & UINT_MAX; \
302 last = latest; \
303 }
304
305 #define IGB_FC_PAUSE_TIME 0x0680
306 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
307 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
308
309 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
310
311 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
312
313 /*
314 * The set of PCI devices this driver supports
315 */
316 static const struct rte_pci_id pci_id_igb_map[] = {
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
321 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
324 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
325
326 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
327 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
328 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
329
330 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
335 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
336
337 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
338 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
339 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
340 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
341 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
342 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
343 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
344 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
345 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
346 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
347 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
348 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
349 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
350 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
351 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
352 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
353 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
354 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
355 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
356 { .vendor_id = 0, /* sentinel */ },
357 };
358
359 /*
360 * The set of PCI devices this driver supports (for 82576&I350 VF)
361 */
362 static const struct rte_pci_id pci_id_igbvf_map[] = {
363 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
364 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
365 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
366 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
367 { .vendor_id = 0, /* sentinel */ },
368 };
369
370 static const struct rte_eth_desc_lim rx_desc_lim = {
371 .nb_max = E1000_MAX_RING_DESC,
372 .nb_min = E1000_MIN_RING_DESC,
373 .nb_align = IGB_RXD_ALIGN,
374 };
375
376 static const struct rte_eth_desc_lim tx_desc_lim = {
377 .nb_max = E1000_MAX_RING_DESC,
378 .nb_min = E1000_MIN_RING_DESC,
379 .nb_align = IGB_RXD_ALIGN,
380 .nb_seg_max = IGB_TX_MAX_SEG,
381 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
382 };
383
384 static const struct eth_dev_ops eth_igb_ops = {
385 .dev_configure = eth_igb_configure,
386 .dev_start = eth_igb_start,
387 .dev_stop = eth_igb_stop,
388 .dev_set_link_up = eth_igb_dev_set_link_up,
389 .dev_set_link_down = eth_igb_dev_set_link_down,
390 .dev_close = eth_igb_close,
391 .promiscuous_enable = eth_igb_promiscuous_enable,
392 .promiscuous_disable = eth_igb_promiscuous_disable,
393 .allmulticast_enable = eth_igb_allmulticast_enable,
394 .allmulticast_disable = eth_igb_allmulticast_disable,
395 .link_update = eth_igb_link_update,
396 .stats_get = eth_igb_stats_get,
397 .xstats_get = eth_igb_xstats_get,
398 .xstats_get_by_id = eth_igb_xstats_get_by_id,
399 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
400 .xstats_get_names = eth_igb_xstats_get_names,
401 .stats_reset = eth_igb_stats_reset,
402 .xstats_reset = eth_igb_xstats_reset,
403 .fw_version_get = eth_igb_fw_version_get,
404 .dev_infos_get = eth_igb_infos_get,
405 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
406 .mtu_set = eth_igb_mtu_set,
407 .vlan_filter_set = eth_igb_vlan_filter_set,
408 .vlan_tpid_set = eth_igb_vlan_tpid_set,
409 .vlan_offload_set = eth_igb_vlan_offload_set,
410 .rx_queue_setup = eth_igb_rx_queue_setup,
411 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
412 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
413 .rx_queue_release = eth_igb_rx_queue_release,
414 .rx_queue_count = eth_igb_rx_queue_count,
415 .rx_descriptor_done = eth_igb_rx_descriptor_done,
416 .rx_descriptor_status = eth_igb_rx_descriptor_status,
417 .tx_descriptor_status = eth_igb_tx_descriptor_status,
418 .tx_queue_setup = eth_igb_tx_queue_setup,
419 .tx_queue_release = eth_igb_tx_queue_release,
420 .tx_done_cleanup = eth_igb_tx_done_cleanup,
421 .dev_led_on = eth_igb_led_on,
422 .dev_led_off = eth_igb_led_off,
423 .flow_ctrl_get = eth_igb_flow_ctrl_get,
424 .flow_ctrl_set = eth_igb_flow_ctrl_set,
425 .mac_addr_add = eth_igb_rar_set,
426 .mac_addr_remove = eth_igb_rar_clear,
427 .mac_addr_set = eth_igb_default_mac_addr_set,
428 .reta_update = eth_igb_rss_reta_update,
429 .reta_query = eth_igb_rss_reta_query,
430 .rss_hash_update = eth_igb_rss_hash_update,
431 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
432 .filter_ctrl = eth_igb_filter_ctrl,
433 .set_mc_addr_list = eth_igb_set_mc_addr_list,
434 .rxq_info_get = igb_rxq_info_get,
435 .txq_info_get = igb_txq_info_get,
436 .timesync_enable = igb_timesync_enable,
437 .timesync_disable = igb_timesync_disable,
438 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
439 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
440 .get_reg = eth_igb_get_regs,
441 .get_eeprom_length = eth_igb_get_eeprom_length,
442 .get_eeprom = eth_igb_get_eeprom,
443 .set_eeprom = eth_igb_set_eeprom,
444 .timesync_adjust_time = igb_timesync_adjust_time,
445 .timesync_read_time = igb_timesync_read_time,
446 .timesync_write_time = igb_timesync_write_time,
447 };
448
449 /*
450 * dev_ops for virtual function, bare necessities for basic vf
451 * operation have been implemented
452 */
453 static const struct eth_dev_ops igbvf_eth_dev_ops = {
454 .dev_configure = igbvf_dev_configure,
455 .dev_start = igbvf_dev_start,
456 .dev_stop = igbvf_dev_stop,
457 .dev_close = igbvf_dev_close,
458 .promiscuous_enable = igbvf_promiscuous_enable,
459 .promiscuous_disable = igbvf_promiscuous_disable,
460 .allmulticast_enable = igbvf_allmulticast_enable,
461 .allmulticast_disable = igbvf_allmulticast_disable,
462 .link_update = eth_igb_link_update,
463 .stats_get = eth_igbvf_stats_get,
464 .xstats_get = eth_igbvf_xstats_get,
465 .xstats_get_names = eth_igbvf_xstats_get_names,
466 .stats_reset = eth_igbvf_stats_reset,
467 .xstats_reset = eth_igbvf_stats_reset,
468 .vlan_filter_set = igbvf_vlan_filter_set,
469 .dev_infos_get = eth_igbvf_infos_get,
470 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
471 .rx_queue_setup = eth_igb_rx_queue_setup,
472 .rx_queue_release = eth_igb_rx_queue_release,
473 .tx_queue_setup = eth_igb_tx_queue_setup,
474 .tx_queue_release = eth_igb_tx_queue_release,
475 .set_mc_addr_list = eth_igb_set_mc_addr_list,
476 .rxq_info_get = igb_rxq_info_get,
477 .txq_info_get = igb_txq_info_get,
478 .mac_addr_set = igbvf_default_mac_addr_set,
479 .get_reg = igbvf_get_regs,
480 };
481
482 /* store statistics names and its offset in stats structure */
483 struct rte_igb_xstats_name_off {
484 char name[RTE_ETH_XSTATS_NAME_SIZE];
485 unsigned offset;
486 };
487
488 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
489 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
490 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
491 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
492 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
493 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
494 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
495 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
496 ecol)},
497 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
498 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
499 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
500 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
501 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
502 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
503 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
504 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
505 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
506 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
507 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
508 fcruc)},
509 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
510 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
511 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
512 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
513 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
514 prc1023)},
515 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
516 prc1522)},
517 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
518 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
519 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
520 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
521 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
522 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
523 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
524 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
525 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
526 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
527 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
528 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
529 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
530 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
531 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
532 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
533 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
534 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
535 ptc1023)},
536 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
537 ptc1522)},
538 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
539 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
540 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
541 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
542 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
543 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
544 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
545
546 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
547 };
548
549 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
550 sizeof(rte_igb_stats_strings[0]))
551
552 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
553 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
554 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
555 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
556 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
557 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
558 };
559
560 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
561 sizeof(rte_igbvf_stats_strings[0]))
562
563 /**
564 * Atomically reads the link status information from global
565 * structure rte_eth_dev.
566 *
567 * @param dev
568 * - Pointer to the structure rte_eth_dev to read from.
569 * - Pointer to the buffer to be saved with the link status.
570 *
571 * @return
572 * - On success, zero.
573 * - On failure, negative value.
574 */
575 static inline int
576 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
577 struct rte_eth_link *link)
578 {
579 struct rte_eth_link *dst = link;
580 struct rte_eth_link *src = &(dev->data->dev_link);
581
582 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
583 *(uint64_t *)src) == 0)
584 return -1;
585
586 return 0;
587 }
588
589 /**
590 * Atomically writes the link status information into global
591 * structure rte_eth_dev.
592 *
593 * @param dev
594 * - Pointer to the structure rte_eth_dev to read from.
595 * - Pointer to the buffer to be saved with the link status.
596 *
597 * @return
598 * - On success, zero.
599 * - On failure, negative value.
600 */
601 static inline int
602 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
603 struct rte_eth_link *link)
604 {
605 struct rte_eth_link *dst = &(dev->data->dev_link);
606 struct rte_eth_link *src = link;
607
608 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
609 *(uint64_t *)src) == 0)
610 return -1;
611
612 return 0;
613 }
614
615 static inline void
616 igb_intr_enable(struct rte_eth_dev *dev)
617 {
618 struct e1000_interrupt *intr =
619 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
620 struct e1000_hw *hw =
621 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
622
623 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
624 E1000_WRITE_FLUSH(hw);
625 }
626
627 static void
628 igb_intr_disable(struct e1000_hw *hw)
629 {
630 E1000_WRITE_REG(hw, E1000_IMC, ~0);
631 E1000_WRITE_FLUSH(hw);
632 }
633
634 static inline void
635 igbvf_intr_enable(struct rte_eth_dev *dev)
636 {
637 struct e1000_hw *hw =
638 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
639
640 /* only for mailbox */
641 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
642 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
643 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
644 E1000_WRITE_FLUSH(hw);
645 }
646
647 /* only for mailbox now. If RX/TX needed, should extend this function. */
648 static void
649 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
650 {
651 uint32_t tmp = 0;
652
653 /* mailbox */
654 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
655 tmp |= E1000_VTIVAR_VALID;
656 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
657 }
658
659 static void
660 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
661 {
662 struct e1000_hw *hw =
663 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
664
665 /* Configure VF other cause ivar */
666 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
667 }
668
669 static inline int32_t
670 igb_pf_reset_hw(struct e1000_hw *hw)
671 {
672 uint32_t ctrl_ext;
673 int32_t status;
674
675 status = e1000_reset_hw(hw);
676
677 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
678 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
679 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
680 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
681 E1000_WRITE_FLUSH(hw);
682
683 return status;
684 }
685
686 static void
687 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
688 {
689 struct e1000_hw *hw =
690 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
691
692
693 hw->vendor_id = pci_dev->id.vendor_id;
694 hw->device_id = pci_dev->id.device_id;
695 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
696 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
697
698 e1000_set_mac_type(hw);
699
700 /* need to check if it is a vf device below */
701 }
702
703 static int
704 igb_reset_swfw_lock(struct e1000_hw *hw)
705 {
706 int ret_val;
707
708 /*
709 * Do mac ops initialization manually here, since we will need
710 * some function pointers set by this call.
711 */
712 ret_val = e1000_init_mac_params(hw);
713 if (ret_val)
714 return ret_val;
715
716 /*
717 * SMBI lock should not fail in this early stage. If this is the case,
718 * it is due to an improper exit of the application.
719 * So force the release of the faulty lock.
720 */
721 if (e1000_get_hw_semaphore_generic(hw) < 0) {
722 PMD_DRV_LOG(DEBUG, "SMBI lock released");
723 }
724 e1000_put_hw_semaphore_generic(hw);
725
726 if (hw->mac.ops.acquire_swfw_sync != NULL) {
727 uint16_t mask;
728
729 /*
730 * Phy lock should not fail in this early stage. If this is the case,
731 * it is due to an improper exit of the application.
732 * So force the release of the faulty lock.
733 */
734 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
735 if (hw->bus.func > E1000_FUNC_1)
736 mask <<= 2;
737 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
738 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
739 hw->bus.func);
740 }
741 hw->mac.ops.release_swfw_sync(hw, mask);
742
743 /*
744 * This one is more tricky since it is common to all ports; but
745 * swfw_sync retries last long enough (1s) to be almost sure that if
746 * lock can not be taken it is due to an improper lock of the
747 * semaphore.
748 */
749 mask = E1000_SWFW_EEP_SM;
750 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
751 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
752 }
753 hw->mac.ops.release_swfw_sync(hw, mask);
754 }
755
756 return E1000_SUCCESS;
757 }
758
759 static int
760 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
761 {
762 int error = 0;
763 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
764 struct e1000_hw *hw =
765 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
766 struct e1000_vfta * shadow_vfta =
767 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
768 struct e1000_filter_info *filter_info =
769 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
770 struct e1000_adapter *adapter =
771 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
772
773 uint32_t ctrl_ext;
774
775 eth_dev->dev_ops = &eth_igb_ops;
776 eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
777 eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
778 eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
779
780 /* for secondary processes, we don't initialise any further as primary
781 * has already done this work. Only check we don't need a different
782 * RX function */
783 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
784 if (eth_dev->data->scattered_rx)
785 eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
786 return 0;
787 }
788
789 rte_eth_copy_pci_info(eth_dev, pci_dev);
790 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
791
792 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
793
794 igb_identify_hardware(eth_dev, pci_dev);
795 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
796 error = -EIO;
797 goto err_late;
798 }
799
800 e1000_get_bus_info(hw);
801
802 /* Reset any pending lock */
803 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
804 error = -EIO;
805 goto err_late;
806 }
807
808 /* Finish initialization */
809 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
810 error = -EIO;
811 goto err_late;
812 }
813
814 hw->mac.autoneg = 1;
815 hw->phy.autoneg_wait_to_complete = 0;
816 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
817
818 /* Copper options */
819 if (hw->phy.media_type == e1000_media_type_copper) {
820 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
821 hw->phy.disable_polarity_correction = 0;
822 hw->phy.ms_type = e1000_ms_hw_default;
823 }
824
825 /*
826 * Start from a known state, this is important in reading the nvm
827 * and mac from that.
828 */
829 igb_pf_reset_hw(hw);
830
831 /* Make sure we have a good EEPROM before we read from it */
832 if (e1000_validate_nvm_checksum(hw) < 0) {
833 /*
834 * Some PCI-E parts fail the first check due to
835 * the link being in sleep state, call it again,
836 * if it fails a second time its a real issue.
837 */
838 if (e1000_validate_nvm_checksum(hw) < 0) {
839 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
840 error = -EIO;
841 goto err_late;
842 }
843 }
844
845 /* Read the permanent MAC address out of the EEPROM */
846 if (e1000_read_mac_addr(hw) != 0) {
847 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
848 error = -EIO;
849 goto err_late;
850 }
851
852 /* Allocate memory for storing MAC addresses */
853 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
854 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
855 if (eth_dev->data->mac_addrs == NULL) {
856 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
857 "store MAC addresses",
858 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
859 error = -ENOMEM;
860 goto err_late;
861 }
862
863 /* Copy the permanent MAC address */
864 ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
865
866 /* initialize the vfta */
867 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
868
869 /* Now initialize the hardware */
870 if (igb_hardware_init(hw) != 0) {
871 PMD_INIT_LOG(ERR, "Hardware initialization failed");
872 rte_free(eth_dev->data->mac_addrs);
873 eth_dev->data->mac_addrs = NULL;
874 error = -ENODEV;
875 goto err_late;
876 }
877 hw->mac.get_link_status = 1;
878 adapter->stopped = 0;
879
880 /* Indicate SOL/IDER usage */
881 if (e1000_check_reset_block(hw) < 0) {
882 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
883 "SOL/IDER session");
884 }
885
886 /* initialize PF if max_vfs not zero */
887 igb_pf_host_init(eth_dev);
888
889 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
890 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
891 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
892 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
893 E1000_WRITE_FLUSH(hw);
894
895 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
896 eth_dev->data->port_id, pci_dev->id.vendor_id,
897 pci_dev->id.device_id);
898
899 rte_intr_callback_register(&pci_dev->intr_handle,
900 eth_igb_interrupt_handler,
901 (void *)eth_dev);
902
903 /* enable uio/vfio intr/eventfd mapping */
904 rte_intr_enable(&pci_dev->intr_handle);
905
906 /* enable support intr */
907 igb_intr_enable(eth_dev);
908
909 TAILQ_INIT(&filter_info->flex_list);
910 filter_info->flex_mask = 0;
911 TAILQ_INIT(&filter_info->twotuple_list);
912 filter_info->twotuple_mask = 0;
913 TAILQ_INIT(&filter_info->fivetuple_list);
914 filter_info->fivetuple_mask = 0;
915
916 return 0;
917
918 err_late:
919 igb_hw_control_release(hw);
920
921 return error;
922 }
923
924 static int
925 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
926 {
927 struct rte_pci_device *pci_dev;
928 struct rte_intr_handle *intr_handle;
929 struct e1000_hw *hw;
930 struct e1000_adapter *adapter =
931 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
932
933 PMD_INIT_FUNC_TRACE();
934
935 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
936 return -EPERM;
937
938 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
939 pci_dev = E1000_DEV_TO_PCI(eth_dev);
940 intr_handle = &pci_dev->intr_handle;
941
942 if (adapter->stopped == 0)
943 eth_igb_close(eth_dev);
944
945 eth_dev->dev_ops = NULL;
946 eth_dev->rx_pkt_burst = NULL;
947 eth_dev->tx_pkt_burst = NULL;
948
949 /* Reset any pending lock */
950 igb_reset_swfw_lock(hw);
951
952 rte_free(eth_dev->data->mac_addrs);
953 eth_dev->data->mac_addrs = NULL;
954
955 /* uninitialize PF if max_vfs not zero */
956 igb_pf_host_uninit(eth_dev);
957
958 /* disable uio intr before callback unregister */
959 rte_intr_disable(intr_handle);
960 rte_intr_callback_unregister(intr_handle,
961 eth_igb_interrupt_handler, eth_dev);
962
963 return 0;
964 }
965
966 /*
967 * Virtual Function device init
968 */
969 static int
970 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
971 {
972 struct rte_pci_device *pci_dev;
973 struct rte_intr_handle *intr_handle;
974 struct e1000_adapter *adapter =
975 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
976 struct e1000_hw *hw =
977 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
978 int diag;
979 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
980
981 PMD_INIT_FUNC_TRACE();
982
983 eth_dev->dev_ops = &igbvf_eth_dev_ops;
984 eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
985 eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
986 eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
987
988 /* for secondary processes, we don't initialise any further as primary
989 * has already done this work. Only check we don't need a different
990 * RX function */
991 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
992 if (eth_dev->data->scattered_rx)
993 eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
994 return 0;
995 }
996
997 pci_dev = E1000_DEV_TO_PCI(eth_dev);
998 rte_eth_copy_pci_info(eth_dev, pci_dev);
999 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1000
1001 hw->device_id = pci_dev->id.device_id;
1002 hw->vendor_id = pci_dev->id.vendor_id;
1003 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1004 adapter->stopped = 0;
1005
1006 /* Initialize the shared code (base driver) */
1007 diag = e1000_setup_init_funcs(hw, TRUE);
1008 if (diag != 0) {
1009 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1010 diag);
1011 return -EIO;
1012 }
1013
1014 /* init_mailbox_params */
1015 hw->mbx.ops.init_params(hw);
1016
1017 /* Disable the interrupts for VF */
1018 igbvf_intr_disable(hw);
1019
1020 diag = hw->mac.ops.reset_hw(hw);
1021
1022 /* Allocate memory for storing MAC addresses */
1023 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1024 hw->mac.rar_entry_count, 0);
1025 if (eth_dev->data->mac_addrs == NULL) {
1026 PMD_INIT_LOG(ERR,
1027 "Failed to allocate %d bytes needed to store MAC "
1028 "addresses",
1029 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1030 return -ENOMEM;
1031 }
1032
1033 /* Generate a random MAC address, if none was assigned by PF. */
1034 if (is_zero_ether_addr(perm_addr)) {
1035 eth_random_addr(perm_addr->addr_bytes);
1036 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1037 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1038 "%02x:%02x:%02x:%02x:%02x:%02x",
1039 perm_addr->addr_bytes[0],
1040 perm_addr->addr_bytes[1],
1041 perm_addr->addr_bytes[2],
1042 perm_addr->addr_bytes[3],
1043 perm_addr->addr_bytes[4],
1044 perm_addr->addr_bytes[5]);
1045 }
1046
1047 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1048 if (diag) {
1049 rte_free(eth_dev->data->mac_addrs);
1050 eth_dev->data->mac_addrs = NULL;
1051 return diag;
1052 }
1053 /* Copy the permanent MAC address */
1054 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1055 &eth_dev->data->mac_addrs[0]);
1056
1057 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1058 "mac.type=%s",
1059 eth_dev->data->port_id, pci_dev->id.vendor_id,
1060 pci_dev->id.device_id, "igb_mac_82576_vf");
1061
1062 intr_handle = &pci_dev->intr_handle;
1063 rte_intr_callback_register(intr_handle,
1064 eth_igbvf_interrupt_handler, eth_dev);
1065
1066 return 0;
1067 }
1068
1069 static int
1070 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1071 {
1072 struct e1000_adapter *adapter =
1073 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1074 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
1075
1076 PMD_INIT_FUNC_TRACE();
1077
1078 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1079 return -EPERM;
1080
1081 if (adapter->stopped == 0)
1082 igbvf_dev_close(eth_dev);
1083
1084 eth_dev->dev_ops = NULL;
1085 eth_dev->rx_pkt_burst = NULL;
1086 eth_dev->tx_pkt_burst = NULL;
1087
1088 rte_free(eth_dev->data->mac_addrs);
1089 eth_dev->data->mac_addrs = NULL;
1090
1091 /* disable uio intr before callback unregister */
1092 rte_intr_disable(&pci_dev->intr_handle);
1093 rte_intr_callback_unregister(&pci_dev->intr_handle,
1094 eth_igbvf_interrupt_handler,
1095 (void *)eth_dev);
1096
1097 return 0;
1098 }
1099
1100 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1101 struct rte_pci_device *pci_dev)
1102 {
1103 return rte_eth_dev_pci_generic_probe(pci_dev,
1104 sizeof(struct e1000_adapter), eth_igb_dev_init);
1105 }
1106
1107 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1108 {
1109 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1110 }
1111
1112 static struct rte_pci_driver rte_igb_pmd = {
1113 .id_table = pci_id_igb_map,
1114 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1115 .probe = eth_igb_pci_probe,
1116 .remove = eth_igb_pci_remove,
1117 };
1118
1119
1120 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1121 struct rte_pci_device *pci_dev)
1122 {
1123 return rte_eth_dev_pci_generic_probe(pci_dev,
1124 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1125 }
1126
1127 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1128 {
1129 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1130 }
1131
1132 /*
1133 * virtual function driver struct
1134 */
1135 static struct rte_pci_driver rte_igbvf_pmd = {
1136 .id_table = pci_id_igbvf_map,
1137 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1138 .probe = eth_igbvf_pci_probe,
1139 .remove = eth_igbvf_pci_remove,
1140 };
1141
1142 static void
1143 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1144 {
1145 struct e1000_hw *hw =
1146 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1147 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1148 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1149 rctl |= E1000_RCTL_VFE;
1150 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1151 }
1152
1153 static int
1154 igb_check_mq_mode(struct rte_eth_dev *dev)
1155 {
1156 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1157 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1158 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1159 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1160
1161 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1162 tx_mq_mode == ETH_MQ_TX_DCB ||
1163 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1164 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1165 return -EINVAL;
1166 }
1167 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1168 /* Check multi-queue mode.
1169 * To no break software we accept ETH_MQ_RX_NONE as this might
1170 * be used to turn off VLAN filter.
1171 */
1172
1173 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1174 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1175 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1176 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1177 } else {
1178 /* Only support one queue on VFs.
1179 * RSS together with SRIOV is not supported.
1180 */
1181 PMD_INIT_LOG(ERR, "SRIOV is active,"
1182 " wrong mq_mode rx %d.",
1183 rx_mq_mode);
1184 return -EINVAL;
1185 }
1186 /* TX mode is not used here, so mode might be ignored.*/
1187 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1188 /* SRIOV only works in VMDq enable mode */
1189 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1190 " TX mode %d is not supported. "
1191 " Driver will behave as %d mode.",
1192 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1193 }
1194
1195 /* check valid queue number */
1196 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1197 PMD_INIT_LOG(ERR, "SRIOV is active,"
1198 " only support one queue on VFs.");
1199 return -EINVAL;
1200 }
1201 } else {
1202 /* To no break software that set invalid mode, only display
1203 * warning if invalid mode is used.
1204 */
1205 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1206 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1207 rx_mq_mode != ETH_MQ_RX_RSS) {
1208 /* RSS together with VMDq not supported*/
1209 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1210 rx_mq_mode);
1211 return -EINVAL;
1212 }
1213
1214 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1215 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1216 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1217 " Due to txmode is meaningless in this"
1218 " driver, just ignore.",
1219 tx_mq_mode);
1220 }
1221 }
1222 return 0;
1223 }
1224
1225 static int
1226 eth_igb_configure(struct rte_eth_dev *dev)
1227 {
1228 struct e1000_interrupt *intr =
1229 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1230 int ret;
1231
1232 PMD_INIT_FUNC_TRACE();
1233
1234 /* multipe queue mode checking */
1235 ret = igb_check_mq_mode(dev);
1236 if (ret != 0) {
1237 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1238 ret);
1239 return ret;
1240 }
1241
1242 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1243 PMD_INIT_FUNC_TRACE();
1244
1245 return 0;
1246 }
1247
1248 static int
1249 eth_igb_start(struct rte_eth_dev *dev)
1250 {
1251 struct e1000_hw *hw =
1252 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1253 struct e1000_adapter *adapter =
1254 E1000_DEV_PRIVATE(dev->data->dev_private);
1255 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1256 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1257 int ret, mask;
1258 uint32_t intr_vector = 0;
1259 uint32_t ctrl_ext;
1260 uint32_t *speeds;
1261 int num_speeds;
1262 bool autoneg;
1263
1264 PMD_INIT_FUNC_TRACE();
1265
1266 /* disable uio/vfio intr/eventfd mapping */
1267 rte_intr_disable(intr_handle);
1268
1269 /* Power up the phy. Needed to make the link go Up */
1270 eth_igb_dev_set_link_up(dev);
1271
1272 /*
1273 * Packet Buffer Allocation (PBA)
1274 * Writing PBA sets the receive portion of the buffer
1275 * the remainder is used for the transmit buffer.
1276 */
1277 if (hw->mac.type == e1000_82575) {
1278 uint32_t pba;
1279
1280 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1281 E1000_WRITE_REG(hw, E1000_PBA, pba);
1282 }
1283
1284 /* Put the address into the Receive Address Array */
1285 e1000_rar_set(hw, hw->mac.addr, 0);
1286
1287 /* Initialize the hardware */
1288 if (igb_hardware_init(hw)) {
1289 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1290 return -EIO;
1291 }
1292 adapter->stopped = 0;
1293
1294 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1295
1296 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1297 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1298 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1299 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1300 E1000_WRITE_FLUSH(hw);
1301
1302 /* configure PF module if SRIOV enabled */
1303 igb_pf_host_configure(dev);
1304
1305 /* check and configure queue intr-vector mapping */
1306 if ((rte_intr_cap_multiple(intr_handle) ||
1307 !RTE_ETH_DEV_SRIOV(dev).active) &&
1308 dev->data->dev_conf.intr_conf.rxq != 0) {
1309 intr_vector = dev->data->nb_rx_queues;
1310 if (rte_intr_efd_enable(intr_handle, intr_vector))
1311 return -1;
1312 }
1313
1314 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1315 intr_handle->intr_vec =
1316 rte_zmalloc("intr_vec",
1317 dev->data->nb_rx_queues * sizeof(int), 0);
1318 if (intr_handle->intr_vec == NULL) {
1319 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1320 " intr_vec", dev->data->nb_rx_queues);
1321 return -ENOMEM;
1322 }
1323 }
1324
1325 /* confiugre msix for rx interrupt */
1326 eth_igb_configure_msix_intr(dev);
1327
1328 /* Configure for OS presence */
1329 igb_init_manageability(hw);
1330
1331 eth_igb_tx_init(dev);
1332
1333 /* This can fail when allocating mbufs for descriptor rings */
1334 ret = eth_igb_rx_init(dev);
1335 if (ret) {
1336 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1337 igb_dev_clear_queues(dev);
1338 return ret;
1339 }
1340
1341 e1000_clear_hw_cntrs_base_generic(hw);
1342
1343 /*
1344 * VLAN Offload Settings
1345 */
1346 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1347 ETH_VLAN_EXTEND_MASK;
1348 eth_igb_vlan_offload_set(dev, mask);
1349
1350 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1351 /* Enable VLAN filter since VMDq always use VLAN filter */
1352 igb_vmdq_vlan_hw_filter_enable(dev);
1353 }
1354
1355 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1356 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1357 (hw->mac.type == e1000_i211)) {
1358 /* Configure EITR with the maximum possible value (0xFFFF) */
1359 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1360 }
1361
1362 /* Setup link speed and duplex */
1363 speeds = &dev->data->dev_conf.link_speeds;
1364 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1365 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1366 hw->mac.autoneg = 1;
1367 } else {
1368 num_speeds = 0;
1369 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1370
1371 /* Reset */
1372 hw->phy.autoneg_advertised = 0;
1373
1374 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1375 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1376 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1377 num_speeds = -1;
1378 goto error_invalid_config;
1379 }
1380 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1381 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1382 num_speeds++;
1383 }
1384 if (*speeds & ETH_LINK_SPEED_10M) {
1385 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1386 num_speeds++;
1387 }
1388 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1389 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1390 num_speeds++;
1391 }
1392 if (*speeds & ETH_LINK_SPEED_100M) {
1393 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1394 num_speeds++;
1395 }
1396 if (*speeds & ETH_LINK_SPEED_1G) {
1397 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1398 num_speeds++;
1399 }
1400 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1401 goto error_invalid_config;
1402
1403 /* Set/reset the mac.autoneg based on the link speed,
1404 * fixed or not
1405 */
1406 if (!autoneg) {
1407 hw->mac.autoneg = 0;
1408 hw->mac.forced_speed_duplex =
1409 hw->phy.autoneg_advertised;
1410 } else {
1411 hw->mac.autoneg = 1;
1412 }
1413 }
1414
1415 e1000_setup_link(hw);
1416
1417 if (rte_intr_allow_others(intr_handle)) {
1418 /* check if lsc interrupt is enabled */
1419 if (dev->data->dev_conf.intr_conf.lsc != 0)
1420 eth_igb_lsc_interrupt_setup(dev);
1421 } else {
1422 rte_intr_callback_unregister(intr_handle,
1423 eth_igb_interrupt_handler,
1424 (void *)dev);
1425 if (dev->data->dev_conf.intr_conf.lsc != 0)
1426 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1427 " no intr multiplex");
1428 }
1429
1430 /* check if rxq interrupt is enabled */
1431 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1432 rte_intr_dp_is_en(intr_handle))
1433 eth_igb_rxq_interrupt_setup(dev);
1434
1435 /* enable uio/vfio intr/eventfd mapping */
1436 rte_intr_enable(intr_handle);
1437
1438 /* resume enabled intr since hw reset */
1439 igb_intr_enable(dev);
1440
1441 PMD_INIT_LOG(DEBUG, "<<");
1442
1443 return 0;
1444
1445 error_invalid_config:
1446 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1447 dev->data->dev_conf.link_speeds, dev->data->port_id);
1448 igb_dev_clear_queues(dev);
1449 return -EINVAL;
1450 }
1451
1452 /*********************************************************************
1453 *
1454 * This routine disables all traffic on the adapter by issuing a
1455 * global reset on the MAC.
1456 *
1457 **********************************************************************/
1458 static void
1459 eth_igb_stop(struct rte_eth_dev *dev)
1460 {
1461 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1462 struct e1000_filter_info *filter_info =
1463 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1464 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1465 struct rte_eth_link link;
1466 struct e1000_flex_filter *p_flex;
1467 struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1468 struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1469 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1470
1471 igb_intr_disable(hw);
1472
1473 /* disable intr eventfd mapping */
1474 rte_intr_disable(intr_handle);
1475
1476 igb_pf_reset_hw(hw);
1477 E1000_WRITE_REG(hw, E1000_WUC, 0);
1478
1479 /* Set bit for Go Link disconnect */
1480 if (hw->mac.type >= e1000_82580) {
1481 uint32_t phpm_reg;
1482
1483 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1484 phpm_reg |= E1000_82580_PM_GO_LINKD;
1485 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1486 }
1487
1488 /* Power down the phy. Needed to make the link go Down */
1489 eth_igb_dev_set_link_down(dev);
1490
1491 igb_dev_clear_queues(dev);
1492
1493 /* clear the recorded link status */
1494 memset(&link, 0, sizeof(link));
1495 rte_igb_dev_atomic_write_link_status(dev, &link);
1496
1497 /* Remove all flex filters of the device */
1498 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1499 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1500 rte_free(p_flex);
1501 }
1502 filter_info->flex_mask = 0;
1503
1504 /* Remove all ntuple filters of the device */
1505 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1506 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1507 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1508 TAILQ_REMOVE(&filter_info->fivetuple_list,
1509 p_5tuple, entries);
1510 rte_free(p_5tuple);
1511 }
1512 filter_info->fivetuple_mask = 0;
1513 for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1514 p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1515 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1516 TAILQ_REMOVE(&filter_info->twotuple_list,
1517 p_2tuple, entries);
1518 rte_free(p_2tuple);
1519 }
1520 filter_info->twotuple_mask = 0;
1521
1522 if (!rte_intr_allow_others(intr_handle))
1523 /* resume to the default handler */
1524 rte_intr_callback_register(intr_handle,
1525 eth_igb_interrupt_handler,
1526 (void *)dev);
1527
1528 /* Clean datapath event and queue/vec mapping */
1529 rte_intr_efd_disable(intr_handle);
1530 if (intr_handle->intr_vec != NULL) {
1531 rte_free(intr_handle->intr_vec);
1532 intr_handle->intr_vec = NULL;
1533 }
1534 }
1535
1536 static int
1537 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1538 {
1539 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1540
1541 if (hw->phy.media_type == e1000_media_type_copper)
1542 e1000_power_up_phy(hw);
1543 else
1544 e1000_power_up_fiber_serdes_link(hw);
1545
1546 return 0;
1547 }
1548
1549 static int
1550 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1551 {
1552 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1553
1554 if (hw->phy.media_type == e1000_media_type_copper)
1555 e1000_power_down_phy(hw);
1556 else
1557 e1000_shutdown_fiber_serdes_link(hw);
1558
1559 return 0;
1560 }
1561
1562 static void
1563 eth_igb_close(struct rte_eth_dev *dev)
1564 {
1565 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1566 struct e1000_adapter *adapter =
1567 E1000_DEV_PRIVATE(dev->data->dev_private);
1568 struct rte_eth_link link;
1569 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1570 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1571
1572 eth_igb_stop(dev);
1573 adapter->stopped = 1;
1574
1575 e1000_phy_hw_reset(hw);
1576 igb_release_manageability(hw);
1577 igb_hw_control_release(hw);
1578
1579 /* Clear bit for Go Link disconnect */
1580 if (hw->mac.type >= e1000_82580) {
1581 uint32_t phpm_reg;
1582
1583 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1584 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1585 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1586 }
1587
1588 igb_dev_free_queues(dev);
1589
1590 if (intr_handle->intr_vec) {
1591 rte_free(intr_handle->intr_vec);
1592 intr_handle->intr_vec = NULL;
1593 }
1594
1595 memset(&link, 0, sizeof(link));
1596 rte_igb_dev_atomic_write_link_status(dev, &link);
1597 }
1598
1599 static int
1600 igb_get_rx_buffer_size(struct e1000_hw *hw)
1601 {
1602 uint32_t rx_buf_size;
1603 if (hw->mac.type == e1000_82576) {
1604 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1605 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1606 /* PBS needs to be translated according to a lookup table */
1607 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1608 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1609 rx_buf_size = (rx_buf_size << 10);
1610 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1611 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1612 } else {
1613 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1614 }
1615
1616 return rx_buf_size;
1617 }
1618
1619 /*********************************************************************
1620 *
1621 * Initialize the hardware
1622 *
1623 **********************************************************************/
1624 static int
1625 igb_hardware_init(struct e1000_hw *hw)
1626 {
1627 uint32_t rx_buf_size;
1628 int diag;
1629
1630 /* Let the firmware know the OS is in control */
1631 igb_hw_control_acquire(hw);
1632
1633 /*
1634 * These parameters control the automatic generation (Tx) and
1635 * response (Rx) to Ethernet PAUSE frames.
1636 * - High water mark should allow for at least two standard size (1518)
1637 * frames to be received after sending an XOFF.
1638 * - Low water mark works best when it is very near the high water mark.
1639 * This allows the receiver to restart by sending XON when it has
1640 * drained a bit. Here we use an arbitrary value of 1500 which will
1641 * restart after one full frame is pulled from the buffer. There
1642 * could be several smaller frames in the buffer and if so they will
1643 * not trigger the XON until their total number reduces the buffer
1644 * by 1500.
1645 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1646 */
1647 rx_buf_size = igb_get_rx_buffer_size(hw);
1648
1649 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1650 hw->fc.low_water = hw->fc.high_water - 1500;
1651 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1652 hw->fc.send_xon = 1;
1653
1654 /* Set Flow control, use the tunable location if sane */
1655 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1656 hw->fc.requested_mode = igb_fc_setting;
1657 else
1658 hw->fc.requested_mode = e1000_fc_none;
1659
1660 /* Issue a global reset */
1661 igb_pf_reset_hw(hw);
1662 E1000_WRITE_REG(hw, E1000_WUC, 0);
1663
1664 diag = e1000_init_hw(hw);
1665 if (diag < 0)
1666 return diag;
1667
1668 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1669 e1000_get_phy_info(hw);
1670 e1000_check_for_link(hw);
1671
1672 return 0;
1673 }
1674
1675 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1676 static void
1677 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1678 {
1679 int pause_frames;
1680
1681 uint64_t old_gprc = stats->gprc;
1682 uint64_t old_gptc = stats->gptc;
1683 uint64_t old_tpr = stats->tpr;
1684 uint64_t old_tpt = stats->tpt;
1685 uint64_t old_rpthc = stats->rpthc;
1686 uint64_t old_hgptc = stats->hgptc;
1687
1688 if(hw->phy.media_type == e1000_media_type_copper ||
1689 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1690 stats->symerrs +=
1691 E1000_READ_REG(hw,E1000_SYMERRS);
1692 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1693 }
1694
1695 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1696 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1697 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1698 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1699
1700 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1701 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1702 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1703 stats->dc += E1000_READ_REG(hw, E1000_DC);
1704 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1705 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1706 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1707 /*
1708 ** For watchdog management we need to know if we have been
1709 ** paused during the last interval, so capture that here.
1710 */
1711 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1712 stats->xoffrxc += pause_frames;
1713 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1714 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1715 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1716 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1717 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1718 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1719 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1720 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1721 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1722 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1723 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1724 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1725
1726 /* For the 64-bit byte counters the low dword must be read first. */
1727 /* Both registers clear on the read of the high dword */
1728
1729 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1730 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1731 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1732 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1733 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1734 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1735 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1736
1737 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1738 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1739 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1740 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1741 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1742
1743 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1744 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1745
1746 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1747 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1748 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1749 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1750 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1751 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1752
1753 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1754 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1755 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1756 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1757 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1758 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1759 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1760 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1761
1762 /* Interrupt Counts */
1763
1764 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1765 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1766 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1767 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1768 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1769 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1770 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1771 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1772 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1773
1774 /* Host to Card Statistics */
1775
1776 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1777 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1778 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1779 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1780 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1781 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1782 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1783 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1784 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1785 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1786 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1787 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1788 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1789 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1790 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1791 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1792
1793 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1794 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1795 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1796 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1797 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1798 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1799 }
1800
1801 static void
1802 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1803 {
1804 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1805 struct e1000_hw_stats *stats =
1806 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1807
1808 igb_read_stats_registers(hw, stats);
1809
1810 if (rte_stats == NULL)
1811 return;
1812
1813 /* Rx Errors */
1814 rte_stats->imissed = stats->mpc;
1815 rte_stats->ierrors = stats->crcerrs +
1816 stats->rlec + stats->ruc + stats->roc +
1817 stats->rxerrc + stats->algnerrc + stats->cexterr;
1818
1819 /* Tx Errors */
1820 rte_stats->oerrors = stats->ecol + stats->latecol;
1821
1822 rte_stats->ipackets = stats->gprc;
1823 rte_stats->opackets = stats->gptc;
1824 rte_stats->ibytes = stats->gorc;
1825 rte_stats->obytes = stats->gotc;
1826 }
1827
1828 static void
1829 eth_igb_stats_reset(struct rte_eth_dev *dev)
1830 {
1831 struct e1000_hw_stats *hw_stats =
1832 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1833
1834 /* HW registers are cleared on read */
1835 eth_igb_stats_get(dev, NULL);
1836
1837 /* Reset software totals */
1838 memset(hw_stats, 0, sizeof(*hw_stats));
1839 }
1840
1841 static void
1842 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1843 {
1844 struct e1000_hw_stats *stats =
1845 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1846
1847 /* HW registers are cleared on read */
1848 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1849
1850 /* Reset software totals */
1851 memset(stats, 0, sizeof(*stats));
1852 }
1853
1854 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1855 struct rte_eth_xstat_name *xstats_names,
1856 __rte_unused unsigned int size)
1857 {
1858 unsigned i;
1859
1860 if (xstats_names == NULL)
1861 return IGB_NB_XSTATS;
1862
1863 /* Note: limit checked in rte_eth_xstats_names() */
1864
1865 for (i = 0; i < IGB_NB_XSTATS; i++) {
1866 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1867 "%s", rte_igb_stats_strings[i].name);
1868 }
1869
1870 return IGB_NB_XSTATS;
1871 }
1872
1873 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1874 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1875 unsigned int limit)
1876 {
1877 unsigned int i;
1878
1879 if (!ids) {
1880 if (xstats_names == NULL)
1881 return IGB_NB_XSTATS;
1882
1883 for (i = 0; i < IGB_NB_XSTATS; i++)
1884 snprintf(xstats_names[i].name,
1885 sizeof(xstats_names[i].name),
1886 "%s", rte_igb_stats_strings[i].name);
1887
1888 return IGB_NB_XSTATS;
1889
1890 } else {
1891 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1892
1893 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1894 IGB_NB_XSTATS);
1895
1896 for (i = 0; i < limit; i++) {
1897 if (ids[i] >= IGB_NB_XSTATS) {
1898 PMD_INIT_LOG(ERR, "id value isn't valid");
1899 return -1;
1900 }
1901 strcpy(xstats_names[i].name,
1902 xstats_names_copy[ids[i]].name);
1903 }
1904 return limit;
1905 }
1906 }
1907
1908 static int
1909 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1910 unsigned n)
1911 {
1912 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913 struct e1000_hw_stats *hw_stats =
1914 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1915 unsigned i;
1916
1917 if (n < IGB_NB_XSTATS)
1918 return IGB_NB_XSTATS;
1919
1920 igb_read_stats_registers(hw, hw_stats);
1921
1922 /* If this is a reset xstats is NULL, and we have cleared the
1923 * registers by reading them.
1924 */
1925 if (!xstats)
1926 return 0;
1927
1928 /* Extended stats */
1929 for (i = 0; i < IGB_NB_XSTATS; i++) {
1930 xstats[i].id = i;
1931 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1932 rte_igb_stats_strings[i].offset);
1933 }
1934
1935 return IGB_NB_XSTATS;
1936 }
1937
1938 static int
1939 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1940 uint64_t *values, unsigned int n)
1941 {
1942 unsigned int i;
1943
1944 if (!ids) {
1945 struct e1000_hw *hw =
1946 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1947 struct e1000_hw_stats *hw_stats =
1948 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1949
1950 if (n < IGB_NB_XSTATS)
1951 return IGB_NB_XSTATS;
1952
1953 igb_read_stats_registers(hw, hw_stats);
1954
1955 /* If this is a reset xstats is NULL, and we have cleared the
1956 * registers by reading them.
1957 */
1958 if (!values)
1959 return 0;
1960
1961 /* Extended stats */
1962 for (i = 0; i < IGB_NB_XSTATS; i++)
1963 values[i] = *(uint64_t *)(((char *)hw_stats) +
1964 rte_igb_stats_strings[i].offset);
1965
1966 return IGB_NB_XSTATS;
1967
1968 } else {
1969 uint64_t values_copy[IGB_NB_XSTATS];
1970
1971 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1972 IGB_NB_XSTATS);
1973
1974 for (i = 0; i < n; i++) {
1975 if (ids[i] >= IGB_NB_XSTATS) {
1976 PMD_INIT_LOG(ERR, "id value isn't valid");
1977 return -1;
1978 }
1979 values[i] = values_copy[ids[i]];
1980 }
1981 return n;
1982 }
1983 }
1984
1985 static void
1986 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1987 {
1988 /* Good Rx packets, include VF loopback */
1989 UPDATE_VF_STAT(E1000_VFGPRC,
1990 hw_stats->last_gprc, hw_stats->gprc);
1991
1992 /* Good Rx octets, include VF loopback */
1993 UPDATE_VF_STAT(E1000_VFGORC,
1994 hw_stats->last_gorc, hw_stats->gorc);
1995
1996 /* Good Tx packets, include VF loopback */
1997 UPDATE_VF_STAT(E1000_VFGPTC,
1998 hw_stats->last_gptc, hw_stats->gptc);
1999
2000 /* Good Tx octets, include VF loopback */
2001 UPDATE_VF_STAT(E1000_VFGOTC,
2002 hw_stats->last_gotc, hw_stats->gotc);
2003
2004 /* Rx Multicst packets */
2005 UPDATE_VF_STAT(E1000_VFMPRC,
2006 hw_stats->last_mprc, hw_stats->mprc);
2007
2008 /* Good Rx loopback packets */
2009 UPDATE_VF_STAT(E1000_VFGPRLBC,
2010 hw_stats->last_gprlbc, hw_stats->gprlbc);
2011
2012 /* Good Rx loopback octets */
2013 UPDATE_VF_STAT(E1000_VFGORLBC,
2014 hw_stats->last_gorlbc, hw_stats->gorlbc);
2015
2016 /* Good Tx loopback packets */
2017 UPDATE_VF_STAT(E1000_VFGPTLBC,
2018 hw_stats->last_gptlbc, hw_stats->gptlbc);
2019
2020 /* Good Tx loopback octets */
2021 UPDATE_VF_STAT(E1000_VFGOTLBC,
2022 hw_stats->last_gotlbc, hw_stats->gotlbc);
2023 }
2024
2025 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2026 struct rte_eth_xstat_name *xstats_names,
2027 __rte_unused unsigned limit)
2028 {
2029 unsigned i;
2030
2031 if (xstats_names != NULL)
2032 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2033 snprintf(xstats_names[i].name,
2034 sizeof(xstats_names[i].name), "%s",
2035 rte_igbvf_stats_strings[i].name);
2036 }
2037 return IGBVF_NB_XSTATS;
2038 }
2039
2040 static int
2041 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2042 unsigned n)
2043 {
2044 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2046 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2047 unsigned i;
2048
2049 if (n < IGBVF_NB_XSTATS)
2050 return IGBVF_NB_XSTATS;
2051
2052 igbvf_read_stats_registers(hw, hw_stats);
2053
2054 if (!xstats)
2055 return 0;
2056
2057 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2058 xstats[i].id = i;
2059 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2060 rte_igbvf_stats_strings[i].offset);
2061 }
2062
2063 return IGBVF_NB_XSTATS;
2064 }
2065
2066 static void
2067 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2068 {
2069 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2070 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2071 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2072
2073 igbvf_read_stats_registers(hw, hw_stats);
2074
2075 if (rte_stats == NULL)
2076 return;
2077
2078 rte_stats->ipackets = hw_stats->gprc;
2079 rte_stats->ibytes = hw_stats->gorc;
2080 rte_stats->opackets = hw_stats->gptc;
2081 rte_stats->obytes = hw_stats->gotc;
2082 }
2083
2084 static void
2085 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2086 {
2087 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2088 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2089
2090 /* Sync HW register to the last stats */
2091 eth_igbvf_stats_get(dev, NULL);
2092
2093 /* reset HW current stats*/
2094 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2095 offsetof(struct e1000_vf_stats, gprc));
2096 }
2097
2098 static int
2099 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2100 size_t fw_size)
2101 {
2102 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103 struct e1000_fw_version fw;
2104 int ret;
2105
2106 e1000_get_fw_version(hw, &fw);
2107
2108 switch (hw->mac.type) {
2109 case e1000_i210:
2110 case e1000_i211:
2111 if (!(e1000_get_flash_presence_i210(hw))) {
2112 ret = snprintf(fw_version, fw_size,
2113 "%2d.%2d-%d",
2114 fw.invm_major, fw.invm_minor,
2115 fw.invm_img_type);
2116 break;
2117 }
2118 /* fall through */
2119 default:
2120 /* if option rom is valid, display its version too */
2121 if (fw.or_valid) {
2122 ret = snprintf(fw_version, fw_size,
2123 "%d.%d, 0x%08x, %d.%d.%d",
2124 fw.eep_major, fw.eep_minor, fw.etrack_id,
2125 fw.or_major, fw.or_build, fw.or_patch);
2126 /* no option rom */
2127 } else {
2128 if (fw.etrack_id != 0X0000) {
2129 ret = snprintf(fw_version, fw_size,
2130 "%d.%d, 0x%08x",
2131 fw.eep_major, fw.eep_minor,
2132 fw.etrack_id);
2133 } else {
2134 ret = snprintf(fw_version, fw_size,
2135 "%d.%d.%d",
2136 fw.eep_major, fw.eep_minor,
2137 fw.eep_build);
2138 }
2139 }
2140 break;
2141 }
2142
2143 ret += 1; /* add the size of '\0' */
2144 if (fw_size < (u32)ret)
2145 return ret;
2146 else
2147 return 0;
2148 }
2149
2150 static void
2151 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2152 {
2153 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2154
2155 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2156 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2157 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2158 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2159 dev_info->rx_offload_capa =
2160 DEV_RX_OFFLOAD_VLAN_STRIP |
2161 DEV_RX_OFFLOAD_IPV4_CKSUM |
2162 DEV_RX_OFFLOAD_UDP_CKSUM |
2163 DEV_RX_OFFLOAD_TCP_CKSUM;
2164 dev_info->tx_offload_capa =
2165 DEV_TX_OFFLOAD_VLAN_INSERT |
2166 DEV_TX_OFFLOAD_IPV4_CKSUM |
2167 DEV_TX_OFFLOAD_UDP_CKSUM |
2168 DEV_TX_OFFLOAD_TCP_CKSUM |
2169 DEV_TX_OFFLOAD_SCTP_CKSUM |
2170 DEV_TX_OFFLOAD_TCP_TSO;
2171
2172 switch (hw->mac.type) {
2173 case e1000_82575:
2174 dev_info->max_rx_queues = 4;
2175 dev_info->max_tx_queues = 4;
2176 dev_info->max_vmdq_pools = 0;
2177 break;
2178
2179 case e1000_82576:
2180 dev_info->max_rx_queues = 16;
2181 dev_info->max_tx_queues = 16;
2182 dev_info->max_vmdq_pools = ETH_8_POOLS;
2183 dev_info->vmdq_queue_num = 16;
2184 break;
2185
2186 case e1000_82580:
2187 dev_info->max_rx_queues = 8;
2188 dev_info->max_tx_queues = 8;
2189 dev_info->max_vmdq_pools = ETH_8_POOLS;
2190 dev_info->vmdq_queue_num = 8;
2191 break;
2192
2193 case e1000_i350:
2194 dev_info->max_rx_queues = 8;
2195 dev_info->max_tx_queues = 8;
2196 dev_info->max_vmdq_pools = ETH_8_POOLS;
2197 dev_info->vmdq_queue_num = 8;
2198 break;
2199
2200 case e1000_i354:
2201 dev_info->max_rx_queues = 8;
2202 dev_info->max_tx_queues = 8;
2203 break;
2204
2205 case e1000_i210:
2206 dev_info->max_rx_queues = 4;
2207 dev_info->max_tx_queues = 4;
2208 dev_info->max_vmdq_pools = 0;
2209 break;
2210
2211 case e1000_i211:
2212 dev_info->max_rx_queues = 2;
2213 dev_info->max_tx_queues = 2;
2214 dev_info->max_vmdq_pools = 0;
2215 break;
2216
2217 default:
2218 /* Should not happen */
2219 break;
2220 }
2221 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2222 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2223 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2224
2225 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2226 .rx_thresh = {
2227 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2228 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2229 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2230 },
2231 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2232 .rx_drop_en = 0,
2233 };
2234
2235 dev_info->default_txconf = (struct rte_eth_txconf) {
2236 .tx_thresh = {
2237 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2238 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2239 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2240 },
2241 .txq_flags = 0,
2242 };
2243
2244 dev_info->rx_desc_lim = rx_desc_lim;
2245 dev_info->tx_desc_lim = tx_desc_lim;
2246
2247 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2248 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2249 ETH_LINK_SPEED_1G;
2250 }
2251
2252 static const uint32_t *
2253 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2254 {
2255 static const uint32_t ptypes[] = {
2256 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2257 RTE_PTYPE_L2_ETHER,
2258 RTE_PTYPE_L3_IPV4,
2259 RTE_PTYPE_L3_IPV4_EXT,
2260 RTE_PTYPE_L3_IPV6,
2261 RTE_PTYPE_L3_IPV6_EXT,
2262 RTE_PTYPE_L4_TCP,
2263 RTE_PTYPE_L4_UDP,
2264 RTE_PTYPE_L4_SCTP,
2265 RTE_PTYPE_TUNNEL_IP,
2266 RTE_PTYPE_INNER_L3_IPV6,
2267 RTE_PTYPE_INNER_L3_IPV6_EXT,
2268 RTE_PTYPE_INNER_L4_TCP,
2269 RTE_PTYPE_INNER_L4_UDP,
2270 RTE_PTYPE_UNKNOWN
2271 };
2272
2273 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2274 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2275 return ptypes;
2276 return NULL;
2277 }
2278
2279 static void
2280 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2281 {
2282 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2283
2284 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2285 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2286 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2287 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2288 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2289 DEV_RX_OFFLOAD_IPV4_CKSUM |
2290 DEV_RX_OFFLOAD_UDP_CKSUM |
2291 DEV_RX_OFFLOAD_TCP_CKSUM;
2292 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2293 DEV_TX_OFFLOAD_IPV4_CKSUM |
2294 DEV_TX_OFFLOAD_UDP_CKSUM |
2295 DEV_TX_OFFLOAD_TCP_CKSUM |
2296 DEV_TX_OFFLOAD_SCTP_CKSUM |
2297 DEV_TX_OFFLOAD_TCP_TSO;
2298 switch (hw->mac.type) {
2299 case e1000_vfadapt:
2300 dev_info->max_rx_queues = 2;
2301 dev_info->max_tx_queues = 2;
2302 break;
2303 case e1000_vfadapt_i350:
2304 dev_info->max_rx_queues = 1;
2305 dev_info->max_tx_queues = 1;
2306 break;
2307 default:
2308 /* Should not happen */
2309 break;
2310 }
2311
2312 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2313 .rx_thresh = {
2314 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2315 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2316 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2317 },
2318 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2319 .rx_drop_en = 0,
2320 };
2321
2322 dev_info->default_txconf = (struct rte_eth_txconf) {
2323 .tx_thresh = {
2324 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2325 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2326 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2327 },
2328 .txq_flags = 0,
2329 };
2330
2331 dev_info->rx_desc_lim = rx_desc_lim;
2332 dev_info->tx_desc_lim = tx_desc_lim;
2333 }
2334
2335 /* return 0 means link status changed, -1 means not changed */
2336 static int
2337 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2338 {
2339 struct e1000_hw *hw =
2340 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2341 struct rte_eth_link link, old;
2342 int link_check, count;
2343
2344 link_check = 0;
2345 hw->mac.get_link_status = 1;
2346
2347 /* possible wait-to-complete in up to 9 seconds */
2348 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2349 /* Read the real link status */
2350 switch (hw->phy.media_type) {
2351 case e1000_media_type_copper:
2352 /* Do the work to read phy */
2353 e1000_check_for_link(hw);
2354 link_check = !hw->mac.get_link_status;
2355 break;
2356
2357 case e1000_media_type_fiber:
2358 e1000_check_for_link(hw);
2359 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2360 E1000_STATUS_LU);
2361 break;
2362
2363 case e1000_media_type_internal_serdes:
2364 e1000_check_for_link(hw);
2365 link_check = hw->mac.serdes_has_link;
2366 break;
2367
2368 /* VF device is type_unknown */
2369 case e1000_media_type_unknown:
2370 eth_igbvf_link_update(hw);
2371 link_check = !hw->mac.get_link_status;
2372 break;
2373
2374 default:
2375 break;
2376 }
2377 if (link_check || wait_to_complete == 0)
2378 break;
2379 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2380 }
2381 memset(&link, 0, sizeof(link));
2382 rte_igb_dev_atomic_read_link_status(dev, &link);
2383 old = link;
2384
2385 /* Now we check if a transition has happened */
2386 if (link_check) {
2387 uint16_t duplex, speed;
2388 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2389 link.link_duplex = (duplex == FULL_DUPLEX) ?
2390 ETH_LINK_FULL_DUPLEX :
2391 ETH_LINK_HALF_DUPLEX;
2392 link.link_speed = speed;
2393 link.link_status = ETH_LINK_UP;
2394 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2395 ETH_LINK_SPEED_FIXED);
2396 } else if (!link_check) {
2397 link.link_speed = 0;
2398 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2399 link.link_status = ETH_LINK_DOWN;
2400 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2401 }
2402 rte_igb_dev_atomic_write_link_status(dev, &link);
2403
2404 /* not changed */
2405 if (old.link_status == link.link_status)
2406 return -1;
2407
2408 /* changed */
2409 return 0;
2410 }
2411
2412 /*
2413 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2414 * For ASF and Pass Through versions of f/w this means
2415 * that the driver is loaded.
2416 */
2417 static void
2418 igb_hw_control_acquire(struct e1000_hw *hw)
2419 {
2420 uint32_t ctrl_ext;
2421
2422 /* Let firmware know the driver has taken over */
2423 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2424 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2425 }
2426
2427 /*
2428 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2429 * For ASF and Pass Through versions of f/w this means that the
2430 * driver is no longer loaded.
2431 */
2432 static void
2433 igb_hw_control_release(struct e1000_hw *hw)
2434 {
2435 uint32_t ctrl_ext;
2436
2437 /* Let firmware taken over control of h/w */
2438 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2439 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2440 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2441 }
2442
2443 /*
2444 * Bit of a misnomer, what this really means is
2445 * to enable OS management of the system... aka
2446 * to disable special hardware management features.
2447 */
2448 static void
2449 igb_init_manageability(struct e1000_hw *hw)
2450 {
2451 if (e1000_enable_mng_pass_thru(hw)) {
2452 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2453 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2454
2455 /* disable hardware interception of ARP */
2456 manc &= ~(E1000_MANC_ARP_EN);
2457
2458 /* enable receiving management packets to the host */
2459 manc |= E1000_MANC_EN_MNG2HOST;
2460 manc2h |= 1 << 5; /* Mng Port 623 */
2461 manc2h |= 1 << 6; /* Mng Port 664 */
2462 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2463 E1000_WRITE_REG(hw, E1000_MANC, manc);
2464 }
2465 }
2466
2467 static void
2468 igb_release_manageability(struct e1000_hw *hw)
2469 {
2470 if (e1000_enable_mng_pass_thru(hw)) {
2471 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2472
2473 manc |= E1000_MANC_ARP_EN;
2474 manc &= ~E1000_MANC_EN_MNG2HOST;
2475
2476 E1000_WRITE_REG(hw, E1000_MANC, manc);
2477 }
2478 }
2479
2480 static void
2481 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2482 {
2483 struct e1000_hw *hw =
2484 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2485 uint32_t rctl;
2486
2487 rctl = E1000_READ_REG(hw, E1000_RCTL);
2488 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2489 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2490 }
2491
2492 static void
2493 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2494 {
2495 struct e1000_hw *hw =
2496 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2497 uint32_t rctl;
2498
2499 rctl = E1000_READ_REG(hw, E1000_RCTL);
2500 rctl &= (~E1000_RCTL_UPE);
2501 if (dev->data->all_multicast == 1)
2502 rctl |= E1000_RCTL_MPE;
2503 else
2504 rctl &= (~E1000_RCTL_MPE);
2505 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2506 }
2507
2508 static void
2509 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2510 {
2511 struct e1000_hw *hw =
2512 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2513 uint32_t rctl;
2514
2515 rctl = E1000_READ_REG(hw, E1000_RCTL);
2516 rctl |= E1000_RCTL_MPE;
2517 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2518 }
2519
2520 static void
2521 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2522 {
2523 struct e1000_hw *hw =
2524 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2525 uint32_t rctl;
2526
2527 if (dev->data->promiscuous == 1)
2528 return; /* must remain in all_multicast mode */
2529 rctl = E1000_READ_REG(hw, E1000_RCTL);
2530 rctl &= (~E1000_RCTL_MPE);
2531 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2532 }
2533
2534 static int
2535 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2536 {
2537 struct e1000_hw *hw =
2538 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539 struct e1000_vfta * shadow_vfta =
2540 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2541 uint32_t vfta;
2542 uint32_t vid_idx;
2543 uint32_t vid_bit;
2544
2545 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2546 E1000_VFTA_ENTRY_MASK);
2547 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2548 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2549 if (on)
2550 vfta |= vid_bit;
2551 else
2552 vfta &= ~vid_bit;
2553 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2554
2555 /* update local VFTA copy */
2556 shadow_vfta->vfta[vid_idx] = vfta;
2557
2558 return 0;
2559 }
2560
2561 static int
2562 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2563 enum rte_vlan_type vlan_type,
2564 uint16_t tpid)
2565 {
2566 struct e1000_hw *hw =
2567 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2568 uint32_t reg, qinq;
2569
2570 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2571 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2572
2573 /* only outer TPID of double VLAN can be configured*/
2574 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2575 reg = E1000_READ_REG(hw, E1000_VET);
2576 reg = (reg & (~E1000_VET_VET_EXT)) |
2577 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2578 E1000_WRITE_REG(hw, E1000_VET, reg);
2579
2580 return 0;
2581 }
2582
2583 /* all other TPID values are read-only*/
2584 PMD_DRV_LOG(ERR, "Not supported");
2585
2586 return -ENOTSUP;
2587 }
2588
2589 static void
2590 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2591 {
2592 struct e1000_hw *hw =
2593 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2594 uint32_t reg;
2595
2596 /* Filter Table Disable */
2597 reg = E1000_READ_REG(hw, E1000_RCTL);
2598 reg &= ~E1000_RCTL_CFIEN;
2599 reg &= ~E1000_RCTL_VFE;
2600 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2601 }
2602
2603 static void
2604 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2605 {
2606 struct e1000_hw *hw =
2607 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2608 struct e1000_vfta * shadow_vfta =
2609 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2610 uint32_t reg;
2611 int i;
2612
2613 /* Filter Table Enable, CFI not used for packet acceptance */
2614 reg = E1000_READ_REG(hw, E1000_RCTL);
2615 reg &= ~E1000_RCTL_CFIEN;
2616 reg |= E1000_RCTL_VFE;
2617 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2618
2619 /* restore VFTA table */
2620 for (i = 0; i < IGB_VFTA_SIZE; i++)
2621 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2622 }
2623
2624 static void
2625 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2626 {
2627 struct e1000_hw *hw =
2628 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2629 uint32_t reg;
2630
2631 /* VLAN Mode Disable */
2632 reg = E1000_READ_REG(hw, E1000_CTRL);
2633 reg &= ~E1000_CTRL_VME;
2634 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2635 }
2636
2637 static void
2638 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2639 {
2640 struct e1000_hw *hw =
2641 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2642 uint32_t reg;
2643
2644 /* VLAN Mode Enable */
2645 reg = E1000_READ_REG(hw, E1000_CTRL);
2646 reg |= E1000_CTRL_VME;
2647 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2648 }
2649
2650 static void
2651 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2652 {
2653 struct e1000_hw *hw =
2654 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2655 uint32_t reg;
2656
2657 /* CTRL_EXT: Extended VLAN */
2658 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2659 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2660 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2661
2662 /* Update maximum packet length */
2663 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2664 E1000_WRITE_REG(hw, E1000_RLPML,
2665 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2666 VLAN_TAG_SIZE);
2667 }
2668
2669 static void
2670 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2671 {
2672 struct e1000_hw *hw =
2673 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2674 uint32_t reg;
2675
2676 /* CTRL_EXT: Extended VLAN */
2677 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2678 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2679 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2680
2681 /* Update maximum packet length */
2682 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2683 E1000_WRITE_REG(hw, E1000_RLPML,
2684 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2685 2 * VLAN_TAG_SIZE);
2686 }
2687
2688 static void
2689 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2690 {
2691 if(mask & ETH_VLAN_STRIP_MASK){
2692 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2693 igb_vlan_hw_strip_enable(dev);
2694 else
2695 igb_vlan_hw_strip_disable(dev);
2696 }
2697
2698 if(mask & ETH_VLAN_FILTER_MASK){
2699 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2700 igb_vlan_hw_filter_enable(dev);
2701 else
2702 igb_vlan_hw_filter_disable(dev);
2703 }
2704
2705 if(mask & ETH_VLAN_EXTEND_MASK){
2706 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2707 igb_vlan_hw_extend_enable(dev);
2708 else
2709 igb_vlan_hw_extend_disable(dev);
2710 }
2711 }
2712
2713
2714 /**
2715 * It enables the interrupt mask and then enable the interrupt.
2716 *
2717 * @param dev
2718 * Pointer to struct rte_eth_dev.
2719 *
2720 * @return
2721 * - On success, zero.
2722 * - On failure, a negative value.
2723 */
2724 static int
2725 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2726 {
2727 struct e1000_interrupt *intr =
2728 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2729
2730 intr->mask |= E1000_ICR_LSC;
2731
2732 return 0;
2733 }
2734
2735 /* It clears the interrupt causes and enables the interrupt.
2736 * It will be called once only during nic initialized.
2737 *
2738 * @param dev
2739 * Pointer to struct rte_eth_dev.
2740 *
2741 * @return
2742 * - On success, zero.
2743 * - On failure, a negative value.
2744 */
2745 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2746 {
2747 uint32_t mask, regval;
2748 struct e1000_hw *hw =
2749 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2750 struct rte_eth_dev_info dev_info;
2751
2752 memset(&dev_info, 0, sizeof(dev_info));
2753 eth_igb_infos_get(dev, &dev_info);
2754
2755 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2756 regval = E1000_READ_REG(hw, E1000_EIMS);
2757 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2758
2759 return 0;
2760 }
2761
2762 /*
2763 * It reads ICR and gets interrupt causes, check it and set a bit flag
2764 * to update link status.
2765 *
2766 * @param dev
2767 * Pointer to struct rte_eth_dev.
2768 *
2769 * @return
2770 * - On success, zero.
2771 * - On failure, a negative value.
2772 */
2773 static int
2774 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2775 {
2776 uint32_t icr;
2777 struct e1000_hw *hw =
2778 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2779 struct e1000_interrupt *intr =
2780 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2781
2782 igb_intr_disable(hw);
2783
2784 /* read-on-clear nic registers here */
2785 icr = E1000_READ_REG(hw, E1000_ICR);
2786
2787 intr->flags = 0;
2788 if (icr & E1000_ICR_LSC) {
2789 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2790 }
2791
2792 if (icr & E1000_ICR_VMMB)
2793 intr->flags |= E1000_FLAG_MAILBOX;
2794
2795 return 0;
2796 }
2797
2798 /*
2799 * It executes link_update after knowing an interrupt is prsent.
2800 *
2801 * @param dev
2802 * Pointer to struct rte_eth_dev.
2803 *
2804 * @return
2805 * - On success, zero.
2806 * - On failure, a negative value.
2807 */
2808 static int
2809 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2810 struct rte_intr_handle *intr_handle)
2811 {
2812 struct e1000_hw *hw =
2813 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2814 struct e1000_interrupt *intr =
2815 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2816 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
2817 uint32_t tctl, rctl;
2818 struct rte_eth_link link;
2819 int ret;
2820
2821 if (intr->flags & E1000_FLAG_MAILBOX) {
2822 igb_pf_mbx_process(dev);
2823 intr->flags &= ~E1000_FLAG_MAILBOX;
2824 }
2825
2826 igb_intr_enable(dev);
2827 rte_intr_enable(intr_handle);
2828
2829 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2830 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2831
2832 /* set get_link_status to check register later */
2833 hw->mac.get_link_status = 1;
2834 ret = eth_igb_link_update(dev, 0);
2835
2836 /* check if link has changed */
2837 if (ret < 0)
2838 return 0;
2839
2840 memset(&link, 0, sizeof(link));
2841 rte_igb_dev_atomic_read_link_status(dev, &link);
2842 if (link.link_status) {
2843 PMD_INIT_LOG(INFO,
2844 " Port %d: Link Up - speed %u Mbps - %s",
2845 dev->data->port_id,
2846 (unsigned)link.link_speed,
2847 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2848 "full-duplex" : "half-duplex");
2849 } else {
2850 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2851 dev->data->port_id);
2852 }
2853
2854 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2855 pci_dev->addr.domain,
2856 pci_dev->addr.bus,
2857 pci_dev->addr.devid,
2858 pci_dev->addr.function);
2859 tctl = E1000_READ_REG(hw, E1000_TCTL);
2860 rctl = E1000_READ_REG(hw, E1000_RCTL);
2861 if (link.link_status) {
2862 /* enable Tx/Rx */
2863 tctl |= E1000_TCTL_EN;
2864 rctl |= E1000_RCTL_EN;
2865 } else {
2866 /* disable Tx/Rx */
2867 tctl &= ~E1000_TCTL_EN;
2868 rctl &= ~E1000_RCTL_EN;
2869 }
2870 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2871 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2872 E1000_WRITE_FLUSH(hw);
2873 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2874 }
2875
2876 return 0;
2877 }
2878
2879 /**
2880 * Interrupt handler which shall be registered at first.
2881 *
2882 * @param handle
2883 * Pointer to interrupt handle.
2884 * @param param
2885 * The address of parameter (struct rte_eth_dev *) regsitered before.
2886 *
2887 * @return
2888 * void
2889 */
2890 static void
2891 eth_igb_interrupt_handler(void *param)
2892 {
2893 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2894
2895 eth_igb_interrupt_get_status(dev);
2896 eth_igb_interrupt_action(dev, dev->intr_handle);
2897 }
2898
2899 static int
2900 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2901 {
2902 uint32_t eicr;
2903 struct e1000_hw *hw =
2904 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2905 struct e1000_interrupt *intr =
2906 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2907
2908 igbvf_intr_disable(hw);
2909
2910 /* read-on-clear nic registers here */
2911 eicr = E1000_READ_REG(hw, E1000_EICR);
2912 intr->flags = 0;
2913
2914 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2915 intr->flags |= E1000_FLAG_MAILBOX;
2916
2917 return 0;
2918 }
2919
2920 void igbvf_mbx_process(struct rte_eth_dev *dev)
2921 {
2922 struct e1000_hw *hw =
2923 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2924 struct e1000_mbx_info *mbx = &hw->mbx;
2925 u32 in_msg = 0;
2926
2927 if (mbx->ops.read(hw, &in_msg, 1, 0))
2928 return;
2929
2930 /* PF reset VF event */
2931 if (in_msg == E1000_PF_CONTROL_MSG)
2932 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2933 }
2934
2935 static int
2936 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2937 {
2938 struct e1000_interrupt *intr =
2939 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2940
2941 if (intr->flags & E1000_FLAG_MAILBOX) {
2942 igbvf_mbx_process(dev);
2943 intr->flags &= ~E1000_FLAG_MAILBOX;
2944 }
2945
2946 igbvf_intr_enable(dev);
2947 rte_intr_enable(intr_handle);
2948
2949 return 0;
2950 }
2951
2952 static void
2953 eth_igbvf_interrupt_handler(void *param)
2954 {
2955 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2956
2957 eth_igbvf_interrupt_get_status(dev);
2958 eth_igbvf_interrupt_action(dev, dev->intr_handle);
2959 }
2960
2961 static int
2962 eth_igb_led_on(struct rte_eth_dev *dev)
2963 {
2964 struct e1000_hw *hw;
2965
2966 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2967 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2968 }
2969
2970 static int
2971 eth_igb_led_off(struct rte_eth_dev *dev)
2972 {
2973 struct e1000_hw *hw;
2974
2975 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2976 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2977 }
2978
2979 static int
2980 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2981 {
2982 struct e1000_hw *hw;
2983 uint32_t ctrl;
2984 int tx_pause;
2985 int rx_pause;
2986
2987 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2988 fc_conf->pause_time = hw->fc.pause_time;
2989 fc_conf->high_water = hw->fc.high_water;
2990 fc_conf->low_water = hw->fc.low_water;
2991 fc_conf->send_xon = hw->fc.send_xon;
2992 fc_conf->autoneg = hw->mac.autoneg;
2993
2994 /*
2995 * Return rx_pause and tx_pause status according to actual setting of
2996 * the TFCE and RFCE bits in the CTRL register.
2997 */
2998 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2999 if (ctrl & E1000_CTRL_TFCE)
3000 tx_pause = 1;
3001 else
3002 tx_pause = 0;
3003
3004 if (ctrl & E1000_CTRL_RFCE)
3005 rx_pause = 1;
3006 else
3007 rx_pause = 0;
3008
3009 if (rx_pause && tx_pause)
3010 fc_conf->mode = RTE_FC_FULL;
3011 else if (rx_pause)
3012 fc_conf->mode = RTE_FC_RX_PAUSE;
3013 else if (tx_pause)
3014 fc_conf->mode = RTE_FC_TX_PAUSE;
3015 else
3016 fc_conf->mode = RTE_FC_NONE;
3017
3018 return 0;
3019 }
3020
3021 static int
3022 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3023 {
3024 struct e1000_hw *hw;
3025 int err;
3026 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3027 e1000_fc_none,
3028 e1000_fc_rx_pause,
3029 e1000_fc_tx_pause,
3030 e1000_fc_full
3031 };
3032 uint32_t rx_buf_size;
3033 uint32_t max_high_water;
3034 uint32_t rctl;
3035
3036 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3037 if (fc_conf->autoneg != hw->mac.autoneg)
3038 return -ENOTSUP;
3039 rx_buf_size = igb_get_rx_buffer_size(hw);
3040 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3041
3042 /* At least reserve one Ethernet frame for watermark */
3043 max_high_water = rx_buf_size - ETHER_MAX_LEN;
3044 if ((fc_conf->high_water > max_high_water) ||
3045 (fc_conf->high_water < fc_conf->low_water)) {
3046 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3047 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3048 return -EINVAL;
3049 }
3050
3051 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3052 hw->fc.pause_time = fc_conf->pause_time;
3053 hw->fc.high_water = fc_conf->high_water;
3054 hw->fc.low_water = fc_conf->low_water;
3055 hw->fc.send_xon = fc_conf->send_xon;
3056
3057 err = e1000_setup_link_generic(hw);
3058 if (err == E1000_SUCCESS) {
3059
3060 /* check if we want to forward MAC frames - driver doesn't have native
3061 * capability to do that, so we'll write the registers ourselves */
3062
3063 rctl = E1000_READ_REG(hw, E1000_RCTL);
3064
3065 /* set or clear MFLCN.PMCF bit depending on configuration */
3066 if (fc_conf->mac_ctrl_frame_fwd != 0)
3067 rctl |= E1000_RCTL_PMCF;
3068 else
3069 rctl &= ~E1000_RCTL_PMCF;
3070
3071 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3072 E1000_WRITE_FLUSH(hw);
3073
3074 return 0;
3075 }
3076
3077 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3078 return -EIO;
3079 }
3080
3081 #define E1000_RAH_POOLSEL_SHIFT (18)
3082 static int
3083 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3084 uint32_t index, __rte_unused uint32_t pool)
3085 {
3086 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3087 uint32_t rah;
3088
3089 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3090 rah = E1000_READ_REG(hw, E1000_RAH(index));
3091 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3092 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3093 return 0;
3094 }
3095
3096 static void
3097 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3098 {
3099 uint8_t addr[ETHER_ADDR_LEN];
3100 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3101
3102 memset(addr, 0, sizeof(addr));
3103
3104 e1000_rar_set(hw, addr, index);
3105 }
3106
3107 static void
3108 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3109 struct ether_addr *addr)
3110 {
3111 eth_igb_rar_clear(dev, 0);
3112
3113 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3114 }
3115 /*
3116 * Virtual Function operations
3117 */
3118 static void
3119 igbvf_intr_disable(struct e1000_hw *hw)
3120 {
3121 PMD_INIT_FUNC_TRACE();
3122
3123 /* Clear interrupt mask to stop from interrupts being generated */
3124 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3125
3126 E1000_WRITE_FLUSH(hw);
3127 }
3128
3129 static void
3130 igbvf_stop_adapter(struct rte_eth_dev *dev)
3131 {
3132 u32 reg_val;
3133 u16 i;
3134 struct rte_eth_dev_info dev_info;
3135 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3136
3137 memset(&dev_info, 0, sizeof(dev_info));
3138 eth_igbvf_infos_get(dev, &dev_info);
3139
3140 /* Clear interrupt mask to stop from interrupts being generated */
3141 igbvf_intr_disable(hw);
3142
3143 /* Clear any pending interrupts, flush previous writes */
3144 E1000_READ_REG(hw, E1000_EICR);
3145
3146 /* Disable the transmit unit. Each queue must be disabled. */
3147 for (i = 0; i < dev_info.max_tx_queues; i++)
3148 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3149
3150 /* Disable the receive unit by stopping each queue */
3151 for (i = 0; i < dev_info.max_rx_queues; i++) {
3152 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3153 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3154 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3155 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3156 ;
3157 }
3158
3159 /* flush all queues disables */
3160 E1000_WRITE_FLUSH(hw);
3161 msec_delay(2);
3162 }
3163
3164 static int eth_igbvf_link_update(struct e1000_hw *hw)
3165 {
3166 struct e1000_mbx_info *mbx = &hw->mbx;
3167 struct e1000_mac_info *mac = &hw->mac;
3168 int ret_val = E1000_SUCCESS;
3169
3170 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3171
3172 /*
3173 * We only want to run this if there has been a rst asserted.
3174 * in this case that could mean a link change, device reset,
3175 * or a virtual function reset
3176 */
3177
3178 /* If we were hit with a reset or timeout drop the link */
3179 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3180 mac->get_link_status = TRUE;
3181
3182 if (!mac->get_link_status)
3183 goto out;
3184
3185 /* if link status is down no point in checking to see if pf is up */
3186 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3187 goto out;
3188
3189 /* if we passed all the tests above then the link is up and we no
3190 * longer need to check for link */
3191 mac->get_link_status = FALSE;
3192
3193 out:
3194 return ret_val;
3195 }
3196
3197
3198 static int
3199 igbvf_dev_configure(struct rte_eth_dev *dev)
3200 {
3201 struct rte_eth_conf* conf = &dev->data->dev_conf;
3202
3203 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3204 dev->data->port_id);
3205
3206 /*
3207 * VF has no ability to enable/disable HW CRC
3208 * Keep the persistent behavior the same as Host PF
3209 */
3210 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3211 if (!conf->rxmode.hw_strip_crc) {
3212 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3213 conf->rxmode.hw_strip_crc = 1;
3214 }
3215 #else
3216 if (conf->rxmode.hw_strip_crc) {
3217 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3218 conf->rxmode.hw_strip_crc = 0;
3219 }
3220 #endif
3221
3222 return 0;
3223 }
3224
3225 static int
3226 igbvf_dev_start(struct rte_eth_dev *dev)
3227 {
3228 struct e1000_hw *hw =
3229 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3230 struct e1000_adapter *adapter =
3231 E1000_DEV_PRIVATE(dev->data->dev_private);
3232 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3233 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3234 int ret;
3235 uint32_t intr_vector = 0;
3236
3237 PMD_INIT_FUNC_TRACE();
3238
3239 hw->mac.ops.reset_hw(hw);
3240 adapter->stopped = 0;
3241
3242 /* Set all vfta */
3243 igbvf_set_vfta_all(dev,1);
3244
3245 eth_igbvf_tx_init(dev);
3246
3247 /* This can fail when allocating mbufs for descriptor rings */
3248 ret = eth_igbvf_rx_init(dev);
3249 if (ret) {
3250 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3251 igb_dev_clear_queues(dev);
3252 return ret;
3253 }
3254
3255 /* check and configure queue intr-vector mapping */
3256 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3257 intr_vector = dev->data->nb_rx_queues;
3258 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3259 if (ret)
3260 return ret;
3261 }
3262
3263 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3264 intr_handle->intr_vec =
3265 rte_zmalloc("intr_vec",
3266 dev->data->nb_rx_queues * sizeof(int), 0);
3267 if (!intr_handle->intr_vec) {
3268 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3269 " intr_vec", dev->data->nb_rx_queues);
3270 return -ENOMEM;
3271 }
3272 }
3273
3274 eth_igbvf_configure_msix_intr(dev);
3275
3276 /* enable uio/vfio intr/eventfd mapping */
3277 rte_intr_enable(intr_handle);
3278
3279 /* resume enabled intr since hw reset */
3280 igbvf_intr_enable(dev);
3281
3282 return 0;
3283 }
3284
3285 static void
3286 igbvf_dev_stop(struct rte_eth_dev *dev)
3287 {
3288 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3289 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3290
3291 PMD_INIT_FUNC_TRACE();
3292
3293 igbvf_stop_adapter(dev);
3294
3295 /*
3296 * Clear what we set, but we still keep shadow_vfta to
3297 * restore after device starts
3298 */
3299 igbvf_set_vfta_all(dev,0);
3300
3301 igb_dev_clear_queues(dev);
3302
3303 /* disable intr eventfd mapping */
3304 rte_intr_disable(intr_handle);
3305
3306 /* Clean datapath event and queue/vec mapping */
3307 rte_intr_efd_disable(intr_handle);
3308 if (intr_handle->intr_vec) {
3309 rte_free(intr_handle->intr_vec);
3310 intr_handle->intr_vec = NULL;
3311 }
3312 }
3313
3314 static void
3315 igbvf_dev_close(struct rte_eth_dev *dev)
3316 {
3317 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3318 struct e1000_adapter *adapter =
3319 E1000_DEV_PRIVATE(dev->data->dev_private);
3320 struct ether_addr addr;
3321
3322 PMD_INIT_FUNC_TRACE();
3323
3324 e1000_reset_hw(hw);
3325
3326 igbvf_dev_stop(dev);
3327 adapter->stopped = 1;
3328 igb_dev_free_queues(dev);
3329
3330 /**
3331 * reprogram the RAR with a zero mac address,
3332 * to ensure that the VF traffic goes to the PF
3333 * after stop, close and detach of the VF.
3334 **/
3335
3336 memset(&addr, 0, sizeof(addr));
3337 igbvf_default_mac_addr_set(dev, &addr);
3338 }
3339
3340 static void
3341 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3342 {
3343 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3344
3345 /* Set both unicast and multicast promisc */
3346 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3347 }
3348
3349 static void
3350 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3351 {
3352 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3353
3354 /* If in allmulticast mode leave multicast promisc */
3355 if (dev->data->all_multicast == 1)
3356 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3357 else
3358 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3359 }
3360
3361 static void
3362 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3363 {
3364 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3365
3366 /* In promiscuous mode multicast promisc already set */
3367 if (dev->data->promiscuous == 0)
3368 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3369 }
3370
3371 static void
3372 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3373 {
3374 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3375
3376 /* In promiscuous mode leave multicast promisc enabled */
3377 if (dev->data->promiscuous == 0)
3378 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3379 }
3380
3381 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3382 {
3383 struct e1000_mbx_info *mbx = &hw->mbx;
3384 uint32_t msgbuf[2];
3385 s32 err;
3386
3387 /* After set vlan, vlan strip will also be enabled in igb driver*/
3388 msgbuf[0] = E1000_VF_SET_VLAN;
3389 msgbuf[1] = vid;
3390 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3391 if (on)
3392 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3393
3394 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3395 if (err)
3396 goto mbx_err;
3397
3398 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3399 if (err)
3400 goto mbx_err;
3401
3402 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3403 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3404 err = -EINVAL;
3405
3406 mbx_err:
3407 return err;
3408 }
3409
3410 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3411 {
3412 struct e1000_hw *hw =
3413 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3414 struct e1000_vfta * shadow_vfta =
3415 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3416 int i = 0, j = 0, vfta = 0, mask = 1;
3417
3418 for (i = 0; i < IGB_VFTA_SIZE; i++){
3419 vfta = shadow_vfta->vfta[i];
3420 if(vfta){
3421 mask = 1;
3422 for (j = 0; j < 32; j++){
3423 if(vfta & mask)
3424 igbvf_set_vfta(hw,
3425 (uint16_t)((i<<5)+j), on);
3426 mask<<=1;
3427 }
3428 }
3429 }
3430
3431 }
3432
3433 static int
3434 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3435 {
3436 struct e1000_hw *hw =
3437 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3438 struct e1000_vfta * shadow_vfta =
3439 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3440 uint32_t vid_idx = 0;
3441 uint32_t vid_bit = 0;
3442 int ret = 0;
3443
3444 PMD_INIT_FUNC_TRACE();
3445
3446 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3447 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3448 if(ret){
3449 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3450 return ret;
3451 }
3452 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3453 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3454
3455 /*Save what we set and retore it after device reset*/
3456 if (on)
3457 shadow_vfta->vfta[vid_idx] |= vid_bit;
3458 else
3459 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3460
3461 return 0;
3462 }
3463
3464 static void
3465 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3466 {
3467 struct e1000_hw *hw =
3468 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3469
3470 /* index is not used by rar_set() */
3471 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3472 }
3473
3474
3475 static int
3476 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3477 struct rte_eth_rss_reta_entry64 *reta_conf,
3478 uint16_t reta_size)
3479 {
3480 uint8_t i, j, mask;
3481 uint32_t reta, r;
3482 uint16_t idx, shift;
3483 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3484
3485 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3486 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3487 "(%d) doesn't match the number hardware can supported "
3488 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3489 return -EINVAL;
3490 }
3491
3492 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3493 idx = i / RTE_RETA_GROUP_SIZE;
3494 shift = i % RTE_RETA_GROUP_SIZE;
3495 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3496 IGB_4_BIT_MASK);
3497 if (!mask)
3498 continue;
3499 if (mask == IGB_4_BIT_MASK)
3500 r = 0;
3501 else
3502 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3503 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3504 if (mask & (0x1 << j))
3505 reta |= reta_conf[idx].reta[shift + j] <<
3506 (CHAR_BIT * j);
3507 else
3508 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3509 }
3510 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3511 }
3512
3513 return 0;
3514 }
3515
3516 static int
3517 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3518 struct rte_eth_rss_reta_entry64 *reta_conf,
3519 uint16_t reta_size)
3520 {
3521 uint8_t i, j, mask;
3522 uint32_t reta;
3523 uint16_t idx, shift;
3524 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3525
3526 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3527 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3528 "(%d) doesn't match the number hardware can supported "
3529 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3530 return -EINVAL;
3531 }
3532
3533 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3534 idx = i / RTE_RETA_GROUP_SIZE;
3535 shift = i % RTE_RETA_GROUP_SIZE;
3536 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3537 IGB_4_BIT_MASK);
3538 if (!mask)
3539 continue;
3540 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3541 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3542 if (mask & (0x1 << j))
3543 reta_conf[idx].reta[shift + j] =
3544 ((reta >> (CHAR_BIT * j)) &
3545 IGB_8_BIT_MASK);
3546 }
3547 }
3548
3549 return 0;
3550 }
3551
3552 #define MAC_TYPE_FILTER_SUP(type) do {\
3553 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3554 (type) != e1000_82576)\
3555 return -ENOTSUP;\
3556 } while (0)
3557
3558 static int
3559 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3560 struct rte_eth_syn_filter *filter,
3561 bool add)
3562 {
3563 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3564 uint32_t synqf, rfctl;
3565
3566 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3567 return -EINVAL;
3568
3569 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3570
3571 if (add) {
3572 if (synqf & E1000_SYN_FILTER_ENABLE)
3573 return -EINVAL;
3574
3575 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3576 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3577
3578 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3579 if (filter->hig_pri)
3580 rfctl |= E1000_RFCTL_SYNQFP;
3581 else
3582 rfctl &= ~E1000_RFCTL_SYNQFP;
3583
3584 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3585 } else {
3586 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3587 return -ENOENT;
3588 synqf = 0;
3589 }
3590
3591 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3592 E1000_WRITE_FLUSH(hw);
3593 return 0;
3594 }
3595
3596 static int
3597 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3598 struct rte_eth_syn_filter *filter)
3599 {
3600 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601 uint32_t synqf, rfctl;
3602
3603 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3604 if (synqf & E1000_SYN_FILTER_ENABLE) {
3605 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3606 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3607 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3608 E1000_SYN_FILTER_QUEUE_SHIFT);
3609 return 0;
3610 }
3611
3612 return -ENOENT;
3613 }
3614
3615 static int
3616 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3617 enum rte_filter_op filter_op,
3618 void *arg)
3619 {
3620 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3621 int ret;
3622
3623 MAC_TYPE_FILTER_SUP(hw->mac.type);
3624
3625 if (filter_op == RTE_ETH_FILTER_NOP)
3626 return 0;
3627
3628 if (arg == NULL) {
3629 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3630 filter_op);
3631 return -EINVAL;
3632 }
3633
3634 switch (filter_op) {
3635 case RTE_ETH_FILTER_ADD:
3636 ret = eth_igb_syn_filter_set(dev,
3637 (struct rte_eth_syn_filter *)arg,
3638 TRUE);
3639 break;
3640 case RTE_ETH_FILTER_DELETE:
3641 ret = eth_igb_syn_filter_set(dev,
3642 (struct rte_eth_syn_filter *)arg,
3643 FALSE);
3644 break;
3645 case RTE_ETH_FILTER_GET:
3646 ret = eth_igb_syn_filter_get(dev,
3647 (struct rte_eth_syn_filter *)arg);
3648 break;
3649 default:
3650 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3651 ret = -EINVAL;
3652 break;
3653 }
3654
3655 return ret;
3656 }
3657
3658 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
3659 if ((type) != e1000_82580 && (type) != e1000_i350)\
3660 return -ENOSYS; \
3661 } while (0)
3662
3663 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3664 static inline int
3665 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3666 struct e1000_2tuple_filter_info *filter_info)
3667 {
3668 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3669 return -EINVAL;
3670 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3671 return -EINVAL; /* filter index is out of range. */
3672 if (filter->tcp_flags > TCP_FLAG_ALL)
3673 return -EINVAL; /* flags is invalid. */
3674
3675 switch (filter->dst_port_mask) {
3676 case UINT16_MAX:
3677 filter_info->dst_port_mask = 0;
3678 filter_info->dst_port = filter->dst_port;
3679 break;
3680 case 0:
3681 filter_info->dst_port_mask = 1;
3682 break;
3683 default:
3684 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3685 return -EINVAL;
3686 }
3687
3688 switch (filter->proto_mask) {
3689 case UINT8_MAX:
3690 filter_info->proto_mask = 0;
3691 filter_info->proto = filter->proto;
3692 break;
3693 case 0:
3694 filter_info->proto_mask = 1;
3695 break;
3696 default:
3697 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3698 return -EINVAL;
3699 }
3700
3701 filter_info->priority = (uint8_t)filter->priority;
3702 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3703 filter_info->tcp_flags = filter->tcp_flags;
3704 else
3705 filter_info->tcp_flags = 0;
3706
3707 return 0;
3708 }
3709
3710 static inline struct e1000_2tuple_filter *
3711 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3712 struct e1000_2tuple_filter_info *key)
3713 {
3714 struct e1000_2tuple_filter *it;
3715
3716 TAILQ_FOREACH(it, filter_list, entries) {
3717 if (memcmp(key, &it->filter_info,
3718 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3719 return it;
3720 }
3721 }
3722 return NULL;
3723 }
3724
3725 /*
3726 * igb_add_2tuple_filter - add a 2tuple filter
3727 *
3728 * @param
3729 * dev: Pointer to struct rte_eth_dev.
3730 * ntuple_filter: ponter to the filter that will be added.
3731 *
3732 * @return
3733 * - On success, zero.
3734 * - On failure, a negative value.
3735 */
3736 static int
3737 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3738 struct rte_eth_ntuple_filter *ntuple_filter)
3739 {
3740 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3741 struct e1000_filter_info *filter_info =
3742 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3743 struct e1000_2tuple_filter *filter;
3744 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3745 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3746 int i, ret;
3747
3748 filter = rte_zmalloc("e1000_2tuple_filter",
3749 sizeof(struct e1000_2tuple_filter), 0);
3750 if (filter == NULL)
3751 return -ENOMEM;
3752
3753 ret = ntuple_filter_to_2tuple(ntuple_filter,
3754 &filter->filter_info);
3755 if (ret < 0) {
3756 rte_free(filter);
3757 return ret;
3758 }
3759 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3760 &filter->filter_info) != NULL) {
3761 PMD_DRV_LOG(ERR, "filter exists.");
3762 rte_free(filter);
3763 return -EEXIST;
3764 }
3765 filter->queue = ntuple_filter->queue;
3766
3767 /*
3768 * look for an unused 2tuple filter index,
3769 * and insert the filter to list.
3770 */
3771 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3772 if (!(filter_info->twotuple_mask & (1 << i))) {
3773 filter_info->twotuple_mask |= 1 << i;
3774 filter->index = i;
3775 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3776 filter,
3777 entries);
3778 break;
3779 }
3780 }
3781 if (i >= E1000_MAX_TTQF_FILTERS) {
3782 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3783 rte_free(filter);
3784 return -ENOSYS;
3785 }
3786
3787 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3788 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3789 imir |= E1000_IMIR_PORT_BP;
3790 else
3791 imir &= ~E1000_IMIR_PORT_BP;
3792
3793 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3794
3795 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3796 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3797 ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3798 if (filter->filter_info.proto_mask == 0)
3799 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3800
3801 /* tcp flags bits setting. */
3802 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3803 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3804 imir_ext |= E1000_IMIREXT_CTRL_URG;
3805 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3806 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3807 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3808 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3809 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3810 imir_ext |= E1000_IMIREXT_CTRL_RST;
3811 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3812 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3813 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3814 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3815 } else
3816 imir_ext |= E1000_IMIREXT_CTRL_BP;
3817 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3818 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3819 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3820 return 0;
3821 }
3822
3823 /*
3824 * igb_remove_2tuple_filter - remove a 2tuple filter
3825 *
3826 * @param
3827 * dev: Pointer to struct rte_eth_dev.
3828 * ntuple_filter: ponter to the filter that will be removed.
3829 *
3830 * @return
3831 * - On success, zero.
3832 * - On failure, a negative value.
3833 */
3834 static int
3835 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3836 struct rte_eth_ntuple_filter *ntuple_filter)
3837 {
3838 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3839 struct e1000_filter_info *filter_info =
3840 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3841 struct e1000_2tuple_filter_info filter_2tuple;
3842 struct e1000_2tuple_filter *filter;
3843 int ret;
3844
3845 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3846 ret = ntuple_filter_to_2tuple(ntuple_filter,
3847 &filter_2tuple);
3848 if (ret < 0)
3849 return ret;
3850
3851 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3852 &filter_2tuple);
3853 if (filter == NULL) {
3854 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3855 return -ENOENT;
3856 }
3857
3858 filter_info->twotuple_mask &= ~(1 << filter->index);
3859 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3860 rte_free(filter);
3861
3862 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3863 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3864 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3865 return 0;
3866 }
3867
3868 static inline struct e1000_flex_filter *
3869 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3870 struct e1000_flex_filter_info *key)
3871 {
3872 struct e1000_flex_filter *it;
3873
3874 TAILQ_FOREACH(it, filter_list, entries) {
3875 if (memcmp(key, &it->filter_info,
3876 sizeof(struct e1000_flex_filter_info)) == 0)
3877 return it;
3878 }
3879
3880 return NULL;
3881 }
3882
3883 static int
3884 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3885 struct rte_eth_flex_filter *filter,
3886 bool add)
3887 {
3888 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3889 struct e1000_filter_info *filter_info =
3890 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3891 struct e1000_flex_filter *flex_filter, *it;
3892 uint32_t wufc, queueing, mask;
3893 uint32_t reg_off;
3894 uint8_t shift, i, j = 0;
3895
3896 flex_filter = rte_zmalloc("e1000_flex_filter",
3897 sizeof(struct e1000_flex_filter), 0);
3898 if (flex_filter == NULL)
3899 return -ENOMEM;
3900
3901 flex_filter->filter_info.len = filter->len;
3902 flex_filter->filter_info.priority = filter->priority;
3903 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3904 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3905 mask = 0;
3906 /* reverse bits in flex filter's mask*/
3907 for (shift = 0; shift < CHAR_BIT; shift++) {
3908 if (filter->mask[i] & (0x01 << shift))
3909 mask |= (0x80 >> shift);
3910 }
3911 flex_filter->filter_info.mask[i] = mask;
3912 }
3913
3914 wufc = E1000_READ_REG(hw, E1000_WUFC);
3915 if (flex_filter->index < E1000_MAX_FHFT)
3916 reg_off = E1000_FHFT(flex_filter->index);
3917 else
3918 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3919
3920 if (add) {
3921 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3922 &flex_filter->filter_info) != NULL) {
3923 PMD_DRV_LOG(ERR, "filter exists.");
3924 rte_free(flex_filter);
3925 return -EEXIST;
3926 }
3927 flex_filter->queue = filter->queue;
3928 /*
3929 * look for an unused flex filter index
3930 * and insert the filter into the list.
3931 */
3932 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3933 if (!(filter_info->flex_mask & (1 << i))) {
3934 filter_info->flex_mask |= 1 << i;
3935 flex_filter->index = i;
3936 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3937 flex_filter,
3938 entries);
3939 break;
3940 }
3941 }
3942 if (i >= E1000_MAX_FLEX_FILTERS) {
3943 PMD_DRV_LOG(ERR, "flex filters are full.");
3944 rte_free(flex_filter);
3945 return -ENOSYS;
3946 }
3947
3948 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3949 (E1000_WUFC_FLX0 << flex_filter->index));
3950 queueing = filter->len |
3951 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3952 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3953 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3954 queueing);
3955 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3956 E1000_WRITE_REG(hw, reg_off,
3957 flex_filter->filter_info.dwords[j]);
3958 reg_off += sizeof(uint32_t);
3959 E1000_WRITE_REG(hw, reg_off,
3960 flex_filter->filter_info.dwords[++j]);
3961 reg_off += sizeof(uint32_t);
3962 E1000_WRITE_REG(hw, reg_off,
3963 (uint32_t)flex_filter->filter_info.mask[i]);
3964 reg_off += sizeof(uint32_t) * 2;
3965 ++j;
3966 }
3967 } else {
3968 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3969 &flex_filter->filter_info);
3970 if (it == NULL) {
3971 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3972 rte_free(flex_filter);
3973 return -ENOENT;
3974 }
3975
3976 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3977 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3978 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3979 (~(E1000_WUFC_FLX0 << it->index)));
3980
3981 filter_info->flex_mask &= ~(1 << it->index);
3982 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3983 rte_free(it);
3984 rte_free(flex_filter);
3985 }
3986
3987 return 0;
3988 }
3989
3990 static int
3991 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3992 struct rte_eth_flex_filter *filter)
3993 {
3994 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3995 struct e1000_filter_info *filter_info =
3996 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3997 struct e1000_flex_filter flex_filter, *it;
3998 uint32_t wufc, queueing, wufc_en = 0;
3999
4000 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4001 flex_filter.filter_info.len = filter->len;
4002 flex_filter.filter_info.priority = filter->priority;
4003 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4004 memcpy(flex_filter.filter_info.mask, filter->mask,
4005 RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
4006
4007 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4008 &flex_filter.filter_info);
4009 if (it == NULL) {
4010 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4011 return -ENOENT;
4012 }
4013
4014 wufc = E1000_READ_REG(hw, E1000_WUFC);
4015 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4016
4017 if ((wufc & wufc_en) == wufc_en) {
4018 uint32_t reg_off = 0;
4019 if (it->index < E1000_MAX_FHFT)
4020 reg_off = E1000_FHFT(it->index);
4021 else
4022 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4023
4024 queueing = E1000_READ_REG(hw,
4025 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4026 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4027 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4028 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4029 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4030 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4031 return 0;
4032 }
4033 return -ENOENT;
4034 }
4035
4036 static int
4037 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4038 enum rte_filter_op filter_op,
4039 void *arg)
4040 {
4041 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4042 struct rte_eth_flex_filter *filter;
4043 int ret = 0;
4044
4045 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4046
4047 if (filter_op == RTE_ETH_FILTER_NOP)
4048 return ret;
4049
4050 if (arg == NULL) {
4051 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4052 filter_op);
4053 return -EINVAL;
4054 }
4055
4056 filter = (struct rte_eth_flex_filter *)arg;
4057 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4058 || filter->len % sizeof(uint64_t) != 0) {
4059 PMD_DRV_LOG(ERR, "filter's length is out of range");
4060 return -EINVAL;
4061 }
4062 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4063 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4064 return -EINVAL;
4065 }
4066
4067 switch (filter_op) {
4068 case RTE_ETH_FILTER_ADD:
4069 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4070 break;
4071 case RTE_ETH_FILTER_DELETE:
4072 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4073 break;
4074 case RTE_ETH_FILTER_GET:
4075 ret = eth_igb_get_flex_filter(dev, filter);
4076 break;
4077 default:
4078 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4079 ret = -EINVAL;
4080 break;
4081 }
4082
4083 return ret;
4084 }
4085
4086 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4087 static inline int
4088 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4089 struct e1000_5tuple_filter_info *filter_info)
4090 {
4091 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4092 return -EINVAL;
4093 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4094 return -EINVAL; /* filter index is out of range. */
4095 if (filter->tcp_flags > TCP_FLAG_ALL)
4096 return -EINVAL; /* flags is invalid. */
4097
4098 switch (filter->dst_ip_mask) {
4099 case UINT32_MAX:
4100 filter_info->dst_ip_mask = 0;
4101 filter_info->dst_ip = filter->dst_ip;
4102 break;
4103 case 0:
4104 filter_info->dst_ip_mask = 1;
4105 break;
4106 default:
4107 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4108 return -EINVAL;
4109 }
4110
4111 switch (filter->src_ip_mask) {
4112 case UINT32_MAX:
4113 filter_info->src_ip_mask = 0;
4114 filter_info->src_ip = filter->src_ip;
4115 break;
4116 case 0:
4117 filter_info->src_ip_mask = 1;
4118 break;
4119 default:
4120 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4121 return -EINVAL;
4122 }
4123
4124 switch (filter->dst_port_mask) {
4125 case UINT16_MAX:
4126 filter_info->dst_port_mask = 0;
4127 filter_info->dst_port = filter->dst_port;
4128 break;
4129 case 0:
4130 filter_info->dst_port_mask = 1;
4131 break;
4132 default:
4133 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4134 return -EINVAL;
4135 }
4136
4137 switch (filter->src_port_mask) {
4138 case UINT16_MAX:
4139 filter_info->src_port_mask = 0;
4140 filter_info->src_port = filter->src_port;
4141 break;
4142 case 0:
4143 filter_info->src_port_mask = 1;
4144 break;
4145 default:
4146 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4147 return -EINVAL;
4148 }
4149
4150 switch (filter->proto_mask) {
4151 case UINT8_MAX:
4152 filter_info->proto_mask = 0;
4153 filter_info->proto = filter->proto;
4154 break;
4155 case 0:
4156 filter_info->proto_mask = 1;
4157 break;
4158 default:
4159 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4160 return -EINVAL;
4161 }
4162
4163 filter_info->priority = (uint8_t)filter->priority;
4164 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4165 filter_info->tcp_flags = filter->tcp_flags;
4166 else
4167 filter_info->tcp_flags = 0;
4168
4169 return 0;
4170 }
4171
4172 static inline struct e1000_5tuple_filter *
4173 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4174 struct e1000_5tuple_filter_info *key)
4175 {
4176 struct e1000_5tuple_filter *it;
4177
4178 TAILQ_FOREACH(it, filter_list, entries) {
4179 if (memcmp(key, &it->filter_info,
4180 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4181 return it;
4182 }
4183 }
4184 return NULL;
4185 }
4186
4187 /*
4188 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4189 *
4190 * @param
4191 * dev: Pointer to struct rte_eth_dev.
4192 * ntuple_filter: ponter to the filter that will be added.
4193 *
4194 * @return
4195 * - On success, zero.
4196 * - On failure, a negative value.
4197 */
4198 static int
4199 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4200 struct rte_eth_ntuple_filter *ntuple_filter)
4201 {
4202 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4203 struct e1000_filter_info *filter_info =
4204 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4205 struct e1000_5tuple_filter *filter;
4206 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4207 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4208 uint8_t i;
4209 int ret;
4210
4211 filter = rte_zmalloc("e1000_5tuple_filter",
4212 sizeof(struct e1000_5tuple_filter), 0);
4213 if (filter == NULL)
4214 return -ENOMEM;
4215
4216 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4217 &filter->filter_info);
4218 if (ret < 0) {
4219 rte_free(filter);
4220 return ret;
4221 }
4222
4223 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4224 &filter->filter_info) != NULL) {
4225 PMD_DRV_LOG(ERR, "filter exists.");
4226 rte_free(filter);
4227 return -EEXIST;
4228 }
4229 filter->queue = ntuple_filter->queue;
4230
4231 /*
4232 * look for an unused 5tuple filter index,
4233 * and insert the filter to list.
4234 */
4235 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4236 if (!(filter_info->fivetuple_mask & (1 << i))) {
4237 filter_info->fivetuple_mask |= 1 << i;
4238 filter->index = i;
4239 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4240 filter,
4241 entries);
4242 break;
4243 }
4244 }
4245 if (i >= E1000_MAX_FTQF_FILTERS) {
4246 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4247 rte_free(filter);
4248 return -ENOSYS;
4249 }
4250
4251 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4252 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4253 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4254 if (filter->filter_info.dst_ip_mask == 0)
4255 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4256 if (filter->filter_info.src_port_mask == 0)
4257 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4258 if (filter->filter_info.proto_mask == 0)
4259 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4260 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4261 E1000_FTQF_QUEUE_MASK;
4262 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4263 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4264 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4265 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4266
4267 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4268 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4269
4270 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4271 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4272 imir |= E1000_IMIR_PORT_BP;
4273 else
4274 imir &= ~E1000_IMIR_PORT_BP;
4275 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4276
4277 /* tcp flags bits setting. */
4278 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4279 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4280 imir_ext |= E1000_IMIREXT_CTRL_URG;
4281 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4282 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4283 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4284 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4285 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4286 imir_ext |= E1000_IMIREXT_CTRL_RST;
4287 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4288 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4289 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4290 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4291 } else
4292 imir_ext |= E1000_IMIREXT_CTRL_BP;
4293 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4294 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4295 return 0;
4296 }
4297
4298 /*
4299 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4300 *
4301 * @param
4302 * dev: Pointer to struct rte_eth_dev.
4303 * ntuple_filter: ponter to the filter that will be removed.
4304 *
4305 * @return
4306 * - On success, zero.
4307 * - On failure, a negative value.
4308 */
4309 static int
4310 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4311 struct rte_eth_ntuple_filter *ntuple_filter)
4312 {
4313 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4314 struct e1000_filter_info *filter_info =
4315 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4316 struct e1000_5tuple_filter_info filter_5tuple;
4317 struct e1000_5tuple_filter *filter;
4318 int ret;
4319
4320 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4321 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4322 &filter_5tuple);
4323 if (ret < 0)
4324 return ret;
4325
4326 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4327 &filter_5tuple);
4328 if (filter == NULL) {
4329 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4330 return -ENOENT;
4331 }
4332
4333 filter_info->fivetuple_mask &= ~(1 << filter->index);
4334 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4335 rte_free(filter);
4336
4337 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4338 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4339 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4340 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4341 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4342 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4343 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4344 return 0;
4345 }
4346
4347 static int
4348 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4349 {
4350 uint32_t rctl;
4351 struct e1000_hw *hw;
4352 struct rte_eth_dev_info dev_info;
4353 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4354 VLAN_TAG_SIZE);
4355
4356 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4357
4358 #ifdef RTE_LIBRTE_82571_SUPPORT
4359 /* XXX: not bigger than max_rx_pktlen */
4360 if (hw->mac.type == e1000_82571)
4361 return -ENOTSUP;
4362 #endif
4363 eth_igb_infos_get(dev, &dev_info);
4364
4365 /* check that mtu is within the allowed range */
4366 if ((mtu < ETHER_MIN_MTU) ||
4367 (frame_size > dev_info.max_rx_pktlen))
4368 return -EINVAL;
4369
4370 /* refuse mtu that requires the support of scattered packets when this
4371 * feature has not been enabled before. */
4372 if (!dev->data->scattered_rx &&
4373 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4374 return -EINVAL;
4375
4376 rctl = E1000_READ_REG(hw, E1000_RCTL);
4377
4378 /* switch to jumbo mode if needed */
4379 if (frame_size > ETHER_MAX_LEN) {
4380 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4381 rctl |= E1000_RCTL_LPE;
4382 } else {
4383 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4384 rctl &= ~E1000_RCTL_LPE;
4385 }
4386 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4387
4388 /* update max frame size */
4389 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4390
4391 E1000_WRITE_REG(hw, E1000_RLPML,
4392 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4393
4394 return 0;
4395 }
4396
4397 /*
4398 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4399 *
4400 * @param
4401 * dev: Pointer to struct rte_eth_dev.
4402 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4403 * add: if true, add filter, if false, remove filter
4404 *
4405 * @return
4406 * - On success, zero.
4407 * - On failure, a negative value.
4408 */
4409 static int
4410 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4411 struct rte_eth_ntuple_filter *ntuple_filter,
4412 bool add)
4413 {
4414 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4415 int ret;
4416
4417 switch (ntuple_filter->flags) {
4418 case RTE_5TUPLE_FLAGS:
4419 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4420 if (hw->mac.type != e1000_82576)
4421 return -ENOTSUP;
4422 if (add)
4423 ret = igb_add_5tuple_filter_82576(dev,
4424 ntuple_filter);
4425 else
4426 ret = igb_remove_5tuple_filter_82576(dev,
4427 ntuple_filter);
4428 break;
4429 case RTE_2TUPLE_FLAGS:
4430 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4431 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4432 return -ENOTSUP;
4433 if (add)
4434 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4435 else
4436 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4437 break;
4438 default:
4439 ret = -EINVAL;
4440 break;
4441 }
4442
4443 return ret;
4444 }
4445
4446 /*
4447 * igb_get_ntuple_filter - get a ntuple filter
4448 *
4449 * @param
4450 * dev: Pointer to struct rte_eth_dev.
4451 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4452 *
4453 * @return
4454 * - On success, zero.
4455 * - On failure, a negative value.
4456 */
4457 static int
4458 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4459 struct rte_eth_ntuple_filter *ntuple_filter)
4460 {
4461 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4462 struct e1000_filter_info *filter_info =
4463 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4464 struct e1000_5tuple_filter_info filter_5tuple;
4465 struct e1000_2tuple_filter_info filter_2tuple;
4466 struct e1000_5tuple_filter *p_5tuple_filter;
4467 struct e1000_2tuple_filter *p_2tuple_filter;
4468 int ret;
4469
4470 switch (ntuple_filter->flags) {
4471 case RTE_5TUPLE_FLAGS:
4472 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4473 if (hw->mac.type != e1000_82576)
4474 return -ENOTSUP;
4475 memset(&filter_5tuple,
4476 0,
4477 sizeof(struct e1000_5tuple_filter_info));
4478 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4479 &filter_5tuple);
4480 if (ret < 0)
4481 return ret;
4482 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4483 &filter_info->fivetuple_list,
4484 &filter_5tuple);
4485 if (p_5tuple_filter == NULL) {
4486 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4487 return -ENOENT;
4488 }
4489 ntuple_filter->queue = p_5tuple_filter->queue;
4490 break;
4491 case RTE_2TUPLE_FLAGS:
4492 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4493 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4494 return -ENOTSUP;
4495 memset(&filter_2tuple,
4496 0,
4497 sizeof(struct e1000_2tuple_filter_info));
4498 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4499 if (ret < 0)
4500 return ret;
4501 p_2tuple_filter = igb_2tuple_filter_lookup(
4502 &filter_info->twotuple_list,
4503 &filter_2tuple);
4504 if (p_2tuple_filter == NULL) {
4505 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4506 return -ENOENT;
4507 }
4508 ntuple_filter->queue = p_2tuple_filter->queue;
4509 break;
4510 default:
4511 ret = -EINVAL;
4512 break;
4513 }
4514
4515 return 0;
4516 }
4517
4518 /*
4519 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4520 * @dev: pointer to rte_eth_dev structure
4521 * @filter_op:operation will be taken.
4522 * @arg: a pointer to specific structure corresponding to the filter_op
4523 */
4524 static int
4525 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4526 enum rte_filter_op filter_op,
4527 void *arg)
4528 {
4529 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4530 int ret;
4531
4532 MAC_TYPE_FILTER_SUP(hw->mac.type);
4533
4534 if (filter_op == RTE_ETH_FILTER_NOP)
4535 return 0;
4536
4537 if (arg == NULL) {
4538 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4539 filter_op);
4540 return -EINVAL;
4541 }
4542
4543 switch (filter_op) {
4544 case RTE_ETH_FILTER_ADD:
4545 ret = igb_add_del_ntuple_filter(dev,
4546 (struct rte_eth_ntuple_filter *)arg,
4547 TRUE);
4548 break;
4549 case RTE_ETH_FILTER_DELETE:
4550 ret = igb_add_del_ntuple_filter(dev,
4551 (struct rte_eth_ntuple_filter *)arg,
4552 FALSE);
4553 break;
4554 case RTE_ETH_FILTER_GET:
4555 ret = igb_get_ntuple_filter(dev,
4556 (struct rte_eth_ntuple_filter *)arg);
4557 break;
4558 default:
4559 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4560 ret = -EINVAL;
4561 break;
4562 }
4563 return ret;
4564 }
4565
4566 static inline int
4567 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4568 uint16_t ethertype)
4569 {
4570 int i;
4571
4572 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4573 if (filter_info->ethertype_filters[i] == ethertype &&
4574 (filter_info->ethertype_mask & (1 << i)))
4575 return i;
4576 }
4577 return -1;
4578 }
4579
4580 static inline int
4581 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4582 uint16_t ethertype)
4583 {
4584 int i;
4585
4586 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4587 if (!(filter_info->ethertype_mask & (1 << i))) {
4588 filter_info->ethertype_mask |= 1 << i;
4589 filter_info->ethertype_filters[i] = ethertype;
4590 return i;
4591 }
4592 }
4593 return -1;
4594 }
4595
4596 static inline int
4597 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4598 uint8_t idx)
4599 {
4600 if (idx >= E1000_MAX_ETQF_FILTERS)
4601 return -1;
4602 filter_info->ethertype_mask &= ~(1 << idx);
4603 filter_info->ethertype_filters[idx] = 0;
4604 return idx;
4605 }
4606
4607
4608 static int
4609 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4610 struct rte_eth_ethertype_filter *filter,
4611 bool add)
4612 {
4613 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4614 struct e1000_filter_info *filter_info =
4615 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4616 uint32_t etqf = 0;
4617 int ret;
4618
4619 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4620 filter->ether_type == ETHER_TYPE_IPv6) {
4621 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4622 " ethertype filter.", filter->ether_type);
4623 return -EINVAL;
4624 }
4625
4626 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4627 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4628 return -EINVAL;
4629 }
4630 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4631 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4632 return -EINVAL;
4633 }
4634
4635 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4636 if (ret >= 0 && add) {
4637 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4638 filter->ether_type);
4639 return -EEXIST;
4640 }
4641 if (ret < 0 && !add) {
4642 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4643 filter->ether_type);
4644 return -ENOENT;
4645 }
4646
4647 if (add) {
4648 ret = igb_ethertype_filter_insert(filter_info,
4649 filter->ether_type);
4650 if (ret < 0) {
4651 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4652 return -ENOSYS;
4653 }
4654
4655 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4656 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4657 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4658 } else {
4659 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4660 if (ret < 0)
4661 return -ENOSYS;
4662 }
4663 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4664 E1000_WRITE_FLUSH(hw);
4665
4666 return 0;
4667 }
4668
4669 static int
4670 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4671 struct rte_eth_ethertype_filter *filter)
4672 {
4673 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4674 struct e1000_filter_info *filter_info =
4675 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4676 uint32_t etqf;
4677 int ret;
4678
4679 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4680 if (ret < 0) {
4681 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4682 filter->ether_type);
4683 return -ENOENT;
4684 }
4685
4686 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4687 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4688 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4689 filter->flags = 0;
4690 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4691 E1000_ETQF_QUEUE_SHIFT;
4692 return 0;
4693 }
4694
4695 return -ENOENT;
4696 }
4697
4698 /*
4699 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4700 * @dev: pointer to rte_eth_dev structure
4701 * @filter_op:operation will be taken.
4702 * @arg: a pointer to specific structure corresponding to the filter_op
4703 */
4704 static int
4705 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4706 enum rte_filter_op filter_op,
4707 void *arg)
4708 {
4709 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4710 int ret;
4711
4712 MAC_TYPE_FILTER_SUP(hw->mac.type);
4713
4714 if (filter_op == RTE_ETH_FILTER_NOP)
4715 return 0;
4716
4717 if (arg == NULL) {
4718 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4719 filter_op);
4720 return -EINVAL;
4721 }
4722
4723 switch (filter_op) {
4724 case RTE_ETH_FILTER_ADD:
4725 ret = igb_add_del_ethertype_filter(dev,
4726 (struct rte_eth_ethertype_filter *)arg,
4727 TRUE);
4728 break;
4729 case RTE_ETH_FILTER_DELETE:
4730 ret = igb_add_del_ethertype_filter(dev,
4731 (struct rte_eth_ethertype_filter *)arg,
4732 FALSE);
4733 break;
4734 case RTE_ETH_FILTER_GET:
4735 ret = igb_get_ethertype_filter(dev,
4736 (struct rte_eth_ethertype_filter *)arg);
4737 break;
4738 default:
4739 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4740 ret = -EINVAL;
4741 break;
4742 }
4743 return ret;
4744 }
4745
4746 static int
4747 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4748 enum rte_filter_type filter_type,
4749 enum rte_filter_op filter_op,
4750 void *arg)
4751 {
4752 int ret = -EINVAL;
4753
4754 switch (filter_type) {
4755 case RTE_ETH_FILTER_NTUPLE:
4756 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4757 break;
4758 case RTE_ETH_FILTER_ETHERTYPE:
4759 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4760 break;
4761 case RTE_ETH_FILTER_SYN:
4762 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4763 break;
4764 case RTE_ETH_FILTER_FLEXIBLE:
4765 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4766 break;
4767 default:
4768 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4769 filter_type);
4770 break;
4771 }
4772
4773 return ret;
4774 }
4775
4776 static int
4777 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4778 struct ether_addr *mc_addr_set,
4779 uint32_t nb_mc_addr)
4780 {
4781 struct e1000_hw *hw;
4782
4783 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4784 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4785 return 0;
4786 }
4787
4788 static uint64_t
4789 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4790 {
4791 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4792 uint64_t systime_cycles;
4793
4794 switch (hw->mac.type) {
4795 case e1000_i210:
4796 case e1000_i211:
4797 /*
4798 * Need to read System Time Residue Register to be able
4799 * to read the other two registers.
4800 */
4801 E1000_READ_REG(hw, E1000_SYSTIMR);
4802 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4803 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4804 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4805 * NSEC_PER_SEC;
4806 break;
4807 case e1000_82580:
4808 case e1000_i350:
4809 case e1000_i354:
4810 /*
4811 * Need to read System Time Residue Register to be able
4812 * to read the other two registers.
4813 */
4814 E1000_READ_REG(hw, E1000_SYSTIMR);
4815 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4816 /* Only the 8 LSB are valid. */
4817 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4818 & 0xff) << 32;
4819 break;
4820 default:
4821 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4822 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4823 << 32;
4824 break;
4825 }
4826
4827 return systime_cycles;
4828 }
4829
4830 static uint64_t
4831 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4832 {
4833 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4834 uint64_t rx_tstamp_cycles;
4835
4836 switch (hw->mac.type) {
4837 case e1000_i210:
4838 case e1000_i211:
4839 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4840 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4841 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4842 * NSEC_PER_SEC;
4843 break;
4844 case e1000_82580:
4845 case e1000_i350:
4846 case e1000_i354:
4847 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4848 /* Only the 8 LSB are valid. */
4849 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4850 & 0xff) << 32;
4851 break;
4852 default:
4853 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4854 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4855 << 32;
4856 break;
4857 }
4858
4859 return rx_tstamp_cycles;
4860 }
4861
4862 static uint64_t
4863 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4864 {
4865 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4866 uint64_t tx_tstamp_cycles;
4867
4868 switch (hw->mac.type) {
4869 case e1000_i210:
4870 case e1000_i211:
4871 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4872 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4873 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4874 * NSEC_PER_SEC;
4875 break;
4876 case e1000_82580:
4877 case e1000_i350:
4878 case e1000_i354:
4879 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4880 /* Only the 8 LSB are valid. */
4881 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4882 & 0xff) << 32;
4883 break;
4884 default:
4885 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4886 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4887 << 32;
4888 break;
4889 }
4890
4891 return tx_tstamp_cycles;
4892 }
4893
4894 static void
4895 igb_start_timecounters(struct rte_eth_dev *dev)
4896 {
4897 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4898 struct e1000_adapter *adapter =
4899 (struct e1000_adapter *)dev->data->dev_private;
4900 uint32_t incval = 1;
4901 uint32_t shift = 0;
4902 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4903
4904 switch (hw->mac.type) {
4905 case e1000_82580:
4906 case e1000_i350:
4907 case e1000_i354:
4908 /* 32 LSB bits + 8 MSB bits = 40 bits */
4909 mask = (1ULL << 40) - 1;
4910 /* fall-through */
4911 case e1000_i210:
4912 case e1000_i211:
4913 /*
4914 * Start incrementing the register
4915 * used to timestamp PTP packets.
4916 */
4917 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4918 break;
4919 case e1000_82576:
4920 incval = E1000_INCVALUE_82576;
4921 shift = IGB_82576_TSYNC_SHIFT;
4922 E1000_WRITE_REG(hw, E1000_TIMINCA,
4923 E1000_INCPERIOD_82576 | incval);
4924 break;
4925 default:
4926 /* Not supported */
4927 return;
4928 }
4929
4930 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4931 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4932 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4933
4934 adapter->systime_tc.cc_mask = mask;
4935 adapter->systime_tc.cc_shift = shift;
4936 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4937
4938 adapter->rx_tstamp_tc.cc_mask = mask;
4939 adapter->rx_tstamp_tc.cc_shift = shift;
4940 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4941
4942 adapter->tx_tstamp_tc.cc_mask = mask;
4943 adapter->tx_tstamp_tc.cc_shift = shift;
4944 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4945 }
4946
4947 static int
4948 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4949 {
4950 struct e1000_adapter *adapter =
4951 (struct e1000_adapter *)dev->data->dev_private;
4952
4953 adapter->systime_tc.nsec += delta;
4954 adapter->rx_tstamp_tc.nsec += delta;
4955 adapter->tx_tstamp_tc.nsec += delta;
4956
4957 return 0;
4958 }
4959
4960 static int
4961 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4962 {
4963 uint64_t ns;
4964 struct e1000_adapter *adapter =
4965 (struct e1000_adapter *)dev->data->dev_private;
4966
4967 ns = rte_timespec_to_ns(ts);
4968
4969 /* Set the timecounters to a new value. */
4970 adapter->systime_tc.nsec = ns;
4971 adapter->rx_tstamp_tc.nsec = ns;
4972 adapter->tx_tstamp_tc.nsec = ns;
4973
4974 return 0;
4975 }
4976
4977 static int
4978 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4979 {
4980 uint64_t ns, systime_cycles;
4981 struct e1000_adapter *adapter =
4982 (struct e1000_adapter *)dev->data->dev_private;
4983
4984 systime_cycles = igb_read_systime_cyclecounter(dev);
4985 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4986 *ts = rte_ns_to_timespec(ns);
4987
4988 return 0;
4989 }
4990
4991 static int
4992 igb_timesync_enable(struct rte_eth_dev *dev)
4993 {
4994 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4995 uint32_t tsync_ctl;
4996 uint32_t tsauxc;
4997
4998 /* Stop the timesync system time. */
4999 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5000 /* Reset the timesync system time value. */
5001 switch (hw->mac.type) {
5002 case e1000_82580:
5003 case e1000_i350:
5004 case e1000_i354:
5005 case e1000_i210:
5006 case e1000_i211:
5007 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5008 /* fall-through */
5009 case e1000_82576:
5010 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5011 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5012 break;
5013 default:
5014 /* Not supported. */
5015 return -ENOTSUP;
5016 }
5017
5018 /* Enable system time for it isn't on by default. */
5019 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5020 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5021 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5022
5023 igb_start_timecounters(dev);
5024
5025 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5026 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5027 (ETHER_TYPE_1588 |
5028 E1000_ETQF_FILTER_ENABLE |
5029 E1000_ETQF_1588));
5030
5031 /* Enable timestamping of received PTP packets. */
5032 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5033 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5034 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5035
5036 /* Enable Timestamping of transmitted PTP packets. */
5037 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5038 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5039 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5040
5041 return 0;
5042 }
5043
5044 static int
5045 igb_timesync_disable(struct rte_eth_dev *dev)
5046 {
5047 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5048 uint32_t tsync_ctl;
5049
5050 /* Disable timestamping of transmitted PTP packets. */
5051 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5052 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5053 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5054
5055 /* Disable timestamping of received PTP packets. */
5056 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5057 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5058 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5059
5060 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5061 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5062
5063 /* Stop incrementating the System Time registers. */
5064 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5065
5066 return 0;
5067 }
5068
5069 static int
5070 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5071 struct timespec *timestamp,
5072 uint32_t flags __rte_unused)
5073 {
5074 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5075 struct e1000_adapter *adapter =
5076 (struct e1000_adapter *)dev->data->dev_private;
5077 uint32_t tsync_rxctl;
5078 uint64_t rx_tstamp_cycles;
5079 uint64_t ns;
5080
5081 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5082 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5083 return -EINVAL;
5084
5085 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5086 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5087 *timestamp = rte_ns_to_timespec(ns);
5088
5089 return 0;
5090 }
5091
5092 static int
5093 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5094 struct timespec *timestamp)
5095 {
5096 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5097 struct e1000_adapter *adapter =
5098 (struct e1000_adapter *)dev->data->dev_private;
5099 uint32_t tsync_txctl;
5100 uint64_t tx_tstamp_cycles;
5101 uint64_t ns;
5102
5103 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5104 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5105 return -EINVAL;
5106
5107 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5108 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5109 *timestamp = rte_ns_to_timespec(ns);
5110
5111 return 0;
5112 }
5113
5114 static int
5115 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5116 {
5117 int count = 0;
5118 int g_ind = 0;
5119 const struct reg_info *reg_group;
5120
5121 while ((reg_group = igb_regs[g_ind++]))
5122 count += igb_reg_group_count(reg_group);
5123
5124 return count;
5125 }
5126
5127 static int
5128 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5129 {
5130 int count = 0;
5131 int g_ind = 0;
5132 const struct reg_info *reg_group;
5133
5134 while ((reg_group = igbvf_regs[g_ind++]))
5135 count += igb_reg_group_count(reg_group);
5136
5137 return count;
5138 }
5139
5140 static int
5141 eth_igb_get_regs(struct rte_eth_dev *dev,
5142 struct rte_dev_reg_info *regs)
5143 {
5144 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5145 uint32_t *data = regs->data;
5146 int g_ind = 0;
5147 int count = 0;
5148 const struct reg_info *reg_group;
5149
5150 if (data == NULL) {
5151 regs->length = eth_igb_get_reg_length(dev);
5152 regs->width = sizeof(uint32_t);
5153 return 0;
5154 }
5155
5156 /* Support only full register dump */
5157 if ((regs->length == 0) ||
5158 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5159 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5160 hw->device_id;
5161 while ((reg_group = igb_regs[g_ind++]))
5162 count += igb_read_regs_group(dev, &data[count],
5163 reg_group);
5164 return 0;
5165 }
5166
5167 return -ENOTSUP;
5168 }
5169
5170 static int
5171 igbvf_get_regs(struct rte_eth_dev *dev,
5172 struct rte_dev_reg_info *regs)
5173 {
5174 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5175 uint32_t *data = regs->data;
5176 int g_ind = 0;
5177 int count = 0;
5178 const struct reg_info *reg_group;
5179
5180 if (data == NULL) {
5181 regs->length = igbvf_get_reg_length(dev);
5182 regs->width = sizeof(uint32_t);
5183 return 0;
5184 }
5185
5186 /* Support only full register dump */
5187 if ((regs->length == 0) ||
5188 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5189 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5190 hw->device_id;
5191 while ((reg_group = igbvf_regs[g_ind++]))
5192 count += igb_read_regs_group(dev, &data[count],
5193 reg_group);
5194 return 0;
5195 }
5196
5197 return -ENOTSUP;
5198 }
5199
5200 static int
5201 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5202 {
5203 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5204
5205 /* Return unit is byte count */
5206 return hw->nvm.word_size * 2;
5207 }
5208
5209 static int
5210 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5211 struct rte_dev_eeprom_info *in_eeprom)
5212 {
5213 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5214 struct e1000_nvm_info *nvm = &hw->nvm;
5215 uint16_t *data = in_eeprom->data;
5216 int first, length;
5217
5218 first = in_eeprom->offset >> 1;
5219 length = in_eeprom->length >> 1;
5220 if ((first >= hw->nvm.word_size) ||
5221 ((first + length) >= hw->nvm.word_size))
5222 return -EINVAL;
5223
5224 in_eeprom->magic = hw->vendor_id |
5225 ((uint32_t)hw->device_id << 16);
5226
5227 if ((nvm->ops.read) == NULL)
5228 return -ENOTSUP;
5229
5230 return nvm->ops.read(hw, first, length, data);
5231 }
5232
5233 static int
5234 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5235 struct rte_dev_eeprom_info *in_eeprom)
5236 {
5237 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5238 struct e1000_nvm_info *nvm = &hw->nvm;
5239 uint16_t *data = in_eeprom->data;
5240 int first, length;
5241
5242 first = in_eeprom->offset >> 1;
5243 length = in_eeprom->length >> 1;
5244 if ((first >= hw->nvm.word_size) ||
5245 ((first + length) >= hw->nvm.word_size))
5246 return -EINVAL;
5247
5248 in_eeprom->magic = (uint32_t)hw->vendor_id |
5249 ((uint32_t)hw->device_id << 16);
5250
5251 if ((nvm->ops.write) == NULL)
5252 return -ENOTSUP;
5253 return nvm->ops.write(hw, first, length, data);
5254 }
5255
5256 static int
5257 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5258 {
5259 struct e1000_hw *hw =
5260 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5261 uint32_t mask = 1 << queue_id;
5262
5263 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5264 E1000_WRITE_FLUSH(hw);
5265
5266 return 0;
5267 }
5268
5269 static int
5270 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5271 {
5272 struct e1000_hw *hw =
5273 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5274 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5275 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5276 uint32_t mask = 1 << queue_id;
5277 uint32_t regval;
5278
5279 regval = E1000_READ_REG(hw, E1000_EIMS);
5280 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5281 E1000_WRITE_FLUSH(hw);
5282
5283 rte_intr_enable(intr_handle);
5284
5285 return 0;
5286 }
5287
5288 static void
5289 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5290 uint8_t index, uint8_t offset)
5291 {
5292 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5293
5294 /* clear bits */
5295 val &= ~((uint32_t)0xFF << offset);
5296
5297 /* write vector and valid bit */
5298 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5299
5300 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5301 }
5302
5303 static void
5304 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5305 uint8_t queue, uint8_t msix_vector)
5306 {
5307 uint32_t tmp = 0;
5308
5309 if (hw->mac.type == e1000_82575) {
5310 if (direction == 0)
5311 tmp = E1000_EICR_RX_QUEUE0 << queue;
5312 else if (direction == 1)
5313 tmp = E1000_EICR_TX_QUEUE0 << queue;
5314 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5315 } else if (hw->mac.type == e1000_82576) {
5316 if ((direction == 0) || (direction == 1))
5317 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5318 ((queue & 0x8) << 1) +
5319 8 * direction);
5320 } else if ((hw->mac.type == e1000_82580) ||
5321 (hw->mac.type == e1000_i350) ||
5322 (hw->mac.type == e1000_i354) ||
5323 (hw->mac.type == e1000_i210) ||
5324 (hw->mac.type == e1000_i211)) {
5325 if ((direction == 0) || (direction == 1))
5326 eth_igb_write_ivar(hw, msix_vector,
5327 queue >> 1,
5328 ((queue & 0x1) << 4) +
5329 8 * direction);
5330 }
5331 }
5332
5333 /* Sets up the hardware to generate MSI-X interrupts properly
5334 * @hw
5335 * board private structure
5336 */
5337 static void
5338 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5339 {
5340 int queue_id;
5341 uint32_t tmpval, regval, intr_mask;
5342 struct e1000_hw *hw =
5343 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5344 uint32_t vec = E1000_MISC_VEC_ID;
5345 uint32_t base = E1000_MISC_VEC_ID;
5346 uint32_t misc_shift = 0;
5347 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5348 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5349
5350 /* won't configure msix register if no mapping is done
5351 * between intr vector and event fd
5352 */
5353 if (!rte_intr_dp_is_en(intr_handle))
5354 return;
5355
5356 if (rte_intr_allow_others(intr_handle)) {
5357 vec = base = E1000_RX_VEC_START;
5358 misc_shift = 1;
5359 }
5360
5361 /* set interrupt vector for other causes */
5362 if (hw->mac.type == e1000_82575) {
5363 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5364 /* enable MSI-X PBA support */
5365 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5366
5367 /* Auto-Mask interrupts upon ICR read */
5368 tmpval |= E1000_CTRL_EXT_EIAME;
5369 tmpval |= E1000_CTRL_EXT_IRCA;
5370
5371 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5372
5373 /* enable msix_other interrupt */
5374 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5375 regval = E1000_READ_REG(hw, E1000_EIAC);
5376 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5377 regval = E1000_READ_REG(hw, E1000_EIAM);
5378 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5379 } else if ((hw->mac.type == e1000_82576) ||
5380 (hw->mac.type == e1000_82580) ||
5381 (hw->mac.type == e1000_i350) ||
5382 (hw->mac.type == e1000_i354) ||
5383 (hw->mac.type == e1000_i210) ||
5384 (hw->mac.type == e1000_i211)) {
5385 /* turn on MSI-X capability first */
5386 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5387 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5388 E1000_GPIE_NSICR);
5389 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5390 misc_shift;
5391 regval = E1000_READ_REG(hw, E1000_EIAC);
5392 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5393
5394 /* enable msix_other interrupt */
5395 regval = E1000_READ_REG(hw, E1000_EIMS);
5396 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5397 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5398 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5399 }
5400
5401 /* use EIAM to auto-mask when MSI-X interrupt
5402 * is asserted, this saves a register write for every interrupt
5403 */
5404 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5405 misc_shift;
5406 regval = E1000_READ_REG(hw, E1000_EIAM);
5407 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5408
5409 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5410 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5411 intr_handle->intr_vec[queue_id] = vec;
5412 if (vec < base + intr_handle->nb_efd - 1)
5413 vec++;
5414 }
5415
5416 E1000_WRITE_FLUSH(hw);
5417 }
5418
5419 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5420 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5421 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio");
5422 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5423 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5424 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio");
Ceph