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1 /*
2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 *
5 * Copyright (c) 2014, Cisco Systems, Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 *
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in
17 * the documentation and/or other materials provided with the
18 * distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 #ifndef _CQ_ENET_DESC_H_
36 #define _CQ_ENET_DESC_H_
37
38 #include "cq_desc.h"
39
40 /* Ethernet completion queue descriptor: 16B */
41 struct cq_enet_wq_desc {
42 __le16 completed_index;
43 __le16 q_number;
44 u8 reserved[11];
45 u8 type_color;
46 };
47
48 static inline void cq_enet_wq_desc_enc(struct cq_enet_wq_desc *desc,
49 u8 type, u8 color, u16 q_number, u16 completed_index)
50 {
51 cq_desc_enc((struct cq_desc *)desc, type,
52 color, q_number, completed_index);
53 }
54
55 static inline void cq_enet_wq_desc_dec(struct cq_enet_wq_desc *desc,
56 u8 *type, u8 *color, u16 *q_number, u16 *completed_index)
57 {
58 cq_desc_dec((struct cq_desc *)desc, type,
59 color, q_number, completed_index);
60 }
61
62 /* Completion queue descriptor: Ethernet receive queue, 16B */
63 struct cq_enet_rq_desc {
64 __le16 completed_index_flags;
65 __le16 q_number_rss_type_flags;
66 __le32 rss_hash;
67 __le16 bytes_written_flags;
68 __le16 vlan;
69 __le16 checksum_fcoe;
70 u8 flags;
71 u8 type_color;
72 };
73
74 #define CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT (0x1 << 12)
75 #define CQ_ENET_RQ_DESC_FLAGS_FCOE (0x1 << 13)
76 #define CQ_ENET_RQ_DESC_FLAGS_EOP (0x1 << 14)
77 #define CQ_ENET_RQ_DESC_FLAGS_SOP (0x1 << 15)
78
79 #define CQ_ENET_RQ_DESC_RSS_TYPE_BITS 4
80 #define CQ_ENET_RQ_DESC_RSS_TYPE_MASK \
81 ((1 << CQ_ENET_RQ_DESC_RSS_TYPE_BITS) - 1)
82 #define CQ_ENET_RQ_DESC_RSS_TYPE_NONE 0
83 #define CQ_ENET_RQ_DESC_RSS_TYPE_IPv4 1
84 #define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv4 2
85 #define CQ_ENET_RQ_DESC_RSS_TYPE_IPv6 3
86 #define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6 4
87 #define CQ_ENET_RQ_DESC_RSS_TYPE_IPv6_EX 5
88 #define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6_EX 6
89
90 #define CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC (0x1 << 14)
91
92 #define CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS 14
93 #define CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK \
94 ((1 << CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS) - 1)
95 #define CQ_ENET_RQ_DESC_FLAGS_TRUNCATED (0x1 << 14)
96 #define CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED (0x1 << 15)
97
98 #define CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_BITS 12
99 #define CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_MASK \
100 ((1 << CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_BITS) - 1)
101 #define CQ_ENET_RQ_DESC_VLAN_TCI_CFI_MASK (0x1 << 12)
102 #define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_BITS 3
103 #define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_MASK \
104 ((1 << CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_BITS) - 1)
105 #define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_SHIFT 13
106
107 #define CQ_ENET_RQ_DESC_FCOE_SOF_BITS 8
108 #define CQ_ENET_RQ_DESC_FCOE_SOF_MASK \
109 ((1 << CQ_ENET_RQ_DESC_FCOE_SOF_BITS) - 1)
110 #define CQ_ENET_RQ_DESC_FCOE_EOF_BITS 8
111 #define CQ_ENET_RQ_DESC_FCOE_EOF_MASK \
112 ((1 << CQ_ENET_RQ_DESC_FCOE_EOF_BITS) - 1)
113 #define CQ_ENET_RQ_DESC_FCOE_EOF_SHIFT 8
114
115 #define CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK (0x1 << 0)
116 #define CQ_ENET_RQ_DESC_FCOE_FC_CRC_OK (0x1 << 0)
117 #define CQ_ENET_RQ_DESC_FLAGS_UDP (0x1 << 1)
118 #define CQ_ENET_RQ_DESC_FCOE_ENC_ERROR (0x1 << 1)
119 #define CQ_ENET_RQ_DESC_FLAGS_TCP (0x1 << 2)
120 #define CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK (0x1 << 3)
121 #define CQ_ENET_RQ_DESC_FLAGS_IPV6 (0x1 << 4)
122 #define CQ_ENET_RQ_DESC_FLAGS_IPV4 (0x1 << 5)
123 #define CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT (0x1 << 6)
124 #define CQ_ENET_RQ_DESC_FLAGS_FCS_OK (0x1 << 7)
125
126 static inline void cq_enet_rq_desc_enc(struct cq_enet_rq_desc *desc,
127 u8 type, u8 color, u16 q_number, u16 completed_index,
128 u8 ingress_port, u8 fcoe, u8 eop, u8 sop, u8 rss_type, u8 csum_not_calc,
129 u32 rss_hash, u16 bytes_written, u8 packet_error, u8 vlan_stripped,
130 u16 vlan, u16 checksum, u8 fcoe_sof, u8 fcoe_fc_crc_ok,
131 u8 fcoe_enc_error, u8 fcoe_eof, u8 tcp_udp_csum_ok, u8 udp, u8 tcp,
132 u8 ipv4_csum_ok, u8 ipv6, u8 ipv4, u8 ipv4_fragment, u8 fcs_ok)
133 {
134 cq_desc_enc((struct cq_desc *)desc, type,
135 color, q_number, completed_index);
136
137 desc->completed_index_flags |= cpu_to_le16(
138 (ingress_port ? CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT : 0) |
139 (fcoe ? CQ_ENET_RQ_DESC_FLAGS_FCOE : 0) |
140 (eop ? CQ_ENET_RQ_DESC_FLAGS_EOP : 0) |
141 (sop ? CQ_ENET_RQ_DESC_FLAGS_SOP : 0));
142
143 desc->q_number_rss_type_flags |= cpu_to_le16(
144 ((rss_type & CQ_ENET_RQ_DESC_RSS_TYPE_MASK) <<
145 CQ_DESC_Q_NUM_BITS) |
146 (csum_not_calc ? CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC : 0));
147
148 desc->rss_hash = cpu_to_le32(rss_hash);
149
150 desc->bytes_written_flags = cpu_to_le16(
151 (bytes_written & CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK) |
152 (packet_error ? CQ_ENET_RQ_DESC_FLAGS_TRUNCATED : 0) |
153 (vlan_stripped ? CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED : 0));
154
155 desc->vlan = cpu_to_le16(vlan);
156
157 if (fcoe) {
158 desc->checksum_fcoe = cpu_to_le16(
159 (fcoe_sof & CQ_ENET_RQ_DESC_FCOE_SOF_MASK) |
160 ((fcoe_eof & CQ_ENET_RQ_DESC_FCOE_EOF_MASK) <<
161 CQ_ENET_RQ_DESC_FCOE_EOF_SHIFT));
162 } else {
163 desc->checksum_fcoe = cpu_to_le16(checksum);
164 }
165
166 desc->flags =
167 (tcp_udp_csum_ok ? CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK : 0) |
168 (udp ? CQ_ENET_RQ_DESC_FLAGS_UDP : 0) |
169 (tcp ? CQ_ENET_RQ_DESC_FLAGS_TCP : 0) |
170 (ipv4_csum_ok ? CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK : 0) |
171 (ipv6 ? CQ_ENET_RQ_DESC_FLAGS_IPV6 : 0) |
172 (ipv4 ? CQ_ENET_RQ_DESC_FLAGS_IPV4 : 0) |
173 (ipv4_fragment ? CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT : 0) |
174 (fcs_ok ? CQ_ENET_RQ_DESC_FLAGS_FCS_OK : 0) |
175 (fcoe_fc_crc_ok ? CQ_ENET_RQ_DESC_FCOE_FC_CRC_OK : 0) |
176 (fcoe_enc_error ? CQ_ENET_RQ_DESC_FCOE_ENC_ERROR : 0);
177 }
178
179 static inline void cq_enet_rq_desc_dec(struct cq_enet_rq_desc *desc,
180 u8 *type, u8 *color, u16 *q_number, u16 *completed_index,
181 u8 *ingress_port, u8 *fcoe, u8 *eop, u8 *sop, u8 *rss_type,
182 u8 *csum_not_calc, u32 *rss_hash, u16 *bytes_written, u8 *packet_error,
183 u8 *vlan_stripped, u16 *vlan_tci, u16 *checksum, u8 *fcoe_sof,
184 u8 *fcoe_fc_crc_ok, u8 *fcoe_enc_error, u8 *fcoe_eof,
185 u8 *tcp_udp_csum_ok, u8 *udp, u8 *tcp, u8 *ipv4_csum_ok,
186 u8 *ipv6, u8 *ipv4, u8 *ipv4_fragment, u8 *fcs_ok)
187 {
188 u16 completed_index_flags;
189 u16 q_number_rss_type_flags;
190 u16 bytes_written_flags;
191
192 cq_desc_dec((struct cq_desc *)desc, type,
193 color, q_number, completed_index);
194
195 completed_index_flags = le16_to_cpu(desc->completed_index_flags);
196 q_number_rss_type_flags =
197 le16_to_cpu(desc->q_number_rss_type_flags);
198 bytes_written_flags = le16_to_cpu(desc->bytes_written_flags);
199
200 *ingress_port = (completed_index_flags &
201 CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT) ? 1 : 0;
202 *fcoe = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_FCOE) ?
203 1 : 0;
204 *eop = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_EOP) ?
205 1 : 0;
206 *sop = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_SOP) ?
207 1 : 0;
208
209 *rss_type = (u8)((q_number_rss_type_flags >> CQ_DESC_Q_NUM_BITS) &
210 CQ_ENET_RQ_DESC_RSS_TYPE_MASK);
211 *csum_not_calc = (q_number_rss_type_flags &
212 CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC) ? 1 : 0;
213
214 *rss_hash = le32_to_cpu(desc->rss_hash);
215
216 *bytes_written = bytes_written_flags &
217 CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
218 *packet_error = (bytes_written_flags &
219 CQ_ENET_RQ_DESC_FLAGS_TRUNCATED) ? 1 : 0;
220 *vlan_stripped = (bytes_written_flags &
221 CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED) ? 1 : 0;
222
223 /*
224 * Tag Control Information(16) = user_priority(3) + cfi(1) + vlan(12)
225 */
226 *vlan_tci = le16_to_cpu(desc->vlan);
227
228 if (*fcoe) {
229 *fcoe_sof = (u8)(le16_to_cpu(desc->checksum_fcoe) &
230 CQ_ENET_RQ_DESC_FCOE_SOF_MASK);
231 *fcoe_fc_crc_ok = (desc->flags &
232 CQ_ENET_RQ_DESC_FCOE_FC_CRC_OK) ? 1 : 0;
233 *fcoe_enc_error = (desc->flags &
234 CQ_ENET_RQ_DESC_FCOE_ENC_ERROR) ? 1 : 0;
235 *fcoe_eof = (u8)((le16_to_cpu(desc->checksum_fcoe) >>
236 CQ_ENET_RQ_DESC_FCOE_EOF_SHIFT) &
237 CQ_ENET_RQ_DESC_FCOE_EOF_MASK);
238 *checksum = 0;
239 } else {
240 *fcoe_sof = 0;
241 *fcoe_fc_crc_ok = 0;
242 *fcoe_enc_error = 0;
243 *fcoe_eof = 0;
244 *checksum = le16_to_cpu(desc->checksum_fcoe);
245 }
246
247 *tcp_udp_csum_ok =
248 (desc->flags & CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK) ? 1 : 0;
249 *udp = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_UDP) ? 1 : 0;
250 *tcp = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_TCP) ? 1 : 0;
251 *ipv4_csum_ok =
252 (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK) ? 1 : 0;
253 *ipv6 = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV6) ? 1 : 0;
254 *ipv4 = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4) ? 1 : 0;
255 *ipv4_fragment =
256 (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT) ? 1 : 0;
257 *fcs_ok = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_FCS_OK) ? 1 : 0;
258 }
259
260 #endif /* _CQ_ENET_DESC_H_ */