1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
6 #include "i40e_prototype.h"
9 * i40e_diag_set_loopback
10 * @hw: pointer to the hw struct
11 * @mode: loopback mode
13 * Set chosen loopback mode
15 enum i40e_status_code
i40e_diag_set_loopback(struct i40e_hw
*hw
,
16 enum i40e_lb_mode mode
)
18 enum i40e_status_code ret_code
= I40E_SUCCESS
;
20 if (i40e_aq_set_lb_modes(hw
, mode
, NULL
))
21 ret_code
= I40E_ERR_DIAG_TEST_FAILED
;
27 * i40e_diag_reg_pattern_test
28 * @hw: pointer to the hw struct
29 * @reg: reg to be tested
30 * @mask: bits to be touched
32 static enum i40e_status_code
i40e_diag_reg_pattern_test(struct i40e_hw
*hw
,
35 const u32 patterns
[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
36 u32 pat
, val
, orig_val
;
39 orig_val
= rd32(hw
, reg
);
40 for (i
= 0; i
< ARRAY_SIZE(patterns
); i
++) {
42 wr32(hw
, reg
, (pat
& mask
));
44 if ((val
& mask
) != (pat
& mask
)) {
45 return I40E_ERR_DIAG_TEST_FAILED
;
49 wr32(hw
, reg
, orig_val
);
51 if (val
!= orig_val
) {
52 return I40E_ERR_DIAG_TEST_FAILED
;
58 static struct i40e_diag_reg_test_info i40e_reg_list
[] = {
59 /* offset mask elements stride */
60 {I40E_QTX_CTL(0), 0x0000FFBF, 1, I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},
61 {I40E_PFINT_ITR0(0), 0x00000FFF, 3, I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)},
62 {I40E_PFINT_ITRN(0, 0), 0x00000FFF, 1, I40E_PFINT_ITRN(0, 1) - I40E_PFINT_ITRN(0, 0)},
63 {I40E_PFINT_ITRN(1, 0), 0x00000FFF, 1, I40E_PFINT_ITRN(1, 1) - I40E_PFINT_ITRN(1, 0)},
64 {I40E_PFINT_ITRN(2, 0), 0x00000FFF, 1, I40E_PFINT_ITRN(2, 1) - I40E_PFINT_ITRN(2, 0)},
65 {I40E_PFINT_STAT_CTL0
, 0x0000000C, 1, 0},
66 {I40E_PFINT_LNKLST0
, 0x00001FFF, 1, 0},
67 {I40E_PFINT_LNKLSTN(0), 0x000007FF, 1, I40E_PFINT_LNKLSTN(1) - I40E_PFINT_LNKLSTN(0)},
68 {I40E_QINT_TQCTL(0), 0x000000FF, 1, I40E_QINT_TQCTL(1) - I40E_QINT_TQCTL(0)},
69 {I40E_QINT_RQCTL(0), 0x000000FF, 1, I40E_QINT_RQCTL(1) - I40E_QINT_RQCTL(0)},
70 {I40E_PFINT_ICR0_ENA
, 0xF7F20000, 1, 0},
76 * @hw: pointer to the hw struct
78 * Perform registers diagnostic test
80 enum i40e_status_code
i40e_diag_reg_test(struct i40e_hw
*hw
)
82 enum i40e_status_code ret_code
= I40E_SUCCESS
;
86 for (i
= 0; i40e_reg_list
[i
].offset
!= 0 &&
87 ret_code
== I40E_SUCCESS
; i
++) {
89 /* set actual reg range for dynamically allocated resources */
90 if (i40e_reg_list
[i
].offset
== I40E_QTX_CTL(0) &&
91 hw
->func_caps
.num_tx_qp
!= 0)
92 i40e_reg_list
[i
].elements
= hw
->func_caps
.num_tx_qp
;
93 if ((i40e_reg_list
[i
].offset
== I40E_PFINT_ITRN(0, 0) ||
94 i40e_reg_list
[i
].offset
== I40E_PFINT_ITRN(1, 0) ||
95 i40e_reg_list
[i
].offset
== I40E_PFINT_ITRN(2, 0) ||
96 i40e_reg_list
[i
].offset
== I40E_QINT_TQCTL(0) ||
97 i40e_reg_list
[i
].offset
== I40E_QINT_RQCTL(0)) &&
98 hw
->func_caps
.num_msix_vectors
!= 0)
99 i40e_reg_list
[i
].elements
=
100 hw
->func_caps
.num_msix_vectors
- 1;
102 /* test register access */
103 mask
= i40e_reg_list
[i
].mask
;
104 for (j
= 0; j
< i40e_reg_list
[i
].elements
&&
105 ret_code
== I40E_SUCCESS
; j
++) {
106 reg
= i40e_reg_list
[i
].offset
107 + (j
* i40e_reg_list
[i
].stride
);
108 ret_code
= i40e_diag_reg_pattern_test(hw
, reg
, mask
);
116 * i40e_diag_eeprom_test
117 * @hw: pointer to the hw struct
119 * Perform EEPROM diagnostic test
121 enum i40e_status_code
i40e_diag_eeprom_test(struct i40e_hw
*hw
)
123 enum i40e_status_code ret_code
;
126 /* read NVM control word and if NVM valid, validate EEPROM checksum*/
127 ret_code
= i40e_read_nvm_word(hw
, I40E_SR_NVM_CONTROL_WORD
, ®_val
);
128 if ((ret_code
== I40E_SUCCESS
) &&
129 ((reg_val
& I40E_SR_CONTROL_WORD_1_MASK
) ==
130 BIT(I40E_SR_CONTROL_WORD_1_SHIFT
)))
131 return i40e_validate_nvm_checksum(hw
, NULL
);
133 return I40E_ERR_DIAG_TEST_FAILED
;
137 * i40e_diag_fw_alive_test
138 * @hw: pointer to the hw struct
140 * Perform FW alive diagnostic test
142 enum i40e_status_code
i40e_diag_fw_alive_test(struct i40e_hw
*hw
)
144 UNREFERENCED_1PARAMETER(hw
);