ceph/src/seastar/dpdk/drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef LINUX_MACROS
  53 #ifndef BIT
  54 #define BIT(a) (1UL << (a))
  55 #endif /* BIT */
  56 #ifndef BIT_ULL
  57 #define BIT_ULL(a) (1ULL << (a))
  58 #endif /* BIT_ULL */
  59 #endif /* LINUX_MACROS */
  60
  61 #ifndef I40E_MASK
  62 /* I40E_MASK is a macro used on 32 bit registers */
  63 #define I40E_MASK(mask, shift) (mask << shift)
  64 #endif
  65
  66 #define I40E_MAX_PF                     16
  67 #define I40E_MAX_PF_VSI                 64
  68 #define I40E_MAX_PF_QP                  128
  69 #define I40E_MAX_VSI_QP                 16
  70 #define I40E_MAX_VF_VSI                 3
  71 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  73
  74 /* something less than 1 minute */
  75 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  76
  77 /* Max default timeout in ms, */
  78 #define I40E_MAX_NVM_TIMEOUT            18000
  79
  80 /* Check whether address is multicast. */
  81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  82
  83 /* Check whether an address is broadcast. */
  84 #define I40E_IS_BROADCAST(address)      \
  85         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  86         (((u8 *)(address))[1] == ((u8)0xff)))
  87
  88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  89 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  90
  91 /* forward declaration */
  92 struct i40e_hw;
  93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  94
  95 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  96 /* Data type manipulation macros. */
  97 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  98 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  99
 100 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 101 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 102
 103 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 104 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 105
 106 /* Number of Transmit Descriptors must be a multiple of 8. */
 107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 108 /* Number of Receive Descriptors must be a multiple of 32 if
 109  * the number of descriptors is greater than 32.
 110  */
 111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 112
 113 #define I40E_DESC_UNUSED(R)     \
 114         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 115         (R)->next_to_clean - (R)->next_to_use - 1)
 116
 117 /* bitfields for Tx queue mapping in QTX_CTL */
 118 #define I40E_QTX_CTL_VF_QUEUE   0x0
 119 #define I40E_QTX_CTL_VM_QUEUE   0x1
 120 #define I40E_QTX_CTL_PF_QUEUE   0x2
 121
 122 /* debug masks - set these bits in hw->debug_mask to control output */
 123 enum i40e_debug_mask {
 124         I40E_DEBUG_INIT                 = 0x00000001,
 125         I40E_DEBUG_RELEASE              = 0x00000002,
 126
 127         I40E_DEBUG_LINK                 = 0x00000010,
 128         I40E_DEBUG_PHY                  = 0x00000020,
 129         I40E_DEBUG_HMC                  = 0x00000040,
 130         I40E_DEBUG_NVM                  = 0x00000080,
 131         I40E_DEBUG_LAN                  = 0x00000100,
 132         I40E_DEBUG_FLOW                 = 0x00000200,
 133         I40E_DEBUG_DCB                  = 0x00000400,
 134         I40E_DEBUG_DIAG                 = 0x00000800,
 135         I40E_DEBUG_FD                   = 0x00001000,
 136         I40E_DEBUG_PACKAGE              = 0x00002000,
 137
 138         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 139         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 140         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 141         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 142         I40E_DEBUG_AQ                   = 0x0F000000,
 143
 144         I40E_DEBUG_USER                 = 0xF0000000,
 145
 146         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 147 };
 148
 149 /* PCI Bus Info */
 150 #define I40E_PCI_LINK_STATUS            0xB2
 151 #define I40E_PCI_LINK_WIDTH             0x3F0
 152 #define I40E_PCI_LINK_WIDTH_1           0x10
 153 #define I40E_PCI_LINK_WIDTH_2           0x20
 154 #define I40E_PCI_LINK_WIDTH_4           0x40
 155 #define I40E_PCI_LINK_WIDTH_8           0x80
 156 #define I40E_PCI_LINK_SPEED             0xF
 157 #define I40E_PCI_LINK_SPEED_2500        0x1
 158 #define I40E_PCI_LINK_SPEED_5000        0x2
 159 #define I40E_PCI_LINK_SPEED_8000        0x3
 160
 161 #define I40E_MDIO_CLAUSE22_STCODE_MASK  I40E_MASK(1, \
 162                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 163 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_MASK(1, \
 164                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 165 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_MASK(2, \
 166                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 167
 168 #define I40E_MDIO_CLAUSE45_STCODE_MASK  I40E_MASK(0, \
 169                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 170 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_MASK(0, \
 171                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 172 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_MASK(1, \
 173                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 174 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    I40E_MASK(2, \
 175                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 176 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_MASK(3, \
 177                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 178
 179 #define I40E_PHY_COM_REG_PAGE                   0x1E
 180 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 181 #define I40E_PHY_LED_MANUAL_ON                  0x100
 182 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 183 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 184 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 185
 186 /* Memory types */
 187 enum i40e_memset_type {
 188         I40E_NONDMA_MEM = 0,
 189         I40E_DMA_MEM
 190 };
 191
 192 /* Memcpy types */
 193 enum i40e_memcpy_type {
 194         I40E_NONDMA_TO_NONDMA = 0,
 195         I40E_NONDMA_TO_DMA,
 196         I40E_DMA_TO_DMA,
 197         I40E_DMA_TO_NONDMA
 198 };
 199
 200 #define I40E_FW_API_VERSION_MINOR_X722  0x0005
 201 #define I40E_FW_API_VERSION_MINOR_X710  0x0005
 202
 203
 204 /* These are structs for managing the hardware information and the operations.
 205  * The structures of function pointers are filled out at init time when we
 206  * know for sure exactly which hardware we're working with.  This gives us the
 207  * flexibility of using the same main driver code but adapting to slightly
 208  * different hardware needs as new parts are developed.  For this architecture,
 209  * the Firmware and AdminQ are intended to insulate the driver from most of the
 210  * future changes, but these structures will also do part of the job.
 211  */
 212 enum i40e_mac_type {
 213         I40E_MAC_UNKNOWN = 0,
 214         I40E_MAC_XL710,
 215         I40E_MAC_VF,
 216         I40E_MAC_X722,
 217         I40E_MAC_X722_VF,
 218         I40E_MAC_GENERIC,
 219 };
 220
 221 enum i40e_media_type {
 222         I40E_MEDIA_TYPE_UNKNOWN = 0,
 223         I40E_MEDIA_TYPE_FIBER,
 224         I40E_MEDIA_TYPE_BASET,
 225         I40E_MEDIA_TYPE_BACKPLANE,
 226         I40E_MEDIA_TYPE_CX4,
 227         I40E_MEDIA_TYPE_DA,
 228         I40E_MEDIA_TYPE_VIRTUAL
 229 };
 230
 231 enum i40e_fc_mode {
 232         I40E_FC_NONE = 0,
 233         I40E_FC_RX_PAUSE,
 234         I40E_FC_TX_PAUSE,
 235         I40E_FC_FULL,
 236         I40E_FC_PFC,
 237         I40E_FC_DEFAULT
 238 };
 239
 240 enum i40e_set_fc_aq_failures {
 241         I40E_SET_FC_AQ_FAIL_NONE = 0,
 242         I40E_SET_FC_AQ_FAIL_GET = 1,
 243         I40E_SET_FC_AQ_FAIL_SET = 2,
 244         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 245         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 246 };
 247
 248 enum i40e_vsi_type {
 249         I40E_VSI_MAIN   = 0,
 250         I40E_VSI_VMDQ1  = 1,
 251         I40E_VSI_VMDQ2  = 2,
 252         I40E_VSI_CTRL   = 3,
 253         I40E_VSI_FCOE   = 4,
 254         I40E_VSI_MIRROR = 5,
 255         I40E_VSI_SRIOV  = 6,
 256         I40E_VSI_FDIR   = 7,
 257         I40E_VSI_TYPE_UNKNOWN
 258 };
 259
 260 enum i40e_queue_type {
 261         I40E_QUEUE_TYPE_RX = 0,
 262         I40E_QUEUE_TYPE_TX,
 263         I40E_QUEUE_TYPE_PE_CEQ,
 264         I40E_QUEUE_TYPE_UNKNOWN
 265 };
 266
 267 struct i40e_link_status {
 268         enum i40e_aq_phy_type phy_type;
 269         enum i40e_aq_link_speed link_speed;
 270         u8 link_info;
 271         u8 an_info;
 272         u8 fec_info;
 273         u8 ext_info;
 274         u8 loopback;
 275         /* is Link Status Event notification to SW enabled */
 276         bool lse_enable;
 277         u16 max_frame_size;
 278         bool crc_enable;
 279         u8 pacing;
 280         u8 requested_speeds;
 281         u8 module_type[3];
 282         /* 1st byte: module identifier */
 283 #define I40E_MODULE_TYPE_SFP            0x03
 284 #define I40E_MODULE_TYPE_QSFP           0x0D
 285         /* 2nd byte: ethernet compliance codes for 10/40G */
 286 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 287 #define I40E_MODULE_TYPE_40G_LR4        0x02
 288 #define I40E_MODULE_TYPE_40G_SR4        0x04
 289 #define I40E_MODULE_TYPE_40G_CR4        0x08
 290 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 291 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 292 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 293 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 294         /* 3rd byte: ethernet compliance codes for 1G */
 295 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 296 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 297 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 298 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 299 };
 300
 301 struct i40e_phy_info {
 302         struct i40e_link_status link_info;
 303         struct i40e_link_status link_info_old;
 304         bool get_link_info;
 305         enum i40e_media_type media_type;
 306         /* all the phy types the NVM is capable of */
 307         u64 phy_types;
 308 };
 309
 310 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 311 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 312 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 313 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 314 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 315 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 316 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 317 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 318 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 319 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 320 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 321 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 322 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 323 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 324 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 325 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 326 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 327 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 328 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 329 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 330 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 331 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 332 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 333 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 334 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 335 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 336 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 337                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 338 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 339 /*
 340  * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
 341  * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
 342  * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
 343  * a shift is needed to adjust for this with values larger than 31. The
 344  * only affected values are I40E_PHY_TYPE_25GBASE_*.
 345  */
 346 #define I40E_PHY_TYPE_OFFSET 1
 347 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
 348                                              I40E_PHY_TYPE_OFFSET)
 349 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
 350                                              I40E_PHY_TYPE_OFFSET)
 351 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
 352                                              I40E_PHY_TYPE_OFFSET)
 353 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
 354                                              I40E_PHY_TYPE_OFFSET)
 355 #define I40E_HW_CAP_MAX_GPIO                    30
 356 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 357 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 358
 359 enum i40e_acpi_programming_method {
 360         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 361         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 362 };
 363
 364 #define I40E_WOL_SUPPORT_MASK                   0x1
 365 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       0x2
 366 #define I40E_PROXY_SUPPORT_MASK                 0x4
 367
 368 /* Capabilities of a PF or a VF or the whole device */
 369 struct i40e_hw_capabilities {
 370         u32  switch_mode;
 371 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 372 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 373 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 374
 375         u32  management_mode;
 376         u32  mng_protocols_over_mctp;
 377 #define I40E_MNG_PROTOCOL_PLDM          0x2
 378 #define I40E_MNG_PROTOCOL_OEM_COMMANDS  0x4
 379 #define I40E_MNG_PROTOCOL_NCSI          0x8
 380         u32  npar_enable;
 381         u32  os2bmc;
 382         u32  valid_functions;
 383         bool sr_iov_1_1;
 384         bool vmdq;
 385         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 386         bool evb_802_1_qbh; /* Bridge Port Extension */
 387         bool dcb;
 388         bool fcoe;
 389         bool iscsi; /* Indicates iSCSI enabled */
 390         bool flex10_enable;
 391         bool flex10_capable;
 392         u32  flex10_mode;
 393 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 394 #define I40E_FLEX10_MODE_DCC            0x1
 395 #define I40E_FLEX10_MODE_DCI            0x2
 396
 397         u32 flex10_status;
 398 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 399 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 400
 401         bool sec_rev_disabled;
 402         bool update_disabled;
 403 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 404 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 405
 406         bool mgmt_cem;
 407         bool ieee_1588;
 408         bool iwarp;
 409         bool fd;
 410         u32 fd_filters_guaranteed;
 411         u32 fd_filters_best_effort;
 412         bool rss;
 413         u32 rss_table_size;
 414         u32 rss_table_entry_width;
 415         bool led[I40E_HW_CAP_MAX_GPIO];
 416         bool sdp[I40E_HW_CAP_MAX_GPIO];
 417         u32 nvm_image_type;
 418         u32 num_flow_director_filters;
 419         u32 num_vfs;
 420         u32 vf_base_id;
 421         u32 num_vsis;
 422         u32 num_rx_qp;
 423         u32 num_tx_qp;
 424         u32 base_queue;
 425         u32 num_msix_vectors;
 426         u32 num_msix_vectors_vf;
 427         u32 led_pin_num;
 428         u32 sdp_pin_num;
 429         u32 mdio_port_num;
 430         u32 mdio_port_mode;
 431         u8 rx_buf_chain_len;
 432         u32 enabled_tcmap;
 433         u32 maxtc;
 434         u64 wr_csr_prot;
 435         bool apm_wol_support;
 436         enum i40e_acpi_programming_method acpi_prog_method;
 437         bool proxy_support;
 438 };
 439
 440 struct i40e_mac_info {
 441         enum i40e_mac_type type;
 442         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 443         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 444         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 445         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 446         u16 max_fcoeq;
 447 };
 448
 449 enum i40e_aq_resources_ids {
 450         I40E_NVM_RESOURCE_ID = 1
 451 };
 452
 453 enum i40e_aq_resource_access_type {
 454         I40E_RESOURCE_READ = 1,
 455         I40E_RESOURCE_WRITE
 456 };
 457
 458 struct i40e_nvm_info {
 459         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 460         u32 timeout;              /* [ms] */
 461         u16 sr_size;              /* Shadow RAM size in words */
 462         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 463         u16 version;              /* NVM package version */
 464         u32 eetrack;              /* NVM data version */
 465         u32 oem_ver;              /* OEM version info */
 466 };
 467
 468 /* definitions used in NVM update support */
 469
 470 enum i40e_nvmupd_cmd {
 471         I40E_NVMUPD_INVALID,
 472         I40E_NVMUPD_READ_CON,
 473         I40E_NVMUPD_READ_SNT,
 474         I40E_NVMUPD_READ_LCB,
 475         I40E_NVMUPD_READ_SA,
 476         I40E_NVMUPD_WRITE_ERA,
 477         I40E_NVMUPD_WRITE_CON,
 478         I40E_NVMUPD_WRITE_SNT,
 479         I40E_NVMUPD_WRITE_LCB,
 480         I40E_NVMUPD_WRITE_SA,
 481         I40E_NVMUPD_CSUM_CON,
 482         I40E_NVMUPD_CSUM_SA,
 483         I40E_NVMUPD_CSUM_LCB,
 484         I40E_NVMUPD_STATUS,
 485         I40E_NVMUPD_EXEC_AQ,
 486         I40E_NVMUPD_GET_AQ_RESULT,
 487 };
 488
 489 enum i40e_nvmupd_state {
 490         I40E_NVMUPD_STATE_INIT,
 491         I40E_NVMUPD_STATE_READING,
 492         I40E_NVMUPD_STATE_WRITING,
 493         I40E_NVMUPD_STATE_INIT_WAIT,
 494         I40E_NVMUPD_STATE_WRITE_WAIT,
 495         I40E_NVMUPD_STATE_ERROR
 496 };
 497
 498 /* nvm_access definition and its masks/shifts need to be accessible to
 499  * application, core driver, and shared code.  Where is the right file?
 500  */
 501 #define I40E_NVM_READ   0xB
 502 #define I40E_NVM_WRITE  0xC
 503
 504 #define I40E_NVM_MOD_PNT_MASK 0xFF
 505
 506 #define I40E_NVM_TRANS_SHIFT    8
 507 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 508 #define I40E_NVM_CON            0x0
 509 #define I40E_NVM_SNT            0x1
 510 #define I40E_NVM_LCB            0x2
 511 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 512 #define I40E_NVM_ERA            0x4
 513 #define I40E_NVM_CSUM           0x8
 514 #define I40E_NVM_EXEC           0xf
 515
 516 #define I40E_NVM_ADAPT_SHIFT    16
 517 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 518
 519 #define I40E_NVMUPD_MAX_DATA    4096
 520 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 521
 522 struct i40e_nvm_access {
 523         u32 command;
 524         u32 config;
 525         u32 offset;     /* in bytes */
 526         u32 data_size;  /* in bytes */
 527         u8 data[1];
 528 };
 529
 530 /* PCI bus types */
 531 enum i40e_bus_type {
 532         i40e_bus_type_unknown = 0,
 533         i40e_bus_type_pci,
 534         i40e_bus_type_pcix,
 535         i40e_bus_type_pci_express,
 536         i40e_bus_type_reserved
 537 };
 538
 539 /* PCI bus speeds */
 540 enum i40e_bus_speed {
 541         i40e_bus_speed_unknown  = 0,
 542         i40e_bus_speed_33       = 33,
 543         i40e_bus_speed_66       = 66,
 544         i40e_bus_speed_100      = 100,
 545         i40e_bus_speed_120      = 120,
 546         i40e_bus_speed_133      = 133,
 547         i40e_bus_speed_2500     = 2500,
 548         i40e_bus_speed_5000     = 5000,
 549         i40e_bus_speed_8000     = 8000,
 550         i40e_bus_speed_reserved
 551 };
 552
 553 /* PCI bus widths */
 554 enum i40e_bus_width {
 555         i40e_bus_width_unknown  = 0,
 556         i40e_bus_width_pcie_x1  = 1,
 557         i40e_bus_width_pcie_x2  = 2,
 558         i40e_bus_width_pcie_x4  = 4,
 559         i40e_bus_width_pcie_x8  = 8,
 560         i40e_bus_width_32       = 32,
 561         i40e_bus_width_64       = 64,
 562         i40e_bus_width_reserved
 563 };
 564
 565 /* Bus parameters */
 566 struct i40e_bus_info {
 567         enum i40e_bus_speed speed;
 568         enum i40e_bus_width width;
 569         enum i40e_bus_type type;
 570
 571         u16 func;
 572         u16 device;
 573         u16 lan_id;
 574         u16 bus_id;
 575 };
 576
 577 /* Flow control (FC) parameters */
 578 struct i40e_fc_info {
 579         enum i40e_fc_mode current_mode; /* FC mode in effect */
 580         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 581 };
 582
 583 #define I40E_MAX_TRAFFIC_CLASS          8
 584 #define I40E_MAX_USER_PRIORITY          8
 585 #define I40E_DCBX_MAX_APPS              32
 586 #define I40E_LLDPDU_SIZE                1500
 587 #define I40E_TLV_STATUS_OPER            0x1
 588 #define I40E_TLV_STATUS_SYNC            0x2
 589 #define I40E_TLV_STATUS_ERR             0x4
 590 #define I40E_CEE_OPER_MAX_APPS          3
 591 #define I40E_APP_PROTOID_FCOE           0x8906
 592 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 593 #define I40E_APP_PROTOID_FIP            0x8914
 594 #define I40E_APP_SEL_ETHTYPE            0x1
 595 #define I40E_APP_SEL_TCPIP              0x2
 596 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 597 #define I40E_CEE_APP_SEL_TCPIP          0x1
 598
 599 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 600 struct i40e_dcb_ets_config {
 601         u8 willing;
 602         u8 cbs;
 603         u8 maxtcs;
 604         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 605         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 606         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 607 };
 608
 609 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 610 struct i40e_dcb_pfc_config {
 611         u8 willing;
 612         u8 mbc;
 613         u8 pfccap;
 614         u8 pfcenable;
 615 };
 616
 617 /* CEE or IEEE 802.1Qaz Application Priority data */
 618 struct i40e_dcb_app_priority_table {
 619         u8  priority;
 620         u8  selector;
 621         u16 protocolid;
 622 };
 623
 624 struct i40e_dcbx_config {
 625         u8  dcbx_mode;
 626 #define I40E_DCBX_MODE_CEE      0x1
 627 #define I40E_DCBX_MODE_IEEE     0x2
 628         u8  app_mode;
 629 #define I40E_DCBX_APPS_NON_WILLING      0x1
 630         u32 numapps;
 631         u32 tlv_status; /* CEE mode TLV status */
 632         struct i40e_dcb_ets_config etscfg;
 633         struct i40e_dcb_ets_config etsrec;
 634         struct i40e_dcb_pfc_config pfc;
 635         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 636 };
 637
 638 /* Port hardware description */
 639 struct i40e_hw {
 640         u8 *hw_addr;
 641         void *back;
 642
 643         /* subsystem structs */
 644         struct i40e_phy_info phy;
 645         struct i40e_mac_info mac;
 646         struct i40e_bus_info bus;
 647         struct i40e_nvm_info nvm;
 648         struct i40e_fc_info fc;
 649
 650         /* pci info */
 651         u16 device_id;
 652         u16 vendor_id;
 653         u16 subsystem_device_id;
 654         u16 subsystem_vendor_id;
 655         u8 revision_id;
 656         u8 port;
 657         bool adapter_stopped;
 658
 659         /* capabilities for entire device and PCI func */
 660         struct i40e_hw_capabilities dev_caps;
 661         struct i40e_hw_capabilities func_caps;
 662
 663         /* Flow Director shared filter space */
 664         u16 fdir_shared_filter_count;
 665
 666         /* device profile info */
 667         u8  pf_id;
 668         u16 main_vsi_seid;
 669
 670         /* for multi-function MACs */
 671         u16 partition_id;
 672         u16 num_partitions;
 673         u16 num_ports;
 674
 675         /* Closest numa node to the device */
 676         u16 numa_node;
 677
 678         /* Admin Queue info */
 679         struct i40e_adminq_info aq;
 680
 681         /* state of nvm update process */
 682         enum i40e_nvmupd_state nvmupd_state;
 683         struct i40e_aq_desc nvm_wb_desc;
 684         struct i40e_virt_mem nvm_buff;
 685         bool nvm_release_on_done;
 686         u16 nvm_wait_opcode;
 687
 688         /* HMC info */
 689         struct i40e_hmc_info hmc; /* HMC info struct */
 690
 691         /* LLDP/DCBX Status */
 692         u16 dcbx_status;
 693
 694         /* DCBX info */
 695         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 696         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 697         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 698
 699         /* WoL and proxy support */
 700         u16 num_wol_proxy_filters;
 701         u16 wol_proxy_vsi_seid;
 702
 703 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 704         u64 flags;
 705
 706         /* debug mask */
 707         u32 debug_mask;
 708         char err_str[16];
 709 };
 710
 711 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
 712 {
 713         return (hw->mac.type == I40E_MAC_VF ||
 714                 hw->mac.type == I40E_MAC_X722_VF);
 715 }
 716
 717 struct i40e_driver_version {
 718         u8 major_version;
 719         u8 minor_version;
 720         u8 build_version;
 721         u8 subbuild_version;
 722         u8 driver_string[32];
 723 };
 724
 725 /* RX Descriptors */
 726 union i40e_16byte_rx_desc {
 727         struct {
 728                 __le64 pkt_addr; /* Packet buffer address */
 729                 __le64 hdr_addr; /* Header buffer address */
 730         } read;
 731         struct {
 732                 struct {
 733                         struct {
 734                                 union {
 735                                         __le16 mirroring_status;
 736                                         __le16 fcoe_ctx_id;
 737                                 } mirr_fcoe;
 738                                 __le16 l2tag1;
 739                         } lo_dword;
 740                         union {
 741                                 __le32 rss; /* RSS Hash */
 742                                 __le32 fd_id; /* Flow director filter id */
 743                                 __le32 fcoe_param; /* FCoE DDP Context id */
 744                         } hi_dword;
 745                 } qword0;
 746                 struct {
 747                         /* ext status/error/pktype/length */
 748                         __le64 status_error_len;
 749                 } qword1;
 750         } wb;  /* writeback */
 751 };
 752
 753 union i40e_32byte_rx_desc {
 754         struct {
 755                 __le64  pkt_addr; /* Packet buffer address */
 756                 __le64  hdr_addr; /* Header buffer address */
 757                         /* bit 0 of hdr_buffer_addr is DD bit */
 758                 __le64  rsvd1;
 759                 __le64  rsvd2;
 760         } read;
 761         struct {
 762                 struct {
 763                         struct {
 764                                 union {
 765                                         __le16 mirroring_status;
 766                                         __le16 fcoe_ctx_id;
 767                                 } mirr_fcoe;
 768                                 __le16 l2tag1;
 769                         } lo_dword;
 770                         union {
 771                                 __le32 rss; /* RSS Hash */
 772                                 __le32 fcoe_param; /* FCoE DDP Context id */
 773                                 /* Flow director filter id in case of
 774                                  * Programming status desc WB
 775                                  */
 776                                 __le32 fd_id;
 777                         } hi_dword;
 778                 } qword0;
 779                 struct {
 780                         /* status/error/pktype/length */
 781                         __le64 status_error_len;
 782                 } qword1;
 783                 struct {
 784                         __le16 ext_status; /* extended status */
 785                         __le16 rsvd;
 786                         __le16 l2tag2_1;
 787                         __le16 l2tag2_2;
 788                 } qword2;
 789                 struct {
 790                         union {
 791                                 __le32 flex_bytes_lo;
 792                                 __le32 pe_status;
 793                         } lo_dword;
 794                         union {
 795                                 __le32 flex_bytes_hi;
 796                                 __le32 fd_id;
 797                         } hi_dword;
 798                 } qword3;
 799         } wb;  /* writeback */
 800 };
 801
 802 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 803 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 804                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 805 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 806 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 807                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 808
 809 enum i40e_rx_desc_status_bits {
 810         /* Note: These are predefined bit offsets */
 811         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 812         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 813         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 814         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 815         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 816         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 817         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 818         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 819
 820         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 821         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 822         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 823         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 824         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 825         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 826         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 827         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 828 };
 829
 830 #define I40E_RXD_QW1_STATUS_SHIFT       0
 831 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 832                                          I40E_RXD_QW1_STATUS_SHIFT)
 833
 834 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 835 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 836                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 837
 838 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 839 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 840
 841 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 842 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 843                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 844
 845 enum i40e_rx_desc_fltstat_values {
 846         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 847         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 848         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 849         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 850 };
 851
 852 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 853 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 854 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 855 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 856
 857 #define I40E_RXD_QW1_ERROR_SHIFT        19
 858 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 859
 860 enum i40e_rx_desc_error_bits {
 861         /* Note: These are predefined bit offsets */
 862         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 863         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 864         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 865         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 866         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 867         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 868         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 869         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 870         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 871 };
 872
 873 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 874         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 875         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 876         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 877         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 878         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 879 };
 880
 881 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 882 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 883
 884 /* Packet type non-ip values */
 885 enum i40e_rx_l2_ptype {
 886         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 887         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 888         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 889         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 890         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 891         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 892         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 893         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 894         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 895         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 896         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 897         I40E_RX_PTYPE_L2_ARP                            = 11,
 898         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 899         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 900         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 901         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 902         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 903         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 904         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 905         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 906         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 907         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 908         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 909         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 910         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 911         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 912 };
 913
 914 struct i40e_rx_ptype_decoded {
 915         u32 ptype:8;
 916         u32 known:1;
 917         u32 outer_ip:1;
 918         u32 outer_ip_ver:1;
 919         u32 outer_frag:1;
 920         u32 tunnel_type:3;
 921         u32 tunnel_end_prot:2;
 922         u32 tunnel_end_frag:1;
 923         u32 inner_prot:4;
 924         u32 payload_layer:3;
 925 };
 926
 927 enum i40e_rx_ptype_outer_ip {
 928         I40E_RX_PTYPE_OUTER_L2  = 0,
 929         I40E_RX_PTYPE_OUTER_IP  = 1
 930 };
 931
 932 enum i40e_rx_ptype_outer_ip_ver {
 933         I40E_RX_PTYPE_OUTER_NONE        = 0,
 934         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 935         I40E_RX_PTYPE_OUTER_IPV6        = 1
 936 };
 937
 938 enum i40e_rx_ptype_outer_fragmented {
 939         I40E_RX_PTYPE_NOT_FRAG  = 0,
 940         I40E_RX_PTYPE_FRAG      = 1
 941 };
 942
 943 enum i40e_rx_ptype_tunnel_type {
 944         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 945         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 946         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 947         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 948         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 949 };
 950
 951 enum i40e_rx_ptype_tunnel_end_prot {
 952         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 953         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 954         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 955 };
 956
 957 enum i40e_rx_ptype_inner_prot {
 958         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 959         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 960         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 961         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 962         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 963         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 964 };
 965
 966 enum i40e_rx_ptype_payload_layer {
 967         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 968         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 969         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 970         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 971 };
 972
 973 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 974 #define I40E_RX_PTYPE_SHIFT             56
 975
 976 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 977 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 978                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 979
 980 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 981 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 982                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 983
 984 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 985 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 986
 987 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 988 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 989
 990 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 991 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 992                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 993
 994 enum i40e_rx_desc_ext_status_bits {
 995         /* Note: These are predefined bit offsets */
 996         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 997         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 998         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 999         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
1000         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
1001         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1002         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
1003 };
1004
1005 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
1006 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1007
1008 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
1009 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1010
1011 enum i40e_rx_desc_pe_status_bits {
1012         /* Note: These are predefined bit offsets */
1013         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1014         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1015         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1016         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1017         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1018         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1019         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1020         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1021         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1022 };
1023
1024 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1025 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1026
1027 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1028 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1029                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1030
1031 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1032 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1033                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1034
1035 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1036 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1037                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1038
1039 enum i40e_rx_prog_status_desc_status_bits {
1040         /* Note: These are predefined bit offsets */
1041         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1042         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1043 };
1044
1045 enum i40e_rx_prog_status_desc_prog_id_masks {
1046         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1047         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1048         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1049 };
1050
1051 enum i40e_rx_prog_status_desc_error_bits {
1052         /* Note: These are predefined bit offsets */
1053         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1054         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1055         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1056         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1057 };
1058
1059 #define I40E_TWO_BIT_MASK       0x3
1060 #define I40E_THREE_BIT_MASK     0x7
1061 #define I40E_FOUR_BIT_MASK      0xF
1062 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1063
1064 /* TX Descriptor */
1065 struct i40e_tx_desc {
1066         __le64 buffer_addr; /* Address of descriptor's data buf */
1067         __le64 cmd_type_offset_bsz;
1068 };
1069
1070 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1071 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1072
1073 enum i40e_tx_desc_dtype_value {
1074         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1075         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1076         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1077         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1078         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1079         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1080         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1081         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1082         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1083         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1084 };
1085
1086 #define I40E_TXD_QW1_CMD_SHIFT  4
1087 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1088
1089 enum i40e_tx_desc_cmd_bits {
1090         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1091         I40E_TX_DESC_CMD_RS                     = 0x0002,
1092         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1093         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1094         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1095         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1096         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1097         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1098         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1099         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1100         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1101         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1102         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1103         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1104         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1105         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1106         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1107         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1108 };
1109
1110 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1111 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1112                                          I40E_TXD_QW1_OFFSET_SHIFT)
1113
1114 enum i40e_tx_desc_length_fields {
1115         /* Note: These are predefined bit offsets */
1116         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1117         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1118         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1119 };
1120
1121 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1122 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1123 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1124 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1125
1126 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1127 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1128                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1129
1130 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1131 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1132
1133 /* Context descriptors */
1134 struct i40e_tx_context_desc {
1135         __le32 tunneling_params;
1136         __le16 l2tag2;
1137         __le16 rsvd;
1138         __le64 type_cmd_tso_mss;
1139 };
1140
1141 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1142 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1143
1144 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1145 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1146
1147 enum i40e_tx_ctx_desc_cmd_bits {
1148         I40E_TX_CTX_DESC_TSO            = 0x01,
1149         I40E_TX_CTX_DESC_TSYN           = 0x02,
1150         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1151         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1152         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1153         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1154         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1155         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1156         I40E_TX_CTX_DESC_SWPE           = 0x40
1157 };
1158
1159 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1160 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1161                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1162
1163 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1164 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1165                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1166
1167 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1168 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1169
1170 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1171 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1172                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1173
1174 enum i40e_tx_ctx_desc_eipt_offload {
1175         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1176         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1177         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1178         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1179 };
1180
1181 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1182 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1183                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1184
1185 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1186 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1187
1188 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1189 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1190
1191 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1192 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1193
1194 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1195
1196 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1197 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1198                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1199
1200 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1201 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1202                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1203
1204 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1205 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1206 struct i40e_nop_desc {
1207         __le64 rsvd;
1208         __le64 dtype_cmd;
1209 };
1210
1211 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1212 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1213
1214 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1215 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1216
1217 enum i40e_tx_nop_desc_cmd_bits {
1218         /* Note: These are predefined bit offsets */
1219         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1220         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1221         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1222 };
1223
1224 struct i40e_filter_program_desc {
1225         __le32 qindex_flex_ptype_vsi;
1226         __le32 rsvd;
1227         __le32 dtype_cmd_cntindex;
1228         __le32 fd_id;
1229 };
1230 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1231 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1232                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1233 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1234 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1235                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1236 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1237 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1238                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1239
1240 /* Packet Classifier Types for filters */
1241 enum i40e_filter_pctype {
1242         /* Note: Values 0-28 are reserved for future use.
1243          * Value 29, 30, 32 are not supported on XL710 and X710.
1244          */
1245         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1246         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1247         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1248         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1249         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1250         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1251         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1252         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1253         /* Note: Values 37-38 are reserved for future use.
1254          * Value 39, 40, 42 are not supported on XL710 and X710.
1255          */
1256         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1257         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1258         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1259         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1260         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1261         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1262         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1263         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1264         /* Note: Value 47 is reserved for future use */
1265         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1266         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1267         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1268         /* Note: Values 51-62 are reserved for future use */
1269         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1270 };
1271
1272 enum i40e_filter_program_desc_dest {
1273         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1274         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1275         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1276 };
1277
1278 enum i40e_filter_program_desc_fd_status {
1279         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1280         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1281         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1282         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1283 };
1284
1285 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1286 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1287                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1288
1289 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1290 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1291
1292 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1293 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1294                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1295
1296 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1297 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1298
1299 enum i40e_filter_program_desc_pcmd {
1300         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1301         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1302 };
1303
1304 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1305 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1306
1307 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1308 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1309
1310 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1311                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1312 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1313                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1314
1315 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1316                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1317 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1318
1319 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1320 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1321                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1322
1323 enum i40e_filter_type {
1324         I40E_FLOW_DIRECTOR_FLTR = 0,
1325         I40E_PE_QUAD_HASH_FLTR = 1,
1326         I40E_ETHERTYPE_FLTR,
1327         I40E_FCOE_CTX_FLTR,
1328         I40E_MAC_VLAN_FLTR,
1329         I40E_HASH_FLTR
1330 };
1331
1332 struct i40e_vsi_context {
1333         u16 seid;
1334         u16 uplink_seid;
1335         u16 vsi_number;
1336         u16 vsis_allocated;
1337         u16 vsis_unallocated;
1338         u16 flags;
1339         u8 pf_num;
1340         u8 vf_num;
1341         u8 connection_type;
1342         struct i40e_aqc_vsi_properties_data info;
1343 };
1344
1345 struct i40e_veb_context {
1346         u16 seid;
1347         u16 uplink_seid;
1348         u16 veb_number;
1349         u16 vebs_allocated;
1350         u16 vebs_unallocated;
1351         u16 flags;
1352         struct i40e_aqc_get_veb_parameters_completion info;
1353 };
1354
1355 /* Statistics collected by each port, VSI, VEB, and S-channel */
1356 struct i40e_eth_stats {
1357         u64 rx_bytes;                   /* gorc */
1358         u64 rx_unicast;                 /* uprc */
1359         u64 rx_multicast;               /* mprc */
1360         u64 rx_broadcast;               /* bprc */
1361         u64 rx_discards;                /* rdpc */
1362         u64 rx_unknown_protocol;        /* rupp */
1363         u64 tx_bytes;                   /* gotc */
1364         u64 tx_unicast;                 /* uptc */
1365         u64 tx_multicast;               /* mptc */
1366         u64 tx_broadcast;               /* bptc */
1367         u64 tx_discards;                /* tdpc */
1368         u64 tx_errors;                  /* tepc */
1369 };
1370
1371 /* Statistics collected per VEB per TC */
1372 struct i40e_veb_tc_stats {
1373         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1374         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1375         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1376         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1377 };
1378
1379 /* Statistics collected per function for FCoE */
1380 struct i40e_fcoe_stats {
1381         u64 rx_fcoe_packets;            /* fcoeprc */
1382         u64 rx_fcoe_dwords;             /* focedwrc */
1383         u64 rx_fcoe_dropped;            /* fcoerpdc */
1384         u64 tx_fcoe_packets;            /* fcoeptc */
1385         u64 tx_fcoe_dwords;             /* focedwtc */
1386         u64 fcoe_bad_fccrc;             /* fcoecrc */
1387         u64 fcoe_last_error;            /* fcoelast */
1388         u64 fcoe_ddp_count;             /* fcoeddpc */
1389 };
1390
1391 /* offset to per function FCoE statistics block */
1392 #define I40E_FCOE_VF_STAT_OFFSET        0
1393 #define I40E_FCOE_PF_STAT_OFFSET        128
1394 #define I40E_FCOE_STAT_MAX              (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1395
1396 /* Statistics collected by the MAC */
1397 struct i40e_hw_port_stats {
1398         /* eth stats collected by the port */
1399         struct i40e_eth_stats eth;
1400
1401         /* additional port specific stats */
1402         u64 tx_dropped_link_down;       /* tdold */
1403         u64 crc_errors;                 /* crcerrs */
1404         u64 illegal_bytes;              /* illerrc */
1405         u64 error_bytes;                /* errbc */
1406         u64 mac_local_faults;           /* mlfc */
1407         u64 mac_remote_faults;          /* mrfc */
1408         u64 rx_length_errors;           /* rlec */
1409         u64 link_xon_rx;                /* lxonrxc */
1410         u64 link_xoff_rx;               /* lxoffrxc */
1411         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1412         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1413         u64 link_xon_tx;                /* lxontxc */
1414         u64 link_xoff_tx;               /* lxofftxc */
1415         u64 priority_xon_tx[8];         /* pxontxc[8] */
1416         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1417         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1418         u64 rx_size_64;                 /* prc64 */
1419         u64 rx_size_127;                /* prc127 */
1420         u64 rx_size_255;                /* prc255 */
1421         u64 rx_size_511;                /* prc511 */
1422         u64 rx_size_1023;               /* prc1023 */
1423         u64 rx_size_1522;               /* prc1522 */
1424         u64 rx_size_big;                /* prc9522 */
1425         u64 rx_undersize;               /* ruc */
1426         u64 rx_fragments;               /* rfc */
1427         u64 rx_oversize;                /* roc */
1428         u64 rx_jabber;                  /* rjc */
1429         u64 tx_size_64;                 /* ptc64 */
1430         u64 tx_size_127;                /* ptc127 */
1431         u64 tx_size_255;                /* ptc255 */
1432         u64 tx_size_511;                /* ptc511 */
1433         u64 tx_size_1023;               /* ptc1023 */
1434         u64 tx_size_1522;               /* ptc1522 */
1435         u64 tx_size_big;                /* ptc9522 */
1436         u64 mac_short_packet_dropped;   /* mspdc */
1437         u64 checksum_error;             /* xec */
1438         /* flow director stats */
1439         u64 fd_atr_match;
1440         u64 fd_sb_match;
1441         u64 fd_atr_tunnel_match;
1442         u32 fd_atr_status;
1443         u32 fd_sb_status;
1444         /* EEE LPI */
1445         u32 tx_lpi_status;
1446         u32 rx_lpi_status;
1447         u64 tx_lpi_count;               /* etlpic */
1448         u64 rx_lpi_count;               /* erlpic */
1449 };
1450
1451 /* Checksum and Shadow RAM pointers */
1452 #define I40E_SR_NVM_CONTROL_WORD                0x00
1453 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1454 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1455 #define I40E_SR_OPTION_ROM_PTR                  0x05
1456 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1457 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1458 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1459 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1460 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1461 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1462 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1463 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1464 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1465 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1466 #define I40E_SR_PBA_FLAGS                       0x15
1467 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1468 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1469 #define I40E_NVM_OEM_VER_OFF                    0x83
1470 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1471 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1472 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1473 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1474 #define I40E_SR_NVM_MAP_VERSION                 0x29
1475 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1476 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1477 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1478 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1479 #define I40E_SR_VPD_PTR                         0x2F
1480 #define I40E_SR_PXE_SETUP_PTR                   0x30
1481 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1482 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1483 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1484 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1485 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1486 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1487 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1488 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1489 #define I40E_SR_PHY_ACTIVITY_LIST_PTR           0x3D
1490 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1491 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1492 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1493 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1494 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1495 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1496 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1497 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1498 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1499 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1500
1501 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1502 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1503 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1504 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1505 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1506
1507 /* Shadow RAM related */
1508 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1509 #define I40E_SR_BUF_ALIGNMENT           4096
1510 #define I40E_SR_WORDS_IN_1KB            512
1511 /* Checksum should be calculated such that after adding all the words,
1512  * including the checksum word itself, the sum should be 0xBABA.
1513  */
1514 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1515
1516 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1517
1518 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1519
1520 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1521         I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1522         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1523         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1524         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1525         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1526         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1527         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1528         I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1529         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1530         I40E_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1531         I40E_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1532         I40E_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1533         I40E_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1534 };
1535
1536 /* FCoE DIF/DIX Context descriptor */
1537 struct i40e_fcoe_difdix_context_desc {
1538         __le64 flags_buff0_buff1_ref;
1539         __le64 difapp_msk_bias;
1540 };
1541
1542 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT    0
1543 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK     (0xFFFULL << \
1544                                         I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1545
1546 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1547         /* 2 BITS */
1548         I40E_FCOE_DIFDIX_CTX_DESC_RSVD                          = 0x0000,
1549         /* 1 BIT  */
1550         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK                = 0x0000,
1551         /* 1 BIT  */
1552         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK             = 0x0004,
1553         /* 2 BITS */
1554         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE                  = 0x0000,
1555         /* 2 BITS */
1556         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY            = 0x0008,
1557         /* 2 BITS */
1558         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG     = 0x0010,
1559         /* 2 BITS */
1560         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG  = 0x0018,
1561         /* 2 BITS */
1562         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST                  = 0x0000,
1563         /* 2 BITS */
1564         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK               = 0x0020,
1565         /* 2 BITS */
1566         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG                = 0x0040,
1567         /* 2 BITS */
1568         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD                  = 0x0060,
1569         /* 1 BIT  */
1570         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM                  = 0x0000,
1571         /* 1 BIT  */
1572         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC                   = 0x0080,
1573         /* 2 BITS */
1574         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG                 = 0x0000,
1575         /* 2 BITS */
1576         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF                   = 0x0100,
1577         /* 2 BITS */
1578         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD                  = 0x0200,
1579         /* 2 BITS */
1580         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS              = 0x0300,
1581         /* 1 BIT  */
1582         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG                  = 0x0000,
1583         /* 1 BIT  */
1584         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG                    = 0x0400,
1585         /* 1 BIT */
1586         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B                   = 0x0000,
1587         /* 1 BIT */
1588         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K                     = 0x0800
1589 };
1590
1591 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT    12
1592 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK     (0x3FFULL << \
1593                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1594
1595 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT    22
1596 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK     (0x3FFULL << \
1597                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1598
1599 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT      32
1600 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK       (0xFFFFFFFFULL << \
1601                                         I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1602
1603 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT      0
1604 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK       (0xFFFFULL << \
1605                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1606
1607 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT  16
1608 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK   (0xFFFFULL << \
1609                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1610
1611 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1612 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK  (0xFFFFFFFFULL << \
1613                                         I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1614
1615 /* FCoE DIF/DIX Buffers descriptor */
1616 struct i40e_fcoe_difdix_buffers_desc {
1617         __le64 buff_addr0;
1618         __le64 buff_addr1;
1619 };
1620
1621 /* FCoE DDP Context descriptor */
1622 struct i40e_fcoe_ddp_context_desc {
1623         __le64 rsvd;
1624         __le64 type_cmd_foff_lsize;
1625 };
1626
1627 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1628 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1629                                         I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1630
1631 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1632 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1633                                          I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1634
1635 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1636         I40E_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1637         I40E_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1638         I40E_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1639         I40E_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1640         I40E_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1641         I40E_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1642 };
1643
1644 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1645 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1646                                          I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1647
1648 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1649 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1650                                         I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1651
1652 /* FCoE DDP/DWO Queue Context descriptor */
1653 struct i40e_fcoe_queue_context_desc {
1654         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1655         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1656 };
1657
1658 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1659 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1660                                         I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1661
1662 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1663 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1664                                         I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1665
1666 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1667 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1668                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1669
1670 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1671 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1672                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1673
1674 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1675         I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1676         I40E_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1677 };
1678
1679 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1680 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1681                                         I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1682
1683 /* FCoE DDP/DWO Filter Context descriptor */
1684 struct i40e_fcoe_filter_context_desc {
1685         __le32 param;
1686         __le16 seqn;
1687
1688         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1689         __le16 rsvd_dmaindx;
1690
1691         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1692         __le64 flags_rsvd_lanq;
1693 };
1694
1695 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1696 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1697                                         I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1698
1699 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1700         I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1701         I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1702         I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1703         I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1704         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1705         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1706 };
1707
1708 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1709 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1710                                         I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1711
1712 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1713 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1714                         I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1715
1716 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1717 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1718                         I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1719
1720 enum i40e_switch_element_types {
1721         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1722         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1723         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1724         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1725         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1726         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1727         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1728         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1729         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1730 };
1731
1732 /* Supported EtherType filters */
1733 enum i40e_ether_type_index {
1734         I40E_ETHER_TYPE_1588            = 0,
1735         I40E_ETHER_TYPE_FIP             = 1,
1736         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1737         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1738         I40E_ETHER_TYPE_LLDP            = 4,
1739         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1740         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1741         I40E_ETHER_TYPE_QCN_CNM         = 7,
1742         I40E_ETHER_TYPE_8021X           = 8,
1743         I40E_ETHER_TYPE_ARP             = 9,
1744         I40E_ETHER_TYPE_RSV1            = 10,
1745         I40E_ETHER_TYPE_RSV2            = 11,
1746 };
1747
1748 /* Filter context base size is 1K */
1749 #define I40E_HASH_FILTER_BASE_SIZE      1024
1750 /* Supported Hash filter values */
1751 enum i40e_hash_filter_size {
1752         I40E_HASH_FILTER_SIZE_1K        = 0,
1753         I40E_HASH_FILTER_SIZE_2K        = 1,
1754         I40E_HASH_FILTER_SIZE_4K        = 2,
1755         I40E_HASH_FILTER_SIZE_8K        = 3,
1756         I40E_HASH_FILTER_SIZE_16K       = 4,
1757         I40E_HASH_FILTER_SIZE_32K       = 5,
1758         I40E_HASH_FILTER_SIZE_64K       = 6,
1759         I40E_HASH_FILTER_SIZE_128K      = 7,
1760         I40E_HASH_FILTER_SIZE_256K      = 8,
1761         I40E_HASH_FILTER_SIZE_512K      = 9,
1762         I40E_HASH_FILTER_SIZE_1M        = 10,
1763 };
1764
1765 /* DMA context base size is 0.5K */
1766 #define I40E_DMA_CNTX_BASE_SIZE         512
1767 /* Supported DMA context values */
1768 enum i40e_dma_cntx_size {
1769         I40E_DMA_CNTX_SIZE_512          = 0,
1770         I40E_DMA_CNTX_SIZE_1K           = 1,
1771         I40E_DMA_CNTX_SIZE_2K           = 2,
1772         I40E_DMA_CNTX_SIZE_4K           = 3,
1773         I40E_DMA_CNTX_SIZE_8K           = 4,
1774         I40E_DMA_CNTX_SIZE_16K          = 5,
1775         I40E_DMA_CNTX_SIZE_32K          = 6,
1776         I40E_DMA_CNTX_SIZE_64K          = 7,
1777         I40E_DMA_CNTX_SIZE_128K         = 8,
1778         I40E_DMA_CNTX_SIZE_256K         = 9,
1779 };
1780
1781 /* Supported Hash look up table (LUT) sizes */
1782 enum i40e_hash_lut_size {
1783         I40E_HASH_LUT_SIZE_128          = 0,
1784         I40E_HASH_LUT_SIZE_512          = 1,
1785 };
1786
1787 /* Structure to hold a per PF filter control settings */
1788 struct i40e_filter_control_settings {
1789         /* number of PE Quad Hash filter buckets */
1790         enum i40e_hash_filter_size pe_filt_num;
1791         /* number of PE Quad Hash contexts */
1792         enum i40e_dma_cntx_size pe_cntx_num;
1793         /* number of FCoE filter buckets */
1794         enum i40e_hash_filter_size fcoe_filt_num;
1795         /* number of FCoE DDP contexts */
1796         enum i40e_dma_cntx_size fcoe_cntx_num;
1797         /* size of the Hash LUT */
1798         enum i40e_hash_lut_size hash_lut_size;
1799         /* enable FDIR filters for PF and its VFs */
1800         bool enable_fdir;
1801         /* enable Ethertype filters for PF and its VFs */
1802         bool enable_ethtype;
1803         /* enable MAC/VLAN filters for PF and its VFs */
1804         bool enable_macvlan;
1805 };
1806
1807 /* Structure to hold device level control filter counts */
1808 struct i40e_control_filter_stats {
1809         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1810         u16 etype_used;       /* Used perfect EtherType filters */
1811         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1812         u16 etype_free;       /* Un-used perfect EtherType filters */
1813 };
1814
1815 enum i40e_reset_type {
1816         I40E_RESET_POR          = 0,
1817         I40E_RESET_CORER        = 1,
1818         I40E_RESET_GLOBR        = 2,
1819         I40E_RESET_EMPR         = 3,
1820 };
1821
1822 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1823 #define I40E_NVM_LLDP_CFG_PTR           0xD
1824 struct i40e_lldp_variables {
1825         u16 length;
1826         u16 adminstatus;
1827         u16 msgfasttx;
1828         u16 msgtxinterval;
1829         u16 txparams;
1830         u16 timers;
1831         u16 crc8;
1832 };
1833
1834 /* Offsets into Alternate Ram */
1835 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1836 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1837 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1838 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1839 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1840 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1841
1842 /* Alternate Ram Bandwidth Masks */
1843 #define I40E_ALT_BW_VALUE_MASK          0xFF
1844 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1845 #define I40E_ALT_BW_VALID_MASK          0x80000000
1846
1847 /* RSS Hash Table Size */
1848 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1849
1850 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1851 #define I40E_L3_SRC_SHIFT               47
1852 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1853 #define I40E_L3_V6_SRC_SHIFT            43
1854 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1855 #define I40E_L3_DST_SHIFT               35
1856 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1857 #define I40E_L3_V6_DST_SHIFT            35
1858 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1859 #define I40E_L4_SRC_SHIFT               34
1860 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1861 #define I40E_L4_DST_SHIFT               33
1862 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1863 #define I40E_VERIFY_TAG_SHIFT           31
1864 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1865
1866 #define I40E_FLEX_50_SHIFT              13
1867 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1868 #define I40E_FLEX_51_SHIFT              12
1869 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1870 #define I40E_FLEX_52_SHIFT              11
1871 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1872 #define I40E_FLEX_53_SHIFT              10
1873 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1874 #define I40E_FLEX_54_SHIFT              9
1875 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1876 #define I40E_FLEX_55_SHIFT              8
1877 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1878 #define I40E_FLEX_56_SHIFT              7
1879 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1880 #define I40E_FLEX_57_SHIFT              6
1881 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1882
1883 /* Version format for Dynamic Device Personalization(DDP) */
1884 struct i40e_ddp_version {
1885         u8 major;
1886         u8 minor;
1887         u8 update;
1888         u8 draft;
1889 };
1890
1891 #define I40E_DDP_NAME_SIZE      32
1892
1893 /* Package header */
1894 struct i40e_package_header {
1895         struct i40e_ddp_version version;
1896         u32 segment_count;
1897         u32 segment_offset[1];
1898 };
1899
1900 /* Generic segment header */
1901 struct i40e_generic_seg_header {
1902 #define SEGMENT_TYPE_METADATA   0x00000001
1903 #define SEGMENT_TYPE_NOTES      0x00000002
1904 #define SEGMENT_TYPE_I40E       0x00000011
1905 #define SEGMENT_TYPE_X722       0x00000012
1906         u32 type;
1907         struct i40e_ddp_version version;
1908         u32 size;
1909         char name[I40E_DDP_NAME_SIZE];
1910 };
1911
1912 struct i40e_metadata_segment {
1913         struct i40e_generic_seg_header header;
1914         struct i40e_ddp_version version;
1915         u32 track_id;
1916         char     name[I40E_DDP_NAME_SIZE];
1917 };
1918
1919 struct i40e_device_id_entry {
1920         u32 vendor_dev_id;
1921         u32 sub_vendor_dev_id;
1922 };
1923
1924 struct i40e_profile_segment {
1925         struct i40e_generic_seg_header header;
1926         struct i40e_ddp_version version;
1927         char name[I40E_DDP_NAME_SIZE];
1928         u32 device_table_count;
1929         struct i40e_device_id_entry device_table[1];
1930 };
1931
1932 struct i40e_section_table {
1933         u32 section_count;
1934         u32 section_offset[1];
1935 };
1936
1937 struct i40e_profile_section_header {
1938         u16 tbl_size;
1939         u16 data_end;
1940         struct {
1941 #define SECTION_TYPE_INFO       0x00000010
1942 #define SECTION_TYPE_MMIO       0x00000800
1943 #define SECTION_TYPE_AQ         0x00000801
1944 #define SECTION_TYPE_NOTE       0x80000000
1945 #define SECTION_TYPE_NAME       0x80000001
1946                 u32 type;
1947                 u32 offset;
1948                 u32 size;
1949         } section;
1950 };
1951
1952 struct i40e_profile_info {
1953         u32 track_id;
1954         struct i40e_ddp_version version;
1955         u8 op;
1956 #define I40E_DDP_ADD_TRACKID            0x01
1957 #define I40E_DDP_REMOVE_TRACKID 0x02
1958         u8 reserved[7];
1959         u8 name[I40E_DDP_NAME_SIZE];
1960 };
1961 #endif /* _I40E_TYPE_H_ */