]> git.proxmox.com Git - ceph.git/blob - ceph/src/seastar/dpdk/drivers/net/i40e/i40e_rxtx_vec_common.h
update sources to ceph Nautilus 14.2.1
[ceph.git] / ceph / src / seastar / dpdk / drivers / net / i40e / i40e_rxtx_vec_common.h
1 /*-
2 * BSD LICENSE
3 *
4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef _I40E_RXTX_VEC_COMMON_H_
35 #define _I40E_RXTX_VEC_COMMON_H_
36 #include <stdint.h>
37 #include <rte_ethdev.h>
38 #include <rte_malloc.h>
39
40 #include "i40e_ethdev.h"
41 #include "i40e_rxtx.h"
42
43 static inline uint16_t
44 reassemble_packets(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_bufs,
45 uint16_t nb_bufs, uint8_t *split_flags)
46 {
47 struct rte_mbuf *pkts[RTE_I40E_VPMD_RX_BURST]; /*finished pkts*/
48 struct rte_mbuf *start = rxq->pkt_first_seg;
49 struct rte_mbuf *end = rxq->pkt_last_seg;
50 unsigned pkt_idx, buf_idx;
51
52 for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
53 if (end != NULL) {
54 /* processing a split packet */
55 end->next = rx_bufs[buf_idx];
56 rx_bufs[buf_idx]->data_len += rxq->crc_len;
57
58 start->nb_segs++;
59 start->pkt_len += rx_bufs[buf_idx]->data_len;
60 end = end->next;
61
62 if (!split_flags[buf_idx]) {
63 /* it's the last packet of the set */
64 start->hash = end->hash;
65 start->ol_flags = end->ol_flags;
66 /* we need to strip crc for the whole packet */
67 start->pkt_len -= rxq->crc_len;
68 if (end->data_len > rxq->crc_len)
69 end->data_len -= rxq->crc_len;
70 else {
71 /* free up last mbuf */
72 struct rte_mbuf *secondlast = start;
73
74 start->nb_segs--;
75 while (secondlast->next != end)
76 secondlast = secondlast->next;
77 secondlast->data_len -= (rxq->crc_len -
78 end->data_len);
79 secondlast->next = NULL;
80 rte_pktmbuf_free_seg(end);
81 }
82 pkts[pkt_idx++] = start;
83 start = end = NULL;
84 }
85 } else {
86 /* not processing a split packet */
87 if (!split_flags[buf_idx]) {
88 /* not a split packet, save and skip */
89 pkts[pkt_idx++] = rx_bufs[buf_idx];
90 continue;
91 }
92 end = start = rx_bufs[buf_idx];
93 rx_bufs[buf_idx]->data_len += rxq->crc_len;
94 rx_bufs[buf_idx]->pkt_len += rxq->crc_len;
95 }
96 }
97
98 /* save the partial packet for next time */
99 rxq->pkt_first_seg = start;
100 rxq->pkt_last_seg = end;
101 memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
102 return pkt_idx;
103 }
104
105 static inline int __attribute__((always_inline))
106 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
107 {
108 struct i40e_tx_entry *txep;
109 uint32_t n;
110 uint32_t i;
111 int nb_free = 0;
112 struct rte_mbuf *m, *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];
113
114 /* check DD bits on threshold descriptor */
115 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
116 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
117 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
118 return 0;
119
120 n = txq->tx_rs_thresh;
121
122 /* first buffer to free from S/W ring is at index
123 * tx_next_dd - (tx_rs_thresh-1)
124 */
125 txep = &txq->sw_ring[txq->tx_next_dd - (n - 1)];
126 m = rte_pktmbuf_prefree_seg(txep[0].mbuf);
127 if (likely(m != NULL)) {
128 free[0] = m;
129 nb_free = 1;
130 for (i = 1; i < n; i++) {
131 m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
132 if (likely(m != NULL)) {
133 if (likely(m->pool == free[0]->pool)) {
134 free[nb_free++] = m;
135 } else {
136 rte_mempool_put_bulk(free[0]->pool,
137 (void *)free,
138 nb_free);
139 free[0] = m;
140 nb_free = 1;
141 }
142 }
143 }
144 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
145 } else {
146 for (i = 1; i < n; i++) {
147 m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
148 if (m != NULL)
149 rte_mempool_put(m->pool, m);
150 }
151 }
152
153 /* buffers were freed, update counters */
154 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
155 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
156 if (txq->tx_next_dd >= txq->nb_tx_desc)
157 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
158
159 return txq->tx_rs_thresh;
160 }
161
162 static inline void __attribute__((always_inline))
163 tx_backlog_entry(struct i40e_tx_entry *txep,
164 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
165 {
166 int i;
167
168 for (i = 0; i < (int)nb_pkts; ++i)
169 txep[i].mbuf = tx_pkts[i];
170 }
171
172 static inline void
173 _i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
174 {
175 const unsigned mask = rxq->nb_rx_desc - 1;
176 unsigned i;
177
178 if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_rx_desc)
179 return;
180
181 /* free all mbufs that are valid in the ring */
182 if (rxq->rxrearm_nb == 0) {
183 for (i = 0; i < rxq->nb_rx_desc; i++) {
184 if (rxq->sw_ring[i].mbuf != NULL)
185 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
186 }
187 } else {
188 for (i = rxq->rx_tail;
189 i != rxq->rxrearm_start;
190 i = (i + 1) & mask) {
191 if (rxq->sw_ring[i].mbuf != NULL)
192 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
193 }
194 }
195
196 rxq->rxrearm_nb = rxq->nb_rx_desc;
197
198 /* set all entries to NULL */
199 memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);
200 }
201
202 static inline int
203 i40e_rxq_vec_setup_default(struct i40e_rx_queue *rxq)
204 {
205 uintptr_t p;
206 struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
207
208 mb_def.nb_segs = 1;
209 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
210 mb_def.port = rxq->port_id;
211 rte_mbuf_refcnt_set(&mb_def, 1);
212
213 /* prevent compiler reordering: rearm_data covers previous fields */
214 rte_compiler_barrier();
215 p = (uintptr_t)&mb_def.rearm_data;
216 rxq->mbuf_initializer = *(uint64_t *)p;
217 return 0;
218 }
219
220 static inline int
221 i40e_rx_vec_dev_conf_condition_check_default(struct rte_eth_dev *dev)
222 {
223 #ifndef RTE_LIBRTE_IEEE1588
224 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
225 struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
226
227 /* no fdir support */
228 if (fconf->mode != RTE_FDIR_MODE_NONE)
229 return -1;
230
231 /* - no csum error report support
232 * - no header split support
233 */
234 if (rxmode->header_split == 1)
235 return -1;
236
237 /* no QinQ support */
238 if (rxmode->hw_vlan_extend == 1)
239 return -1;
240
241 return 0;
242 #else
243 RTE_SET_USED(dev);
244 return -1;
245 #endif
246 }
247 #endif