ceph/src/seastar/dpdk/drivers/net/ice/base/ice_controlq.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2019
   3  */
   4
   5 #ifndef _ICE_CONTROLQ_H_
   6 #define _ICE_CONTROLQ_H_
   7
   8 #include "ice_adminq_cmd.h"
   9
  10
  11 /* Maximum buffer lengths for all control queue types */
  12 #define ICE_AQ_MAX_BUF_LEN 4096
  13 #define ICE_MBXQ_MAX_BUF_LEN 4096
  14
  15 #define ICE_CTL_Q_DESC(R, i) \
  16         (&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
  17
  18 #define ICE_CTL_Q_DESC_UNUSED(R) \
  19         (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  20               (R)->next_to_clean - (R)->next_to_use - 1)
  21
  22 /* Defines that help manage the driver vs FW API checks.
  23  * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
  24  */
  25 #define EXP_FW_API_VER_BRANCH           0x00
  26 #define EXP_FW_API_VER_MAJOR            0x01
  27 #define EXP_FW_API_VER_MINOR            0x03
  28
  29 /* Different control queue types: These are mainly for SW consumption. */
  30 enum ice_ctl_q {
  31         ICE_CTL_Q_UNKNOWN = 0,
  32         ICE_CTL_Q_ADMIN,
  33         ICE_CTL_Q_MAILBOX,
  34 };
  35
  36 /* Control Queue default settings */
  37 #define ICE_CTL_Q_SQ_CMD_TIMEOUT        250  /* msecs */
  38
  39 struct ice_ctl_q_ring {
  40         void *dma_head;                 /* Virtual address to dma head */
  41         struct ice_dma_mem desc_buf;    /* descriptor ring memory */
  42         void *cmd_buf;                  /* command buffer memory */
  43
  44         union {
  45                 struct ice_dma_mem *sq_bi;
  46                 struct ice_dma_mem *rq_bi;
  47         } r;
  48
  49         u16 count;              /* Number of descriptors */
  50
  51         /* used for interrupt processing */
  52         u16 next_to_use;
  53         u16 next_to_clean;
  54
  55         /* used for queue tracking */
  56         u32 head;
  57         u32 tail;
  58         u32 len;
  59         u32 bah;
  60         u32 bal;
  61         u32 len_mask;
  62         u32 len_ena_mask;
  63         u32 head_mask;
  64 };
  65
  66 /* sq transaction details */
  67 struct ice_sq_cd {
  68         struct ice_aq_desc *wb_desc;
  69 };
  70
  71 #define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))
  72
  73 /* rq event information */
  74 struct ice_rq_event_info {
  75         struct ice_aq_desc desc;
  76         u16 msg_len;
  77         u16 buf_len;
  78         u8 *msg_buf;
  79 };
  80
  81 /* Control Queue information */
  82 struct ice_ctl_q_info {
  83         enum ice_ctl_q qtype;
  84         struct ice_ctl_q_ring rq;       /* receive queue */
  85         struct ice_ctl_q_ring sq;       /* send queue */
  86         u32 sq_cmd_timeout;             /* send queue cmd write back timeout */
  87         u16 num_rq_entries;             /* receive queue depth */
  88         u16 num_sq_entries;             /* send queue depth */
  89         u16 rq_buf_size;                /* receive queue buffer size */
  90         u16 sq_buf_size;                /* send queue buffer size */
  91         struct ice_lock sq_lock;                /* Send queue lock */
  92         struct ice_lock rq_lock;                /* Receive queue lock */
  93         enum ice_aq_err sq_last_status; /* last status on send queue */
  94         enum ice_aq_err rq_last_status; /* last status on receive queue */
  95 };
  96
  97 #endif /* _ICE_CONTROLQ_H_ */