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update sources to ceph Nautilus 14.2.1
[ceph.git] / ceph / src / seastar / dpdk / drivers / net / ixgbe / base / ixgbe_phy.c
1 /*******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ***************************************************************************/
33
34 #include "ixgbe_api.h"
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
37
38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
50 u8 *sff8472_data);
51
52 /**
53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
54 * @hw: pointer to the hardware structure
55 * @byte: byte to send
56 *
57 * Returns an error code on error.
58 */
59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
60 {
61 s32 status;
62
63 status = ixgbe_clock_out_i2c_byte(hw, byte);
64 if (status)
65 return status;
66 return ixgbe_get_i2c_ack(hw);
67 }
68
69 /**
70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
71 * @hw: pointer to the hardware structure
72 * @byte: pointer to a u8 to receive the byte
73 *
74 * Returns an error code on error.
75 */
76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
77 {
78 s32 status;
79
80 status = ixgbe_clock_in_i2c_byte(hw, byte);
81 if (status)
82 return status;
83 /* ACK */
84 return ixgbe_clock_out_i2c_bit(hw, false);
85 }
86
87 /**
88 * ixgbe_ones_comp_byte_add - Perform one's complement addition
89 * @add1 - addend 1
90 * @add2 - addend 2
91 *
92 * Returns one's complement 8-bit sum.
93 */
94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
95 {
96 u16 sum = add1 + add2;
97
98 sum = (sum & 0xFF) + (sum >> 8);
99 return sum & 0xFF;
100 }
101
102 /**
103 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
104 * @hw: pointer to the hardware structure
105 * @addr: I2C bus address to read from
106 * @reg: I2C device register to read from
107 * @val: pointer to location to receive read value
108 * @lock: true if to take and release semaphore
109 *
110 * Returns an error code on error.
111 */
112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
113 u16 *val, bool lock)
114 {
115 u32 swfw_mask = hw->phy.phy_semaphore_mask;
116 int max_retry = 3;
117 int retry = 0;
118 u8 csum_byte;
119 u8 high_bits;
120 u8 low_bits;
121 u8 reg_high;
122 u8 csum;
123
124 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
125 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
126 csum = ~csum;
127 do {
128 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
129 return IXGBE_ERR_SWFW_SYNC;
130 ixgbe_i2c_start(hw);
131 /* Device Address and write indication */
132 if (ixgbe_out_i2c_byte_ack(hw, addr))
133 goto fail;
134 /* Write bits 14:8 */
135 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
136 goto fail;
137 /* Write bits 7:0 */
138 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
139 goto fail;
140 /* Write csum */
141 if (ixgbe_out_i2c_byte_ack(hw, csum))
142 goto fail;
143 /* Re-start condition */
144 ixgbe_i2c_start(hw);
145 /* Device Address and read indication */
146 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
147 goto fail;
148 /* Get upper bits */
149 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
150 goto fail;
151 /* Get low bits */
152 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
153 goto fail;
154 /* Get csum */
155 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
156 goto fail;
157 /* NACK */
158 if (ixgbe_clock_out_i2c_bit(hw, false))
159 goto fail;
160 ixgbe_i2c_stop(hw);
161 if (lock)
162 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
163 *val = (high_bits << 8) | low_bits;
164 return 0;
165
166 fail:
167 ixgbe_i2c_bus_clear(hw);
168 if (lock)
169 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
170 retry++;
171 if (retry < max_retry)
172 DEBUGOUT("I2C byte read combined error - Retrying.\n");
173 else
174 DEBUGOUT("I2C byte read combined error.\n");
175 } while (retry < max_retry);
176
177 return IXGBE_ERR_I2C;
178 }
179
180 /**
181 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
182 * @hw: pointer to the hardware structure
183 * @addr: I2C bus address to write to
184 * @reg: I2C device register to write to
185 * @val: value to write
186 * @lock: true if to take and release semaphore
187 *
188 * Returns an error code on error.
189 */
190 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
191 u16 val, bool lock)
192 {
193 u32 swfw_mask = hw->phy.phy_semaphore_mask;
194 int max_retry = 1;
195 int retry = 0;
196 u8 reg_high;
197 u8 csum;
198
199 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
200 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
201 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
202 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
203 csum = ~csum;
204 do {
205 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
206 return IXGBE_ERR_SWFW_SYNC;
207 ixgbe_i2c_start(hw);
208 /* Device Address and write indication */
209 if (ixgbe_out_i2c_byte_ack(hw, addr))
210 goto fail;
211 /* Write bits 14:8 */
212 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
213 goto fail;
214 /* Write bits 7:0 */
215 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
216 goto fail;
217 /* Write data 15:8 */
218 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
219 goto fail;
220 /* Write data 7:0 */
221 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
222 goto fail;
223 /* Write csum */
224 if (ixgbe_out_i2c_byte_ack(hw, csum))
225 goto fail;
226 ixgbe_i2c_stop(hw);
227 if (lock)
228 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
229 return 0;
230
231 fail:
232 ixgbe_i2c_bus_clear(hw);
233 if (lock)
234 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
235 retry++;
236 if (retry < max_retry)
237 DEBUGOUT("I2C byte write combined error - Retrying.\n");
238 else
239 DEBUGOUT("I2C byte write combined error.\n");
240 } while (retry < max_retry);
241
242 return IXGBE_ERR_I2C;
243 }
244
245 /**
246 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
247 * @hw: pointer to the hardware structure
248 *
249 * Initialize the function pointers.
250 **/
251 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
252 {
253 struct ixgbe_phy_info *phy = &hw->phy;
254
255 DEBUGFUNC("ixgbe_init_phy_ops_generic");
256
257 /* PHY */
258 phy->ops.identify = ixgbe_identify_phy_generic;
259 phy->ops.reset = ixgbe_reset_phy_generic;
260 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
261 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
262 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
263 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
264 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
265 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
266 phy->ops.check_link = NULL;
267 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
268 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
269 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
270 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
271 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
272 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
273 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
274 phy->ops.identify_sfp = ixgbe_identify_module_generic;
275 phy->sfp_type = ixgbe_sfp_type_unknown;
276 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
277 phy->ops.write_i2c_byte_unlocked =
278 ixgbe_write_i2c_byte_generic_unlocked;
279 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
280 return IXGBE_SUCCESS;
281 }
282
283 /**
284 * ixgbe_probe_phy - Probe a single address for a PHY
285 * @hw: pointer to hardware structure
286 * @phy_addr: PHY address to probe
287 *
288 * Returns true if PHY found
289 */
290 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
291 {
292 u16 ext_ability = 0;
293
294 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
295 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
296 phy_addr);
297 return false;
298 }
299
300 if (ixgbe_get_phy_id(hw))
301 return false;
302
303 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
304
305 if (hw->phy.type == ixgbe_phy_unknown) {
306 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
307 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
308 if (ext_ability &
309 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
310 IXGBE_MDIO_PHY_1000BASET_ABILITY))
311 hw->phy.type = ixgbe_phy_cu_unknown;
312 else
313 hw->phy.type = ixgbe_phy_generic;
314 }
315
316 return true;
317 }
318
319 /**
320 * ixgbe_identify_phy_generic - Get physical layer module
321 * @hw: pointer to hardware structure
322 *
323 * Determines the physical layer module found on the current adapter.
324 **/
325 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
326 {
327 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
328 u16 phy_addr;
329
330 DEBUGFUNC("ixgbe_identify_phy_generic");
331
332 if (!hw->phy.phy_semaphore_mask) {
333 if (hw->bus.lan_id)
334 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
335 else
336 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
337 }
338
339 if (hw->phy.type != ixgbe_phy_unknown)
340 return IXGBE_SUCCESS;
341
342 if (hw->phy.nw_mng_if_sel) {
343 phy_addr = (hw->phy.nw_mng_if_sel &
344 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
345 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
346 if (ixgbe_probe_phy(hw, phy_addr))
347 return IXGBE_SUCCESS;
348 else
349 return IXGBE_ERR_PHY_ADDR_INVALID;
350 }
351
352 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
353 if (ixgbe_probe_phy(hw, phy_addr)) {
354 status = IXGBE_SUCCESS;
355 break;
356 }
357 }
358
359 /* Certain media types do not have a phy so an address will not
360 * be found and the code will take this path. Caller has to
361 * decide if it is an error or not.
362 */
363 if (status != IXGBE_SUCCESS)
364 hw->phy.addr = 0;
365
366 return status;
367 }
368
369 /**
370 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
371 * @hw: pointer to the hardware structure
372 *
373 * This function checks the MMNGC.MNG_VETO bit to see if there are
374 * any constraints on link from manageability. For MAC's that don't
375 * have this bit just return faluse since the link can not be blocked
376 * via this method.
377 **/
378 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
379 {
380 u32 mmngc;
381
382 DEBUGFUNC("ixgbe_check_reset_blocked");
383
384 /* If we don't have this bit, it can't be blocking */
385 if (hw->mac.type == ixgbe_mac_82598EB)
386 return false;
387
388 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
389 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
390 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
391 "MNG_VETO bit detected.\n");
392 return true;
393 }
394
395 return false;
396 }
397
398 /**
399 * ixgbe_validate_phy_addr - Determines phy address is valid
400 * @hw: pointer to hardware structure
401 *
402 **/
403 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
404 {
405 u16 phy_id = 0;
406 bool valid = false;
407
408 DEBUGFUNC("ixgbe_validate_phy_addr");
409
410 hw->phy.addr = phy_addr;
411 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
412 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
413
414 if (phy_id != 0xFFFF && phy_id != 0x0)
415 valid = true;
416
417 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
418
419 return valid;
420 }
421
422 /**
423 * ixgbe_get_phy_id - Get the phy type
424 * @hw: pointer to hardware structure
425 *
426 **/
427 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
428 {
429 u32 status;
430 u16 phy_id_high = 0;
431 u16 phy_id_low = 0;
432
433 DEBUGFUNC("ixgbe_get_phy_id");
434
435 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
436 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
437 &phy_id_high);
438
439 if (status == IXGBE_SUCCESS) {
440 hw->phy.id = (u32)(phy_id_high << 16);
441 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
442 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
443 &phy_id_low);
444 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
445 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
446 }
447 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
448 phy_id_high, phy_id_low);
449
450 return status;
451 }
452
453 /**
454 * ixgbe_get_phy_type_from_id - Get the phy type
455 * @phy_id: PHY ID information
456 *
457 **/
458 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
459 {
460 enum ixgbe_phy_type phy_type;
461
462 DEBUGFUNC("ixgbe_get_phy_type_from_id");
463
464 switch (phy_id) {
465 case TN1010_PHY_ID:
466 phy_type = ixgbe_phy_tn;
467 break;
468 case X550_PHY_ID2:
469 case X550_PHY_ID3:
470 case X540_PHY_ID:
471 phy_type = ixgbe_phy_aq;
472 break;
473 case QT2022_PHY_ID:
474 phy_type = ixgbe_phy_qt;
475 break;
476 case ATH_PHY_ID:
477 phy_type = ixgbe_phy_nl;
478 break;
479 case X557_PHY_ID:
480 case X557_PHY_ID2:
481 phy_type = ixgbe_phy_x550em_ext_t;
482 break;
483 case IXGBE_M88E1500_E_PHY_ID:
484 case IXGBE_M88E1543_E_PHY_ID:
485 phy_type = ixgbe_phy_ext_1g_t;
486 break;
487 default:
488 phy_type = ixgbe_phy_unknown;
489 break;
490 }
491 return phy_type;
492 }
493
494 /**
495 * ixgbe_reset_phy_generic - Performs a PHY reset
496 * @hw: pointer to hardware structure
497 **/
498 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
499 {
500 u32 i;
501 u16 ctrl = 0;
502 s32 status = IXGBE_SUCCESS;
503
504 DEBUGFUNC("ixgbe_reset_phy_generic");
505
506 if (hw->phy.type == ixgbe_phy_unknown)
507 status = ixgbe_identify_phy_generic(hw);
508
509 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
510 goto out;
511
512 /* Don't reset PHY if it's shut down due to overtemp. */
513 if (!hw->phy.reset_if_overtemp &&
514 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
515 goto out;
516
517 /* Blocked by MNG FW so bail */
518 if (ixgbe_check_reset_blocked(hw))
519 goto out;
520
521 /*
522 * Perform soft PHY reset to the PHY_XS.
523 * This will cause a soft reset to the PHY
524 */
525 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
526 IXGBE_MDIO_PHY_XS_DEV_TYPE,
527 IXGBE_MDIO_PHY_XS_RESET);
528
529 /*
530 * Poll for reset bit to self-clear indicating reset is complete.
531 * Some PHYs could take up to 3 seconds to complete and need about
532 * 1.7 usec delay after the reset is complete.
533 */
534 for (i = 0; i < 30; i++) {
535 msec_delay(100);
536 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
537 status = hw->phy.ops.read_reg(hw,
538 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
539 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
540 &ctrl);
541 if (status != IXGBE_SUCCESS)
542 return status;
543
544 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
545 usec_delay(2);
546 break;
547 }
548 } else {
549 status = hw->phy.ops.read_reg(hw,
550 IXGBE_MDIO_PHY_XS_CONTROL,
551 IXGBE_MDIO_PHY_XS_DEV_TYPE,
552 &ctrl);
553 if (status != IXGBE_SUCCESS)
554 return status;
555
556 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
557 usec_delay(2);
558 break;
559 }
560 }
561 }
562
563 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
564 status = IXGBE_ERR_RESET_FAILED;
565 ERROR_REPORT1(IXGBE_ERROR_POLLING,
566 "PHY reset polling failed to complete.\n");
567 }
568
569 out:
570 return status;
571 }
572
573 /**
574 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
575 * the SWFW lock
576 * @hw: pointer to hardware structure
577 * @reg_addr: 32 bit address of PHY register to read
578 * @phy_data: Pointer to read data from PHY register
579 **/
580 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
581 u16 *phy_data)
582 {
583 u32 i, data, command;
584
585 /* Setup and write the address cycle command */
586 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
587 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
588 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
589 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
590
591 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
592
593 /*
594 * Check every 10 usec to see if the address cycle completed.
595 * The MDI Command bit will clear when the operation is
596 * complete
597 */
598 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
599 usec_delay(10);
600
601 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
602 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
603 break;
604 }
605
606
607 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
608 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
609 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
610 return IXGBE_ERR_PHY;
611 }
612
613 /*
614 * Address cycle complete, setup and write the read
615 * command
616 */
617 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
618 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
619 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
620 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
621
622 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
623
624 /*
625 * Check every 10 usec to see if the address cycle
626 * completed. The MDI Command bit will clear when the
627 * operation is complete
628 */
629 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
630 usec_delay(10);
631
632 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
633 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
634 break;
635 }
636
637 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
638 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
639 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
640 return IXGBE_ERR_PHY;
641 }
642
643 /*
644 * Read operation is complete. Get the data
645 * from MSRWD
646 */
647 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
648 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
649 *phy_data = (u16)(data);
650
651 return IXGBE_SUCCESS;
652 }
653
654 /**
655 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
656 * using the SWFW lock - this function is needed in most cases
657 * @hw: pointer to hardware structure
658 * @reg_addr: 32 bit address of PHY register to read
659 * @phy_data: Pointer to read data from PHY register
660 **/
661 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
662 u32 device_type, u16 *phy_data)
663 {
664 s32 status;
665 u32 gssr = hw->phy.phy_semaphore_mask;
666
667 DEBUGFUNC("ixgbe_read_phy_reg_generic");
668
669 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
670 return IXGBE_ERR_SWFW_SYNC;
671
672 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
673
674 hw->mac.ops.release_swfw_sync(hw, gssr);
675
676 return status;
677 }
678
679 /**
680 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
681 * without SWFW lock
682 * @hw: pointer to hardware structure
683 * @reg_addr: 32 bit PHY register to write
684 * @device_type: 5 bit device type
685 * @phy_data: Data to write to the PHY register
686 **/
687 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
688 u32 device_type, u16 phy_data)
689 {
690 u32 i, command;
691
692 /* Put the data in the MDI single read and write data register*/
693 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
694
695 /* Setup and write the address cycle command */
696 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
697 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
698 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
699 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
700
701 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
702
703 /*
704 * Check every 10 usec to see if the address cycle completed.
705 * The MDI Command bit will clear when the operation is
706 * complete
707 */
708 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
709 usec_delay(10);
710
711 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
712 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
713 break;
714 }
715
716 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
717 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
718 return IXGBE_ERR_PHY;
719 }
720
721 /*
722 * Address cycle complete, setup and write the write
723 * command
724 */
725 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
726 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
727 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
728 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
729
730 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
731
732 /*
733 * Check every 10 usec to see if the address cycle
734 * completed. The MDI Command bit will clear when the
735 * operation is complete
736 */
737 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
738 usec_delay(10);
739
740 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
741 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
742 break;
743 }
744
745 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
746 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
747 return IXGBE_ERR_PHY;
748 }
749
750 return IXGBE_SUCCESS;
751 }
752
753 /**
754 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
755 * using SWFW lock- this function is needed in most cases
756 * @hw: pointer to hardware structure
757 * @reg_addr: 32 bit PHY register to write
758 * @device_type: 5 bit device type
759 * @phy_data: Data to write to the PHY register
760 **/
761 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
762 u32 device_type, u16 phy_data)
763 {
764 s32 status;
765 u32 gssr = hw->phy.phy_semaphore_mask;
766
767 DEBUGFUNC("ixgbe_write_phy_reg_generic");
768
769 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
770 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
771 phy_data);
772 hw->mac.ops.release_swfw_sync(hw, gssr);
773 } else {
774 status = IXGBE_ERR_SWFW_SYNC;
775 }
776
777 return status;
778 }
779
780 /**
781 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
782 * @hw: pointer to hardware structure
783 *
784 * Restart auto-negotiation and PHY and waits for completion.
785 **/
786 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
787 {
788 s32 status = IXGBE_SUCCESS;
789 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
790 bool autoneg = false;
791 ixgbe_link_speed speed;
792
793 DEBUGFUNC("ixgbe_setup_phy_link_generic");
794
795 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
796
797 /* Set or unset auto-negotiation 10G advertisement */
798 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
799 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
800 &autoneg_reg);
801
802 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
803 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
804 (speed & IXGBE_LINK_SPEED_10GB_FULL))
805 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
806
807 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
808 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
809 autoneg_reg);
810
811 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
812 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
813 &autoneg_reg);
814
815 if (hw->mac.type == ixgbe_mac_X550) {
816 /* Set or unset auto-negotiation 5G advertisement */
817 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
818 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
819 (speed & IXGBE_LINK_SPEED_5GB_FULL))
820 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
821
822 /* Set or unset auto-negotiation 2.5G advertisement */
823 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
824 if ((hw->phy.autoneg_advertised &
825 IXGBE_LINK_SPEED_2_5GB_FULL) &&
826 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
827 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
828 }
829
830 /* Set or unset auto-negotiation 1G advertisement */
831 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
832 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
833 (speed & IXGBE_LINK_SPEED_1GB_FULL))
834 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
835
836 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
837 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
838 autoneg_reg);
839
840 /* Set or unset auto-negotiation 100M advertisement */
841 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
842 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
843 &autoneg_reg);
844
845 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
846 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
847 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
848 (speed & IXGBE_LINK_SPEED_100_FULL))
849 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
850
851 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
852 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
853 autoneg_reg);
854
855 /* Blocked by MNG FW so don't reset PHY */
856 if (ixgbe_check_reset_blocked(hw))
857 return status;
858
859 /* Restart PHY auto-negotiation. */
860 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
861 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
862
863 autoneg_reg |= IXGBE_MII_RESTART;
864
865 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
866 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
867
868 return status;
869 }
870
871 /**
872 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
873 * @hw: pointer to hardware structure
874 * @speed: new link speed
875 **/
876 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
877 ixgbe_link_speed speed,
878 bool autoneg_wait_to_complete)
879 {
880 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
881
882 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
883
884 /*
885 * Clear autoneg_advertised and set new values based on input link
886 * speed.
887 */
888 hw->phy.autoneg_advertised = 0;
889
890 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
891 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
892
893 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
894 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
895
896 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
897 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
898
899 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
900 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
901
902 if (speed & IXGBE_LINK_SPEED_100_FULL)
903 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
904
905 if (speed & IXGBE_LINK_SPEED_10_FULL)
906 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
907
908 /* Setup link based on the new speed settings */
909 ixgbe_setup_phy_link(hw);
910
911 return IXGBE_SUCCESS;
912 }
913
914 /**
915 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
916 * @hw: pointer to hardware structure
917 *
918 * Determines the supported link capabilities by reading the PHY auto
919 * negotiation register.
920 **/
921 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
922 {
923 s32 status;
924 u16 speed_ability;
925
926 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
927 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
928 &speed_ability);
929 if (status)
930 return status;
931
932 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
933 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
934 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
935 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
936 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
937 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
938
939 switch (hw->mac.type) {
940 case ixgbe_mac_X550:
941 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
942 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
943 break;
944 case ixgbe_mac_X550EM_x:
945 case ixgbe_mac_X550EM_a:
946 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
947 break;
948 default:
949 break;
950 }
951
952 return status;
953 }
954
955 /**
956 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
957 * @hw: pointer to hardware structure
958 * @speed: pointer to link speed
959 * @autoneg: boolean auto-negotiation value
960 **/
961 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
962 ixgbe_link_speed *speed,
963 bool *autoneg)
964 {
965 s32 status = IXGBE_SUCCESS;
966
967 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
968
969 *autoneg = true;
970 if (!hw->phy.speeds_supported)
971 status = ixgbe_get_copper_speeds_supported(hw);
972
973 *speed = hw->phy.speeds_supported;
974 return status;
975 }
976
977 /**
978 * ixgbe_check_phy_link_tnx - Determine link and speed status
979 * @hw: pointer to hardware structure
980 *
981 * Reads the VS1 register to determine if link is up and the current speed for
982 * the PHY.
983 **/
984 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
985 bool *link_up)
986 {
987 s32 status = IXGBE_SUCCESS;
988 u32 time_out;
989 u32 max_time_out = 10;
990 u16 phy_link = 0;
991 u16 phy_speed = 0;
992 u16 phy_data = 0;
993
994 DEBUGFUNC("ixgbe_check_phy_link_tnx");
995
996 /* Initialize speed and link to default case */
997 *link_up = false;
998 *speed = IXGBE_LINK_SPEED_10GB_FULL;
999
1000 /*
1001 * Check current speed and link status of the PHY register.
1002 * This is a vendor specific register and may have to
1003 * be changed for other copper PHYs.
1004 */
1005 for (time_out = 0; time_out < max_time_out; time_out++) {
1006 usec_delay(10);
1007 status = hw->phy.ops.read_reg(hw,
1008 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1009 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1010 &phy_data);
1011 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1012 phy_speed = phy_data &
1013 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1014 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1015 *link_up = true;
1016 if (phy_speed ==
1017 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1018 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1019 break;
1020 }
1021 }
1022
1023 return status;
1024 }
1025
1026 /**
1027 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1028 * @hw: pointer to hardware structure
1029 *
1030 * Restart auto-negotiation and PHY and waits for completion.
1031 **/
1032 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1033 {
1034 s32 status = IXGBE_SUCCESS;
1035 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1036 bool autoneg = false;
1037 ixgbe_link_speed speed;
1038
1039 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1040
1041 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1042
1043 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1044 /* Set or unset auto-negotiation 10G advertisement */
1045 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1046 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1047 &autoneg_reg);
1048
1049 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1050 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1051 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1052
1053 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1054 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1055 autoneg_reg);
1056 }
1057
1058 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1059 /* Set or unset auto-negotiation 1G advertisement */
1060 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1061 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1062 &autoneg_reg);
1063
1064 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1065 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1066 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1067
1068 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1069 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1070 autoneg_reg);
1071 }
1072
1073 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1074 /* Set or unset auto-negotiation 100M advertisement */
1075 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1076 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1077 &autoneg_reg);
1078
1079 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1080 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1081 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1082
1083 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1084 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1085 autoneg_reg);
1086 }
1087
1088 /* Blocked by MNG FW so don't reset PHY */
1089 if (ixgbe_check_reset_blocked(hw))
1090 return status;
1091
1092 /* Restart PHY auto-negotiation. */
1093 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1094 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1095
1096 autoneg_reg |= IXGBE_MII_RESTART;
1097
1098 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1099 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1100
1101 return status;
1102 }
1103
1104 /**
1105 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1106 * @hw: pointer to hardware structure
1107 * @firmware_version: pointer to the PHY Firmware Version
1108 **/
1109 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1110 u16 *firmware_version)
1111 {
1112 s32 status;
1113
1114 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1115
1116 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1117 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1118 firmware_version);
1119
1120 return status;
1121 }
1122
1123 /**
1124 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1125 * @hw: pointer to hardware structure
1126 * @firmware_version: pointer to the PHY Firmware Version
1127 **/
1128 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1129 u16 *firmware_version)
1130 {
1131 s32 status;
1132
1133 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1134
1135 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1136 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1137 firmware_version);
1138
1139 return status;
1140 }
1141
1142 /**
1143 * ixgbe_reset_phy_nl - Performs a PHY reset
1144 * @hw: pointer to hardware structure
1145 **/
1146 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1147 {
1148 u16 phy_offset, control, eword, edata, block_crc;
1149 bool end_data = false;
1150 u16 list_offset, data_offset;
1151 u16 phy_data = 0;
1152 s32 ret_val = IXGBE_SUCCESS;
1153 u32 i;
1154
1155 DEBUGFUNC("ixgbe_reset_phy_nl");
1156
1157 /* Blocked by MNG FW so bail */
1158 if (ixgbe_check_reset_blocked(hw))
1159 goto out;
1160
1161 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1162 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1163
1164 /* reset the PHY and poll for completion */
1165 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1166 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1167 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1168
1169 for (i = 0; i < 100; i++) {
1170 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1171 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1172 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1173 break;
1174 msec_delay(10);
1175 }
1176
1177 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1178 DEBUGOUT("PHY reset did not complete.\n");
1179 ret_val = IXGBE_ERR_PHY;
1180 goto out;
1181 }
1182
1183 /* Get init offsets */
1184 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1185 &data_offset);
1186 if (ret_val != IXGBE_SUCCESS)
1187 goto out;
1188
1189 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1190 data_offset++;
1191 while (!end_data) {
1192 /*
1193 * Read control word from PHY init contents offset
1194 */
1195 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1196 if (ret_val)
1197 goto err_eeprom;
1198 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1199 IXGBE_CONTROL_SHIFT_NL;
1200 edata = eword & IXGBE_DATA_MASK_NL;
1201 switch (control) {
1202 case IXGBE_DELAY_NL:
1203 data_offset++;
1204 DEBUGOUT1("DELAY: %d MS\n", edata);
1205 msec_delay(edata);
1206 break;
1207 case IXGBE_DATA_NL:
1208 DEBUGOUT("DATA:\n");
1209 data_offset++;
1210 ret_val = hw->eeprom.ops.read(hw, data_offset,
1211 &phy_offset);
1212 if (ret_val)
1213 goto err_eeprom;
1214 data_offset++;
1215 for (i = 0; i < edata; i++) {
1216 ret_val = hw->eeprom.ops.read(hw, data_offset,
1217 &eword);
1218 if (ret_val)
1219 goto err_eeprom;
1220 hw->phy.ops.write_reg(hw, phy_offset,
1221 IXGBE_TWINAX_DEV, eword);
1222 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1223 phy_offset);
1224 data_offset++;
1225 phy_offset++;
1226 }
1227 break;
1228 case IXGBE_CONTROL_NL:
1229 data_offset++;
1230 DEBUGOUT("CONTROL:\n");
1231 if (edata == IXGBE_CONTROL_EOL_NL) {
1232 DEBUGOUT("EOL\n");
1233 end_data = true;
1234 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1235 DEBUGOUT("SOL\n");
1236 } else {
1237 DEBUGOUT("Bad control value\n");
1238 ret_val = IXGBE_ERR_PHY;
1239 goto out;
1240 }
1241 break;
1242 default:
1243 DEBUGOUT("Bad control type\n");
1244 ret_val = IXGBE_ERR_PHY;
1245 goto out;
1246 }
1247 }
1248
1249 out:
1250 return ret_val;
1251
1252 err_eeprom:
1253 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1254 "eeprom read at offset %d failed", data_offset);
1255 return IXGBE_ERR_PHY;
1256 }
1257
1258 /**
1259 * ixgbe_identify_module_generic - Identifies module type
1260 * @hw: pointer to hardware structure
1261 *
1262 * Determines HW type and calls appropriate function.
1263 **/
1264 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1265 {
1266 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1267
1268 DEBUGFUNC("ixgbe_identify_module_generic");
1269
1270 switch (hw->mac.ops.get_media_type(hw)) {
1271 case ixgbe_media_type_fiber:
1272 status = ixgbe_identify_sfp_module_generic(hw);
1273 break;
1274
1275 case ixgbe_media_type_fiber_qsfp:
1276 status = ixgbe_identify_qsfp_module_generic(hw);
1277 break;
1278
1279 default:
1280 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1281 status = IXGBE_ERR_SFP_NOT_PRESENT;
1282 break;
1283 }
1284
1285 return status;
1286 }
1287
1288 /**
1289 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1290 * @hw: pointer to hardware structure
1291 *
1292 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1293 **/
1294 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1295 {
1296 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1297 u32 vendor_oui = 0;
1298 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1299 u8 identifier = 0;
1300 u8 comp_codes_1g = 0;
1301 u8 comp_codes_10g = 0;
1302 u8 oui_bytes[3] = {0, 0, 0};
1303 u8 cable_tech = 0;
1304 u8 cable_spec = 0;
1305 u16 enforce_sfp = 0;
1306
1307 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1308
1309 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1310 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1311 status = IXGBE_ERR_SFP_NOT_PRESENT;
1312 goto out;
1313 }
1314
1315 /* LAN ID is needed for I2C access */
1316 hw->mac.ops.set_lan_id(hw);
1317
1318 status = hw->phy.ops.read_i2c_eeprom(hw,
1319 IXGBE_SFF_IDENTIFIER,
1320 &identifier);
1321
1322 if (status != IXGBE_SUCCESS)
1323 goto err_read_i2c_eeprom;
1324
1325 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1326 hw->phy.type = ixgbe_phy_sfp_unsupported;
1327 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1328 } else {
1329 status = hw->phy.ops.read_i2c_eeprom(hw,
1330 IXGBE_SFF_1GBE_COMP_CODES,
1331 &comp_codes_1g);
1332
1333 if (status != IXGBE_SUCCESS)
1334 goto err_read_i2c_eeprom;
1335
1336 status = hw->phy.ops.read_i2c_eeprom(hw,
1337 IXGBE_SFF_10GBE_COMP_CODES,
1338 &comp_codes_10g);
1339
1340 if (status != IXGBE_SUCCESS)
1341 goto err_read_i2c_eeprom;
1342 status = hw->phy.ops.read_i2c_eeprom(hw,
1343 IXGBE_SFF_CABLE_TECHNOLOGY,
1344 &cable_tech);
1345
1346 if (status != IXGBE_SUCCESS)
1347 goto err_read_i2c_eeprom;
1348
1349 /* ID Module
1350 * =========
1351 * 0 SFP_DA_CU
1352 * 1 SFP_SR
1353 * 2 SFP_LR
1354 * 3 SFP_DA_CORE0 - 82599-specific
1355 * 4 SFP_DA_CORE1 - 82599-specific
1356 * 5 SFP_SR/LR_CORE0 - 82599-specific
1357 * 6 SFP_SR/LR_CORE1 - 82599-specific
1358 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1359 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1360 * 9 SFP_1g_cu_CORE0 - 82599-specific
1361 * 10 SFP_1g_cu_CORE1 - 82599-specific
1362 * 11 SFP_1g_sx_CORE0 - 82599-specific
1363 * 12 SFP_1g_sx_CORE1 - 82599-specific
1364 */
1365 if (hw->mac.type == ixgbe_mac_82598EB) {
1366 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1367 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1368 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1369 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1370 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1371 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1372 else
1373 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1374 } else {
1375 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1376 if (hw->bus.lan_id == 0)
1377 hw->phy.sfp_type =
1378 ixgbe_sfp_type_da_cu_core0;
1379 else
1380 hw->phy.sfp_type =
1381 ixgbe_sfp_type_da_cu_core1;
1382 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1383 hw->phy.ops.read_i2c_eeprom(
1384 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1385 &cable_spec);
1386 if (cable_spec &
1387 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1388 if (hw->bus.lan_id == 0)
1389 hw->phy.sfp_type =
1390 ixgbe_sfp_type_da_act_lmt_core0;
1391 else
1392 hw->phy.sfp_type =
1393 ixgbe_sfp_type_da_act_lmt_core1;
1394 } else {
1395 hw->phy.sfp_type =
1396 ixgbe_sfp_type_unknown;
1397 }
1398 } else if (comp_codes_10g &
1399 (IXGBE_SFF_10GBASESR_CAPABLE |
1400 IXGBE_SFF_10GBASELR_CAPABLE)) {
1401 if (hw->bus.lan_id == 0)
1402 hw->phy.sfp_type =
1403 ixgbe_sfp_type_srlr_core0;
1404 else
1405 hw->phy.sfp_type =
1406 ixgbe_sfp_type_srlr_core1;
1407 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1408 if (hw->bus.lan_id == 0)
1409 hw->phy.sfp_type =
1410 ixgbe_sfp_type_1g_cu_core0;
1411 else
1412 hw->phy.sfp_type =
1413 ixgbe_sfp_type_1g_cu_core1;
1414 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1415 if (hw->bus.lan_id == 0)
1416 hw->phy.sfp_type =
1417 ixgbe_sfp_type_1g_sx_core0;
1418 else
1419 hw->phy.sfp_type =
1420 ixgbe_sfp_type_1g_sx_core1;
1421 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1422 if (hw->bus.lan_id == 0)
1423 hw->phy.sfp_type =
1424 ixgbe_sfp_type_1g_lx_core0;
1425 else
1426 hw->phy.sfp_type =
1427 ixgbe_sfp_type_1g_lx_core1;
1428 } else {
1429 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1430 }
1431 }
1432
1433 if (hw->phy.sfp_type != stored_sfp_type)
1434 hw->phy.sfp_setup_needed = true;
1435
1436 /* Determine if the SFP+ PHY is dual speed or not. */
1437 hw->phy.multispeed_fiber = false;
1438 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1439 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1440 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1441 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1442 hw->phy.multispeed_fiber = true;
1443
1444 /* Determine PHY vendor */
1445 if (hw->phy.type != ixgbe_phy_nl) {
1446 hw->phy.id = identifier;
1447 status = hw->phy.ops.read_i2c_eeprom(hw,
1448 IXGBE_SFF_VENDOR_OUI_BYTE0,
1449 &oui_bytes[0]);
1450
1451 if (status != IXGBE_SUCCESS)
1452 goto err_read_i2c_eeprom;
1453
1454 status = hw->phy.ops.read_i2c_eeprom(hw,
1455 IXGBE_SFF_VENDOR_OUI_BYTE1,
1456 &oui_bytes[1]);
1457
1458 if (status != IXGBE_SUCCESS)
1459 goto err_read_i2c_eeprom;
1460
1461 status = hw->phy.ops.read_i2c_eeprom(hw,
1462 IXGBE_SFF_VENDOR_OUI_BYTE2,
1463 &oui_bytes[2]);
1464
1465 if (status != IXGBE_SUCCESS)
1466 goto err_read_i2c_eeprom;
1467
1468 vendor_oui =
1469 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1470 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1471 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1472
1473 switch (vendor_oui) {
1474 case IXGBE_SFF_VENDOR_OUI_TYCO:
1475 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1476 hw->phy.type =
1477 ixgbe_phy_sfp_passive_tyco;
1478 break;
1479 case IXGBE_SFF_VENDOR_OUI_FTL:
1480 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1481 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1482 else
1483 hw->phy.type = ixgbe_phy_sfp_ftl;
1484 break;
1485 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1486 hw->phy.type = ixgbe_phy_sfp_avago;
1487 break;
1488 case IXGBE_SFF_VENDOR_OUI_INTEL:
1489 hw->phy.type = ixgbe_phy_sfp_intel;
1490 break;
1491 default:
1492 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1493 hw->phy.type =
1494 ixgbe_phy_sfp_passive_unknown;
1495 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1496 hw->phy.type =
1497 ixgbe_phy_sfp_active_unknown;
1498 else
1499 hw->phy.type = ixgbe_phy_sfp_unknown;
1500 break;
1501 }
1502 }
1503
1504 /* Allow any DA cable vendor */
1505 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1506 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1507 status = IXGBE_SUCCESS;
1508 goto out;
1509 }
1510
1511 /* Verify supported 1G SFP modules */
1512 if (comp_codes_10g == 0 &&
1513 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1514 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1515 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1516 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1517 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1518 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1519 hw->phy.type = ixgbe_phy_sfp_unsupported;
1520 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1521 goto out;
1522 }
1523
1524 /* Anything else 82598-based is supported */
1525 if (hw->mac.type == ixgbe_mac_82598EB) {
1526 status = IXGBE_SUCCESS;
1527 goto out;
1528 }
1529
1530 ixgbe_get_device_caps(hw, &enforce_sfp);
1531 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1532 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1533 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1534 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1535 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1536 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1537 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1538 /* Make sure we're a supported PHY type */
1539 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1540 status = IXGBE_SUCCESS;
1541 } else {
1542 if (hw->allow_unsupported_sfp == true) {
1543 EWARN(hw,
1544 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1545 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1546 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1547 status = IXGBE_SUCCESS;
1548 } else {
1549 DEBUGOUT("SFP+ module not supported\n");
1550 hw->phy.type =
1551 ixgbe_phy_sfp_unsupported;
1552 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1553 }
1554 }
1555 } else {
1556 status = IXGBE_SUCCESS;
1557 }
1558 }
1559
1560 out:
1561 return status;
1562
1563 err_read_i2c_eeprom:
1564 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1565 if (hw->phy.type != ixgbe_phy_nl) {
1566 hw->phy.id = 0;
1567 hw->phy.type = ixgbe_phy_unknown;
1568 }
1569 return IXGBE_ERR_SFP_NOT_PRESENT;
1570 }
1571
1572 /**
1573 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1574 * @hw: pointer to hardware structure
1575 *
1576 * Determines physical layer capabilities of the current SFP.
1577 */
1578 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1579 {
1580 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1581 u8 comp_codes_10g = 0;
1582 u8 comp_codes_1g = 0;
1583
1584 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1585
1586 hw->phy.ops.identify_sfp(hw);
1587 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1588 return physical_layer;
1589
1590 switch (hw->phy.type) {
1591 case ixgbe_phy_sfp_passive_tyco:
1592 case ixgbe_phy_sfp_passive_unknown:
1593 case ixgbe_phy_qsfp_passive_unknown:
1594 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1595 break;
1596 case ixgbe_phy_sfp_ftl_active:
1597 case ixgbe_phy_sfp_active_unknown:
1598 case ixgbe_phy_qsfp_active_unknown:
1599 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1600 break;
1601 case ixgbe_phy_sfp_avago:
1602 case ixgbe_phy_sfp_ftl:
1603 case ixgbe_phy_sfp_intel:
1604 case ixgbe_phy_sfp_unknown:
1605 hw->phy.ops.read_i2c_eeprom(hw,
1606 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1607 hw->phy.ops.read_i2c_eeprom(hw,
1608 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1609 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1610 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1611 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1612 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1613 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1614 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1615 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1616 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1617 break;
1618 case ixgbe_phy_qsfp_intel:
1619 case ixgbe_phy_qsfp_unknown:
1620 hw->phy.ops.read_i2c_eeprom(hw,
1621 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1622 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1623 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1624 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1625 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1626 break;
1627 default:
1628 break;
1629 }
1630
1631 return physical_layer;
1632 }
1633
1634 /**
1635 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1636 * @hw: pointer to hardware structure
1637 *
1638 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1639 **/
1640 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1641 {
1642 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1643 u32 vendor_oui = 0;
1644 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1645 u8 identifier = 0;
1646 u8 comp_codes_1g = 0;
1647 u8 comp_codes_10g = 0;
1648 u8 oui_bytes[3] = {0, 0, 0};
1649 u16 enforce_sfp = 0;
1650 u8 connector = 0;
1651 u8 cable_length = 0;
1652 u8 device_tech = 0;
1653 bool active_cable = false;
1654
1655 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1656
1657 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1658 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1659 status = IXGBE_ERR_SFP_NOT_PRESENT;
1660 goto out;
1661 }
1662
1663 /* LAN ID is needed for I2C access */
1664 hw->mac.ops.set_lan_id(hw);
1665
1666 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1667 &identifier);
1668
1669 if (status != IXGBE_SUCCESS)
1670 goto err_read_i2c_eeprom;
1671
1672 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1673 hw->phy.type = ixgbe_phy_sfp_unsupported;
1674 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1675 goto out;
1676 }
1677
1678 hw->phy.id = identifier;
1679
1680 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1681 &comp_codes_10g);
1682
1683 if (status != IXGBE_SUCCESS)
1684 goto err_read_i2c_eeprom;
1685
1686 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1687 &comp_codes_1g);
1688
1689 if (status != IXGBE_SUCCESS)
1690 goto err_read_i2c_eeprom;
1691
1692 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1693 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1694 if (hw->bus.lan_id == 0)
1695 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1696 else
1697 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1698 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1699 IXGBE_SFF_10GBASELR_CAPABLE)) {
1700 if (hw->bus.lan_id == 0)
1701 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1702 else
1703 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1704 } else {
1705 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1706 active_cable = true;
1707
1708 if (!active_cable) {
1709 /* check for active DA cables that pre-date
1710 * SFF-8436 v3.6 */
1711 hw->phy.ops.read_i2c_eeprom(hw,
1712 IXGBE_SFF_QSFP_CONNECTOR,
1713 &connector);
1714
1715 hw->phy.ops.read_i2c_eeprom(hw,
1716 IXGBE_SFF_QSFP_CABLE_LENGTH,
1717 &cable_length);
1718
1719 hw->phy.ops.read_i2c_eeprom(hw,
1720 IXGBE_SFF_QSFP_DEVICE_TECH,
1721 &device_tech);
1722
1723 if ((connector ==
1724 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1725 (cable_length > 0) &&
1726 ((device_tech >> 4) ==
1727 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1728 active_cable = true;
1729 }
1730
1731 if (active_cable) {
1732 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1733 if (hw->bus.lan_id == 0)
1734 hw->phy.sfp_type =
1735 ixgbe_sfp_type_da_act_lmt_core0;
1736 else
1737 hw->phy.sfp_type =
1738 ixgbe_sfp_type_da_act_lmt_core1;
1739 } else {
1740 /* unsupported module type */
1741 hw->phy.type = ixgbe_phy_sfp_unsupported;
1742 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1743 goto out;
1744 }
1745 }
1746
1747 if (hw->phy.sfp_type != stored_sfp_type)
1748 hw->phy.sfp_setup_needed = true;
1749
1750 /* Determine if the QSFP+ PHY is dual speed or not. */
1751 hw->phy.multispeed_fiber = false;
1752 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1753 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1754 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1755 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1756 hw->phy.multispeed_fiber = true;
1757
1758 /* Determine PHY vendor for optical modules */
1759 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1760 IXGBE_SFF_10GBASELR_CAPABLE)) {
1761 status = hw->phy.ops.read_i2c_eeprom(hw,
1762 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1763 &oui_bytes[0]);
1764
1765 if (status != IXGBE_SUCCESS)
1766 goto err_read_i2c_eeprom;
1767
1768 status = hw->phy.ops.read_i2c_eeprom(hw,
1769 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1770 &oui_bytes[1]);
1771
1772 if (status != IXGBE_SUCCESS)
1773 goto err_read_i2c_eeprom;
1774
1775 status = hw->phy.ops.read_i2c_eeprom(hw,
1776 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1777 &oui_bytes[2]);
1778
1779 if (status != IXGBE_SUCCESS)
1780 goto err_read_i2c_eeprom;
1781
1782 vendor_oui =
1783 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1784 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1785 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1786
1787 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1788 hw->phy.type = ixgbe_phy_qsfp_intel;
1789 else
1790 hw->phy.type = ixgbe_phy_qsfp_unknown;
1791
1792 ixgbe_get_device_caps(hw, &enforce_sfp);
1793 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1794 /* Make sure we're a supported PHY type */
1795 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1796 status = IXGBE_SUCCESS;
1797 } else {
1798 if (hw->allow_unsupported_sfp == true) {
1799 EWARN(hw,
1800 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1801 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1802 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1803 status = IXGBE_SUCCESS;
1804 } else {
1805 DEBUGOUT("QSFP module not supported\n");
1806 hw->phy.type =
1807 ixgbe_phy_sfp_unsupported;
1808 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1809 }
1810 }
1811 } else {
1812 status = IXGBE_SUCCESS;
1813 }
1814 }
1815
1816 out:
1817 return status;
1818
1819 err_read_i2c_eeprom:
1820 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1821 hw->phy.id = 0;
1822 hw->phy.type = ixgbe_phy_unknown;
1823
1824 return IXGBE_ERR_SFP_NOT_PRESENT;
1825 }
1826
1827 /**
1828 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1829 * @hw: pointer to hardware structure
1830 * @list_offset: offset to the SFP ID list
1831 * @data_offset: offset to the SFP data block
1832 *
1833 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1834 * so it returns the offsets to the phy init sequence block.
1835 **/
1836 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1837 u16 *list_offset,
1838 u16 *data_offset)
1839 {
1840 u16 sfp_id;
1841 u16 sfp_type = hw->phy.sfp_type;
1842
1843 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1844
1845 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1846 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1847
1848 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1849 return IXGBE_ERR_SFP_NOT_PRESENT;
1850
1851 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1852 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1853 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1854
1855 /*
1856 * Limiting active cables and 1G Phys must be initialized as
1857 * SR modules
1858 */
1859 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1860 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1861 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1862 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1863 sfp_type = ixgbe_sfp_type_srlr_core0;
1864 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1865 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1866 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1867 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1868 sfp_type = ixgbe_sfp_type_srlr_core1;
1869
1870 /* Read offset to PHY init contents */
1871 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1872 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1873 "eeprom read at offset %d failed",
1874 IXGBE_PHY_INIT_OFFSET_NL);
1875 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1876 }
1877
1878 if ((!*list_offset) || (*list_offset == 0xFFFF))
1879 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1880
1881 /* Shift offset to first ID word */
1882 (*list_offset)++;
1883
1884 /*
1885 * Find the matching SFP ID in the EEPROM
1886 * and program the init sequence
1887 */
1888 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1889 goto err_phy;
1890
1891 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1892 if (sfp_id == sfp_type) {
1893 (*list_offset)++;
1894 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1895 goto err_phy;
1896 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1897 DEBUGOUT("SFP+ module not supported\n");
1898 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1899 } else {
1900 break;
1901 }
1902 } else {
1903 (*list_offset) += 2;
1904 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1905 goto err_phy;
1906 }
1907 }
1908
1909 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1910 DEBUGOUT("No matching SFP+ module found\n");
1911 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1912 }
1913
1914 return IXGBE_SUCCESS;
1915
1916 err_phy:
1917 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1918 "eeprom read at offset %d failed", *list_offset);
1919 return IXGBE_ERR_PHY;
1920 }
1921
1922 /**
1923 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1924 * @hw: pointer to hardware structure
1925 * @byte_offset: EEPROM byte offset to read
1926 * @eeprom_data: value read
1927 *
1928 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1929 **/
1930 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1931 u8 *eeprom_data)
1932 {
1933 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1934
1935 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1936 IXGBE_I2C_EEPROM_DEV_ADDR,
1937 eeprom_data);
1938 }
1939
1940 /**
1941 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1942 * @hw: pointer to hardware structure
1943 * @byte_offset: byte offset at address 0xA2
1944 * @eeprom_data: value read
1945 *
1946 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1947 **/
1948 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1949 u8 *sff8472_data)
1950 {
1951 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1952 IXGBE_I2C_EEPROM_DEV_ADDR2,
1953 sff8472_data);
1954 }
1955
1956 /**
1957 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1958 * @hw: pointer to hardware structure
1959 * @byte_offset: EEPROM byte offset to write
1960 * @eeprom_data: value to write
1961 *
1962 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1963 **/
1964 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1965 u8 eeprom_data)
1966 {
1967 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1968
1969 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1970 IXGBE_I2C_EEPROM_DEV_ADDR,
1971 eeprom_data);
1972 }
1973
1974 /**
1975 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1976 * @hw: pointer to hardware structure
1977 * @offset: eeprom offset to be read
1978 * @addr: I2C address to be read
1979 */
1980 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1981 {
1982 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1983 offset == IXGBE_SFF_IDENTIFIER &&
1984 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1985 return true;
1986 return false;
1987 }
1988
1989 /**
1990 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1991 * @hw: pointer to hardware structure
1992 * @byte_offset: byte offset to read
1993 * @data: value read
1994 * @lock: true if to take and release semaphore
1995 *
1996 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1997 * a specified device address.
1998 **/
1999 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2000 u8 dev_addr, u8 *data, bool lock)
2001 {
2002 s32 status;
2003 u32 max_retry = 10;
2004 u32 retry = 0;
2005 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2006 bool nack = 1;
2007 *data = 0;
2008
2009 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2010
2011 if (hw->mac.type >= ixgbe_mac_X550)
2012 max_retry = 3;
2013 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2014 max_retry = IXGBE_SFP_DETECT_RETRIES;
2015
2016 do {
2017 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2018 return IXGBE_ERR_SWFW_SYNC;
2019
2020 ixgbe_i2c_start(hw);
2021
2022 /* Device Address and write indication */
2023 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2024 if (status != IXGBE_SUCCESS)
2025 goto fail;
2026
2027 status = ixgbe_get_i2c_ack(hw);
2028 if (status != IXGBE_SUCCESS)
2029 goto fail;
2030
2031 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2032 if (status != IXGBE_SUCCESS)
2033 goto fail;
2034
2035 status = ixgbe_get_i2c_ack(hw);
2036 if (status != IXGBE_SUCCESS)
2037 goto fail;
2038
2039 ixgbe_i2c_start(hw);
2040
2041 /* Device Address and read indication */
2042 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2043 if (status != IXGBE_SUCCESS)
2044 goto fail;
2045
2046 status = ixgbe_get_i2c_ack(hw);
2047 if (status != IXGBE_SUCCESS)
2048 goto fail;
2049
2050 status = ixgbe_clock_in_i2c_byte(hw, data);
2051 if (status != IXGBE_SUCCESS)
2052 goto fail;
2053
2054 status = ixgbe_clock_out_i2c_bit(hw, nack);
2055 if (status != IXGBE_SUCCESS)
2056 goto fail;
2057
2058 ixgbe_i2c_stop(hw);
2059 if (lock)
2060 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2061 return IXGBE_SUCCESS;
2062
2063 fail:
2064 ixgbe_i2c_bus_clear(hw);
2065 if (lock) {
2066 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2067 msec_delay(100);
2068 }
2069 retry++;
2070 if (retry < max_retry)
2071 DEBUGOUT("I2C byte read error - Retrying.\n");
2072 else
2073 DEBUGOUT("I2C byte read error.\n");
2074
2075 } while (retry < max_retry);
2076
2077 return status;
2078 }
2079
2080 /**
2081 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2082 * @hw: pointer to hardware structure
2083 * @byte_offset: byte offset to read
2084 * @data: value read
2085 *
2086 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2087 * a specified device address.
2088 **/
2089 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2090 u8 dev_addr, u8 *data)
2091 {
2092 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2093 data, true);
2094 }
2095
2096 /**
2097 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2098 * @hw: pointer to hardware structure
2099 * @byte_offset: byte offset to read
2100 * @data: value read
2101 *
2102 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2103 * a specified device address.
2104 **/
2105 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2106 u8 dev_addr, u8 *data)
2107 {
2108 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2109 data, false);
2110 }
2111
2112 /**
2113 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2114 * @hw: pointer to hardware structure
2115 * @byte_offset: byte offset to write
2116 * @data: value to write
2117 * @lock: true if to take and release semaphore
2118 *
2119 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2120 * a specified device address.
2121 **/
2122 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2123 u8 dev_addr, u8 data, bool lock)
2124 {
2125 s32 status;
2126 u32 max_retry = 1;
2127 u32 retry = 0;
2128 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2129
2130 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2131
2132 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2133 IXGBE_SUCCESS)
2134 return IXGBE_ERR_SWFW_SYNC;
2135
2136 do {
2137 ixgbe_i2c_start(hw);
2138
2139 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2140 if (status != IXGBE_SUCCESS)
2141 goto fail;
2142
2143 status = ixgbe_get_i2c_ack(hw);
2144 if (status != IXGBE_SUCCESS)
2145 goto fail;
2146
2147 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2148 if (status != IXGBE_SUCCESS)
2149 goto fail;
2150
2151 status = ixgbe_get_i2c_ack(hw);
2152 if (status != IXGBE_SUCCESS)
2153 goto fail;
2154
2155 status = ixgbe_clock_out_i2c_byte(hw, data);
2156 if (status != IXGBE_SUCCESS)
2157 goto fail;
2158
2159 status = ixgbe_get_i2c_ack(hw);
2160 if (status != IXGBE_SUCCESS)
2161 goto fail;
2162
2163 ixgbe_i2c_stop(hw);
2164 if (lock)
2165 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2166 return IXGBE_SUCCESS;
2167
2168 fail:
2169 ixgbe_i2c_bus_clear(hw);
2170 retry++;
2171 if (retry < max_retry)
2172 DEBUGOUT("I2C byte write error - Retrying.\n");
2173 else
2174 DEBUGOUT("I2C byte write error.\n");
2175 } while (retry < max_retry);
2176
2177 if (lock)
2178 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2179
2180 return status;
2181 }
2182
2183 /**
2184 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2185 * @hw: pointer to hardware structure
2186 * @byte_offset: byte offset to write
2187 * @data: value to write
2188 *
2189 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2190 * a specified device address.
2191 **/
2192 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2193 u8 dev_addr, u8 data)
2194 {
2195 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2196 data, true);
2197 }
2198
2199 /**
2200 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2201 * @hw: pointer to hardware structure
2202 * @byte_offset: byte offset to write
2203 * @data: value to write
2204 *
2205 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2206 * a specified device address.
2207 **/
2208 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2209 u8 dev_addr, u8 data)
2210 {
2211 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2212 data, false);
2213 }
2214
2215 /**
2216 * ixgbe_i2c_start - Sets I2C start condition
2217 * @hw: pointer to hardware structure
2218 *
2219 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2220 * Set bit-bang mode on X550 hardware.
2221 **/
2222 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2223 {
2224 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2225
2226 DEBUGFUNC("ixgbe_i2c_start");
2227
2228 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2229
2230 /* Start condition must begin with data and clock high */
2231 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2232 ixgbe_raise_i2c_clk(hw, &i2cctl);
2233
2234 /* Setup time for start condition (4.7us) */
2235 usec_delay(IXGBE_I2C_T_SU_STA);
2236
2237 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2238
2239 /* Hold time for start condition (4us) */
2240 usec_delay(IXGBE_I2C_T_HD_STA);
2241
2242 ixgbe_lower_i2c_clk(hw, &i2cctl);
2243
2244 /* Minimum low period of clock is 4.7 us */
2245 usec_delay(IXGBE_I2C_T_LOW);
2246
2247 }
2248
2249 /**
2250 * ixgbe_i2c_stop - Sets I2C stop condition
2251 * @hw: pointer to hardware structure
2252 *
2253 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2254 * Disables bit-bang mode and negates data output enable on X550
2255 * hardware.
2256 **/
2257 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2258 {
2259 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2260 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2261 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2262 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2263
2264 DEBUGFUNC("ixgbe_i2c_stop");
2265
2266 /* Stop condition must begin with data low and clock high */
2267 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2268 ixgbe_raise_i2c_clk(hw, &i2cctl);
2269
2270 /* Setup time for stop condition (4us) */
2271 usec_delay(IXGBE_I2C_T_SU_STO);
2272
2273 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2274
2275 /* bus free time between stop and start (4.7us)*/
2276 usec_delay(IXGBE_I2C_T_BUF);
2277
2278 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2279 i2cctl &= ~bb_en_bit;
2280 i2cctl |= data_oe_bit | clk_oe_bit;
2281 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2282 IXGBE_WRITE_FLUSH(hw);
2283 }
2284 }
2285
2286 /**
2287 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2288 * @hw: pointer to hardware structure
2289 * @data: data byte to clock in
2290 *
2291 * Clocks in one byte data via I2C data/clock
2292 **/
2293 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2294 {
2295 s32 i;
2296 bool bit = 0;
2297
2298 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2299
2300 *data = 0;
2301 for (i = 7; i >= 0; i--) {
2302 ixgbe_clock_in_i2c_bit(hw, &bit);
2303 *data |= bit << i;
2304 }
2305
2306 return IXGBE_SUCCESS;
2307 }
2308
2309 /**
2310 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2311 * @hw: pointer to hardware structure
2312 * @data: data byte clocked out
2313 *
2314 * Clocks out one byte data via I2C data/clock
2315 **/
2316 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2317 {
2318 s32 status = IXGBE_SUCCESS;
2319 s32 i;
2320 u32 i2cctl;
2321 bool bit;
2322
2323 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2324
2325 for (i = 7; i >= 0; i--) {
2326 bit = (data >> i) & 0x1;
2327 status = ixgbe_clock_out_i2c_bit(hw, bit);
2328
2329 if (status != IXGBE_SUCCESS)
2330 break;
2331 }
2332
2333 /* Release SDA line (set high) */
2334 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2335 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2336 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2337 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2338 IXGBE_WRITE_FLUSH(hw);
2339
2340 return status;
2341 }
2342
2343 /**
2344 * ixgbe_get_i2c_ack - Polls for I2C ACK
2345 * @hw: pointer to hardware structure
2346 *
2347 * Clocks in/out one bit via I2C data/clock
2348 **/
2349 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2350 {
2351 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2352 s32 status = IXGBE_SUCCESS;
2353 u32 i = 0;
2354 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2355 u32 timeout = 10;
2356 bool ack = 1;
2357
2358 DEBUGFUNC("ixgbe_get_i2c_ack");
2359
2360 if (data_oe_bit) {
2361 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2362 i2cctl |= data_oe_bit;
2363 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2364 IXGBE_WRITE_FLUSH(hw);
2365 }
2366 ixgbe_raise_i2c_clk(hw, &i2cctl);
2367
2368 /* Minimum high period of clock is 4us */
2369 usec_delay(IXGBE_I2C_T_HIGH);
2370
2371 /* Poll for ACK. Note that ACK in I2C spec is
2372 * transition from 1 to 0 */
2373 for (i = 0; i < timeout; i++) {
2374 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2375 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2376
2377 usec_delay(1);
2378 if (!ack)
2379 break;
2380 }
2381
2382 if (ack) {
2383 DEBUGOUT("I2C ack was not received.\n");
2384 status = IXGBE_ERR_I2C;
2385 }
2386
2387 ixgbe_lower_i2c_clk(hw, &i2cctl);
2388
2389 /* Minimum low period of clock is 4.7 us */
2390 usec_delay(IXGBE_I2C_T_LOW);
2391
2392 return status;
2393 }
2394
2395 /**
2396 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2397 * @hw: pointer to hardware structure
2398 * @data: read data value
2399 *
2400 * Clocks in one bit via I2C data/clock
2401 **/
2402 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2403 {
2404 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2405 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2406
2407 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2408
2409 if (data_oe_bit) {
2410 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2411 i2cctl |= data_oe_bit;
2412 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2413 IXGBE_WRITE_FLUSH(hw);
2414 }
2415 ixgbe_raise_i2c_clk(hw, &i2cctl);
2416
2417 /* Minimum high period of clock is 4us */
2418 usec_delay(IXGBE_I2C_T_HIGH);
2419
2420 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2421 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2422
2423 ixgbe_lower_i2c_clk(hw, &i2cctl);
2424
2425 /* Minimum low period of clock is 4.7 us */
2426 usec_delay(IXGBE_I2C_T_LOW);
2427
2428 return IXGBE_SUCCESS;
2429 }
2430
2431 /**
2432 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2433 * @hw: pointer to hardware structure
2434 * @data: data value to write
2435 *
2436 * Clocks out one bit via I2C data/clock
2437 **/
2438 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2439 {
2440 s32 status;
2441 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2442
2443 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2444
2445 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2446 if (status == IXGBE_SUCCESS) {
2447 ixgbe_raise_i2c_clk(hw, &i2cctl);
2448
2449 /* Minimum high period of clock is 4us */
2450 usec_delay(IXGBE_I2C_T_HIGH);
2451
2452 ixgbe_lower_i2c_clk(hw, &i2cctl);
2453
2454 /* Minimum low period of clock is 4.7 us.
2455 * This also takes care of the data hold time.
2456 */
2457 usec_delay(IXGBE_I2C_T_LOW);
2458 } else {
2459 status = IXGBE_ERR_I2C;
2460 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2461 "I2C data was not set to %X\n", data);
2462 }
2463
2464 return status;
2465 }
2466
2467 /**
2468 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2469 * @hw: pointer to hardware structure
2470 * @i2cctl: Current value of I2CCTL register
2471 *
2472 * Raises the I2C clock line '0'->'1'
2473 * Negates the I2C clock output enable on X550 hardware.
2474 **/
2475 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2476 {
2477 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2478 u32 i = 0;
2479 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2480 u32 i2cctl_r = 0;
2481
2482 DEBUGFUNC("ixgbe_raise_i2c_clk");
2483
2484 if (clk_oe_bit) {
2485 *i2cctl |= clk_oe_bit;
2486 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2487 }
2488
2489 for (i = 0; i < timeout; i++) {
2490 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2491
2492 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2493 IXGBE_WRITE_FLUSH(hw);
2494 /* SCL rise time (1000ns) */
2495 usec_delay(IXGBE_I2C_T_RISE);
2496
2497 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2498 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2499 break;
2500 }
2501 }
2502
2503 /**
2504 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2505 * @hw: pointer to hardware structure
2506 * @i2cctl: Current value of I2CCTL register
2507 *
2508 * Lowers the I2C clock line '1'->'0'
2509 * Asserts the I2C clock output enable on X550 hardware.
2510 **/
2511 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2512 {
2513 DEBUGFUNC("ixgbe_lower_i2c_clk");
2514
2515 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2516 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2517
2518 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2519 IXGBE_WRITE_FLUSH(hw);
2520
2521 /* SCL fall time (300ns) */
2522 usec_delay(IXGBE_I2C_T_FALL);
2523 }
2524
2525 /**
2526 * ixgbe_set_i2c_data - Sets the I2C data bit
2527 * @hw: pointer to hardware structure
2528 * @i2cctl: Current value of I2CCTL register
2529 * @data: I2C data value (0 or 1) to set
2530 *
2531 * Sets the I2C data bit
2532 * Asserts the I2C data output enable on X550 hardware.
2533 **/
2534 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2535 {
2536 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2537 s32 status = IXGBE_SUCCESS;
2538
2539 DEBUGFUNC("ixgbe_set_i2c_data");
2540
2541 if (data)
2542 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2543 else
2544 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2545 *i2cctl &= ~data_oe_bit;
2546
2547 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2548 IXGBE_WRITE_FLUSH(hw);
2549
2550 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2551 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2552
2553 if (!data) /* Can't verify data in this case */
2554 return IXGBE_SUCCESS;
2555 if (data_oe_bit) {
2556 *i2cctl |= data_oe_bit;
2557 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2558 IXGBE_WRITE_FLUSH(hw);
2559 }
2560
2561 /* Verify data was set correctly */
2562 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2563 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2564 status = IXGBE_ERR_I2C;
2565 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2566 "Error - I2C data was not set to %X.\n",
2567 data);
2568 }
2569
2570 return status;
2571 }
2572
2573 /**
2574 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2575 * @hw: pointer to hardware structure
2576 * @i2cctl: Current value of I2CCTL register
2577 *
2578 * Returns the I2C data bit value
2579 * Negates the I2C data output enable on X550 hardware.
2580 **/
2581 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2582 {
2583 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2584 bool data;
2585
2586 DEBUGFUNC("ixgbe_get_i2c_data");
2587
2588 if (data_oe_bit) {
2589 *i2cctl |= data_oe_bit;
2590 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2591 IXGBE_WRITE_FLUSH(hw);
2592 usec_delay(IXGBE_I2C_T_FALL);
2593 }
2594
2595 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2596 data = 1;
2597 else
2598 data = 0;
2599
2600 return data;
2601 }
2602
2603 /**
2604 * ixgbe_i2c_bus_clear - Clears the I2C bus
2605 * @hw: pointer to hardware structure
2606 *
2607 * Clears the I2C bus by sending nine clock pulses.
2608 * Used when data line is stuck low.
2609 **/
2610 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2611 {
2612 u32 i2cctl;
2613 u32 i;
2614
2615 DEBUGFUNC("ixgbe_i2c_bus_clear");
2616
2617 ixgbe_i2c_start(hw);
2618 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2619
2620 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2621
2622 for (i = 0; i < 9; i++) {
2623 ixgbe_raise_i2c_clk(hw, &i2cctl);
2624
2625 /* Min high period of clock is 4us */
2626 usec_delay(IXGBE_I2C_T_HIGH);
2627
2628 ixgbe_lower_i2c_clk(hw, &i2cctl);
2629
2630 /* Min low period of clock is 4.7us*/
2631 usec_delay(IXGBE_I2C_T_LOW);
2632 }
2633
2634 ixgbe_i2c_start(hw);
2635
2636 /* Put the i2c bus back to default state */
2637 ixgbe_i2c_stop(hw);
2638 }
2639
2640 /**
2641 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2642 * @hw: pointer to hardware structure
2643 *
2644 * Checks if the LASI temp alarm status was triggered due to overtemp
2645 **/
2646 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2647 {
2648 s32 status = IXGBE_SUCCESS;
2649 u16 phy_data = 0;
2650
2651 DEBUGFUNC("ixgbe_tn_check_overtemp");
2652
2653 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2654 goto out;
2655
2656 /* Check that the LASI temp alarm status was triggered */
2657 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2658 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2659
2660 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2661 goto out;
2662
2663 status = IXGBE_ERR_OVERTEMP;
2664 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2665 out:
2666 return status;
2667 }
2668
2669 /**
2670 * ixgbe_set_copper_phy_power - Control power for copper phy
2671 * @hw: pointer to hardware structure
2672 * @on: true for on, false for off
2673 */
2674 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2675 {
2676 u32 status;
2677 u16 reg;
2678
2679 if (!on && ixgbe_mng_present(hw))
2680 return 0;
2681
2682 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2683 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2684 &reg);
2685 if (status)
2686 return status;
2687
2688 if (on) {
2689 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2690 } else {
2691 if (ixgbe_check_reset_blocked(hw))
2692 return 0;
2693 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2694 }
2695
2696 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2697 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2698 reg);
2699 return status;
2700 }
Ceph