ceph/src/seastar/dpdk/drivers/net/ixgbe/base/ixgbe_type.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #ifndef _IXGBE_TYPE_H_
   6 #define _IXGBE_TYPE_H_
   7
   8 /*
   9  * The following is a brief description of the error categories used by the
  10  * ERROR_REPORT* macros.
  11  *
  12  * - IXGBE_ERROR_INVALID_STATE
  13  * This category is for errors which represent a serious failure state that is
  14  * unexpected, and could be potentially harmful to device operation. It should
  15  * not be used for errors relating to issues that can be worked around or
  16  * ignored.
  17  *
  18  * - IXGBE_ERROR_POLLING
  19  * This category is for errors related to polling/timeout issues and should be
  20  * used in any case where the timeout occurred, or a failure to obtain a lock,
  21  * or failure to receive data within the time limit.
  22  *
  23  * - IXGBE_ERROR_CAUTION
  24  * This category should be used for reporting issues that may be the cause of
  25  * other errors, such as temperature warnings. It should indicate an event which
  26  * could be serious, but hasn't necessarily caused problems yet.
  27  *
  28  * - IXGBE_ERROR_SOFTWARE
  29  * This category is intended for errors due to software state preventing
  30  * something. The category is not intended for errors due to bad arguments, or
  31  * due to unsupported features. It should be used when a state occurs which
  32  * prevents action but is not a serious issue.
  33  *
  34  * - IXGBE_ERROR_ARGUMENT
  35  * This category is for when a bad or invalid argument is passed. It should be
  36  * used whenever a function is called and error checking has detected the
  37  * argument is wrong or incorrect.
  38  *
  39  * - IXGBE_ERROR_UNSUPPORTED
  40  * This category is for errors which are due to unsupported circumstances or
  41  * configuration issues. It should not be used when the issue is due to an
  42  * invalid argument, but for when something has occurred that is unsupported
  43  * (Ex: Flow control autonegotiation or an unsupported SFP+ module.)
  44  */
  45
  46 #include "ixgbe_osdep.h"
  47
  48 /* Override this by setting IOMEM in your ixgbe_osdep.h header */
  49
  50 /* Vendor ID */
  51 #define IXGBE_INTEL_VENDOR_ID                   0x8086
  52
  53 /* Device IDs */
  54 #define IXGBE_DEV_ID_82598                      0x10B6
  55 #define IXGBE_DEV_ID_82598_BX                   0x1508
  56 #define IXGBE_DEV_ID_82598AF_DUAL_PORT          0x10C6
  57 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT        0x10C7
  58 #define IXGBE_DEV_ID_82598AT                    0x10C8
  59 #define IXGBE_DEV_ID_82598AT2                   0x150B
  60 #define IXGBE_DEV_ID_82598EB_SFP_LOM            0x10DB
  61 #define IXGBE_DEV_ID_82598EB_CX4                0x10DD
  62 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT        0x10EC
  63 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT         0x10F1
  64 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM      0x10E1
  65 #define IXGBE_DEV_ID_82598EB_XF_LR              0x10F4
  66 #define IXGBE_DEV_ID_82599_KX4                  0x10F7
  67 #define IXGBE_DEV_ID_82599_KX4_MEZZ             0x1514
  68 #define IXGBE_DEV_ID_82599_KR                   0x1517
  69 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE      0x10F8
  70 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ       0x000C
  71 #define IXGBE_DEV_ID_82599_CX4                  0x10F9
  72 #define IXGBE_DEV_ID_82599_SFP                  0x10FB
  73 #define IXGBE_SUBDEV_ID_82599_SFP               0x11A9
  74 #define IXGBE_SUBDEV_ID_82599_SFP_WOL0          0x1071
  75 #define IXGBE_SUBDEV_ID_82599_RNDC              0x1F72
  76 #define IXGBE_SUBDEV_ID_82599_560FLR            0x17D0
  77 #define IXGBE_SUBDEV_ID_82599_ECNA_DP           0x0470
  78 #define IXGBE_SUBDEV_ID_82599_SP_560FLR         0x211B
  79 #define IXGBE_SUBDEV_ID_82599_LOM_SNAP6         0x2159
  80 #define IXGBE_SUBDEV_ID_82599_SFP_1OCP          0x000D
  81 #define IXGBE_SUBDEV_ID_82599_SFP_2OCP          0x0008
  82 #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1      0x8976
  83 #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2      0x06EE
  84 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE       0x152A
  85 #define IXGBE_DEV_ID_82599_SFP_FCOE             0x1529
  86 #define IXGBE_DEV_ID_82599_SFP_EM               0x1507
  87 #define IXGBE_DEV_ID_82599_SFP_SF2              0x154D
  88 #define IXGBE_DEV_ID_82599_SFP_SF_QP            0x154A
  89 #define IXGBE_DEV_ID_82599_QSFP_SF_QP           0x1558
  90 #define IXGBE_DEV_ID_82599EN_SFP                0x1557
  91 #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1        0x0001
  92 #define IXGBE_DEV_ID_82599_XAUI_LOM             0x10FC
  93 #define IXGBE_DEV_ID_82599_T3_LOM               0x151C
  94 #define IXGBE_DEV_ID_82599_VF                   0x10ED
  95 #define IXGBE_DEV_ID_82599_VF_HV                0x152E
  96 #define IXGBE_DEV_ID_X540T                      0x1528
  97 #define IXGBE_DEV_ID_X540_VF                    0x1515
  98 #define IXGBE_DEV_ID_X540_VF_HV                 0x1530
  99 #define IXGBE_DEV_ID_X540T1                     0x1560
 100 #define IXGBE_DEV_ID_X550T                      0x1563
 101 #define IXGBE_DEV_ID_X550T1                     0x15D1
 102 /* Placeholder value, pending official value. */
 103 #define IXGBE_DEV_ID_X550EM_A_KR                0x15C2
 104 #define IXGBE_DEV_ID_X550EM_A_KR_L              0x15C3
 105 #define IXGBE_DEV_ID_X550EM_A_SFP_N             0x15C4
 106 #define IXGBE_DEV_ID_X550EM_A_SGMII             0x15C6
 107 #define IXGBE_DEV_ID_X550EM_A_SGMII_L           0x15C7
 108 #define IXGBE_DEV_ID_X550EM_A_10G_T             0x15C8
 109 #define IXGBE_DEV_ID_X550EM_A_QSFP              0x15CA
 110 #define IXGBE_DEV_ID_X550EM_A_QSFP_N            0x15CC
 111 #define IXGBE_DEV_ID_X550EM_A_SFP               0x15CE
 112 #define IXGBE_DEV_ID_X550EM_A_1G_T              0x15E4
 113 #define IXGBE_DEV_ID_X550EM_A_1G_T_L            0x15E5
 114 #define IXGBE_DEV_ID_X550EM_X_KX4               0x15AA
 115 #define IXGBE_DEV_ID_X550EM_X_KR                0x15AB
 116 #define IXGBE_DEV_ID_X550EM_X_SFP               0x15AC
 117 #define IXGBE_DEV_ID_X550EM_X_10G_T             0x15AD
 118 #define IXGBE_DEV_ID_X550EM_X_1G_T              0x15AE
 119 #define IXGBE_DEV_ID_X550EM_X_XFI               0x15B0
 120 #define IXGBE_DEV_ID_X550_VF_HV                 0x1564
 121 #define IXGBE_DEV_ID_X550_VF                    0x1565
 122 #define IXGBE_DEV_ID_X550EM_A_VF                0x15C5
 123 #define IXGBE_DEV_ID_X550EM_A_VF_HV             0x15B4
 124 #define IXGBE_DEV_ID_X550EM_X_VF                0x15A8
 125 #define IXGBE_DEV_ID_X550EM_X_VF_HV             0x15A9
 126
 127 #define IXGBE_CAT(r, m) IXGBE_##r##m
 128
 129 #define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)])
 130
 131 /* General Registers */
 132 #define IXGBE_CTRL              0x00000
 133 #define IXGBE_STATUS            0x00008
 134 #define IXGBE_CTRL_EXT          0x00018
 135 #define IXGBE_ESDP              0x00020
 136 #define IXGBE_EODSDP            0x00028
 137 #define IXGBE_I2CCTL_82599      0x00028
 138 #define IXGBE_I2CCTL            IXGBE_I2CCTL_82599
 139 #define IXGBE_I2CCTL_X540       IXGBE_I2CCTL_82599
 140 #define IXGBE_I2CCTL_X550       0x15F5C
 141 #define IXGBE_I2CCTL_X550EM_x   IXGBE_I2CCTL_X550
 142 #define IXGBE_I2CCTL_X550EM_a   IXGBE_I2CCTL_X550
 143 #define IXGBE_I2CCTL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2CCTL)
 144 #define IXGBE_PHY_GPIO          0x00028
 145 #define IXGBE_MAC_GPIO          0x00030
 146 #define IXGBE_PHYINT_STATUS0    0x00100
 147 #define IXGBE_PHYINT_STATUS1    0x00104
 148 #define IXGBE_PHYINT_STATUS2    0x00108
 149 #define IXGBE_LEDCTL            0x00200
 150 #define IXGBE_FRTIMER           0x00048
 151 #define IXGBE_TCPTIMER          0x0004C
 152 #define IXGBE_CORESPARE         0x00600
 153 #define IXGBE_EXVET             0x05078
 154
 155 /* NVM Registers */
 156 #define IXGBE_EEC               0x10010
 157 #define IXGBE_EEC_X540          IXGBE_EEC
 158 #define IXGBE_EEC_X550          IXGBE_EEC
 159 #define IXGBE_EEC_X550EM_x      IXGBE_EEC
 160 #define IXGBE_EEC_X550EM_a      0x15FF8
 161 #define IXGBE_EEC_BY_MAC(_hw)   IXGBE_BY_MAC((_hw), EEC)
 162
 163 #define IXGBE_EERD              0x10014
 164 #define IXGBE_EEWR              0x10018
 165
 166 #define IXGBE_FLA               0x1001C
 167 #define IXGBE_FLA_X540          IXGBE_FLA
 168 #define IXGBE_FLA_X550          IXGBE_FLA
 169 #define IXGBE_FLA_X550EM_x      IXGBE_FLA
 170 #define IXGBE_FLA_X550EM_a      0x15F68
 171 #define IXGBE_FLA_BY_MAC(_hw)   IXGBE_BY_MAC((_hw), FLA)
 172
 173 #define IXGBE_EEMNGCTL  0x10110
 174 #define IXGBE_EEMNGDATA 0x10114
 175 #define IXGBE_FLMNGCTL  0x10118
 176 #define IXGBE_FLMNGDATA 0x1011C
 177 #define IXGBE_FLMNGCNT  0x10120
 178 #define IXGBE_FLOP      0x1013C
 179
 180 #define IXGBE_GRC               0x10200
 181 #define IXGBE_GRC_X540          IXGBE_GRC
 182 #define IXGBE_GRC_X550          IXGBE_GRC
 183 #define IXGBE_GRC_X550EM_x      IXGBE_GRC
 184 #define IXGBE_GRC_X550EM_a      0x15F64
 185 #define IXGBE_GRC_BY_MAC(_hw)   IXGBE_BY_MAC((_hw), GRC)
 186
 187 #define IXGBE_SRAMREL           0x10210
 188 #define IXGBE_SRAMREL_X540      IXGBE_SRAMREL
 189 #define IXGBE_SRAMREL_X550      IXGBE_SRAMREL
 190 #define IXGBE_SRAMREL_X550EM_x  IXGBE_SRAMREL
 191 #define IXGBE_SRAMREL_X550EM_a  0x15F6C
 192 #define IXGBE_SRAMREL_BY_MAC(_hw)       IXGBE_BY_MAC((_hw), SRAMREL)
 193
 194 #define IXGBE_PHYDBG    0x10218
 195
 196 /* General Receive Control */
 197 #define IXGBE_GRC_MNG   0x00000001 /* Manageability Enable */
 198 #define IXGBE_GRC_APME  0x00000002 /* APM enabled in EEPROM */
 199
 200 #define IXGBE_VPDDIAG0  0x10204
 201 #define IXGBE_VPDDIAG1  0x10208
 202
 203 /* I2CCTL Bit Masks */
 204 #define IXGBE_I2C_CLK_IN                0x00000001
 205 #define IXGBE_I2C_CLK_IN_X540           IXGBE_I2C_CLK_IN
 206 #define IXGBE_I2C_CLK_IN_X550           0x00004000
 207 #define IXGBE_I2C_CLK_IN_X550EM_x       IXGBE_I2C_CLK_IN_X550
 208 #define IXGBE_I2C_CLK_IN_X550EM_a       IXGBE_I2C_CLK_IN_X550
 209 #define IXGBE_I2C_CLK_IN_BY_MAC(_hw)    IXGBE_BY_MAC((_hw), I2C_CLK_IN)
 210
 211 #define IXGBE_I2C_CLK_OUT               0x00000002
 212 #define IXGBE_I2C_CLK_OUT_X540          IXGBE_I2C_CLK_OUT
 213 #define IXGBE_I2C_CLK_OUT_X550          0x00000200
 214 #define IXGBE_I2C_CLK_OUT_X550EM_x      IXGBE_I2C_CLK_OUT_X550
 215 #define IXGBE_I2C_CLK_OUT_X550EM_a      IXGBE_I2C_CLK_OUT_X550
 216 #define IXGBE_I2C_CLK_OUT_BY_MAC(_hw)   IXGBE_BY_MAC((_hw), I2C_CLK_OUT)
 217
 218 #define IXGBE_I2C_DATA_IN               0x00000004
 219 #define IXGBE_I2C_DATA_IN_X540          IXGBE_I2C_DATA_IN
 220 #define IXGBE_I2C_DATA_IN_X550          0x00001000
 221 #define IXGBE_I2C_DATA_IN_X550EM_x      IXGBE_I2C_DATA_IN_X550
 222 #define IXGBE_I2C_DATA_IN_X550EM_a      IXGBE_I2C_DATA_IN_X550
 223 #define IXGBE_I2C_DATA_IN_BY_MAC(_hw)   IXGBE_BY_MAC((_hw), I2C_DATA_IN)
 224
 225 #define IXGBE_I2C_DATA_OUT              0x00000008
 226 #define IXGBE_I2C_DATA_OUT_X540         IXGBE_I2C_DATA_OUT
 227 #define IXGBE_I2C_DATA_OUT_X550         0x00000400
 228 #define IXGBE_I2C_DATA_OUT_X550EM_x     IXGBE_I2C_DATA_OUT_X550
 229 #define IXGBE_I2C_DATA_OUT_X550EM_a     IXGBE_I2C_DATA_OUT_X550
 230 #define IXGBE_I2C_DATA_OUT_BY_MAC(_hw)  IXGBE_BY_MAC((_hw), I2C_DATA_OUT)
 231
 232 #define IXGBE_I2C_DATA_OE_N_EN          0
 233 #define IXGBE_I2C_DATA_OE_N_EN_X540     IXGBE_I2C_DATA_OE_N_EN
 234 #define IXGBE_I2C_DATA_OE_N_EN_X550     0x00000800
 235 #define IXGBE_I2C_DATA_OE_N_EN_X550EM_x IXGBE_I2C_DATA_OE_N_EN_X550
 236 #define IXGBE_I2C_DATA_OE_N_EN_X550EM_a IXGBE_I2C_DATA_OE_N_EN_X550
 237 #define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN)
 238
 239 #define IXGBE_I2C_BB_EN                 0
 240 #define IXGBE_I2C_BB_EN_X540            IXGBE_I2C_BB_EN
 241 #define IXGBE_I2C_BB_EN_X550            0x00000100
 242 #define IXGBE_I2C_BB_EN_X550EM_x        IXGBE_I2C_BB_EN_X550
 243 #define IXGBE_I2C_BB_EN_X550EM_a        IXGBE_I2C_BB_EN_X550
 244 #define IXGBE_I2C_BB_EN_BY_MAC(_hw)     IXGBE_BY_MAC((_hw), I2C_BB_EN)
 245
 246 #define IXGBE_I2C_CLK_OE_N_EN           0
 247 #define IXGBE_I2C_CLK_OE_N_EN_X540      IXGBE_I2C_CLK_OE_N_EN
 248 #define IXGBE_I2C_CLK_OE_N_EN_X550      0x00002000
 249 #define IXGBE_I2C_CLK_OE_N_EN_X550EM_x  IXGBE_I2C_CLK_OE_N_EN_X550
 250 #define IXGBE_I2C_CLK_OE_N_EN_X550EM_a  IXGBE_I2C_CLK_OE_N_EN_X550
 251 #define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN)
 252 #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT      500
 253
 254 #define IXGBE_I2C_THERMAL_SENSOR_ADDR   0xF8
 255 #define IXGBE_EMC_INTERNAL_DATA         0x00
 256 #define IXGBE_EMC_INTERNAL_THERM_LIMIT  0x20
 257 #define IXGBE_EMC_DIODE1_DATA           0x01
 258 #define IXGBE_EMC_DIODE1_THERM_LIMIT    0x19
 259 #define IXGBE_EMC_DIODE2_DATA           0x23
 260 #define IXGBE_EMC_DIODE2_THERM_LIMIT    0x1A
 261
 262 #define IXGBE_MAX_SENSORS               3
 263
 264 struct ixgbe_thermal_diode_data {
 265         u8 location;
 266         u8 temp;
 267         u8 caution_thresh;
 268         u8 max_op_thresh;
 269 };
 270
 271 struct ixgbe_thermal_sensor_data {
 272         struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS];
 273 };
 274
 275
 276 #define NVM_OROM_OFFSET         0x17
 277 #define NVM_OROM_BLK_LOW        0x83
 278 #define NVM_OROM_BLK_HI         0x84
 279 #define NVM_OROM_PATCH_MASK     0xFF
 280 #define NVM_OROM_SHIFT          8
 281
 282 #define NVM_VER_MASK            0x00FF /* version mask */
 283 #define NVM_VER_SHIFT           8     /* version bit shift */
 284 #define NVM_OEM_PROD_VER_PTR    0x1B  /* OEM Product version block pointer */
 285 #define NVM_OEM_PROD_VER_CAP_OFF 0x1  /* OEM Product version format offset */
 286 #define NVM_OEM_PROD_VER_OFF_L  0x2   /* OEM Product version offset low */
 287 #define NVM_OEM_PROD_VER_OFF_H  0x3   /* OEM Product version offset high */
 288 #define NVM_OEM_PROD_VER_CAP_MASK 0xF /* OEM Product version cap mask */
 289 #define NVM_OEM_PROD_VER_MOD_LEN 0x3  /* OEM Product version module length */
 290 #define NVM_ETK_OFF_LOW         0x2D  /* version low order word */
 291 #define NVM_ETK_OFF_HI          0x2E  /* version high order word */
 292 #define NVM_ETK_SHIFT           16    /* high version word shift */
 293 #define NVM_VER_INVALID         0xFFFF
 294 #define NVM_ETK_VALID           0x8000
 295 #define NVM_INVALID_PTR         0xFFFF
 296 #define NVM_VER_SIZE            32    /* version sting size */
 297
 298 struct ixgbe_nvm_version {
 299         u32 etk_id;
 300         u8  nvm_major;
 301         u16 nvm_minor;
 302         u8  nvm_id;
 303
 304         bool oem_valid;
 305         u8   oem_major;
 306         u8   oem_minor;
 307         u16  oem_release;
 308
 309         bool or_valid;
 310         u8  or_major;
 311         u16 or_build;
 312         u8  or_patch;
 313
 314 };
 315
 316 /* Interrupt Registers */
 317 #define IXGBE_EICR              0x00800
 318 #define IXGBE_EICS              0x00808
 319 #define IXGBE_EIMS              0x00880
 320 #define IXGBE_EIMC              0x00888
 321 #define IXGBE_EIAC              0x00810
 322 #define IXGBE_EIAM              0x00890
 323 #define IXGBE_EICS_EX(_i)       (0x00A90 + (_i) * 4)
 324 #define IXGBE_EIMS_EX(_i)       (0x00AA0 + (_i) * 4)
 325 #define IXGBE_EIMC_EX(_i)       (0x00AB0 + (_i) * 4)
 326 #define IXGBE_EIAM_EX(_i)       (0x00AD0 + (_i) * 4)
 327 /* 82599 EITR is only 12 bits, with the lower 3 always zero */
 328 /*
 329  * 82598 EITR is 16 bits but set the limits based on the max
 330  * supported by all ixgbe hardware
 331  */
 332 #define IXGBE_MAX_INT_RATE      488281
 333 #define IXGBE_MIN_INT_RATE      956
 334 #define IXGBE_MAX_EITR          0x00000FF8
 335 #define IXGBE_MIN_EITR          8
 336 #define IXGBE_EITR(_i)          (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
 337                                  (0x012300 + (((_i) - 24) * 4)))
 338 #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
 339 #define IXGBE_EITR_LLI_MOD      0x00008000
 340 #define IXGBE_EITR_CNT_WDIS     0x80000000
 341 #define IXGBE_IVAR(_i)          (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
 342 #define IXGBE_IVAR_MISC         0x00A00 /* misc MSI-X interrupt causes */
 343 #define IXGBE_EITRSEL           0x00894
 344 #define IXGBE_MSIXT             0x00000 /* MSI-X Table. 0x0000 - 0x01C */
 345 #define IXGBE_MSIXPBA           0x02000 /* MSI-X Pending bit array */
 346 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
 347 #define IXGBE_GPIE              0x00898
 348
 349 /* Flow Control Registers */
 350 #define IXGBE_FCADBUL           0x03210
 351 #define IXGBE_FCADBUH           0x03214
 352 #define IXGBE_FCAMACL           0x04328
 353 #define IXGBE_FCAMACH           0x0432C
 354 #define IXGBE_FCRTH_82599(_i)   (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
 355 #define IXGBE_FCRTL_82599(_i)   (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
 356 #define IXGBE_PFCTOP            0x03008
 357 #define IXGBE_FCTTV(_i)         (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
 358 #define IXGBE_FCRTL(_i)         (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
 359 #define IXGBE_FCRTH(_i)         (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
 360 #define IXGBE_FCRTV             0x032A0
 361 #define IXGBE_FCCFG             0x03D00
 362 #define IXGBE_TFCS              0x0CE00
 363
 364 /* Receive DMA Registers */
 365 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
 366                          (0x0D000 + (((_i) - 64) * 0x40)))
 367 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
 368                          (0x0D004 + (((_i) - 64) * 0x40)))
 369 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
 370                          (0x0D008 + (((_i) - 64) * 0x40)))
 371 #define IXGBE_RDH(_i)   (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
 372                          (0x0D010 + (((_i) - 64) * 0x40)))
 373 #define IXGBE_RDT(_i)   (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
 374                          (0x0D018 + (((_i) - 64) * 0x40)))
 375 #define IXGBE_RXDCTL(_i)        (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
 376                                  (0x0D028 + (((_i) - 64) * 0x40)))
 377 #define IXGBE_RSCCTL(_i)        (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
 378                                  (0x0D02C + (((_i) - 64) * 0x40)))
 379 #define IXGBE_RSCDBU    0x03028
 380 #define IXGBE_RDDCC     0x02F20
 381 #define IXGBE_RXMEMWRAP 0x03190
 382 #define IXGBE_STARCTRL  0x03024
 383 /*
 384  * Split and Replication Receive Control Registers
 385  * 00-15 : 0x02100 + n*4
 386  * 16-64 : 0x01014 + n*0x40
 387  * 64-127: 0x0D014 + (n-64)*0x40
 388  */
 389 #define IXGBE_SRRCTL(_i)        (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
 390                                  (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
 391                                  (0x0D014 + (((_i) - 64) * 0x40))))
 392 /*
 393  * Rx DCA Control Register:
 394  * 00-15 : 0x02200 + n*4
 395  * 16-64 : 0x0100C + n*0x40
 396  * 64-127: 0x0D00C + (n-64)*0x40
 397  */
 398 #define IXGBE_DCA_RXCTRL(_i)    (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
 399                                  (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
 400                                  (0x0D00C + (((_i) - 64) * 0x40))))
 401 #define IXGBE_RDRXCTL           0x02F00
 402 /* 8 of these 0x03C00 - 0x03C1C */
 403 #define IXGBE_RXPBSIZE(_i)      (0x03C00 + ((_i) * 4))
 404 #define IXGBE_RXCTRL            0x03000
 405 #define IXGBE_DROPEN            0x03D04
 406 #define IXGBE_RXPBSIZE_SHIFT    10
 407 #define IXGBE_RXPBSIZE_MASK     0x000FFC00
 408
 409 /* Receive Registers */
 410 #define IXGBE_RXCSUM            0x05000
 411 #define IXGBE_RFCTL             0x05008
 412 #define IXGBE_DRECCCTL          0x02F08
 413 #define IXGBE_DRECCCTL_DISABLE  0
 414 #define IXGBE_DRECCCTL2         0x02F8C
 415
 416 /* Multicast Table Array - 128 entries */
 417 #define IXGBE_MTA(_i)           (0x05200 + ((_i) * 4))
 418 #define IXGBE_RAL(_i)           (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
 419                                  (0x0A200 + ((_i) * 8)))
 420 #define IXGBE_RAH(_i)           (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
 421                                  (0x0A204 + ((_i) * 8)))
 422 #define IXGBE_MPSAR_LO(_i)      (0x0A600 + ((_i) * 8))
 423 #define IXGBE_MPSAR_HI(_i)      (0x0A604 + ((_i) * 8))
 424 /* Packet split receive type */
 425 #define IXGBE_PSRTYPE(_i)       (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
 426                                  (0x0EA00 + ((_i) * 4)))
 427 /* array of 4096 1-bit vlan filters */
 428 #define IXGBE_VFTA(_i)          (0x0A000 + ((_i) * 4))
 429 /*array of 4096 4-bit vlan vmdq indices */
 430 #define IXGBE_VFTAVIND(_j, _i)  (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
 431 #define IXGBE_FCTRL             0x05080
 432 #define IXGBE_VLNCTRL           0x05088
 433 #define IXGBE_MCSTCTRL          0x05090
 434 #define IXGBE_MRQC              0x05818
 435 #define IXGBE_SAQF(_i)  (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
 436 #define IXGBE_DAQF(_i)  (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
 437 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
 438 #define IXGBE_FTQF(_i)  (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
 439 #define IXGBE_ETQF(_i)  (0x05128 + ((_i) * 4)) /* EType Queue Filter */
 440 #define IXGBE_ETQS(_i)  (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
 441 #define IXGBE_SYNQF     0x0EC30 /* SYN Packet Queue Filter */
 442 #define IXGBE_RQTC      0x0EC70
 443 #define IXGBE_MTQC      0x08120
 444 #define IXGBE_VLVF(_i)  (0x0F100 + ((_i) * 4))  /* 64 of these (0-63) */
 445 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4))  /* 128 of these (0-127) */
 446 #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4))  /* 64 of these (0-63) */
 447 #define IXGBE_PFFLPL            0x050B0
 448 #define IXGBE_PFFLPH            0x050B4
 449 #define IXGBE_VT_CTL            0x051B0
 450 #define IXGBE_PFMAILBOX(_i)     (0x04B00 + (4 * (_i))) /* 64 total */
 451 /* 64 Mailboxes, 16 DW each */
 452 #define IXGBE_PFMBMEM(_i)       (0x13000 + (64 * (_i)))
 453 #define IXGBE_PFMBICR(_i)       (0x00710 + (4 * (_i))) /* 4 total */
 454 #define IXGBE_PFMBIMR(_i)       (0x00720 + (4 * (_i))) /* 4 total */
 455 #define IXGBE_VFRE(_i)          (0x051E0 + ((_i) * 4))
 456 #define IXGBE_VFTE(_i)          (0x08110 + ((_i) * 4))
 457 #define IXGBE_VMECM(_i)         (0x08790 + ((_i) * 4))
 458 #define IXGBE_QDE               0x2F04
 459 #define IXGBE_VMTXSW(_i)        (0x05180 + ((_i) * 4)) /* 2 total */
 460 #define IXGBE_VMOLR(_i)         (0x0F000 + ((_i) * 4)) /* 64 total */
 461 #define IXGBE_UTA(_i)           (0x0F400 + ((_i) * 4))
 462 #define IXGBE_MRCTL(_i)         (0x0F600 + ((_i) * 4))
 463 #define IXGBE_VMRVLAN(_i)       (0x0F610 + ((_i) * 4))
 464 #define IXGBE_VMRVM(_i)         (0x0F630 + ((_i) * 4))
 465 #define IXGBE_LVMMC_RX          0x2FA8
 466 #define IXGBE_LVMMC_TX          0x8108
 467 #define IXGBE_LMVM_RX           0x2FA4
 468 #define IXGBE_LMVM_TX           0x8124
 469 #define IXGBE_WQBR_RX(_i)       (0x2FB0 + ((_i) * 4)) /* 4 total */
 470 #define IXGBE_WQBR_TX(_i)       (0x8130 + ((_i) * 4)) /* 4 total */
 471 #define IXGBE_L34T_IMIR(_i)     (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
 472 #define IXGBE_RXFECCERR0        0x051B8
 473 #define IXGBE_LLITHRESH         0x0EC90
 474 #define IXGBE_IMIR(_i)          (0x05A80 + ((_i) * 4))  /* 8 of these (0-7) */
 475 #define IXGBE_IMIREXT(_i)       (0x05AA0 + ((_i) * 4))  /* 8 of these (0-7) */
 476 #define IXGBE_IMIRVP            0x05AC0
 477 #define IXGBE_VMD_CTL           0x0581C
 478 #define IXGBE_RETA(_i)          (0x05C00 + ((_i) * 4))  /* 32 of these (0-31) */
 479 #define IXGBE_ERETA(_i)         (0x0EE80 + ((_i) * 4))  /* 96 of these (0-95) */
 480 #define IXGBE_RSSRK(_i)         (0x05C80 + ((_i) * 4))  /* 10 of these (0-9) */
 481
 482 /* Registers for setting up RSS on X550 with SRIOV
 483  * _p - pool number (0..63)
 484  * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA)
 485  */
 486 #define IXGBE_PFVFMRQC(_p)      (0x03400 + ((_p) * 4))
 487 #define IXGBE_PFVFRSSRK(_i, _p) (0x018000 + ((_i) * 4) + ((_p) * 0x40))
 488 #define IXGBE_PFVFRETA(_i, _p)  (0x019000 + ((_i) * 4) + ((_p) * 0x40))
 489
 490 /* Flow Director registers */
 491 #define IXGBE_FDIRCTRL  0x0EE00
 492 #define IXGBE_FDIRHKEY  0x0EE68
 493 #define IXGBE_FDIRSKEY  0x0EE6C
 494 #define IXGBE_FDIRDIP4M 0x0EE3C
 495 #define IXGBE_FDIRSIP4M 0x0EE40
 496 #define IXGBE_FDIRTCPM  0x0EE44
 497 #define IXGBE_FDIRUDPM  0x0EE48
 498 #define IXGBE_FDIRSCTPM 0x0EE78
 499 #define IXGBE_FDIRIP6M  0x0EE74
 500 #define IXGBE_FDIRM     0x0EE70
 501
 502 /* Flow Director Stats registers */
 503 #define IXGBE_FDIRFREE  0x0EE38
 504 #define IXGBE_FDIRLEN   0x0EE4C
 505 #define IXGBE_FDIRUSTAT 0x0EE50
 506 #define IXGBE_FDIRFSTAT 0x0EE54
 507 #define IXGBE_FDIRMATCH 0x0EE58
 508 #define IXGBE_FDIRMISS  0x0EE5C
 509
 510 /* Flow Director Programming registers */
 511 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
 512 #define IXGBE_FDIRIPSA  0x0EE18
 513 #define IXGBE_FDIRIPDA  0x0EE1C
 514 #define IXGBE_FDIRPORT  0x0EE20
 515 #define IXGBE_FDIRVLAN  0x0EE24
 516 #define IXGBE_FDIRHASH  0x0EE28
 517 #define IXGBE_FDIRCMD   0x0EE2C
 518
 519 /* Transmit DMA registers */
 520 #define IXGBE_TDBAL(_i)         (0x06000 + ((_i) * 0x40)) /* 32 of them (0-31)*/
 521 #define IXGBE_TDBAH(_i)         (0x06004 + ((_i) * 0x40))
 522 #define IXGBE_TDLEN(_i)         (0x06008 + ((_i) * 0x40))
 523 #define IXGBE_TDH(_i)           (0x06010 + ((_i) * 0x40))
 524 #define IXGBE_TDT(_i)           (0x06018 + ((_i) * 0x40))
 525 #define IXGBE_TXDCTL(_i)        (0x06028 + ((_i) * 0x40))
 526 #define IXGBE_TDWBAL(_i)        (0x06038 + ((_i) * 0x40))
 527 #define IXGBE_TDWBAH(_i)        (0x0603C + ((_i) * 0x40))
 528 #define IXGBE_DTXCTL            0x07E00
 529
 530 #define IXGBE_DMATXCTL          0x04A80
 531 #define IXGBE_PFVFSPOOF(_i)     (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
 532 #define IXGBE_PFDTXGSWC         0x08220
 533 #define IXGBE_DTXMXSZRQ         0x08100
 534 #define IXGBE_DTXTCPFLGL        0x04A88
 535 #define IXGBE_DTXTCPFLGH        0x04A8C
 536 #define IXGBE_LBDRPEN           0x0CA00
 537 #define IXGBE_TXPBTHRESH(_i)    (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
 538
 539 #define IXGBE_DMATXCTL_TE       0x1 /* Transmit Enable */
 540 #define IXGBE_DMATXCTL_NS       0x2 /* No Snoop LSO hdr buffer */
 541 #define IXGBE_DMATXCTL_GDV      0x8 /* Global Double VLAN */
 542 #define IXGBE_DMATXCTL_MDP_EN   0x20 /* Bit 5 */
 543 #define IXGBE_DMATXCTL_MBINTEN  0x40 /* Bit 6 */
 544 #define IXGBE_DMATXCTL_VT_SHIFT 16  /* VLAN EtherType */
 545
 546 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
 547
 548 /* Anti-spoofing defines */
 549 #define IXGBE_SPOOF_MACAS_MASK          0xFF
 550 #define IXGBE_SPOOF_VLANAS_MASK         0xFF00
 551 #define IXGBE_SPOOF_VLANAS_SHIFT        8
 552 #define IXGBE_SPOOF_ETHERTYPEAS         0xFF000000
 553 #define IXGBE_SPOOF_ETHERTYPEAS_SHIFT   16
 554 #define IXGBE_PFVFSPOOF_REG_COUNT       8
 555 /* 16 of these (0-15) */
 556 #define IXGBE_DCA_TXCTRL(_i)            (0x07200 + ((_i) * 4))
 557 /* Tx DCA Control register : 128 of these (0-127) */
 558 #define IXGBE_DCA_TXCTRL_82599(_i)      (0x0600C + ((_i) * 0x40))
 559 #define IXGBE_TIPG                      0x0CB00
 560 #define IXGBE_TXPBSIZE(_i)              (0x0CC00 + ((_i) * 4)) /* 8 of these */
 561 #define IXGBE_MNGTXMAP                  0x0CD10
 562 #define IXGBE_TIPG_FIBER_DEFAULT        3
 563 #define IXGBE_TXPBSIZE_SHIFT            10
 564
 565 /* Wake up registers */
 566 #define IXGBE_WUC       0x05800
 567 #define IXGBE_WUFC      0x05808
 568 #define IXGBE_WUS       0x05810
 569 #define IXGBE_IPAV      0x05838
 570 #define IXGBE_IP4AT     0x05840 /* IPv4 table 0x5840-0x5858 */
 571 #define IXGBE_IP6AT     0x05880 /* IPv6 table 0x5880-0x588F */
 572
 573 #define IXGBE_WUPL      0x05900
 574 #define IXGBE_WUPM      0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
 575 #define IXGBE_PROXYS    0x05F60 /* Proxying Status Register */
 576 #define IXGBE_PROXYFC   0x05F64 /* Proxying Filter Control Register */
 577 #define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */
 578
 579 /* masks for accessing VXLAN and GENEVE UDP ports */
 580 #define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK      0x0000ffff /* VXLAN port */
 581 #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK     0xffff0000 /* GENEVE port */
 582 #define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK        0xffffffff /* GENEVE/VXLAN */
 583 #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT    16
 584
 585 #define IXGBE_FHFT(_n)  (0x09000 + ((_n) * 0x100)) /* Flex host filter table */
 586 /* Ext Flexible Host Filter Table */
 587 #define IXGBE_FHFT_EXT(_n)      (0x09800 + ((_n) * 0x100))
 588 #define IXGBE_FHFT_EXT_X550(_n) (0x09600 + ((_n) * 0x100))
 589
 590 /* Four Flexible Filters are supported */
 591 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX         4
 592 /* Six Flexible Filters are supported */
 593 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6       6
 594 /* Eight Flexible Filters are supported */
 595 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_8       8
 596 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX     2
 597
 598 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
 599 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX          128
 600 #define IXGBE_FHFT_LENGTH_OFFSET                0xFC  /* Length byte in FHFT */
 601 #define IXGBE_FHFT_LENGTH_MASK                  0x0FF /* Length in lower byte */
 602
 603 /* Definitions for power management and wakeup registers */
 604 /* Wake Up Control */
 605 #define IXGBE_WUC_PME_EN        0x00000002 /* PME Enable */
 606 #define IXGBE_WUC_PME_STATUS    0x00000004 /* PME Status */
 607 #define IXGBE_WUC_WKEN          0x00000010 /* Enable PE_WAKE_N pin assertion  */
 608
 609 /* Wake Up Filter Control */
 610 #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
 611 #define IXGBE_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
 612 #define IXGBE_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
 613 #define IXGBE_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
 614 #define IXGBE_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
 615 #define IXGBE_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
 616 #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
 617 #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
 618 #define IXGBE_WUFC_MNG  0x00000100 /* Directed Mgmt Packet Wakeup Enable */
 619
 620 #define IXGBE_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
 621 #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
 622 #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
 623 #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
 624 #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
 625 #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
 626 #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
 627 #define IXGBE_WUFC_FLX_FILTERS          0x000F0000 /* Mask for 4 flex filters */
 628 #define IXGBE_WUFC_FLX_FILTERS_6        0x003F0000 /* Mask for 6 flex filters */
 629 #define IXGBE_WUFC_FLX_FILTERS_8        0x00FF0000 /* Mask for 8 flex filters */
 630 #define IXGBE_WUFC_FW_RST_WK    0x80000000 /* Ena wake on FW reset assertion */
 631 /* Mask for Ext. flex filters */
 632 #define IXGBE_WUFC_EXT_FLX_FILTERS      0x00300000
 633 #define IXGBE_WUFC_ALL_FILTERS          0x000F00FF /* Mask all 4 flex filters */
 634 #define IXGBE_WUFC_ALL_FILTERS_6        0x003F00FF /* Mask all 6 flex filters */
 635 #define IXGBE_WUFC_ALL_FILTERS_8        0x00FF00FF /* Mask all 8 flex filters */
 636 #define IXGBE_WUFC_FLX_OFFSET   16 /* Offset to the Flexible Filters bits */
 637
 638 /* Wake Up Status */
 639 #define IXGBE_WUS_LNKC          IXGBE_WUFC_LNKC
 640 #define IXGBE_WUS_MAG           IXGBE_WUFC_MAG
 641 #define IXGBE_WUS_EX            IXGBE_WUFC_EX
 642 #define IXGBE_WUS_MC            IXGBE_WUFC_MC
 643 #define IXGBE_WUS_BC            IXGBE_WUFC_BC
 644 #define IXGBE_WUS_ARP           IXGBE_WUFC_ARP
 645 #define IXGBE_WUS_IPV4          IXGBE_WUFC_IPV4
 646 #define IXGBE_WUS_IPV6          IXGBE_WUFC_IPV6
 647 #define IXGBE_WUS_MNG           IXGBE_WUFC_MNG
 648 #define IXGBE_WUS_FLX0          IXGBE_WUFC_FLX0
 649 #define IXGBE_WUS_FLX1          IXGBE_WUFC_FLX1
 650 #define IXGBE_WUS_FLX2          IXGBE_WUFC_FLX2
 651 #define IXGBE_WUS_FLX3          IXGBE_WUFC_FLX3
 652 #define IXGBE_WUS_FLX4          IXGBE_WUFC_FLX4
 653 #define IXGBE_WUS_FLX5          IXGBE_WUFC_FLX5
 654 #define IXGBE_WUS_FLX_FILTERS   IXGBE_WUFC_FLX_FILTERS
 655 #define IXGBE_WUS_FW_RST_WK     IXGBE_WUFC_FW_RST_WK
 656 /* Proxy Status */
 657 #define IXGBE_PROXYS_EX         0x00000004 /* Exact packet received */
 658 #define IXGBE_PROXYS_ARP_DIR    0x00000020 /* ARP w/filter match received */
 659 #define IXGBE_PROXYS_NS         0x00000200 /* IPV6 NS received */
 660 #define IXGBE_PROXYS_NS_DIR     0x00000400 /* IPV6 NS w/DA match received */
 661 #define IXGBE_PROXYS_ARP        0x00000800 /* ARP request packet received */
 662 #define IXGBE_PROXYS_MLD        0x00001000 /* IPv6 MLD packet received */
 663
 664 /* Proxying Filter Control */
 665 #define IXGBE_PROXYFC_ENABLE    0x00000001 /* Port Proxying Enable */
 666 #define IXGBE_PROXYFC_EX        0x00000004 /* Directed Exact Proxy Enable */
 667 #define IXGBE_PROXYFC_ARP_DIR   0x00000020 /* Directed ARP Proxy Enable */
 668 #define IXGBE_PROXYFC_NS        0x00000200 /* IPv6 Neighbor Solicitation */
 669 #define IXGBE_PROXYFC_ARP       0x00000800 /* ARP Request Proxy Enable */
 670 #define IXGBE_PROXYFC_MLD       0x00000800 /* IPv6 MLD Proxy Enable */
 671 #define IXGBE_PROXYFC_NO_TCO    0x00008000 /* Ignore TCO packets */
 672
 673 #define IXGBE_WUPL_LENGTH_MASK  0xFFFF
 674
 675 /* DCB registers */
 676 #define IXGBE_DCB_MAX_TRAFFIC_CLASS     8
 677 #define IXGBE_RMCS              0x03D00
 678 #define IXGBE_DPMCS             0x07F40
 679 #define IXGBE_PDPMCS            0x0CD00
 680 #define IXGBE_RUPPBMR           0x050A0
 681 #define IXGBE_RT2CR(_i)         (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
 682 #define IXGBE_RT2SR(_i)         (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
 683 #define IXGBE_TDTQ2TCCR(_i)     (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
 684 #define IXGBE_TDTQ2TCSR(_i)     (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
 685 #define IXGBE_TDPT2TCCR(_i)     (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
 686 #define IXGBE_TDPT2TCSR(_i)     (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
 687
 688 /* Power Management */
 689 /* DMA Coalescing configuration */
 690 struct ixgbe_dmac_config {
 691         u16     watchdog_timer; /* usec units */
 692         bool    fcoe_en;
 693         u32     link_speed;
 694         u8      fcoe_tc;
 695         u8      num_tcs;
 696 };
 697
 698 /*
 699  * DMA Coalescing threshold Rx PB TC[n] value in Kilobyte by link speed.
 700  * DMACRXT = 10Gbps = 10,000 bits / usec = 1250 bytes / usec 70 * 1250 ==
 701  * 87500 bytes [85KB]
 702  */
 703 #define IXGBE_DMACRXT_10G               0x55
 704 #define IXGBE_DMACRXT_1G                0x09
 705 #define IXGBE_DMACRXT_100M              0x01
 706
 707 /* DMA Coalescing registers */
 708 #define IXGBE_DMCMNGTH                  0x15F20 /* Management Threshold */
 709 #define IXGBE_DMACR                     0x02400 /* Control register */
 710 #define IXGBE_DMCTH(_i)                 (0x03300 + ((_i) * 4)) /* 8 of these */
 711 #define IXGBE_DMCTLX                    0x02404 /* Time to Lx request */
 712 /* DMA Coalescing register fields */
 713 #define IXGBE_DMCMNGTH_DMCMNGTH_MASK    0x000FFFF0 /* Mng Threshold mask */
 714 #define IXGBE_DMCMNGTH_DMCMNGTH_SHIFT   4 /* Management Threshold shift */
 715 #define IXGBE_DMACR_DMACWT_MASK         0x0000FFFF /* Watchdog Timer mask */
 716 #define IXGBE_DMACR_HIGH_PRI_TC_MASK    0x00FF0000
 717 #define IXGBE_DMACR_HIGH_PRI_TC_SHIFT   16
 718 #define IXGBE_DMACR_EN_MNG_IND          0x10000000 /* Enable Mng Indications */
 719 #define IXGBE_DMACR_LX_COAL_IND         0x40000000 /* Lx Coalescing indicate */
 720 #define IXGBE_DMACR_DMAC_EN             0x80000000 /* DMA Coalescing Enable */
 721 #define IXGBE_DMCTH_DMACRXT_MASK        0x000001FF /* Receive Threshold mask */
 722 #define IXGBE_DMCTLX_TTLX_MASK          0x00000FFF /* Time to Lx request mask */
 723
 724 /* EEE registers */
 725 #define IXGBE_EEER                      0x043A0 /* EEE register */
 726 #define IXGBE_EEE_STAT                  0x04398 /* EEE Status */
 727 #define IXGBE_EEE_SU                    0x04380 /* EEE Set up */
 728 #define IXGBE_EEE_SU_TEEE_DLY_SHIFT     26
 729 #define IXGBE_TLPIC                     0x041F4 /* EEE Tx LPI count */
 730 #define IXGBE_RLPIC                     0x041F8 /* EEE Rx LPI count */
 731
 732 /* EEE register fields */
 733 #define IXGBE_EEER_TX_LPI_EN            0x00010000 /* Enable EEE LPI TX path */
 734 #define IXGBE_EEER_RX_LPI_EN            0x00020000 /* Enable EEE LPI RX path */
 735 #define IXGBE_EEE_STAT_NEG              0x20000000 /* EEE support neg on link */
 736 #define IXGBE_EEE_RX_LPI_STATUS         0x40000000 /* RX Link in LPI status */
 737 #define IXGBE_EEE_TX_LPI_STATUS         0x80000000 /* TX Link in LPI status */
 738
 739 /* Security Control Registers */
 740 #define IXGBE_SECTXCTRL         0x08800
 741 #define IXGBE_SECTXSTAT         0x08804
 742 #define IXGBE_SECTXBUFFAF       0x08808
 743 #define IXGBE_SECTXMINIFG       0x08810
 744 #define IXGBE_SECRXCTRL         0x08D00
 745 #define IXGBE_SECRXSTAT         0x08D04
 746
 747 /* Security Bit Fields and Masks */
 748 #define IXGBE_SECTXCTRL_SECTX_DIS       0x00000001
 749 #define IXGBE_SECTXCTRL_TX_DIS          0x00000002
 750 #define IXGBE_SECTXCTRL_STORE_FORWARD   0x00000004
 751
 752 #define IXGBE_SECTXSTAT_SECTX_RDY       0x00000001
 753 #define IXGBE_SECTXSTAT_ECC_TXERR       0x00000002
 754
 755 #define IXGBE_SECRXCTRL_SECRX_DIS       0x00000001
 756 #define IXGBE_SECRXCTRL_RX_DIS          0x00000002
 757
 758 #define IXGBE_SECRXSTAT_SECRX_RDY       0x00000001
 759 #define IXGBE_SECRXSTAT_ECC_RXERR       0x00000002
 760
 761 /* LinkSec (MacSec) Registers */
 762 #define IXGBE_LSECTXCAP         0x08A00
 763 #define IXGBE_LSECRXCAP         0x08F00
 764 #define IXGBE_LSECTXCTRL        0x08A04
 765 #define IXGBE_LSECTXSCL         0x08A08 /* SCI Low */
 766 #define IXGBE_LSECTXSCH         0x08A0C /* SCI High */
 767 #define IXGBE_LSECTXSA          0x08A10
 768 #define IXGBE_LSECTXPN0         0x08A14
 769 #define IXGBE_LSECTXPN1         0x08A18
 770 #define IXGBE_LSECTXKEY0(_n)    (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
 771 #define IXGBE_LSECTXKEY1(_n)    (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
 772 #define IXGBE_LSECRXCTRL        0x08F04
 773 #define IXGBE_LSECRXSCL         0x08F08
 774 #define IXGBE_LSECRXSCH         0x08F0C
 775 #define IXGBE_LSECRXSA(_i)      (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
 776 #define IXGBE_LSECRXPN(_i)      (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
 777 #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
 778 #define IXGBE_LSECTXUT          0x08A3C /* OutPktsUntagged */
 779 #define IXGBE_LSECTXPKTE        0x08A40 /* OutPktsEncrypted */
 780 #define IXGBE_LSECTXPKTP        0x08A44 /* OutPktsProtected */
 781 #define IXGBE_LSECTXOCTE        0x08A48 /* OutOctetsEncrypted */
 782 #define IXGBE_LSECTXOCTP        0x08A4C /* OutOctetsProtected */
 783 #define IXGBE_LSECRXUT          0x08F40 /* InPktsUntagged/InPktsNoTag */
 784 #define IXGBE_LSECRXOCTD        0x08F44 /* InOctetsDecrypted */
 785 #define IXGBE_LSECRXOCTV        0x08F48 /* InOctetsValidated */
 786 #define IXGBE_LSECRXBAD         0x08F4C /* InPktsBadTag */
 787 #define IXGBE_LSECRXNOSCI       0x08F50 /* InPktsNoSci */
 788 #define IXGBE_LSECRXUNSCI       0x08F54 /* InPktsUnknownSci */
 789 #define IXGBE_LSECRXUNCH        0x08F58 /* InPktsUnchecked */
 790 #define IXGBE_LSECRXDELAY       0x08F5C /* InPktsDelayed */
 791 #define IXGBE_LSECRXLATE        0x08F60 /* InPktsLate */
 792 #define IXGBE_LSECRXOK(_n)      (0x08F64 + (0x04 * (_n))) /* InPktsOk */
 793 #define IXGBE_LSECRXINV(_n)     (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
 794 #define IXGBE_LSECRXNV(_n)      (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
 795 #define IXGBE_LSECRXUNSA        0x08F7C /* InPktsUnusedSa */
 796 #define IXGBE_LSECRXNUSA        0x08F80 /* InPktsNotUsingSa */
 797
 798 /* LinkSec (MacSec) Bit Fields and Masks */
 799 #define IXGBE_LSECTXCAP_SUM_MASK        0x00FF0000
 800 #define IXGBE_LSECTXCAP_SUM_SHIFT       16
 801 #define IXGBE_LSECRXCAP_SUM_MASK        0x00FF0000
 802 #define IXGBE_LSECRXCAP_SUM_SHIFT       16
 803
 804 #define IXGBE_LSECTXCTRL_EN_MASK        0x00000003
 805 #define IXGBE_LSECTXCTRL_DISABLE        0x0
 806 #define IXGBE_LSECTXCTRL_AUTH           0x1
 807 #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT   0x2
 808 #define IXGBE_LSECTXCTRL_AISCI          0x00000020
 809 #define IXGBE_LSECTXCTRL_PNTHRSH_MASK   0xFFFFFF00
 810 #define IXGBE_LSECTXCTRL_RSV_MASK       0x000000D8
 811
 812 #define IXGBE_LSECRXCTRL_EN_MASK        0x0000000C
 813 #define IXGBE_LSECRXCTRL_EN_SHIFT       2
 814 #define IXGBE_LSECRXCTRL_DISABLE        0x0
 815 #define IXGBE_LSECRXCTRL_CHECK          0x1
 816 #define IXGBE_LSECRXCTRL_STRICT         0x2
 817 #define IXGBE_LSECRXCTRL_DROP           0x3
 818 #define IXGBE_LSECRXCTRL_PLSH           0x00000040
 819 #define IXGBE_LSECRXCTRL_RP             0x00000080
 820 #define IXGBE_LSECRXCTRL_RSV_MASK       0xFFFFFF33
 821
 822 /* IpSec Registers */
 823 #define IXGBE_IPSTXIDX          0x08900
 824 #define IXGBE_IPSTXSALT         0x08904
 825 #define IXGBE_IPSTXKEY(_i)      (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
 826 #define IXGBE_IPSRXIDX          0x08E00
 827 #define IXGBE_IPSRXIPADDR(_i)   (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
 828 #define IXGBE_IPSRXSPI          0x08E14
 829 #define IXGBE_IPSRXIPIDX        0x08E18
 830 #define IXGBE_IPSRXKEY(_i)      (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
 831 #define IXGBE_IPSRXSALT         0x08E2C
 832 #define IXGBE_IPSRXMOD          0x08E30
 833
 834 #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE    0x4
 835
 836 /* DCB registers */
 837 #define IXGBE_RTRPCS            0x02430
 838 #define IXGBE_RTTDCS            0x04900
 839 #define IXGBE_RTTDCS_ARBDIS     0x00000040 /* DCB arbiter disable */
 840 #define IXGBE_RTTPCS            0x0CD00
 841 #define IXGBE_RTRUP2TC          0x03020
 842 #define IXGBE_RTTUP2TC          0x0C800
 843 #define IXGBE_RTRPT4C(_i)       (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
 844 #define IXGBE_TXLLQ(_i)         (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */
 845 #define IXGBE_RTRPT4S(_i)       (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
 846 #define IXGBE_RTTDT2C(_i)       (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
 847 #define IXGBE_RTTDT2S(_i)       (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
 848 #define IXGBE_RTTPT2C(_i)       (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
 849 #define IXGBE_RTTPT2S(_i)       (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
 850 #define IXGBE_RTTDQSEL          0x04904
 851 #define IXGBE_RTTDT1C           0x04908
 852 #define IXGBE_RTTDT1S           0x0490C
 853 #define IXGBE_RTTQCNCR          0x08B00
 854 #define IXGBE_RTTQCNTG          0x04A90
 855 #define IXGBE_RTTBCNRD          0x0498C
 856 #define IXGBE_RTTQCNRR          0x0498C
 857 #define IXGBE_RTTDTECC          0x04990
 858 #define IXGBE_RTTDTECC_NO_BCN   0x00000100
 859
 860 #define IXGBE_RTTBCNRC                  0x04984
 861 #define IXGBE_RTTBCNRC_RS_ENA           0x80000000
 862 #define IXGBE_RTTBCNRC_RF_DEC_MASK      0x00003FFF
 863 #define IXGBE_RTTBCNRC_RF_INT_SHIFT     14
 864 #define IXGBE_RTTBCNRC_RF_INT_MASK \
 865         (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
 866 #define IXGBE_RTTBCNRM  0x04980
 867 #define IXGBE_RTTQCNRM  0x04980
 868
 869 /* BCN (for DCB) Registers */
 870 #define IXGBE_RTTBCNRS  0x04988
 871 #define IXGBE_RTTBCNCR  0x08B00
 872 #define IXGBE_RTTBCNACH 0x08B04
 873 #define IXGBE_RTTBCNACL 0x08B08
 874 #define IXGBE_RTTBCNTG  0x04A90
 875 #define IXGBE_RTTBCNIDX 0x08B0C
 876 #define IXGBE_RTTBCNCP  0x08B10
 877 #define IXGBE_RTFRTIMER 0x08B14
 878 #define IXGBE_RTTBCNRTT 0x05150
 879 #define IXGBE_RTTBCNRD  0x0498C
 880
 881 /* FCoE DMA Context Registers */
 882 /* FCoE Direct DMA Context */
 883 #define IXGBE_FCDDC(_i, _j)     (0x20000 + ((_i) * 0x4) + ((_j) * 0x10))
 884 #define IXGBE_FCPTRL            0x02410 /* FC User Desc. PTR Low */
 885 #define IXGBE_FCPTRH            0x02414 /* FC USer Desc. PTR High */
 886 #define IXGBE_FCBUFF            0x02418 /* FC Buffer Control */
 887 #define IXGBE_FCDMARW           0x02420 /* FC Receive DMA RW */
 888 #define IXGBE_FCBUFF_VALID      (1 << 0)   /* DMA Context Valid */
 889 #define IXGBE_FCBUFF_BUFFSIZE   (3 << 3)   /* User Buffer Size */
 890 #define IXGBE_FCBUFF_WRCONTX    (1 << 7)   /* 0: Initiator, 1: Target */
 891 #define IXGBE_FCBUFF_BUFFCNT    0x0000ff00 /* Number of User Buffers */
 892 #define IXGBE_FCBUFF_OFFSET     0xffff0000 /* User Buffer Offset */
 893 #define IXGBE_FCBUFF_BUFFSIZE_SHIFT     3
 894 #define IXGBE_FCBUFF_BUFFCNT_SHIFT      8
 895 #define IXGBE_FCBUFF_OFFSET_SHIFT       16
 896 #define IXGBE_FCDMARW_WE                (1 << 14)   /* Write enable */
 897 #define IXGBE_FCDMARW_RE                (1 << 15)   /* Read enable */
 898 #define IXGBE_FCDMARW_FCOESEL           0x000001ff  /* FC X_ID: 11 bits */
 899 #define IXGBE_FCDMARW_LASTSIZE          0xffff0000  /* Last User Buffer Size */
 900 #define IXGBE_FCDMARW_LASTSIZE_SHIFT    16
 901 /* FCoE SOF/EOF */
 902 #define IXGBE_TEOFF             0x04A94 /* Tx FC EOF */
 903 #define IXGBE_TSOFF             0x04A98 /* Tx FC SOF */
 904 #define IXGBE_REOFF             0x05158 /* Rx FC EOF */
 905 #define IXGBE_RSOFF             0x051F8 /* Rx FC SOF */
 906 /* FCoE Filter Context Registers */
 907 #define IXGBE_FCD_ID            0x05114 /* FCoE D_ID */
 908 #define IXGBE_FCSMAC            0x0510C /* FCoE Source MAC */
 909 #define IXGBE_FCFLTRW_SMAC_HIGH_SHIFT   16
 910 /* FCoE Direct Filter Context */
 911 #define IXGBE_FCDFC(_i, _j)     (0x28000 + ((_i) * 0x4) + ((_j) * 0x10))
 912 #define IXGBE_FCDFCD(_i)        (0x30000 + ((_i) * 0x4))
 913 #define IXGBE_FCFLT             0x05108 /* FC FLT Context */
 914 #define IXGBE_FCFLTRW           0x05110 /* FC Filter RW Control */
 915 #define IXGBE_FCPARAM           0x051d8 /* FC Offset Parameter */
 916 #define IXGBE_FCFLT_VALID       (1 << 0)   /* Filter Context Valid */
 917 #define IXGBE_FCFLT_FIRST       (1 << 1)   /* Filter First */
 918 #define IXGBE_FCFLT_SEQID       0x00ff0000 /* Sequence ID */
 919 #define IXGBE_FCFLT_SEQCNT      0xff000000 /* Sequence Count */
 920 #define IXGBE_FCFLTRW_RVALDT    (1 << 13)  /* Fast Re-Validation */
 921 #define IXGBE_FCFLTRW_WE        (1 << 14)  /* Write Enable */
 922 #define IXGBE_FCFLTRW_RE        (1 << 15)  /* Read Enable */
 923 /* FCoE Receive Control */
 924 #define IXGBE_FCRXCTRL          0x05100 /* FC Receive Control */
 925 #define IXGBE_FCRXCTRL_FCOELLI  (1 << 0)   /* Low latency interrupt */
 926 #define IXGBE_FCRXCTRL_SAVBAD   (1 << 1)   /* Save Bad Frames */
 927 #define IXGBE_FCRXCTRL_FRSTRDH  (1 << 2)   /* EN 1st Read Header */
 928 #define IXGBE_FCRXCTRL_LASTSEQH (1 << 3)   /* EN Last Header in Seq */
 929 #define IXGBE_FCRXCTRL_ALLH     (1 << 4)   /* EN All Headers */
 930 #define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5)   /* EN 1st Seq. Header */
 931 #define IXGBE_FCRXCTRL_ICRC     (1 << 6)   /* Ignore Bad FC CRC */
 932 #define IXGBE_FCRXCTRL_FCCRCBO  (1 << 7)   /* FC CRC Byte Ordering */
 933 #define IXGBE_FCRXCTRL_FCOEVER  0x00000f00 /* FCoE Version: 4 bits */
 934 #define IXGBE_FCRXCTRL_FCOEVER_SHIFT    8
 935 /* FCoE Redirection */
 936 #define IXGBE_FCRECTL           0x0ED00 /* FC Redirection Control */
 937 #define IXGBE_FCRETA0           0x0ED10 /* FC Redirection Table 0 */
 938 #define IXGBE_FCRETA(_i)        (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
 939 #define IXGBE_FCRECTL_ENA       0x1 /* FCoE Redir Table Enable */
 940 #define IXGBE_FCRETASEL_ENA     0x2 /* FCoE FCRETASEL bit */
 941 #define IXGBE_FCRETA_SIZE       8 /* Max entries in FCRETA */
 942 #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
 943 #define IXGBE_FCRETA_SIZE_X550  32 /* Max entries in FCRETA */
 944 /* Higher 7 bits for the queue index */
 945 #define IXGBE_FCRETA_ENTRY_HIGH_MASK    0x007F0000
 946 #define IXGBE_FCRETA_ENTRY_HIGH_SHIFT   16
 947
 948 /* Stats registers */
 949 #define IXGBE_CRCERRS   0x04000
 950 #define IXGBE_ILLERRC   0x04004
 951 #define IXGBE_ERRBC     0x04008
 952 #define IXGBE_MSPDC     0x04010
 953 #define IXGBE_MPC(_i)   (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
 954 #define IXGBE_MLFC      0x04034
 955 #define IXGBE_MRFC      0x04038
 956 #define IXGBE_RLEC      0x04040
 957 #define IXGBE_LXONTXC   0x03F60
 958 #define IXGBE_LXONRXC   0x0CF60
 959 #define IXGBE_LXOFFTXC  0x03F68
 960 #define IXGBE_LXOFFRXC  0x0CF68
 961 #define IXGBE_LXONRXCNT         0x041A4
 962 #define IXGBE_LXOFFRXCNT        0x041A8
 963 #define IXGBE_PXONRXCNT(_i)     (0x04140 + ((_i) * 4)) /* 8 of these */
 964 #define IXGBE_PXOFFRXCNT(_i)    (0x04160 + ((_i) * 4)) /* 8 of these */
 965 #define IXGBE_PXON2OFFCNT(_i)   (0x03240 + ((_i) * 4)) /* 8 of these */
 966 #define IXGBE_PXONTXC(_i)       (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
 967 #define IXGBE_PXONRXC(_i)       (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
 968 #define IXGBE_PXOFFTXC(_i)      (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
 969 #define IXGBE_PXOFFRXC(_i)      (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
 970 #define IXGBE_PRC64             0x0405C
 971 #define IXGBE_PRC127            0x04060
 972 #define IXGBE_PRC255            0x04064
 973 #define IXGBE_PRC511            0x04068
 974 #define IXGBE_PRC1023           0x0406C
 975 #define IXGBE_PRC1522           0x04070
 976 #define IXGBE_GPRC              0x04074
 977 #define IXGBE_BPRC              0x04078
 978 #define IXGBE_MPRC              0x0407C
 979 #define IXGBE_GPTC              0x04080
 980 #define IXGBE_GORCL             0x04088
 981 #define IXGBE_GORCH             0x0408C
 982 #define IXGBE_GOTCL             0x04090
 983 #define IXGBE_GOTCH             0x04094
 984 #define IXGBE_RNBC(_i)          (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
 985 #define IXGBE_RUC               0x040A4
 986 #define IXGBE_RFC               0x040A8
 987 #define IXGBE_ROC               0x040AC
 988 #define IXGBE_RJC               0x040B0
 989 #define IXGBE_MNGPRC            0x040B4
 990 #define IXGBE_MNGPDC            0x040B8
 991 #define IXGBE_MNGPTC            0x0CF90
 992 #define IXGBE_TORL              0x040C0
 993 #define IXGBE_TORH              0x040C4
 994 #define IXGBE_TPR               0x040D0
 995 #define IXGBE_TPT               0x040D4
 996 #define IXGBE_PTC64             0x040D8
 997 #define IXGBE_PTC127            0x040DC
 998 #define IXGBE_PTC255            0x040E0
 999 #define IXGBE_PTC511            0x040E4
1000 #define IXGBE_PTC1023           0x040E8
1001 #define IXGBE_PTC1522           0x040EC
1002 #define IXGBE_MPTC              0x040F0
1003 #define IXGBE_BPTC              0x040F4
1004 #define IXGBE_XEC               0x04120
1005 #define IXGBE_SSVPC             0x08780
1006
1007 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
1008 #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
1009                          (0x08600 + ((_i) * 4)))
1010 #define IXGBE_TQSM(_i)  (0x08600 + ((_i) * 4))
1011
1012 #define IXGBE_QPRC(_i)  (0x01030 + ((_i) * 0x40)) /* 16 of these */
1013 #define IXGBE_QPTC(_i)  (0x06030 + ((_i) * 0x40)) /* 16 of these */
1014 #define IXGBE_QBRC(_i)  (0x01034 + ((_i) * 0x40)) /* 16 of these */
1015 #define IXGBE_QBTC(_i)  (0x06034 + ((_i) * 0x40)) /* 16 of these */
1016 #define IXGBE_QBRC_L(_i)        (0x01034 + ((_i) * 0x40)) /* 16 of these */
1017 #define IXGBE_QBRC_H(_i)        (0x01038 + ((_i) * 0x40)) /* 16 of these */
1018 #define IXGBE_QPRDC(_i)         (0x01430 + ((_i) * 0x40)) /* 16 of these */
1019 #define IXGBE_QBTC_L(_i)        (0x08700 + ((_i) * 0x8)) /* 16 of these */
1020 #define IXGBE_QBTC_H(_i)        (0x08704 + ((_i) * 0x8)) /* 16 of these */
1021 #define IXGBE_FCCRC             0x05118 /* Num of Good Eth CRC w/ Bad FC CRC */
1022 #define IXGBE_FCOERPDC          0x0241C /* FCoE Rx Packets Dropped Count */
1023 #define IXGBE_FCLAST            0x02424 /* FCoE Last Error Count */
1024 #define IXGBE_FCOEPRC           0x02428 /* Number of FCoE Packets Received */
1025 #define IXGBE_FCOEDWRC          0x0242C /* Number of FCoE DWords Received */
1026 #define IXGBE_FCOEPTC           0x08784 /* Number of FCoE Packets Transmitted */
1027 #define IXGBE_FCOEDWTC          0x08788 /* Number of FCoE DWords Transmitted */
1028 #define IXGBE_FCCRC_CNT_MASK    0x0000FFFF /* CRC_CNT: bit 0 - 15 */
1029 #define IXGBE_FCLAST_CNT_MASK   0x0000FFFF /* Last_CNT: bit 0 - 15 */
1030 #define IXGBE_O2BGPTC           0x041C4
1031 #define IXGBE_O2BSPC            0x087B0
1032 #define IXGBE_B2OSPC            0x041C0
1033 #define IXGBE_B2OGPRC           0x02F90
1034 #define IXGBE_BUPRC             0x04180
1035 #define IXGBE_BMPRC             0x04184
1036 #define IXGBE_BBPRC             0x04188
1037 #define IXGBE_BUPTC             0x0418C
1038 #define IXGBE_BMPTC             0x04190
1039 #define IXGBE_BBPTC             0x04194
1040 #define IXGBE_BCRCERRS          0x04198
1041 #define IXGBE_BXONRXC           0x0419C
1042 #define IXGBE_BXOFFRXC          0x041E0
1043 #define IXGBE_BXONTXC           0x041E4
1044 #define IXGBE_BXOFFTXC          0x041E8
1045
1046 /* Management */
1047 #define IXGBE_MAVTV(_i)         (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
1048 #define IXGBE_MFUTP(_i)         (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
1049 #define IXGBE_MANC              0x05820
1050 #define IXGBE_MFVAL             0x05824
1051 #define IXGBE_MANC2H            0x05860
1052 #define IXGBE_MDEF(_i)          (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
1053 #define IXGBE_MIPAF             0x058B0
1054 #define IXGBE_MMAL(_i)          (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
1055 #define IXGBE_MMAH(_i)          (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
1056 #define IXGBE_FTFT              0x09400 /* 0x9400-0x97FC */
1057 #define IXGBE_METF(_i)          (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
1058 #define IXGBE_MDEF_EXT(_i)      (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
1059 #define IXGBE_LSWFW             0x15F14
1060 #define IXGBE_BMCIP(_i)         (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */
1061 #define IXGBE_BMCIPVAL          0x05060
1062 #define IXGBE_BMCIP_IPADDR_TYPE 0x00000001
1063 #define IXGBE_BMCIP_IPADDR_VALID        0x00000002
1064
1065 /* Management Bit Fields and Masks */
1066 #define IXGBE_MANC_MPROXYE      0x40000000 /* Management Proxy Enable */
1067 #define IXGBE_MANC_RCV_TCO_EN   0x00020000 /* Rcv TCO packet enable */
1068 #define IXGBE_MANC_EN_BMC2OS    0x10000000 /* Ena BMC2OS and OS2BMC traffic */
1069 #define IXGBE_MANC_EN_BMC2OS_SHIFT      28
1070
1071 /* Firmware Semaphore Register */
1072 #define IXGBE_FWSM_MODE_MASK    0xE
1073 #define IXGBE_FWSM_TS_ENABLED   0x1
1074 #define IXGBE_FWSM_FW_MODE_PT   0x4
1075 #define IXGBE_FWSM_FW_NVM_RECOVERY_MODE (1 << 5)
1076 #define IXGBE_FWSM_EXT_ERR_IND_MASK 0x01F80000
1077 #define IXGBE_FWSM_FW_VAL_BIT   (1 << 15)
1078
1079 /* ARC Subsystem registers */
1080 #define IXGBE_HICR              0x15F00
1081 #define IXGBE_FWSTS             0x15F0C
1082 #define IXGBE_HSMC0R            0x15F04
1083 #define IXGBE_HSMC1R            0x15F08
1084 #define IXGBE_SWSR              0x15F10
1085 #define IXGBE_HFDR              0x15FE8
1086 #define IXGBE_FLEX_MNG          0x15800 /* 0x15800 - 0x15EFC */
1087
1088 #define IXGBE_HICR_EN           0x01  /* Enable bit - RO */
1089 /* Driver sets this bit when done to put command in RAM */
1090 #define IXGBE_HICR_C            0x02
1091 #define IXGBE_HICR_SV           0x04  /* Status Validity */
1092 #define IXGBE_HICR_FW_RESET_ENABLE      0x40
1093 #define IXGBE_HICR_FW_RESET     0x80
1094
1095 /* PCI-E registers */
1096 #define IXGBE_GCR               0x11000
1097 #define IXGBE_GTV               0x11004
1098 #define IXGBE_FUNCTAG           0x11008
1099 #define IXGBE_GLT               0x1100C
1100 #define IXGBE_PCIEPIPEADR       0x11004
1101 #define IXGBE_PCIEPIPEDAT       0x11008
1102 #define IXGBE_GSCL_1            0x11010
1103 #define IXGBE_GSCL_2            0x11014
1104 #define IXGBE_GSCL_1_X540       IXGBE_GSCL_1
1105 #define IXGBE_GSCL_2_X540       IXGBE_GSCL_2
1106 #define IXGBE_GSCL_3            0x11018
1107 #define IXGBE_GSCL_4            0x1101C
1108 #define IXGBE_GSCN_0            0x11020
1109 #define IXGBE_GSCN_1            0x11024
1110 #define IXGBE_GSCN_2            0x11028
1111 #define IXGBE_GSCN_3            0x1102C
1112 #define IXGBE_GSCN_0_X540       IXGBE_GSCN_0
1113 #define IXGBE_GSCN_1_X540       IXGBE_GSCN_1
1114 #define IXGBE_GSCN_2_X540       IXGBE_GSCN_2
1115 #define IXGBE_GSCN_3_X540       IXGBE_GSCN_3
1116 #define IXGBE_FACTPS            0x10150
1117 #define IXGBE_FACTPS_X540       IXGBE_FACTPS
1118 #define IXGBE_GSCL_1_X550       0x11800
1119 #define IXGBE_GSCL_2_X550       0x11804
1120 #define IXGBE_GSCL_1_X550EM_x   IXGBE_GSCL_1_X550
1121 #define IXGBE_GSCL_2_X550EM_x   IXGBE_GSCL_2_X550
1122 #define IXGBE_GSCN_0_X550       0x11820
1123 #define IXGBE_GSCN_1_X550       0x11824
1124 #define IXGBE_GSCN_2_X550       0x11828
1125 #define IXGBE_GSCN_3_X550       0x1182C
1126 #define IXGBE_GSCN_0_X550EM_x   IXGBE_GSCN_0_X550
1127 #define IXGBE_GSCN_1_X550EM_x   IXGBE_GSCN_1_X550
1128 #define IXGBE_GSCN_2_X550EM_x   IXGBE_GSCN_2_X550
1129 #define IXGBE_GSCN_3_X550EM_x   IXGBE_GSCN_3_X550
1130 #define IXGBE_FACTPS_X550       IXGBE_FACTPS
1131 #define IXGBE_FACTPS_X550EM_x   IXGBE_FACTPS
1132 #define IXGBE_GSCL_1_X550EM_a   IXGBE_GSCL_1_X550
1133 #define IXGBE_GSCL_2_X550EM_a   IXGBE_GSCL_2_X550
1134 #define IXGBE_GSCN_0_X550EM_a   IXGBE_GSCN_0_X550
1135 #define IXGBE_GSCN_1_X550EM_a   IXGBE_GSCN_1_X550
1136 #define IXGBE_GSCN_2_X550EM_a   IXGBE_GSCN_2_X550
1137 #define IXGBE_GSCN_3_X550EM_a   IXGBE_GSCN_3_X550
1138 #define IXGBE_FACTPS_X550EM_a   0x15FEC
1139 #define IXGBE_FACTPS_BY_MAC(_hw)        IXGBE_BY_MAC((_hw), FACTPS)
1140
1141 #define IXGBE_PCIEANACTL        0x11040
1142 #define IXGBE_SWSM              0x10140
1143 #define IXGBE_SWSM_X540         IXGBE_SWSM
1144 #define IXGBE_SWSM_X550         IXGBE_SWSM
1145 #define IXGBE_SWSM_X550EM_x     IXGBE_SWSM
1146 #define IXGBE_SWSM_X550EM_a     0x15F70
1147 #define IXGBE_SWSM_BY_MAC(_hw)  IXGBE_BY_MAC((_hw), SWSM)
1148
1149 #define IXGBE_FWSM              0x10148
1150 #define IXGBE_FWSM_X540         IXGBE_FWSM
1151 #define IXGBE_FWSM_X550         IXGBE_FWSM
1152 #define IXGBE_FWSM_X550EM_x     IXGBE_FWSM
1153 #define IXGBE_FWSM_X550EM_a     0x15F74
1154 #define IXGBE_FWSM_BY_MAC(_hw)  IXGBE_BY_MAC((_hw), FWSM)
1155
1156 #define IXGBE_SWFW_SYNC         IXGBE_GSSR
1157 #define IXGBE_SWFW_SYNC_X540    IXGBE_SWFW_SYNC
1158 #define IXGBE_SWFW_SYNC_X550    IXGBE_SWFW_SYNC
1159 #define IXGBE_SWFW_SYNC_X550EM_x        IXGBE_SWFW_SYNC
1160 #define IXGBE_SWFW_SYNC_X550EM_a        0x15F78
1161 #define IXGBE_SWFW_SYNC_BY_MAC(_hw)     IXGBE_BY_MAC((_hw), SWFW_SYNC)
1162
1163 #define IXGBE_GSSR              0x10160
1164 #define IXGBE_MREVID            0x11064
1165 #define IXGBE_DCA_ID            0x11070
1166 #define IXGBE_DCA_CTRL          0x11074
1167
1168 /* PCI-E registers 82599-Specific */
1169 #define IXGBE_GCR_EXT           0x11050
1170 #define IXGBE_GSCL_5_82599      0x11030
1171 #define IXGBE_GSCL_6_82599      0x11034
1172 #define IXGBE_GSCL_7_82599      0x11038
1173 #define IXGBE_GSCL_8_82599      0x1103C
1174 #define IXGBE_GSCL_5_X540       IXGBE_GSCL_5_82599
1175 #define IXGBE_GSCL_6_X540       IXGBE_GSCL_6_82599
1176 #define IXGBE_GSCL_7_X540       IXGBE_GSCL_7_82599
1177 #define IXGBE_GSCL_8_X540       IXGBE_GSCL_8_82599
1178 #define IXGBE_PHYADR_82599      0x11040
1179 #define IXGBE_PHYDAT_82599      0x11044
1180 #define IXGBE_PHYCTL_82599      0x11048
1181 #define IXGBE_PBACLR_82599      0x11068
1182 #define IXGBE_CIAA              0x11088
1183 #define IXGBE_CIAD              0x1108C
1184 #define IXGBE_CIAA_82599        IXGBE_CIAA
1185 #define IXGBE_CIAD_82599        IXGBE_CIAD
1186 #define IXGBE_CIAA_X540         IXGBE_CIAA
1187 #define IXGBE_CIAD_X540         IXGBE_CIAD
1188 #define IXGBE_GSCL_5_X550       0x11810
1189 #define IXGBE_GSCL_6_X550       0x11814
1190 #define IXGBE_GSCL_7_X550       0x11818
1191 #define IXGBE_GSCL_8_X550       0x1181C
1192 #define IXGBE_GSCL_5_X550EM_x   IXGBE_GSCL_5_X550
1193 #define IXGBE_GSCL_6_X550EM_x   IXGBE_GSCL_6_X550
1194 #define IXGBE_GSCL_7_X550EM_x   IXGBE_GSCL_7_X550
1195 #define IXGBE_GSCL_8_X550EM_x   IXGBE_GSCL_8_X550
1196 #define IXGBE_CIAA_X550         0x11508
1197 #define IXGBE_CIAD_X550         0x11510
1198 #define IXGBE_CIAA_X550EM_x     IXGBE_CIAA_X550
1199 #define IXGBE_CIAD_X550EM_x     IXGBE_CIAD_X550
1200 #define IXGBE_GSCL_5_X550EM_a   IXGBE_GSCL_5_X550
1201 #define IXGBE_GSCL_6_X550EM_a   IXGBE_GSCL_6_X550
1202 #define IXGBE_GSCL_7_X550EM_a   IXGBE_GSCL_7_X550
1203 #define IXGBE_GSCL_8_X550EM_a   IXGBE_GSCL_8_X550
1204 #define IXGBE_CIAA_X550EM_a     IXGBE_CIAA_X550
1205 #define IXGBE_CIAD_X550EM_a     IXGBE_CIAD_X550
1206 #define IXGBE_CIAA_BY_MAC(_hw)  IXGBE_BY_MAC((_hw), CIAA)
1207 #define IXGBE_CIAD_BY_MAC(_hw)  IXGBE_BY_MAC((_hw), CIAD)
1208 #define IXGBE_PICAUSE           0x110B0
1209 #define IXGBE_PIENA             0x110B8
1210 #define IXGBE_CDQ_MBR_82599     0x110B4
1211 #define IXGBE_PCIESPARE         0x110BC
1212 #define IXGBE_MISC_REG_82599    0x110F0
1213 #define IXGBE_ECC_CTRL_0_82599  0x11100
1214 #define IXGBE_ECC_CTRL_1_82599  0x11104
1215 #define IXGBE_ECC_STATUS_82599  0x110E0
1216 #define IXGBE_BAR_CTRL_82599    0x110F4
1217
1218 /* PCI Express Control */
1219 #define IXGBE_GCR_CMPL_TMOUT_MASK       0x0000F000
1220 #define IXGBE_GCR_CMPL_TMOUT_10ms       0x00001000
1221 #define IXGBE_GCR_CMPL_TMOUT_RESEND     0x00010000
1222 #define IXGBE_GCR_CAP_VER2              0x00040000
1223
1224 #define IXGBE_GCR_EXT_MSIX_EN           0x80000000
1225 #define IXGBE_GCR_EXT_BUFFERS_CLEAR     0x40000000
1226 #define IXGBE_GCR_EXT_VT_MODE_16        0x00000001
1227 #define IXGBE_GCR_EXT_VT_MODE_32        0x00000002
1228 #define IXGBE_GCR_EXT_VT_MODE_64        0x00000003
1229 #define IXGBE_GCR_EXT_SRIOV             (IXGBE_GCR_EXT_MSIX_EN | \
1230                                          IXGBE_GCR_EXT_VT_MODE_64)
1231 #define IXGBE_GCR_EXT_VT_MODE_MASK      0x00000003
1232 /* Time Sync Registers */
1233 #define IXGBE_TSYNCRXCTL        0x05188 /* Rx Time Sync Control register - RW */
1234 #define IXGBE_TSYNCTXCTL        0x08C00 /* Tx Time Sync Control register - RW */
1235 #define IXGBE_RXSTMPL   0x051E8 /* Rx timestamp Low - RO */
1236 #define IXGBE_RXSTMPH   0x051A4 /* Rx timestamp High - RO */
1237 #define IXGBE_RXSATRL   0x051A0 /* Rx timestamp attribute low - RO */
1238 #define IXGBE_RXSATRH   0x051A8 /* Rx timestamp attribute high - RO */
1239 #define IXGBE_RXMTRL    0x05120 /* RX message type register low - RW */
1240 #define IXGBE_TXSTMPL   0x08C04 /* Tx timestamp value Low - RO */
1241 #define IXGBE_TXSTMPH   0x08C08 /* Tx timestamp value High - RO */
1242 #define IXGBE_SYSTIML   0x08C0C /* System time register Low - RO */
1243 #define IXGBE_SYSTIMH   0x08C10 /* System time register High - RO */
1244 #define IXGBE_SYSTIMR   0x08C58 /* System time register Residue - RO */
1245 #define IXGBE_TIMINCA   0x08C14 /* Increment attributes register - RW */
1246 #define IXGBE_TIMADJL   0x08C18 /* Time Adjustment Offset register Low - RW */
1247 #define IXGBE_TIMADJH   0x08C1C /* Time Adjustment Offset register High - RW */
1248 #define IXGBE_TSAUXC    0x08C20 /* TimeSync Auxiliary Control register - RW */
1249 #define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */
1250 #define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */
1251 #define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */
1252 #define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */
1253 #define IXGBE_CLKTIML   0x08C34 /* Clock Out Time Register Low - RW */
1254 #define IXGBE_CLKTIMH   0x08C38 /* Clock Out Time Register High - RW */
1255 #define IXGBE_FREQOUT0  0x08C34 /* Frequency Out 0 Control register - RW */
1256 #define IXGBE_FREQOUT1  0x08C38 /* Frequency Out 1 Control register - RW */
1257 #define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
1258 #define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
1259 #define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
1260 #define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
1261 #define IXGBE_TSIM      0x08C68 /* TimeSync Interrupt Mask Register - RW */
1262 #define IXGBE_TSICR     0x08C60 /* TimeSync Interrupt Cause Register - WO */
1263 #define IXGBE_TSSDP     0x0003C /* TimeSync SDP Configuration Register - RW */
1264
1265 /* Diagnostic Registers */
1266 #define IXGBE_RDSTATCTL         0x02C20
1267 #define IXGBE_RDSTAT(_i)        (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
1268 #define IXGBE_RDHMPN            0x02F08
1269 #define IXGBE_RIC_DW(_i)        (0x02F10 + ((_i) * 4))
1270 #define IXGBE_RDPROBE           0x02F20
1271 #define IXGBE_RDMAM             0x02F30
1272 #define IXGBE_RDMAD             0x02F34
1273 #define IXGBE_TDHMPN            0x07F08
1274 #define IXGBE_TDHMPN2           0x082FC
1275 #define IXGBE_TXDESCIC          0x082CC
1276 #define IXGBE_TIC_DW(_i)        (0x07F10 + ((_i) * 4))
1277 #define IXGBE_TIC_DW2(_i)       (0x082B0 + ((_i) * 4))
1278 #define IXGBE_TDPROBE           0x07F20
1279 #define IXGBE_TXBUFCTRL         0x0C600
1280 #define IXGBE_TXBUFDATA0        0x0C610
1281 #define IXGBE_TXBUFDATA1        0x0C614
1282 #define IXGBE_TXBUFDATA2        0x0C618
1283 #define IXGBE_TXBUFDATA3        0x0C61C
1284 #define IXGBE_RXBUFCTRL         0x03600
1285 #define IXGBE_RXBUFDATA0        0x03610
1286 #define IXGBE_RXBUFDATA1        0x03614
1287 #define IXGBE_RXBUFDATA2        0x03618
1288 #define IXGBE_RXBUFDATA3        0x0361C
1289 #define IXGBE_PCIE_DIAG(_i)     (0x11090 + ((_i) * 4)) /* 8 of these */
1290 #define IXGBE_RFVAL             0x050A4
1291 #define IXGBE_MDFTC1            0x042B8
1292 #define IXGBE_MDFTC2            0x042C0
1293 #define IXGBE_MDFTFIFO1         0x042C4
1294 #define IXGBE_MDFTFIFO2         0x042C8
1295 #define IXGBE_MDFTS             0x042CC
1296 #define IXGBE_RXDATAWRPTR(_i)   (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
1297 #define IXGBE_RXDESCWRPTR(_i)   (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
1298 #define IXGBE_RXDATARDPTR(_i)   (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
1299 #define IXGBE_RXDESCRDPTR(_i)   (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
1300 #define IXGBE_TXDATAWRPTR(_i)   (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
1301 #define IXGBE_TXDESCWRPTR(_i)   (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
1302 #define IXGBE_TXDATARDPTR(_i)   (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
1303 #define IXGBE_TXDESCRDPTR(_i)   (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
1304 #define IXGBE_PCIEECCCTL        0x1106C
1305 #define IXGBE_RXWRPTR(_i)       (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
1306 #define IXGBE_RXUSED(_i)        (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
1307 #define IXGBE_RXRDPTR(_i)       (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
1308 #define IXGBE_RXRDWRPTR(_i)     (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
1309 #define IXGBE_TXWRPTR(_i)       (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
1310 #define IXGBE_TXUSED(_i)        (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
1311 #define IXGBE_TXRDPTR(_i)       (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
1312 #define IXGBE_TXRDWRPTR(_i)     (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
1313 #define IXGBE_PCIEECCCTL0       0x11100
1314 #define IXGBE_PCIEECCCTL1       0x11104
1315 #define IXGBE_RXDBUECC          0x03F70
1316 #define IXGBE_TXDBUECC          0x0CF70
1317 #define IXGBE_RXDBUEST          0x03F74
1318 #define IXGBE_TXDBUEST          0x0CF74
1319 #define IXGBE_PBTXECC           0x0C300
1320 #define IXGBE_PBRXECC           0x03300
1321 #define IXGBE_GHECCR            0x110B0
1322
1323 /* MAC Registers */
1324 #define IXGBE_PCS1GCFIG         0x04200
1325 #define IXGBE_PCS1GLCTL         0x04208
1326 #define IXGBE_PCS1GLSTA         0x0420C
1327 #define IXGBE_PCS1GDBG0         0x04210
1328 #define IXGBE_PCS1GDBG1         0x04214
1329 #define IXGBE_PCS1GANA          0x04218
1330 #define IXGBE_PCS1GANLP         0x0421C
1331 #define IXGBE_PCS1GANNP         0x04220
1332 #define IXGBE_PCS1GANLPNP       0x04224
1333 #define IXGBE_HLREG0            0x04240
1334 #define IXGBE_HLREG1            0x04244
1335 #define IXGBE_PAP               0x04248
1336 #define IXGBE_MACA              0x0424C
1337 #define IXGBE_APAE              0x04250
1338 #define IXGBE_ARD               0x04254
1339 #define IXGBE_AIS               0x04258
1340 #define IXGBE_MSCA              0x0425C
1341 #define IXGBE_MSRWD             0x04260
1342 #define IXGBE_MLADD             0x04264
1343 #define IXGBE_MHADD             0x04268
1344 #define IXGBE_MAXFRS            0x04268
1345 #define IXGBE_TREG              0x0426C
1346 #define IXGBE_PCSS1             0x04288
1347 #define IXGBE_PCSS2             0x0428C
1348 #define IXGBE_XPCSS             0x04290
1349 #define IXGBE_MFLCN             0x04294
1350 #define IXGBE_SERDESC           0x04298
1351 #define IXGBE_MAC_SGMII_BUSY    0x04298
1352 #define IXGBE_MACS              0x0429C
1353 #define IXGBE_AUTOC             0x042A0
1354 #define IXGBE_LINKS             0x042A4
1355 #define IXGBE_LINKS2            0x04324
1356 #define IXGBE_AUTOC2            0x042A8
1357 #define IXGBE_AUTOC3            0x042AC
1358 #define IXGBE_ANLP1             0x042B0
1359 #define IXGBE_ANLP2             0x042B4
1360 #define IXGBE_MACC              0x04330
1361 #define IXGBE_ATLASCTL          0x04800
1362 #define IXGBE_MMNGC             0x042D0
1363 #define IXGBE_ANLPNP1           0x042D4
1364 #define IXGBE_ANLPNP2           0x042D8
1365 #define IXGBE_KRPCSFC           0x042E0
1366 #define IXGBE_KRPCSS            0x042E4
1367 #define IXGBE_FECS1             0x042E8
1368 #define IXGBE_FECS2             0x042EC
1369 #define IXGBE_SMADARCTL         0x14F10
1370 #define IXGBE_MPVC              0x04318
1371 #define IXGBE_SGMIIC            0x04314
1372
1373 /* Statistics Registers */
1374 #define IXGBE_RXNFGPC           0x041B0
1375 #define IXGBE_RXNFGBCL          0x041B4
1376 #define IXGBE_RXNFGBCH          0x041B8
1377 #define IXGBE_RXDGPC            0x02F50
1378 #define IXGBE_RXDGBCL           0x02F54
1379 #define IXGBE_RXDGBCH           0x02F58
1380 #define IXGBE_RXDDGPC           0x02F5C
1381 #define IXGBE_RXDDGBCL          0x02F60
1382 #define IXGBE_RXDDGBCH          0x02F64
1383 #define IXGBE_RXLPBKGPC         0x02F68
1384 #define IXGBE_RXLPBKGBCL        0x02F6C
1385 #define IXGBE_RXLPBKGBCH        0x02F70
1386 #define IXGBE_RXDLPBKGPC        0x02F74
1387 #define IXGBE_RXDLPBKGBCL       0x02F78
1388 #define IXGBE_RXDLPBKGBCH       0x02F7C
1389 #define IXGBE_TXDGPC            0x087A0
1390 #define IXGBE_TXDGBCL           0x087A4
1391 #define IXGBE_TXDGBCH           0x087A8
1392
1393 #define IXGBE_RXDSTATCTRL       0x02F40
1394
1395 /* Copper Pond 2 link timeout */
1396 #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
1397
1398 /* Omer CORECTL */
1399 #define IXGBE_CORECTL                   0x014F00
1400 /* BARCTRL */
1401 #define IXGBE_BARCTRL                   0x110F4
1402 #define IXGBE_BARCTRL_FLSIZE            0x0700
1403 #define IXGBE_BARCTRL_FLSIZE_SHIFT      8
1404 #define IXGBE_BARCTRL_CSRSIZE           0x2000
1405
1406 /* RSCCTL Bit Masks */
1407 #define IXGBE_RSCCTL_RSCEN      0x01
1408 #define IXGBE_RSCCTL_MAXDESC_1  0x00
1409 #define IXGBE_RSCCTL_MAXDESC_4  0x04
1410 #define IXGBE_RSCCTL_MAXDESC_8  0x08
1411 #define IXGBE_RSCCTL_MAXDESC_16 0x0C
1412 #define IXGBE_RSCCTL_TS_DIS     0x02
1413
1414 /* RSCDBU Bit Masks */
1415 #define IXGBE_RSCDBU_RSCSMALDIS_MASK    0x0000007F
1416 #define IXGBE_RSCDBU_RSCACKDIS          0x00000080
1417
1418 /* RDRXCTL Bit Masks */
1419 #define IXGBE_RDRXCTL_RDMTS_1_2         0x00000000 /* Rx Desc Min THLD Size */
1420 #define IXGBE_RDRXCTL_CRCSTRIP          0x00000002 /* CRC Strip */
1421 #define IXGBE_RDRXCTL_PSP               0x00000004 /* Pad Small Packet */
1422 #define IXGBE_RDRXCTL_MVMEN             0x00000020
1423 #define IXGBE_RDRXCTL_RSC_PUSH_DIS      0x00000020
1424 #define IXGBE_RDRXCTL_DMAIDONE          0x00000008 /* DMA init cycle done */
1425 #define IXGBE_RDRXCTL_RSC_PUSH          0x00000080
1426 #define IXGBE_RDRXCTL_AGGDIS            0x00010000 /* Aggregation disable */
1427 #define IXGBE_RDRXCTL_RSCFRSTSIZE       0x003E0000 /* RSC First packet size */
1428 #define IXGBE_RDRXCTL_RSCLLIDIS         0x00800000 /* Disable RSC compl on LLI*/
1429 #define IXGBE_RDRXCTL_RSCACKC           0x02000000 /* must set 1 when RSC ena */
1430 #define IXGBE_RDRXCTL_FCOE_WRFIX        0x04000000 /* must set 1 when RSC ena */
1431 #define IXGBE_RDRXCTL_MBINTEN           0x10000000
1432 #define IXGBE_RDRXCTL_MDP_EN            0x20000000
1433
1434 /* RQTC Bit Masks and Shifts */
1435 #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
1436 #define IXGBE_RQTC_TC0_MASK     (0x7 << 0)
1437 #define IXGBE_RQTC_TC1_MASK     (0x7 << 4)
1438 #define IXGBE_RQTC_TC2_MASK     (0x7 << 8)
1439 #define IXGBE_RQTC_TC3_MASK     (0x7 << 12)
1440 #define IXGBE_RQTC_TC4_MASK     (0x7 << 16)
1441 #define IXGBE_RQTC_TC5_MASK     (0x7 << 20)
1442 #define IXGBE_RQTC_TC6_MASK     (0x7 << 24)
1443 #define IXGBE_RQTC_TC7_MASK     (0x7 << 28)
1444
1445 /* PSRTYPE.RQPL Bit masks and shift */
1446 #define IXGBE_PSRTYPE_RQPL_MASK         0x7
1447 #define IXGBE_PSRTYPE_RQPL_SHIFT        29
1448
1449 /* CTRL Bit Masks */
1450 #define IXGBE_CTRL_GIO_DIS      0x00000004 /* Global IO Master Disable bit */
1451 #define IXGBE_CTRL_LNK_RST      0x00000008 /* Link Reset. Resets everything. */
1452 #define IXGBE_CTRL_RST          0x04000000 /* Reset (SW) */
1453 #define IXGBE_CTRL_RST_MASK     (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1454
1455 /* FACTPS */
1456 #define IXGBE_FACTPS_MNGCG      0x20000000 /* Manageblility Clock Gated */
1457 #define IXGBE_FACTPS_LFS        0x40000000 /* LAN Function Select */
1458
1459 /* MHADD Bit Masks */
1460 #define IXGBE_MHADD_MFS_MASK    0xFFFF0000
1461 #define IXGBE_MHADD_MFS_SHIFT   16
1462
1463 /* Extended Device Control */
1464 #define IXGBE_CTRL_EXT_PFRSTD   0x00004000 /* Physical Function Reset Done */
1465 #define IXGBE_CTRL_EXT_NS_DIS   0x00010000 /* No Snoop disable */
1466 #define IXGBE_CTRL_EXT_RO_DIS   0x00020000 /* Relaxed Ordering disable */
1467 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1468
1469 /* Direct Cache Access (DCA) definitions */
1470 #define IXGBE_DCA_CTRL_DCA_ENABLE       0x00000000 /* DCA Enable */
1471 #define IXGBE_DCA_CTRL_DCA_DISABLE      0x00000001 /* DCA Disable */
1472
1473 #define IXGBE_DCA_CTRL_DCA_MODE_CB1     0x00 /* DCA Mode CB1 */
1474 #define IXGBE_DCA_CTRL_DCA_MODE_CB2     0x02 /* DCA Mode CB2 */
1475
1476 #define IXGBE_DCA_RXCTRL_CPUID_MASK     0x0000001F /* Rx CPUID Mask */
1477 #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599       0xFF000000 /* Rx CPUID Mask */
1478 #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599      24 /* Rx CPUID Shift */
1479 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN    (1 << 5) /* Rx Desc enable */
1480 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN    (1 << 6) /* Rx Desc header ena */
1481 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN    (1 << 7) /* Rx Desc payload ena */
1482 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN    (1 << 9) /* Rx rd Desc Relax Order */
1483 #define IXGBE_DCA_RXCTRL_DATA_WRO_EN    (1 << 13) /* Rx wr data Relax Order */
1484 #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN    (1 << 15) /* Rx wr header RO */
1485
1486 #define IXGBE_DCA_TXCTRL_CPUID_MASK     0x0000001F /* Tx CPUID Mask */
1487 #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599       0xFF000000 /* Tx CPUID Mask */
1488 #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599      24 /* Tx CPUID Shift */
1489 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN    (1 << 5) /* DCA Tx Desc enable */
1490 #define IXGBE_DCA_TXCTRL_DESC_RRO_EN    (1 << 9) /* Tx rd Desc Relax Order */
1491 #define IXGBE_DCA_TXCTRL_DESC_WRO_EN    (1 << 11) /* Tx Desc writeback RO bit */
1492 #define IXGBE_DCA_TXCTRL_DATA_RRO_EN    (1 << 13) /* Tx rd data Relax Order */
1493 #define IXGBE_DCA_MAX_QUEUES_82598      16 /* DCA regs only on 16 queues */
1494
1495 /* MSCA Bit Masks */
1496 #define IXGBE_MSCA_NP_ADDR_MASK         0x0000FFFF /* MDI Addr (new prot) */
1497 #define IXGBE_MSCA_NP_ADDR_SHIFT        0
1498 #define IXGBE_MSCA_DEV_TYPE_MASK        0x001F0000 /* Dev Type (new prot) */
1499 #define IXGBE_MSCA_DEV_TYPE_SHIFT       16 /* Register Address (old prot */
1500 #define IXGBE_MSCA_PHY_ADDR_MASK        0x03E00000 /* PHY Address mask */
1501 #define IXGBE_MSCA_PHY_ADDR_SHIFT       21 /* PHY Address shift*/
1502 #define IXGBE_MSCA_OP_CODE_MASK         0x0C000000 /* OP CODE mask */
1503 #define IXGBE_MSCA_OP_CODE_SHIFT        26 /* OP CODE shift */
1504 #define IXGBE_MSCA_ADDR_CYCLE           0x00000000 /* OP CODE 00 (addr cycle) */
1505 #define IXGBE_MSCA_WRITE                0x04000000 /* OP CODE 01 (wr) */
1506 #define IXGBE_MSCA_READ                 0x0C000000 /* OP CODE 11 (rd) */
1507 #define IXGBE_MSCA_READ_AUTOINC         0x08000000 /* OP CODE 10 (rd auto inc)*/
1508 #define IXGBE_MSCA_ST_CODE_MASK         0x30000000 /* ST Code mask */
1509 #define IXGBE_MSCA_ST_CODE_SHIFT        28 /* ST Code shift */
1510 #define IXGBE_MSCA_NEW_PROTOCOL         0x00000000 /* ST CODE 00 (new prot) */
1511 #define IXGBE_MSCA_OLD_PROTOCOL         0x10000000 /* ST CODE 01 (old prot) */
1512 #define IXGBE_MSCA_MDI_COMMAND          0x40000000 /* Initiate MDI command */
1513 #define IXGBE_MSCA_MDI_IN_PROG_EN       0x80000000 /* MDI in progress ena */
1514
1515 /* MSRWD bit masks */
1516 #define IXGBE_MSRWD_WRITE_DATA_MASK     0x0000FFFF
1517 #define IXGBE_MSRWD_WRITE_DATA_SHIFT    0
1518 #define IXGBE_MSRWD_READ_DATA_MASK      0xFFFF0000
1519 #define IXGBE_MSRWD_READ_DATA_SHIFT     16
1520
1521 /* Atlas registers */
1522 #define IXGBE_ATLAS_PDN_LPBK            0x24
1523 #define IXGBE_ATLAS_PDN_10G             0xB
1524 #define IXGBE_ATLAS_PDN_1G              0xC
1525 #define IXGBE_ATLAS_PDN_AN              0xD
1526
1527 /* Atlas bit masks */
1528 #define IXGBE_ATLASCTL_WRITE_CMD        0x00010000
1529 #define IXGBE_ATLAS_PDN_TX_REG_EN       0x10
1530 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL   0xF0
1531 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL    0xF0
1532 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL    0xF0
1533
1534 /* Omer bit masks */
1535 #define IXGBE_CORECTL_WRITE_CMD         0x00010000
1536
1537 /* Device Type definitions for new protocol MDIO commands */
1538 #define IXGBE_MDIO_ZERO_DEV_TYPE                0x0
1539 #define IXGBE_MDIO_PMA_PMD_DEV_TYPE             0x1
1540 #define IXGBE_MDIO_PCS_DEV_TYPE                 0x3
1541 #define IXGBE_MDIO_PHY_XS_DEV_TYPE              0x4
1542 #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE            0x7
1543 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE   0x1E   /* Device 30 */
1544 #define IXGBE_TWINAX_DEV                        1
1545
1546 #define IXGBE_MDIO_COMMAND_TIMEOUT      100 /* PHY Timeout for 1 GB mode */
1547
1548 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL            0x0 /* VS1 Ctrl Reg */
1549 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS             0x1 /* VS1 Status Reg */
1550 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS        0x0008 /* 1 = Link Up */
1551 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS       0x0010 /* 0-10G, 1-1G */
1552 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED          0x0018
1553 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED           0x0010
1554
1555 #define IXGBE_MDIO_AUTO_NEG_CONTROL     0x0 /* AUTO_NEG Control Reg */
1556 #define IXGBE_MDIO_AUTO_NEG_STATUS      0x1 /* AUTO_NEG Status Reg */
1557 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT 0xC800 /* AUTO_NEG Vendor Status Reg */
1558 #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM 0xCC00 /* AUTO_NEG Vendor TX Reg */
1559 #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */
1560 #define IXGBE_MDIO_AUTO_NEG_VEN_LSC     0x1 /* AUTO_NEG Vendor Tx LSC */
1561 #define IXGBE_MDIO_AUTO_NEG_ADVT        0x10 /* AUTO_NEG Advt Reg */
1562 #define IXGBE_MDIO_AUTO_NEG_LP          0x13 /* AUTO_NEG LP Status Reg */
1563 #define IXGBE_MDIO_AUTO_NEG_EEE_ADVT    0x3C /* AUTO_NEG EEE Advt Reg */
1564 #define IXGBE_AUTO_NEG_10GBASE_EEE_ADVT 0x8  /* AUTO NEG EEE 10GBaseT Advt */
1565 #define IXGBE_AUTO_NEG_1000BASE_EEE_ADVT 0x4  /* AUTO NEG EEE 1000BaseT Advt */
1566 #define IXGBE_AUTO_NEG_100BASE_EEE_ADVT 0x2  /* AUTO NEG EEE 100BaseT Advt */
1567 #define IXGBE_MDIO_PHY_XS_CONTROL       0x0 /* PHY_XS Control Reg */
1568 #define IXGBE_MDIO_PHY_XS_RESET         0x8000 /* PHY_XS Reset */
1569 #define IXGBE_MDIO_PHY_ID_HIGH          0x2 /* PHY ID High Reg*/
1570 #define IXGBE_MDIO_PHY_ID_LOW           0x3 /* PHY ID Low Reg*/
1571 #define IXGBE_MDIO_PHY_SPEED_ABILITY    0x4 /* Speed Ability Reg */
1572 #define IXGBE_MDIO_PHY_SPEED_10G        0x0001 /* 10G capable */
1573 #define IXGBE_MDIO_PHY_SPEED_1G         0x0010 /* 1G capable */
1574 #define IXGBE_MDIO_PHY_SPEED_100M       0x0020 /* 100M capable */
1575 #define IXGBE_MDIO_PHY_EXT_ABILITY      0xB /* Ext Ability Reg */
1576 #define IXGBE_MDIO_PHY_10GBASET_ABILITY         0x0004 /* 10GBaseT capable */
1577 #define IXGBE_MDIO_PHY_1000BASET_ABILITY        0x0020 /* 1000BaseT capable */
1578 #define IXGBE_MDIO_PHY_100BASETX_ABILITY        0x0080 /* 100BaseTX capable */
1579 #define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE       0x0800 /* Set low power mode */
1580 #define IXGBE_AUTO_NEG_LP_STATUS        0xE820 /* AUTO NEG Rx LP Status Reg */
1581 #define IXGBE_AUTO_NEG_LP_1000BASE_CAP  0x8000 /* AUTO NEG Rx LP 1000BaseT Cap */
1582 #define IXGBE_AUTO_NEG_LP_10GBASE_CAP   0x0800 /* AUTO NEG Rx LP 10GBaseT Cap */
1583 #define IXGBE_AUTO_NEG_10GBASET_STAT    0x0021 /* AUTO NEG 10G BaseT Stat */
1584
1585 #define IXGBE_MDIO_TX_VENDOR_ALARMS_3           0xCC02 /* Vendor Alarms 3 Reg */
1586 #define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK  0x3 /* PHY Reset Complete Mask */
1587 #define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */
1588 #define IXGBE_MDIO_POWER_UP_STALL               0x8000 /* Power Up Stall */
1589 #define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK     0xFF00 /* int std mask */
1590 #define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG     0xFC00 /* chip std int flag */
1591 #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK     0xFF01 /* int chip-wide mask */
1592 #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG     0xFC01 /* int chip-wide mask */
1593 #define IXGBE_MDIO_GLOBAL_ALARM_1               0xCC00 /* Global alarm 1 */
1594 #define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT       0x0010 /* device fault */
1595 #define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL     0x4000 /* high temp failure */
1596 #define IXGBE_MDIO_GLOBAL_FAULT_MSG     0xC850 /* Global Fault Message */
1597 #define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP      0x8007 /* high temp failure */
1598 #define IXGBE_MDIO_GLOBAL_INT_MASK              0xD400 /* Global int mask */
1599 #define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN     0x1000 /* autoneg vendor alarm int enable */
1600 #define IXGBE_MDIO_GLOBAL_ALARM_1_INT           0x4 /* int in Global alarm 1 */
1601 #define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN        0x1 /* vendor alarm int enable */
1602 #define IXGBE_MDIO_GLOBAL_STD_ALM2_INT          0x200 /* vendor alarm2 int mask */
1603 #define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN        0x4000 /* int high temp enable */
1604 #define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN 0x0010 /* int dev fault enable */
1605 #define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */
1606 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
1607 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
1608 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
1609 #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */
1610 #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN   0x1 /* PHY TX Vendor LASI enable */
1611 #define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */
1612 #define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */
1613
1614 #define IXGBE_PCRC8ECL          0x0E810 /* PCR CRC-8 Error Count Lo */
1615 #define IXGBE_PCRC8ECH          0x0E811 /* PCR CRC-8 Error Count Hi */
1616 #define IXGBE_PCRC8ECH_MASK     0x1F
1617 #define IXGBE_LDPCECL           0x0E820 /* PCR Uncorrected Error Count Lo */
1618 #define IXGBE_LDPCECH           0x0E821 /* PCR Uncorrected Error Count Hi */
1619
1620 /* MII clause 22/28 definitions */
1621 #define IXGBE_MDIO_PHY_LOW_POWER_MODE   0x0800
1622
1623 #define IXGBE_MDIO_XENPAK_LASI_STATUS           0x9005 /* XENPAK LASI Status register*/
1624 #define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM     0x1 /* Link Status Alarm change */
1625
1626 #define IXGBE_MDIO_AUTO_NEG_LINK_STATUS         0x4 /* Indicates if link is up */
1627
1628 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK  0x7 /* Speed/Duplex Mask */
1629 #define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK         0x6 /* Speed Mask */
1630 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF      0x0 /* 10Mb/s Half Duplex */
1631 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL      0x1 /* 10Mb/s Full Duplex */
1632 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF     0x2 /* 100Mb/s Half Duplex */
1633 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL     0x3 /* 100Mb/s Full Duplex */
1634 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF      0x4 /* 1Gb/s Half Duplex */
1635 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL      0x5 /* 1Gb/s Full Duplex */
1636 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF     0x6 /* 10Gb/s Half Duplex */
1637 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL     0x7 /* 10Gb/s Full Duplex */
1638 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB           0x4 /* 1Gb/s */
1639 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB          0x6 /* 10Gb/s */
1640
1641 #define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG    0x20   /* 10G Control Reg */
1642 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
1643 #define IXGBE_MII_AUTONEG_XNP_TX_REG            0x17   /* 1G XNP Transmit */
1644 #define IXGBE_MII_AUTONEG_ADVERTISE_REG         0x10   /* 100M Advertisement */
1645 #define IXGBE_MII_10GBASE_T_ADVERTISE           0x1000 /* full duplex, bit:12*/
1646 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX     0x4000 /* full duplex, bit:14*/
1647 #define IXGBE_MII_1GBASE_T_ADVERTISE            0x8000 /* full duplex, bit:15*/
1648 #define IXGBE_MII_2_5GBASE_T_ADVERTISE          0x0400
1649 #define IXGBE_MII_5GBASE_T_ADVERTISE            0x0800
1650 #define IXGBE_MII_100BASE_T_ADVERTISE           0x0100 /* full duplex, bit:8 */
1651 #define IXGBE_MII_100BASE_T_ADVERTISE_HALF      0x0080 /* half duplex, bit:7 */
1652 #define IXGBE_MII_RESTART                       0x200
1653 #define IXGBE_MII_AUTONEG_COMPLETE              0x20
1654 #define IXGBE_MII_AUTONEG_LINK_UP               0x04
1655 #define IXGBE_MII_AUTONEG_REG                   0x0
1656
1657 #define IXGBE_PHY_REVISION_MASK         0xFFFFFFF0
1658 #define IXGBE_MAX_PHY_ADDR              32
1659
1660 /* PHY IDs*/
1661 #define TN1010_PHY_ID   0x00A19410
1662 #define TNX_FW_REV      0xB
1663 #define X540_PHY_ID     0x01540200
1664 #define X550_PHY_ID2    0x01540223
1665 #define X550_PHY_ID3    0x01540221
1666 #define X557_PHY_ID     0x01540240
1667 #define X557_PHY_ID2    0x01540250
1668 #define AQ_FW_REV       0x20
1669 #define QT2022_PHY_ID   0x0043A400
1670 #define ATH_PHY_ID      0x03429050
1671
1672 /* PHY Types */
1673 #define IXGBE_M88E1500_E_PHY_ID 0x01410DD0
1674 #define IXGBE_M88E1543_E_PHY_ID 0x01410EA0
1675
1676 /* Special PHY Init Routine */
1677 #define IXGBE_PHY_INIT_OFFSET_NL        0x002B
1678 #define IXGBE_PHY_INIT_END_NL           0xFFFF
1679 #define IXGBE_CONTROL_MASK_NL           0xF000
1680 #define IXGBE_DATA_MASK_NL              0x0FFF
1681 #define IXGBE_CONTROL_SHIFT_NL          12
1682 #define IXGBE_DELAY_NL                  0
1683 #define IXGBE_DATA_NL                   1
1684 #define IXGBE_CONTROL_NL                0x000F
1685 #define IXGBE_CONTROL_EOL_NL            0x0FFF
1686 #define IXGBE_CONTROL_SOL_NL            0x0000
1687
1688 /* General purpose Interrupt Enable */
1689 #define IXGBE_SDP0_GPIEN        0x00000001 /* SDP0 */
1690 #define IXGBE_SDP1_GPIEN        0x00000002 /* SDP1 */
1691 #define IXGBE_SDP2_GPIEN        0x00000004 /* SDP2 */
1692 #define IXGBE_SDP0_GPIEN_X540   0x00000002 /* SDP0 on X540 and X550 */
1693 #define IXGBE_SDP1_GPIEN_X540   0x00000004 /* SDP1 on X540 and X550 */
1694 #define IXGBE_SDP2_GPIEN_X540   0x00000008 /* SDP2 on X540 and X550 */
1695 #define IXGBE_SDP0_GPIEN_X550   IXGBE_SDP0_GPIEN_X540
1696 #define IXGBE_SDP1_GPIEN_X550   IXGBE_SDP1_GPIEN_X540
1697 #define IXGBE_SDP2_GPIEN_X550   IXGBE_SDP2_GPIEN_X540
1698 #define IXGBE_SDP0_GPIEN_X550EM_x       IXGBE_SDP0_GPIEN_X540
1699 #define IXGBE_SDP1_GPIEN_X550EM_x       IXGBE_SDP1_GPIEN_X540
1700 #define IXGBE_SDP2_GPIEN_X550EM_x       IXGBE_SDP2_GPIEN_X540
1701 #define IXGBE_SDP0_GPIEN_X550EM_a       IXGBE_SDP0_GPIEN_X540
1702 #define IXGBE_SDP1_GPIEN_X550EM_a       IXGBE_SDP1_GPIEN_X540
1703 #define IXGBE_SDP2_GPIEN_X550EM_a       IXGBE_SDP2_GPIEN_X540
1704 #define IXGBE_SDP0_GPIEN_BY_MAC(_hw)    IXGBE_BY_MAC((_hw), SDP0_GPIEN)
1705 #define IXGBE_SDP1_GPIEN_BY_MAC(_hw)    IXGBE_BY_MAC((_hw), SDP1_GPIEN)
1706 #define IXGBE_SDP2_GPIEN_BY_MAC(_hw)    IXGBE_BY_MAC((_hw), SDP2_GPIEN)
1707
1708 #define IXGBE_GPIE_MSIX_MODE    0x00000010 /* MSI-X mode */
1709 #define IXGBE_GPIE_OCD          0x00000020 /* Other Clear Disable */
1710 #define IXGBE_GPIE_EIMEN        0x00000040 /* Immediate Interrupt Enable */
1711 #define IXGBE_GPIE_EIAME        0x40000000
1712 #define IXGBE_GPIE_PBA_SUPPORT  0x80000000
1713 #define IXGBE_GPIE_RSC_DELAY_SHIFT      11
1714 #define IXGBE_GPIE_VTMODE_MASK  0x0000C000 /* VT Mode Mask */
1715 #define IXGBE_GPIE_VTMODE_16    0x00004000 /* 16 VFs 8 queues per VF */
1716 #define IXGBE_GPIE_VTMODE_32    0x00008000 /* 32 VFs 4 queues per VF */
1717 #define IXGBE_GPIE_VTMODE_64    0x0000C000 /* 64 VFs 2 queues per VF */
1718
1719 /* Packet Buffer Initialization */
1720 #define IXGBE_MAX_PACKET_BUFFERS        8
1721
1722 #define IXGBE_TXPBSIZE_20KB     0x00005000 /* 20KB Packet Buffer */
1723 #define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
1724 #define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
1725 #define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
1726 #define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
1727 #define IXGBE_RXPBSIZE_128KB    0x00020000 /* 128KB Packet Buffer */
1728 #define IXGBE_RXPBSIZE_MAX      0x00080000 /* 512KB Packet Buffer */
1729 #define IXGBE_TXPBSIZE_MAX      0x00028000 /* 160KB Packet Buffer */
1730
1731 #define IXGBE_TXPKT_SIZE_MAX    0xA /* Max Tx Packet size */
1732 #define IXGBE_MAX_PB            8
1733
1734 /* Packet buffer allocation strategies */
1735 enum {
1736         PBA_STRATEGY_EQUAL      = 0, /* Distribute PB space equally */
1737 #define PBA_STRATEGY_EQUAL      PBA_STRATEGY_EQUAL
1738         PBA_STRATEGY_WEIGHTED   = 1, /* Weight front half of TCs */
1739 #define PBA_STRATEGY_WEIGHTED   PBA_STRATEGY_WEIGHTED
1740 };
1741
1742 /* Transmit Flow Control status */
1743 #define IXGBE_TFCS_TXOFF        0x00000001
1744 #define IXGBE_TFCS_TXOFF0       0x00000100
1745 #define IXGBE_TFCS_TXOFF1       0x00000200
1746 #define IXGBE_TFCS_TXOFF2       0x00000400
1747 #define IXGBE_TFCS_TXOFF3       0x00000800
1748 #define IXGBE_TFCS_TXOFF4       0x00001000
1749 #define IXGBE_TFCS_TXOFF5       0x00002000
1750 #define IXGBE_TFCS_TXOFF6       0x00004000
1751 #define IXGBE_TFCS_TXOFF7       0x00008000
1752
1753 /* TCP Timer */
1754 #define IXGBE_TCPTIMER_KS               0x00000100
1755 #define IXGBE_TCPTIMER_COUNT_ENABLE     0x00000200
1756 #define IXGBE_TCPTIMER_COUNT_FINISH     0x00000400
1757 #define IXGBE_TCPTIMER_LOOP             0x00000800
1758 #define IXGBE_TCPTIMER_DURATION_MASK    0x000000FF
1759
1760 /* HLREG0 Bit Masks */
1761 #define IXGBE_HLREG0_TXCRCEN            0x00000001 /* bit  0 */
1762 #define IXGBE_HLREG0_RXCRCSTRP          0x00000002 /* bit  1 */
1763 #define IXGBE_HLREG0_JUMBOEN            0x00000004 /* bit  2 */
1764 #define IXGBE_HLREG0_TXPADEN            0x00000400 /* bit 10 */
1765 #define IXGBE_HLREG0_TXPAUSEEN          0x00001000 /* bit 12 */
1766 #define IXGBE_HLREG0_RXPAUSEEN          0x00004000 /* bit 14 */
1767 #define IXGBE_HLREG0_LPBK               0x00008000 /* bit 15 */
1768 #define IXGBE_HLREG0_MDCSPD             0x00010000 /* bit 16 */
1769 #define IXGBE_HLREG0_CONTMDC            0x00020000 /* bit 17 */
1770 #define IXGBE_HLREG0_CTRLFLTR           0x00040000 /* bit 18 */
1771 #define IXGBE_HLREG0_PREPEND            0x00F00000 /* bits 20-23 */
1772 #define IXGBE_HLREG0_PRIPAUSEEN         0x01000000 /* bit 24 */
1773 #define IXGBE_HLREG0_RXPAUSERECDA       0x06000000 /* bits 25-26 */
1774 #define IXGBE_HLREG0_RXLNGTHERREN       0x08000000 /* bit 27 */
1775 #define IXGBE_HLREG0_RXPADSTRIPEN       0x10000000 /* bit 28 */
1776
1777 /* VMD_CTL bitmasks */
1778 #define IXGBE_VMD_CTL_VMDQ_EN           0x00000001
1779 #define IXGBE_VMD_CTL_VMDQ_FILTER       0x00000002
1780
1781 /* VT_CTL bitmasks */
1782 #define IXGBE_VT_CTL_DIS_DEFPL          0x20000000 /* disable default pool */
1783 #define IXGBE_VT_CTL_REPLEN             0x40000000 /* replication enabled */
1784 #define IXGBE_VT_CTL_VT_ENABLE          0x00000001  /* Enable VT Mode */
1785 #define IXGBE_VT_CTL_POOL_SHIFT         7
1786 #define IXGBE_VT_CTL_POOL_MASK          (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1787
1788 /* VMOLR bitmasks */
1789 #define IXGBE_VMOLR_UPE         0x00400000 /* unicast promiscuous */
1790 #define IXGBE_VMOLR_VPE         0x00800000 /* VLAN promiscuous */
1791 #define IXGBE_VMOLR_AUPE        0x01000000 /* accept untagged packets */
1792 #define IXGBE_VMOLR_ROMPE       0x02000000 /* accept packets in MTA tbl */
1793 #define IXGBE_VMOLR_ROPE        0x04000000 /* accept packets in UC tbl */
1794 #define IXGBE_VMOLR_BAM         0x08000000 /* accept broadcast packets */
1795 #define IXGBE_VMOLR_MPE         0x10000000 /* multicast promiscuous */
1796
1797 /* VFRE bitmask */
1798 #define IXGBE_VFRE_ENABLE_ALL   0xFFFFFFFF
1799
1800 #define IXGBE_VF_INIT_TIMEOUT   200 /* Number of retries to clear RSTI */
1801
1802 /* RDHMPN and TDHMPN bitmasks */
1803 #define IXGBE_RDHMPN_RDICADDR           0x007FF800
1804 #define IXGBE_RDHMPN_RDICRDREQ          0x00800000
1805 #define IXGBE_RDHMPN_RDICADDR_SHIFT     11
1806 #define IXGBE_TDHMPN_TDICADDR           0x003FF800
1807 #define IXGBE_TDHMPN_TDICRDREQ          0x00800000
1808 #define IXGBE_TDHMPN_TDICADDR_SHIFT     11
1809
1810 #define IXGBE_RDMAM_MEM_SEL_SHIFT               13
1811 #define IXGBE_RDMAM_DWORD_SHIFT                 9
1812 #define IXGBE_RDMAM_DESC_COMP_FIFO              1
1813 #define IXGBE_RDMAM_DFC_CMD_FIFO                2
1814 #define IXGBE_RDMAM_RSC_HEADER_ADDR             3
1815 #define IXGBE_RDMAM_TCN_STATUS_RAM              4
1816 #define IXGBE_RDMAM_WB_COLL_FIFO                5
1817 #define IXGBE_RDMAM_QSC_CNT_RAM                 6
1818 #define IXGBE_RDMAM_QSC_FCOE_RAM                7
1819 #define IXGBE_RDMAM_QSC_QUEUE_CNT               8
1820 #define IXGBE_RDMAM_QSC_QUEUE_RAM               0xA
1821 #define IXGBE_RDMAM_QSC_RSC_RAM                 0xB
1822 #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE         135
1823 #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT         4
1824 #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE          48
1825 #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT          7
1826 #define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE       32
1827 #define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT       4
1828 #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE        256
1829 #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT        9
1830 #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE          8
1831 #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT          4
1832 #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE           64
1833 #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT           4
1834 #define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE          512
1835 #define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT          5
1836 #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE         32
1837 #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT         4
1838 #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE         128
1839 #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT         8
1840 #define IXGBE_RDMAM_QSC_RSC_RAM_RANGE           32
1841 #define IXGBE_RDMAM_QSC_RSC_RAM_COUNT           8
1842
1843 #define IXGBE_TXDESCIC_READY    0x80000000
1844
1845 /* Receive Checksum Control */
1846 #define IXGBE_RXCSUM_IPPCSE     0x00001000 /* IP payload checksum enable */
1847 #define IXGBE_RXCSUM_PCSD       0x00002000 /* packet checksum disabled */
1848
1849 /* FCRTL Bit Masks */
1850 #define IXGBE_FCRTL_XONE        0x80000000 /* XON enable */
1851 #define IXGBE_FCRTH_FCEN        0x80000000 /* Packet buffer fc enable */
1852
1853 /* PAP bit masks*/
1854 #define IXGBE_PAP_TXPAUSECNT_MASK       0x0000FFFF /* Pause counter mask */
1855
1856 /* RMCS Bit Masks */
1857 #define IXGBE_RMCS_RRM                  0x00000002 /* Rx Recycle Mode enable */
1858 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */
1859 #define IXGBE_RMCS_RAC                  0x00000004
1860 /* Deficit Fixed Prio ena */
1861 #define IXGBE_RMCS_DFP                  IXGBE_RMCS_RAC
1862 #define IXGBE_RMCS_TFCE_802_3X          0x00000008 /* Tx Priority FC ena */
1863 #define IXGBE_RMCS_TFCE_PRIORITY        0x00000010 /* Tx Priority FC ena */
1864 #define IXGBE_RMCS_ARBDIS               0x00000040 /* Arbitration disable bit */
1865
1866 /* FCCFG Bit Masks */
1867 #define IXGBE_FCCFG_TFCE_802_3X         0x00000008 /* Tx link FC enable */
1868 #define IXGBE_FCCFG_TFCE_PRIORITY       0x00000010 /* Tx priority FC enable */
1869
1870 /* Interrupt register bitmasks */
1871
1872 /* Extended Interrupt Cause Read */
1873 #define IXGBE_EICR_RTX_QUEUE    0x0000FFFF /* RTx Queue Interrupt */
1874 #define IXGBE_EICR_FLOW_DIR     0x00010000 /* FDir Exception */
1875 #define IXGBE_EICR_RX_MISS      0x00020000 /* Packet Buffer Overrun */
1876 #define IXGBE_EICR_PCI          0x00040000 /* PCI Exception */
1877 #define IXGBE_EICR_MAILBOX      0x00080000 /* VF to PF Mailbox Interrupt */
1878 #define IXGBE_EICR_LSC          0x00100000 /* Link Status Change */
1879 #define IXGBE_EICR_LINKSEC      0x00200000 /* PN Threshold */
1880 #define IXGBE_EICR_MNG          0x00400000 /* Manageability Event Interrupt */
1881 #define IXGBE_EICR_TS           0x00800000 /* Thermal Sensor Event */
1882 #define IXGBE_EICR_TIMESYNC     0x01000000 /* Timesync Event */
1883 #define IXGBE_EICR_GPI_SDP0     0x01000000 /* Gen Purpose Interrupt on SDP0 */
1884 #define IXGBE_EICR_GPI_SDP1     0x02000000 /* Gen Purpose Interrupt on SDP1 */
1885 #define IXGBE_EICR_GPI_SDP2     0x04000000 /* Gen Purpose Interrupt on SDP2 */
1886 #define IXGBE_EICR_ECC          0x10000000 /* ECC Error */
1887 #define IXGBE_EICR_GPI_SDP0_X540 0x02000000 /* Gen Purpose Interrupt on SDP0 */
1888 #define IXGBE_EICR_GPI_SDP1_X540 0x04000000 /* Gen Purpose Interrupt on SDP1 */
1889 #define IXGBE_EICR_GPI_SDP2_X540 0x08000000 /* Gen Purpose Interrupt on SDP2 */
1890 #define IXGBE_EICR_GPI_SDP0_X550        IXGBE_EICR_GPI_SDP0_X540
1891 #define IXGBE_EICR_GPI_SDP1_X550        IXGBE_EICR_GPI_SDP1_X540
1892 #define IXGBE_EICR_GPI_SDP2_X550        IXGBE_EICR_GPI_SDP2_X540
1893 #define IXGBE_EICR_GPI_SDP0_X550EM_x    IXGBE_EICR_GPI_SDP0_X540
1894 #define IXGBE_EICR_GPI_SDP1_X550EM_x    IXGBE_EICR_GPI_SDP1_X540
1895 #define IXGBE_EICR_GPI_SDP2_X550EM_x    IXGBE_EICR_GPI_SDP2_X540
1896 #define IXGBE_EICR_GPI_SDP0_X550EM_a    IXGBE_EICR_GPI_SDP0_X540
1897 #define IXGBE_EICR_GPI_SDP1_X550EM_a    IXGBE_EICR_GPI_SDP1_X540
1898 #define IXGBE_EICR_GPI_SDP2_X550EM_a    IXGBE_EICR_GPI_SDP2_X540
1899 #define IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP0)
1900 #define IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP1)
1901 #define IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP2)
1902
1903 #define IXGBE_EICR_PBUR         0x10000000 /* Packet Buffer Handler Error */
1904 #define IXGBE_EICR_DHER         0x20000000 /* Descriptor Handler Error */
1905 #define IXGBE_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
1906 #define IXGBE_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
1907
1908 /* Extended Interrupt Cause Set */
1909 #define IXGBE_EICS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1910 #define IXGBE_EICS_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1911 #define IXGBE_EICS_RX_MISS      IXGBE_EICR_RX_MISS   /* Pkt Buffer Overrun */
1912 #define IXGBE_EICS_PCI          IXGBE_EICR_PCI /* PCI Exception */
1913 #define IXGBE_EICS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1914 #define IXGBE_EICS_LSC          IXGBE_EICR_LSC /* Link Status Change */
1915 #define IXGBE_EICS_MNG          IXGBE_EICR_MNG /* MNG Event Interrupt */
1916 #define IXGBE_EICS_TIMESYNC     IXGBE_EICR_TIMESYNC /* Timesync Event */
1917 #define IXGBE_EICS_GPI_SDP0     IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1918 #define IXGBE_EICS_GPI_SDP1     IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1919 #define IXGBE_EICS_GPI_SDP2     IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1920 #define IXGBE_EICS_ECC          IXGBE_EICR_ECC /* ECC Error */
1921 #define IXGBE_EICS_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)
1922 #define IXGBE_EICS_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)
1923 #define IXGBE_EICS_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)
1924 #define IXGBE_EICS_PBUR         IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1925 #define IXGBE_EICS_DHER         IXGBE_EICR_DHER /* Desc Handler Error */
1926 #define IXGBE_EICS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1927 #define IXGBE_EICS_OTHER        IXGBE_EICR_OTHER /* INT Cause Active */
1928
1929 /* Extended Interrupt Mask Set */
1930 #define IXGBE_EIMS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1931 #define IXGBE_EIMS_FLOW_DIR     IXGBE_EICR_FLOW_DIR /* FDir Exception */
1932 #define IXGBE_EIMS_RX_MISS      IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1933 #define IXGBE_EIMS_PCI          IXGBE_EICR_PCI /* PCI Exception */
1934 #define IXGBE_EIMS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1935 #define IXGBE_EIMS_LSC          IXGBE_EICR_LSC /* Link Status Change */
1936 #define IXGBE_EIMS_MNG          IXGBE_EICR_MNG /* MNG Event Interrupt */
1937 #define IXGBE_EIMS_TS           IXGBE_EICR_TS /* Thermal Sensor Event */
1938 #define IXGBE_EIMS_TIMESYNC     IXGBE_EICR_TIMESYNC /* Timesync Event */
1939 #define IXGBE_EIMS_GPI_SDP0     IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1940 #define IXGBE_EIMS_GPI_SDP1     IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1941 #define IXGBE_EIMS_GPI_SDP2     IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1942 #define IXGBE_EIMS_ECC          IXGBE_EICR_ECC /* ECC Error */
1943 #define IXGBE_EIMS_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)
1944 #define IXGBE_EIMS_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)
1945 #define IXGBE_EIMS_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)
1946 #define IXGBE_EIMS_PBUR         IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1947 #define IXGBE_EIMS_DHER         IXGBE_EICR_DHER /* Descr Handler Error */
1948 #define IXGBE_EIMS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1949 #define IXGBE_EIMS_OTHER        IXGBE_EICR_OTHER /* INT Cause Active */
1950
1951 /* Extended Interrupt Mask Clear */
1952 #define IXGBE_EIMC_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1953 #define IXGBE_EIMC_FLOW_DIR     IXGBE_EICR_FLOW_DIR /* FDir Exception */
1954 #define IXGBE_EIMC_RX_MISS      IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1955 #define IXGBE_EIMC_PCI          IXGBE_EICR_PCI /* PCI Exception */
1956 #define IXGBE_EIMC_MAILBOX      IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1957 #define IXGBE_EIMC_LSC          IXGBE_EICR_LSC /* Link Status Change */
1958 #define IXGBE_EIMC_MNG          IXGBE_EICR_MNG /* MNG Event Interrupt */
1959 #define IXGBE_EIMC_TIMESYNC     IXGBE_EICR_TIMESYNC /* Timesync Event */
1960 #define IXGBE_EIMC_GPI_SDP0     IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1961 #define IXGBE_EIMC_GPI_SDP1     IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1962 #define IXGBE_EIMC_GPI_SDP2     IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
1963 #define IXGBE_EIMC_ECC          IXGBE_EICR_ECC /* ECC Error */
1964 #define IXGBE_EIMC_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)
1965 #define IXGBE_EIMC_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)
1966 #define IXGBE_EIMC_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)
1967 #define IXGBE_EIMC_PBUR         IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1968 #define IXGBE_EIMC_DHER         IXGBE_EICR_DHER /* Desc Handler Err */
1969 #define IXGBE_EIMC_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1970 #define IXGBE_EIMC_OTHER        IXGBE_EICR_OTHER /* INT Cause Active */
1971
1972 #define IXGBE_EIMS_ENABLE_MASK ( \
1973                                 IXGBE_EIMS_RTX_QUEUE    | \
1974                                 IXGBE_EIMS_LSC          | \
1975                                 IXGBE_EIMS_TCP_TIMER    | \
1976                                 IXGBE_EIMS_OTHER)
1977
1978 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
1979 #define IXGBE_IMIR_PORT_IM_EN   0x00010000  /* TCP port enable */
1980 #define IXGBE_IMIR_PORT_BP      0x00020000  /* TCP port check bypass */
1981 #define IXGBE_IMIREXT_SIZE_BP   0x00001000  /* Packet size bypass */
1982 #define IXGBE_IMIREXT_CTRL_URG  0x00002000  /* Check URG bit in header */
1983 #define IXGBE_IMIREXT_CTRL_ACK  0x00004000  /* Check ACK bit in header */
1984 #define IXGBE_IMIREXT_CTRL_PSH  0x00008000  /* Check PSH bit in header */
1985 #define IXGBE_IMIREXT_CTRL_RST  0x00010000  /* Check RST bit in header */
1986 #define IXGBE_IMIREXT_CTRL_SYN  0x00020000  /* Check SYN bit in header */
1987 #define IXGBE_IMIREXT_CTRL_FIN  0x00040000  /* Check FIN bit in header */
1988 #define IXGBE_IMIREXT_CTRL_BP   0x00080000  /* Bypass check of control bits */
1989 #define IXGBE_IMIR_SIZE_BP_82599        0x00001000 /* Packet size bypass */
1990 #define IXGBE_IMIR_CTRL_URG_82599       0x00002000 /* Check URG bit in header */
1991 #define IXGBE_IMIR_CTRL_ACK_82599       0x00004000 /* Check ACK bit in header */
1992 #define IXGBE_IMIR_CTRL_PSH_82599       0x00008000 /* Check PSH bit in header */
1993 #define IXGBE_IMIR_CTRL_RST_82599       0x00010000 /* Check RST bit in header */
1994 #define IXGBE_IMIR_CTRL_SYN_82599       0x00020000 /* Check SYN bit in header */
1995 #define IXGBE_IMIR_CTRL_FIN_82599       0x00040000 /* Check FIN bit in header */
1996 #define IXGBE_IMIR_CTRL_BP_82599        0x00080000 /* Bypass chk of ctrl bits */
1997 #define IXGBE_IMIR_LLI_EN_82599         0x00100000 /* Enables low latency Int */
1998 #define IXGBE_IMIR_RX_QUEUE_MASK_82599  0x0000007F /* Rx Queue Mask */
1999 #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
2000 #define IXGBE_IMIRVP_PRIORITY_MASK      0x00000007 /* VLAN priority mask */
2001 #define IXGBE_IMIRVP_PRIORITY_EN        0x00000008 /* VLAN priority enable */
2002
2003 #define IXGBE_MAX_FTQF_FILTERS          128
2004 #define IXGBE_FTQF_PROTOCOL_MASK        0x00000003
2005 #define IXGBE_FTQF_PROTOCOL_TCP         0x00000000
2006 #define IXGBE_FTQF_PROTOCOL_UDP         0x00000001
2007 #define IXGBE_FTQF_PROTOCOL_SCTP        2
2008 #define IXGBE_FTQF_PRIORITY_MASK        0x00000007
2009 #define IXGBE_FTQF_PRIORITY_SHIFT       2
2010 #define IXGBE_FTQF_POOL_MASK            0x0000003F
2011 #define IXGBE_FTQF_POOL_SHIFT           8
2012 #define IXGBE_FTQF_5TUPLE_MASK_MASK     0x0000001F
2013 #define IXGBE_FTQF_5TUPLE_MASK_SHIFT    25
2014 #define IXGBE_FTQF_SOURCE_ADDR_MASK     0x1E
2015 #define IXGBE_FTQF_DEST_ADDR_MASK       0x1D
2016 #define IXGBE_FTQF_SOURCE_PORT_MASK     0x1B
2017 #define IXGBE_FTQF_DEST_PORT_MASK       0x17
2018 #define IXGBE_FTQF_PROTOCOL_COMP_MASK   0x0F
2019 #define IXGBE_FTQF_POOL_MASK_EN         0x40000000
2020 #define IXGBE_FTQF_QUEUE_ENABLE         0x80000000
2021
2022 /* Interrupt clear mask */
2023 #define IXGBE_IRQ_CLEAR_MASK    0xFFFFFFFF
2024
2025 /* Interrupt Vector Allocation Registers */
2026 #define IXGBE_IVAR_REG_NUM              25
2027 #define IXGBE_IVAR_REG_NUM_82599        64
2028 #define IXGBE_IVAR_TXRX_ENTRY           96
2029 #define IXGBE_IVAR_RX_ENTRY             64
2030 #define IXGBE_IVAR_RX_QUEUE(_i)         (0 + (_i))
2031 #define IXGBE_IVAR_TX_QUEUE(_i)         (64 + (_i))
2032 #define IXGBE_IVAR_TX_ENTRY             32
2033
2034 #define IXGBE_IVAR_TCP_TIMER_INDEX      96 /* 0 based index */
2035 #define IXGBE_IVAR_OTHER_CAUSES_INDEX   97 /* 0 based index */
2036
2037 #define IXGBE_MSIX_VECTOR(_i)           (0 + (_i))
2038
2039 #define IXGBE_IVAR_ALLOC_VAL            0x80 /* Interrupt Allocation valid */
2040
2041 /* ETYPE Queue Filter/Select Bit Masks */
2042 #define IXGBE_MAX_ETQF_FILTERS          8
2043 #define IXGBE_ETQF_FCOE                 0x08000000 /* bit 27 */
2044 #define IXGBE_ETQF_BCN                  0x10000000 /* bit 28 */
2045 #define IXGBE_ETQF_TX_ANTISPOOF         0x20000000 /* bit 29 */
2046 #define IXGBE_ETQF_1588                 0x40000000 /* bit 30 */
2047 #define IXGBE_ETQF_FILTER_EN            0x80000000 /* bit 31 */
2048 #define IXGBE_ETQF_POOL_ENABLE          (1 << 26) /* bit 26 */
2049 #define IXGBE_ETQF_POOL_SHIFT           20
2050
2051 #define IXGBE_ETQS_RX_QUEUE             0x007F0000 /* bits 22:16 */
2052 #define IXGBE_ETQS_RX_QUEUE_SHIFT       16
2053 #define IXGBE_ETQS_LLI                  0x20000000 /* bit 29 */
2054 #define IXGBE_ETQS_QUEUE_EN             0x80000000 /* bit 31 */
2055
2056 /*
2057  * ETQF filter list: one static filter per filter consumer. This is
2058  *                 to avoid filter collisions later. Add new filters
2059  *                 here!!
2060  *
2061  * Current filters:
2062  *      EAPOL 802.1x (0x888e): Filter 0
2063  *      FCoE (0x8906):   Filter 2
2064  *      1588 (0x88f7):   Filter 3
2065  *      FIP  (0x8914):   Filter 4
2066  *      LLDP (0x88CC):   Filter 5
2067  *      LACP (0x8809):   Filter 6
2068  *      FC   (0x8808):   Filter 7
2069  */
2070 #define IXGBE_ETQF_FILTER_EAPOL         0
2071 #define IXGBE_ETQF_FILTER_FCOE          2
2072 #define IXGBE_ETQF_FILTER_1588          3
2073 #define IXGBE_ETQF_FILTER_FIP           4
2074 #define IXGBE_ETQF_FILTER_LLDP          5
2075 #define IXGBE_ETQF_FILTER_LACP          6
2076 #define IXGBE_ETQF_FILTER_FC            7
2077 /* VLAN Control Bit Masks */
2078 #define IXGBE_VLNCTRL_VET               0x0000FFFF  /* bits 0-15 */
2079 #define IXGBE_VLNCTRL_CFI               0x10000000  /* bit 28 */
2080 #define IXGBE_VLNCTRL_CFIEN             0x20000000  /* bit 29 */
2081 #define IXGBE_VLNCTRL_VFE               0x40000000  /* bit 30 */
2082 #define IXGBE_VLNCTRL_VME               0x80000000  /* bit 31 */
2083
2084 /* VLAN pool filtering masks */
2085 #define IXGBE_VLVF_VIEN                 0x80000000  /* filter is valid */
2086 #define IXGBE_VLVF_ENTRIES              64
2087 #define IXGBE_VLVF_VLANID_MASK          0x00000FFF
2088 /* Per VF Port VLAN insertion rules */
2089 #define IXGBE_VMVIR_VLANA_DEFAULT       0x40000000 /* Always use default VLAN */
2090 #define IXGBE_VMVIR_VLANA_NEVER         0x80000000 /* Never insert VLAN tag */
2091
2092 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE   0x8100  /* 802.1q protocol */
2093
2094 /* STATUS Bit Masks */
2095 #define IXGBE_STATUS_LAN_ID             0x0000000C /* LAN ID */
2096 #define IXGBE_STATUS_LAN_ID_SHIFT       2 /* LAN ID Shift*/
2097 #define IXGBE_STATUS_GIO                0x00080000 /* GIO Master Ena Status */
2098
2099 #define IXGBE_STATUS_LAN_ID_0   0x00000000 /* LAN ID 0 */
2100 #define IXGBE_STATUS_LAN_ID_1   0x00000004 /* LAN ID 1 */
2101
2102 /* ESDP Bit Masks */
2103 #define IXGBE_ESDP_SDP0         0x00000001 /* SDP0 Data Value */
2104 #define IXGBE_ESDP_SDP1         0x00000002 /* SDP1 Data Value */
2105 #define IXGBE_ESDP_SDP2         0x00000004 /* SDP2 Data Value */
2106 #define IXGBE_ESDP_SDP3         0x00000008 /* SDP3 Data Value */
2107 #define IXGBE_ESDP_SDP4         0x00000010 /* SDP4 Data Value */
2108 #define IXGBE_ESDP_SDP5         0x00000020 /* SDP5 Data Value */
2109 #define IXGBE_ESDP_SDP6         0x00000040 /* SDP6 Data Value */
2110 #define IXGBE_ESDP_SDP7         0x00000080 /* SDP7 Data Value */
2111 #define IXGBE_ESDP_SDP0_DIR     0x00000100 /* SDP0 IO direction */
2112 #define IXGBE_ESDP_SDP1_DIR     0x00000200 /* SDP1 IO direction */
2113 #define IXGBE_ESDP_SDP2_DIR     0x00000400 /* SDP1 IO direction */
2114 #define IXGBE_ESDP_SDP3_DIR     0x00000800 /* SDP3 IO direction */
2115 #define IXGBE_ESDP_SDP4_DIR     0x00001000 /* SDP4 IO direction */
2116 #define IXGBE_ESDP_SDP5_DIR     0x00002000 /* SDP5 IO direction */
2117 #define IXGBE_ESDP_SDP6_DIR     0x00004000 /* SDP6 IO direction */
2118 #define IXGBE_ESDP_SDP7_DIR     0x00008000 /* SDP7 IO direction */
2119 #define IXGBE_ESDP_SDP0_NATIVE  0x00010000 /* SDP0 IO mode */
2120 #define IXGBE_ESDP_SDP1_NATIVE  0x00020000 /* SDP1 IO mode */
2121
2122
2123 /* LEDCTL Bit Masks */
2124 #define IXGBE_LED_IVRT_BASE             0x00000040
2125 #define IXGBE_LED_BLINK_BASE            0x00000080
2126 #define IXGBE_LED_MODE_MASK_BASE        0x0000000F
2127 #define IXGBE_LED_OFFSET(_base, _i)     (_base << (8 * (_i)))
2128 #define IXGBE_LED_MODE_SHIFT(_i)        (8*(_i))
2129 #define IXGBE_LED_IVRT(_i)      IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
2130 #define IXGBE_LED_BLINK(_i)     IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
2131 #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
2132 #define IXGBE_X557_LED_MANUAL_SET_MASK  (1 << 8)
2133 #define IXGBE_X557_MAX_LED_INDEX        3
2134 #define IXGBE_X557_LED_PROVISIONING     0xC430
2135
2136 /* LED modes */
2137 #define IXGBE_LED_LINK_UP       0x0
2138 #define IXGBE_LED_LINK_10G      0x1
2139 #define IXGBE_LED_MAC           0x2
2140 #define IXGBE_LED_FILTER        0x3
2141 #define IXGBE_LED_LINK_ACTIVE   0x4
2142 #define IXGBE_LED_LINK_1G       0x5
2143 #define IXGBE_LED_ON            0xE
2144 #define IXGBE_LED_OFF           0xF
2145
2146 /* AUTOC Bit Masks */
2147 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
2148 #define IXGBE_AUTOC_KX4_SUPP    0x80000000
2149 #define IXGBE_AUTOC_KX_SUPP     0x40000000
2150 #define IXGBE_AUTOC_PAUSE       0x30000000
2151 #define IXGBE_AUTOC_ASM_PAUSE   0x20000000
2152 #define IXGBE_AUTOC_SYM_PAUSE   0x10000000
2153 #define IXGBE_AUTOC_RF          0x08000000
2154 #define IXGBE_AUTOC_PD_TMR      0x06000000
2155 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
2156 #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
2157 #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
2158 #define IXGBE_AUTOC_FECA        0x00040000
2159 #define IXGBE_AUTOC_FECR        0x00020000
2160 #define IXGBE_AUTOC_KR_SUPP     0x00010000
2161 #define IXGBE_AUTOC_AN_RESTART  0x00001000
2162 #define IXGBE_AUTOC_FLU         0x00000001
2163 #define IXGBE_AUTOC_LMS_SHIFT   13
2164 #define IXGBE_AUTOC_LMS_10G_SERIAL      (0x3 << IXGBE_AUTOC_LMS_SHIFT)
2165 #define IXGBE_AUTOC_LMS_KX4_KX_KR       (0x4 << IXGBE_AUTOC_LMS_SHIFT)
2166 #define IXGBE_AUTOC_LMS_SGMII_1G_100M   (0x5 << IXGBE_AUTOC_LMS_SHIFT)
2167 #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
2168 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
2169 #define IXGBE_AUTOC_LMS_MASK            (0x7 << IXGBE_AUTOC_LMS_SHIFT)
2170 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN   (0x0 << IXGBE_AUTOC_LMS_SHIFT)
2171 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN  (0x1 << IXGBE_AUTOC_LMS_SHIFT)
2172 #define IXGBE_AUTOC_LMS_1G_AN           (0x2 << IXGBE_AUTOC_LMS_SHIFT)
2173 #define IXGBE_AUTOC_LMS_KX4_AN          (0x4 << IXGBE_AUTOC_LMS_SHIFT)
2174 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN    (0x6 << IXGBE_AUTOC_LMS_SHIFT)
2175 #define IXGBE_AUTOC_LMS_ATTACH_TYPE     (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2176
2177 #define IXGBE_AUTOC_1G_PMA_PMD_MASK     0x00000200
2178 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT    9
2179 #define IXGBE_AUTOC_10G_PMA_PMD_MASK    0x00000180
2180 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT   7
2181 #define IXGBE_AUTOC_10G_XAUI    (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2182 #define IXGBE_AUTOC_10G_KX4     (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2183 #define IXGBE_AUTOC_10G_CX4     (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2184 #define IXGBE_AUTOC_1G_BX       (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2185 #define IXGBE_AUTOC_1G_KX       (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2186 #define IXGBE_AUTOC_1G_SFI      (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2187 #define IXGBE_AUTOC_1G_KX_BX    (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2188
2189 #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
2190 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK    0x00030000
2191 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT   16
2192 #define IXGBE_AUTOC2_10G_KR     (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
2193 #define IXGBE_AUTOC2_10G_XFI    (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
2194 #define IXGBE_AUTOC2_10G_SFI    (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
2195 #define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK    0x50000000
2196 #define IXGBE_AUTOC2_LINK_DISABLE_MASK          0x70000000
2197
2198 #define IXGBE_MACC_FLU          0x00000001
2199 #define IXGBE_MACC_FSV_10G      0x00030000
2200 #define IXGBE_MACC_FS           0x00040000
2201 #define IXGBE_MAC_RX2TX_LPBK    0x00000002
2202
2203 /* Veto Bit definiton */
2204 #define IXGBE_MMNGC_MNG_VETO    0x00000001
2205
2206 /* LINKS Bit Masks */
2207 #define IXGBE_LINKS_KX_AN_COMP  0x80000000
2208 #define IXGBE_LINKS_UP          0x40000000
2209 #define IXGBE_LINKS_SPEED       0x20000000
2210 #define IXGBE_LINKS_MODE        0x18000000
2211 #define IXGBE_LINKS_RX_MODE     0x06000000
2212 #define IXGBE_LINKS_TX_MODE     0x01800000
2213 #define IXGBE_LINKS_XGXS_EN     0x00400000
2214 #define IXGBE_LINKS_SGMII_EN    0x02000000
2215 #define IXGBE_LINKS_PCS_1G_EN   0x00200000
2216 #define IXGBE_LINKS_1G_AN_EN    0x00100000
2217 #define IXGBE_LINKS_KX_AN_IDLE  0x00080000
2218 #define IXGBE_LINKS_1G_SYNC     0x00040000
2219 #define IXGBE_LINKS_10G_ALIGN   0x00020000
2220 #define IXGBE_LINKS_10G_LANE_SYNC       0x00017000
2221 #define IXGBE_LINKS_TL_FAULT            0x00001000
2222 #define IXGBE_LINKS_SIGNAL              0x00000F00
2223
2224 #define IXGBE_LINKS_SPEED_NON_STD       0x08000000
2225 #define IXGBE_LINKS_SPEED_82599         0x30000000
2226 #define IXGBE_LINKS_SPEED_10G_82599     0x30000000
2227 #define IXGBE_LINKS_SPEED_1G_82599      0x20000000
2228 #define IXGBE_LINKS_SPEED_100_82599     0x10000000
2229 #define IXGBE_LINKS_SPEED_10_X550EM_A   0x00000000
2230 #define IXGBE_LINK_UP_TIME              90 /* 9.0 Seconds */
2231 #define IXGBE_AUTO_NEG_TIME             45 /* 4.5 Seconds */
2232
2233 #define IXGBE_LINKS2_AN_SUPPORTED       0x00000040
2234
2235 /* PCS1GLSTA Bit Masks */
2236 #define IXGBE_PCS1GLSTA_LINK_OK         1
2237 #define IXGBE_PCS1GLSTA_SYNK_OK         0x10
2238 #define IXGBE_PCS1GLSTA_AN_COMPLETE     0x10000
2239 #define IXGBE_PCS1GLSTA_AN_PAGE_RX      0x20000
2240 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT    0x40000
2241 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
2242 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS    0x100000
2243
2244 #define IXGBE_PCS1GANA_SYM_PAUSE        0x80
2245 #define IXGBE_PCS1GANA_ASM_PAUSE        0x100
2246
2247 /* PCS1GLCTL Bit Masks */
2248 #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */
2249 #define IXGBE_PCS1GLCTL_FLV_LINK_UP     1
2250 #define IXGBE_PCS1GLCTL_FORCE_LINK      0x20
2251 #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH  0x40
2252 #define IXGBE_PCS1GLCTL_AN_ENABLE       0x10000
2253 #define IXGBE_PCS1GLCTL_AN_RESTART      0x20000
2254
2255 /* ANLP1 Bit Masks */
2256 #define IXGBE_ANLP1_PAUSE               0x0C00
2257 #define IXGBE_ANLP1_SYM_PAUSE           0x0400
2258 #define IXGBE_ANLP1_ASM_PAUSE           0x0800
2259 #define IXGBE_ANLP1_AN_STATE_MASK       0x000f0000
2260
2261 /* SW Semaphore Register bitmasks */
2262 #define IXGBE_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
2263 #define IXGBE_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
2264 #define IXGBE_SWSM_WMNG         0x00000004 /* Wake MNG Clock */
2265 #define IXGBE_SWFW_REGSMP       0x80000000 /* Register Semaphore bit 31 */
2266
2267 /* SW_FW_SYNC/GSSR definitions */
2268 #define IXGBE_GSSR_EEP_SM               0x0001
2269 #define IXGBE_GSSR_PHY0_SM              0x0002
2270 #define IXGBE_GSSR_PHY1_SM              0x0004
2271 #define IXGBE_GSSR_MAC_CSR_SM           0x0008
2272 #define IXGBE_GSSR_FLASH_SM             0x0010
2273 #define IXGBE_GSSR_NVM_UPDATE_SM        0x0200
2274 #define IXGBE_GSSR_SW_MNG_SM            0x0400
2275 #define IXGBE_GSSR_TOKEN_SM     0x40000000 /* SW bit for shared access */
2276 #define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys and both I2Cs */
2277 #define IXGBE_GSSR_I2C_MASK     0x1800
2278 #define IXGBE_GSSR_NVM_PHY_MASK 0xF
2279
2280 /* FW Status register bitmask */
2281 #define IXGBE_FWSTS_FWRI        0x00000200 /* Firmware Reset Indication */
2282
2283 /* EEC Register */
2284 #define IXGBE_EEC_SK            0x00000001 /* EEPROM Clock */
2285 #define IXGBE_EEC_CS            0x00000002 /* EEPROM Chip Select */
2286 #define IXGBE_EEC_DI            0x00000004 /* EEPROM Data In */
2287 #define IXGBE_EEC_DO            0x00000008 /* EEPROM Data Out */
2288 #define IXGBE_EEC_FWE_MASK      0x00000030 /* FLASH Write Enable */
2289 #define IXGBE_EEC_FWE_DIS       0x00000010 /* Disable FLASH writes */
2290 #define IXGBE_EEC_FWE_EN        0x00000020 /* Enable FLASH writes */
2291 #define IXGBE_EEC_FWE_SHIFT     4
2292 #define IXGBE_EEC_REQ           0x00000040 /* EEPROM Access Request */
2293 #define IXGBE_EEC_GNT           0x00000080 /* EEPROM Access Grant */
2294 #define IXGBE_EEC_PRES          0x00000100 /* EEPROM Present */
2295 #define IXGBE_EEC_ARD           0x00000200 /* EEPROM Auto Read Done */
2296 #define IXGBE_EEC_FLUP          0x00800000 /* Flash update command */
2297 #define IXGBE_EEC_SEC1VAL       0x02000000 /* Sector 1 Valid */
2298 #define IXGBE_EEC_FLUDONE       0x04000000 /* Flash update done */
2299 /* EEPROM Addressing bits based on type (0-small, 1-large) */
2300 #define IXGBE_EEC_ADDR_SIZE     0x00000400
2301 #define IXGBE_EEC_SIZE          0x00007800 /* EEPROM Size */
2302 #define IXGBE_EERD_MAX_ADDR     0x00003FFF /* EERD alows 14 bits for addr. */
2303
2304 #define IXGBE_EEC_SIZE_SHIFT            11
2305 #define IXGBE_EEPROM_WORD_SIZE_SHIFT    6
2306 #define IXGBE_EEPROM_OPCODE_BITS        8
2307
2308 /* FLA Register */
2309 #define IXGBE_FLA_LOCKED        0x00000040
2310
2311 /* Part Number String Length */
2312 #define IXGBE_PBANUM_LENGTH     11
2313
2314 /* Checksum and EEPROM pointers */
2315 #define IXGBE_PBANUM_PTR_GUARD          0xFAFA
2316 #define IXGBE_EEPROM_CHECKSUM           0x3F
2317 #define IXGBE_EEPROM_SUM                0xBABA
2318 #define IXGBE_EEPROM_CTRL_4             0x45
2319 #define IXGBE_EE_CTRL_4_INST_ID         0x10
2320 #define IXGBE_EE_CTRL_4_INST_ID_SHIFT   4
2321 #define IXGBE_PCIE_ANALOG_PTR           0x03
2322 #define IXGBE_ATLAS0_CONFIG_PTR         0x04
2323 #define IXGBE_PHY_PTR                   0x04
2324 #define IXGBE_ATLAS1_CONFIG_PTR         0x05
2325 #define IXGBE_OPTION_ROM_PTR            0x05
2326 #define IXGBE_PCIE_GENERAL_PTR          0x06
2327 #define IXGBE_PCIE_CONFIG0_PTR          0x07
2328 #define IXGBE_PCIE_CONFIG1_PTR          0x08
2329 #define IXGBE_CORE0_PTR                 0x09
2330 #define IXGBE_CORE1_PTR                 0x0A
2331 #define IXGBE_MAC0_PTR                  0x0B
2332 #define IXGBE_MAC1_PTR                  0x0C
2333 #define IXGBE_CSR0_CONFIG_PTR           0x0D
2334 #define IXGBE_CSR1_CONFIG_PTR           0x0E
2335 #define IXGBE_PCIE_ANALOG_PTR_X550      0x02
2336 #define IXGBE_SHADOW_RAM_SIZE_X550      0x4000
2337 #define IXGBE_IXGBE_PCIE_GENERAL_SIZE   0x24
2338 #define IXGBE_PCIE_CONFIG_SIZE          0x08
2339 #define IXGBE_EEPROM_LAST_WORD          0x41
2340 #define IXGBE_FW_PTR                    0x0F
2341 #define IXGBE_PBANUM0_PTR               0x15
2342 #define IXGBE_PBANUM1_PTR               0x16
2343 #define IXGBE_ALT_MAC_ADDR_PTR          0x37
2344 #define IXGBE_FREE_SPACE_PTR            0X3E
2345
2346 /* External Thermal Sensor Config */
2347 #define IXGBE_ETS_CFG                   0x26
2348 #define IXGBE_ETS_LTHRES_DELTA_MASK     0x07C0
2349 #define IXGBE_ETS_LTHRES_DELTA_SHIFT    6
2350 #define IXGBE_ETS_TYPE_MASK             0x0038
2351 #define IXGBE_ETS_TYPE_SHIFT            3
2352 #define IXGBE_ETS_TYPE_EMC              0x000
2353 #define IXGBE_ETS_NUM_SENSORS_MASK      0x0007
2354 #define IXGBE_ETS_DATA_LOC_MASK         0x3C00
2355 #define IXGBE_ETS_DATA_LOC_SHIFT        10
2356 #define IXGBE_ETS_DATA_INDEX_MASK       0x0300
2357 #define IXGBE_ETS_DATA_INDEX_SHIFT      8
2358 #define IXGBE_ETS_DATA_HTHRESH_MASK     0x00FF
2359
2360 #define IXGBE_SAN_MAC_ADDR_PTR          0x28
2361 #define IXGBE_DEVICE_CAPS               0x2C
2362 #define IXGBE_82599_SERIAL_NUMBER_MAC_ADDR      0x11
2363 #define IXGBE_X550_SERIAL_NUMBER_MAC_ADDR       0x04
2364
2365 #define IXGBE_PCIE_MSIX_82599_CAPS      0x72
2366 #define IXGBE_MAX_MSIX_VECTORS_82599    0x40
2367 #define IXGBE_PCIE_MSIX_82598_CAPS      0x62
2368 #define IXGBE_MAX_MSIX_VECTORS_82598    0x13
2369
2370 /* MSI-X capability fields masks */
2371 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK     0x7FF
2372
2373 /* Legacy EEPROM word offsets */
2374 #define IXGBE_ISCSI_BOOT_CAPS           0x0033
2375 #define IXGBE_ISCSI_SETUP_PORT_0        0x0030
2376 #define IXGBE_ISCSI_SETUP_PORT_1        0x0034
2377
2378 /* EEPROM Commands - SPI */
2379 #define IXGBE_EEPROM_MAX_RETRY_SPI      5000 /* Max wait 5ms for RDY signal */
2380 #define IXGBE_EEPROM_STATUS_RDY_SPI     0x01
2381 #define IXGBE_EEPROM_READ_OPCODE_SPI    0x03  /* EEPROM read opcode */
2382 #define IXGBE_EEPROM_WRITE_OPCODE_SPI   0x02  /* EEPROM write opcode */
2383 #define IXGBE_EEPROM_A8_OPCODE_SPI      0x08  /* opcode bit-3 = addr bit-8 */
2384 #define IXGBE_EEPROM_WREN_OPCODE_SPI    0x06  /* EEPROM set Write Ena latch */
2385 /* EEPROM reset Write Enable latch */
2386 #define IXGBE_EEPROM_WRDI_OPCODE_SPI    0x04
2387 #define IXGBE_EEPROM_RDSR_OPCODE_SPI    0x05  /* EEPROM read Status reg */
2388 #define IXGBE_EEPROM_WRSR_OPCODE_SPI    0x01  /* EEPROM write Status reg */
2389 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20  /* EEPROM ERASE 4KB */
2390 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI        0xD8  /* EEPROM ERASE 64KB */
2391 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI        0xDB  /* EEPROM ERASE 256B */
2392
2393 /* EEPROM Read Register */
2394 #define IXGBE_EEPROM_RW_REG_DATA        16 /* data offset in EEPROM read reg */
2395 #define IXGBE_EEPROM_RW_REG_DONE        2 /* Offset to READ done bit */
2396 #define IXGBE_EEPROM_RW_REG_START       1 /* First bit to start operation */
2397 #define IXGBE_EEPROM_RW_ADDR_SHIFT      2 /* Shift to the address bits */
2398 #define IXGBE_NVM_POLL_WRITE            1 /* Flag for polling for wr complete */
2399 #define IXGBE_NVM_POLL_READ             0 /* Flag for polling for rd complete */
2400
2401 #define NVM_INIT_CTRL_3         0x38
2402 #define NVM_INIT_CTRL_3_LPLU    0x8
2403 #define NVM_INIT_CTRL_3_D10GMP_PORT0 0x40
2404 #define NVM_INIT_CTRL_3_D10GMP_PORT1 0x100
2405
2406 #define IXGBE_ETH_LENGTH_OF_ADDRESS     6
2407
2408 #define IXGBE_EEPROM_PAGE_SIZE_MAX      128
2409 #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT        256 /* words rd in burst */
2410 #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT        256 /* words wr in burst */
2411 #define IXGBE_EEPROM_CTRL_2             1 /* EEPROM CTRL word 2 */
2412 #define IXGBE_EEPROM_CCD_BIT            2
2413
2414 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
2415 #define IXGBE_EEPROM_GRANT_ATTEMPTS     1000 /* EEPROM attempts to gain grant */
2416 #endif
2417
2418 /* Number of 5 microseconds we wait for EERD read and
2419  * EERW write to complete */
2420 #define IXGBE_EERD_EEWR_ATTEMPTS        100000
2421
2422 /* # attempts we wait for flush update to complete */
2423 #define IXGBE_FLUDONE_ATTEMPTS          20000
2424
2425 #define IXGBE_PCIE_CTRL2                0x5   /* PCIe Control 2 Offset */
2426 #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE   0x8   /* Dummy Function Enable */
2427 #define IXGBE_PCIE_CTRL2_LAN_DISABLE    0x2   /* LAN PCI Disable */
2428 #define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1   /* LAN Disable Select */
2429
2430 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET         0x0
2431 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET         0x3
2432 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP         0x1
2433 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS         0x2
2434 #define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR       (1 << 7)
2435 #define IXGBE_FW_LESM_PARAMETERS_PTR            0x2
2436 #define IXGBE_FW_LESM_STATE_1                   0x1
2437 #define IXGBE_FW_LESM_STATE_ENABLED             0x8000 /* LESM Enable bit */
2438 #define IXGBE_FW_LESM_2_STATES_ENABLED_MASK     0x1F
2439 #define IXGBE_FW_LESM_2_STATES_ENABLED          0x12
2440 #define IXGBE_FW_LESM_STATE0_10G_ENABLED        0x6FFF
2441 #define IXGBE_FW_LESM_STATE1_10G_ENABLED        0x4FFF
2442 #define IXGBE_FW_LESM_STATE0_10G_DISABLED       0x0FFF
2443 #define IXGBE_FW_LESM_STATE1_10G_DISABLED       0x2FFF
2444 #define IXGBE_FW_LESM_PORT0_STATE0_OFFSET       0x2
2445 #define IXGBE_FW_LESM_PORT0_STATE1_OFFSET       0x3
2446 #define IXGBE_FW_LESM_PORT1_STATE0_OFFSET       0x6
2447 #define IXGBE_FW_LESM_PORT1_STATE1_OFFSET       0x7
2448 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR   0x4
2449 #define IXGBE_FW_PATCH_VERSION_4                0x7
2450 #define IXGBE_FCOE_IBA_CAPS_BLK_PTR             0x33 /* iSCSI/FCOE block */
2451 #define IXGBE_FCOE_IBA_CAPS_FCOE                0x20 /* FCOE flags */
2452 #define IXGBE_ISCSI_FCOE_BLK_PTR                0x17 /* iSCSI/FCOE block */
2453 #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET           0x0 /* FCOE flags */
2454 #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE           0x1 /* FCOE flags enable bit */
2455 #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR          0x27 /* Alt. SAN MAC block */
2456 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET      0x0 /* Alt SAN MAC capability */
2457 #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET     0x1 /* Alt SAN MAC 0 offset */
2458 #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET     0x4 /* Alt SAN MAC 1 offset */
2459 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET      0x7 /* Alt WWNN prefix offset */
2460 #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET      0x8 /* Alt WWPN prefix offset */
2461 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC      0x0 /* Alt SAN MAC exists */
2462 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN      0x1 /* Alt WWN base exists */
2463
2464 /* FW header offset */
2465 #define IXGBE_X540_FW_PASSTHROUGH_PATCH_CONFIG_PTR      0x4
2466 #define IXGBE_X540_FW_MODULE_MASK                       0x7FFF
2467 /* 4KB multiplier */
2468 #define IXGBE_X540_FW_MODULE_LENGTH                     0x1000
2469 /* version word 2 (month & day) */
2470 #define IXGBE_X540_FW_PATCH_VERSION_2           0x5
2471 /* version word 3 (silicon compatibility & year) */
2472 #define IXGBE_X540_FW_PATCH_VERSION_3           0x6
2473 /* version word 4 (major & minor numbers) */
2474 #define IXGBE_X540_FW_PATCH_VERSION_4           0x7
2475
2476 #define IXGBE_DEVICE_CAPS_WOL_PORT0_1   0x4 /* WoL supported on ports 0 & 1 */
2477 #define IXGBE_DEVICE_CAPS_WOL_PORT0     0x8 /* WoL supported on port 0 */
2478 #define IXGBE_DEVICE_CAPS_WOL_MASK      0xC /* Mask for WoL capabilities */
2479
2480 /* PCI Bus Info */
2481 #define IXGBE_PCI_DEVICE_STATUS         0xAA
2482 #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING     0x0020
2483 #define IXGBE_PCI_LINK_STATUS           0xB2
2484 #define IXGBE_PCI_DEVICE_CONTROL2       0xC8
2485 #define IXGBE_PCI_LINK_WIDTH            0x3F0
2486 #define IXGBE_PCI_LINK_WIDTH_1          0x10
2487 #define IXGBE_PCI_LINK_WIDTH_2          0x20
2488 #define IXGBE_PCI_LINK_WIDTH_4          0x40
2489 #define IXGBE_PCI_LINK_WIDTH_8          0x80
2490 #define IXGBE_PCI_LINK_SPEED            0xF
2491 #define IXGBE_PCI_LINK_SPEED_2500       0x1
2492 #define IXGBE_PCI_LINK_SPEED_5000       0x2
2493 #define IXGBE_PCI_LINK_SPEED_8000       0x3
2494 #define IXGBE_PCI_HEADER_TYPE_REGISTER  0x0E
2495 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
2496 #define IXGBE_PCI_DEVICE_CONTROL2_16ms  0x0005
2497
2498 #define IXGBE_PCIDEVCTRL2_TIMEO_MASK    0xf
2499 #define IXGBE_PCIDEVCTRL2_16_32ms_def   0x0
2500 #define IXGBE_PCIDEVCTRL2_50_100us      0x1
2501 #define IXGBE_PCIDEVCTRL2_1_2ms         0x2
2502 #define IXGBE_PCIDEVCTRL2_16_32ms       0x5
2503 #define IXGBE_PCIDEVCTRL2_65_130ms      0x6
2504 #define IXGBE_PCIDEVCTRL2_260_520ms     0x9
2505 #define IXGBE_PCIDEVCTRL2_1_2s          0xa
2506 #define IXGBE_PCIDEVCTRL2_4_8s          0xd
2507 #define IXGBE_PCIDEVCTRL2_17_34s        0xe
2508
2509 /* Number of 100 microseconds we wait for PCI Express master disable */
2510 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT        800
2511
2512 /* Check whether address is multicast. This is little-endian specific check.*/
2513 #define IXGBE_IS_MULTICAST(Address) \
2514                 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
2515
2516 /* Check whether an address is broadcast. */
2517 #define IXGBE_IS_BROADCAST(Address) \
2518                 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
2519                 (((u8 *)(Address))[1] == ((u8)0xff)))
2520
2521 /* RAH */
2522 #define IXGBE_RAH_VIND_MASK     0x003C0000
2523 #define IXGBE_RAH_VIND_SHIFT    18
2524 #define IXGBE_RAH_AV            0x80000000
2525 #define IXGBE_CLEAR_VMDQ_ALL    0xFFFFFFFF
2526
2527 /* Header split receive */
2528 #define IXGBE_RFCTL_ISCSI_DIS           0x00000001
2529 #define IXGBE_RFCTL_ISCSI_DWC_MASK      0x0000003E
2530 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT     1
2531 #define IXGBE_RFCTL_RSC_DIS             0x00000020
2532 #define IXGBE_RFCTL_NFSW_DIS            0x00000040
2533 #define IXGBE_RFCTL_NFSR_DIS            0x00000080
2534 #define IXGBE_RFCTL_NFS_VER_MASK        0x00000300
2535 #define IXGBE_RFCTL_NFS_VER_SHIFT       8
2536 #define IXGBE_RFCTL_NFS_VER_2           0
2537 #define IXGBE_RFCTL_NFS_VER_3           1
2538 #define IXGBE_RFCTL_NFS_VER_4           2
2539 #define IXGBE_RFCTL_IPV6_DIS            0x00000400
2540 #define IXGBE_RFCTL_IPV6_XSUM_DIS       0x00000800
2541 #define IXGBE_RFCTL_IPFRSP_DIS          0x00004000
2542 #define IXGBE_RFCTL_IPV6_EX_DIS         0x00010000
2543 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS    0x00020000
2544
2545 /* Transmit Config masks */
2546 #define IXGBE_TXDCTL_ENABLE             0x02000000 /* Ena specific Tx Queue */
2547 #define IXGBE_TXDCTL_SWFLSH             0x04000000 /* Tx Desc. wr-bk flushing */
2548 #define IXGBE_TXDCTL_WTHRESH_SHIFT      16 /* shift to WTHRESH bits */
2549 /* Enable short packet padding to 64 bytes */
2550 #define IXGBE_TX_PAD_ENABLE             0x00000400
2551 #define IXGBE_JUMBO_FRAME_ENABLE        0x00000004  /* Allow jumbo frames */
2552 /* This allows for 16K packets + 4k for vlan */
2553 #define IXGBE_MAX_FRAME_SZ              0x40040000
2554
2555 #define IXGBE_TDWBAL_HEAD_WB_ENABLE     0x1 /* Tx head write-back enable */
2556 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE   0x2 /* Tx seq# write-back enable */
2557
2558 /* Receive Config masks */
2559 #define IXGBE_RXCTRL_RXEN               0x00000001 /* Enable Receiver */
2560 #define IXGBE_RXCTRL_DMBYPS             0x00000002 /* Desc Monitor Bypass */
2561 #define IXGBE_RXDCTL_ENABLE             0x02000000 /* Ena specific Rx Queue */
2562 #define IXGBE_RXDCTL_SWFLSH             0x04000000 /* Rx Desc wr-bk flushing */
2563 #define IXGBE_RXDCTL_RLPMLMASK          0x00003FFF /* X540 supported only */
2564 #define IXGBE_RXDCTL_RLPML_EN           0x00008000
2565 #define IXGBE_RXDCTL_VME                0x40000000 /* VLAN mode enable */
2566
2567 #define IXGBE_TSAUXC_EN_CLK             0x00000004
2568 #define IXGBE_TSAUXC_SYNCLK             0x00000008
2569 #define IXGBE_TSAUXC_SDP0_INT           0x00000040
2570 #define IXGBE_TSAUXC_EN_TT0             0x00000001
2571 #define IXGBE_TSAUXC_EN_TT1             0x00000002
2572 #define IXGBE_TSAUXC_ST0                0x00000010
2573 #define IXGBE_TSAUXC_DISABLE_SYSTIME    0x80000000
2574
2575 #define IXGBE_TSSDP_TS_SDP0_SEL_MASK    0x000000C0
2576 #define IXGBE_TSSDP_TS_SDP0_CLK0        0x00000080
2577 #define IXGBE_TSSDP_TS_SDP0_EN          0x00000100
2578
2579 #define IXGBE_TSYNCTXCTL_VALID          0x00000001 /* Tx timestamp valid */
2580 #define IXGBE_TSYNCTXCTL_ENABLED        0x00000010 /* Tx timestamping enabled */
2581
2582 #define IXGBE_TSYNCRXCTL_VALID          0x00000001 /* Rx timestamp valid */
2583 #define IXGBE_TSYNCRXCTL_TYPE_MASK      0x0000000E /* Rx type mask */
2584 #define IXGBE_TSYNCRXCTL_TYPE_L2_V2     0x00
2585 #define IXGBE_TSYNCRXCTL_TYPE_L4_V1     0x02
2586 #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2  0x04
2587 #define IXGBE_TSYNCRXCTL_TYPE_ALL       0x08
2588 #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2  0x0A
2589 #define IXGBE_TSYNCRXCTL_ENABLED        0x00000010 /* Rx Timestamping enabled */
2590 #define IXGBE_TSYNCRXCTL_TSIP_UT_EN     0x00800000 /* Rx Timestamp in Packet */
2591 #define IXGBE_TSYNCRXCTL_TSIP_UP_MASK   0xFF000000 /* Rx Timestamp UP Mask */
2592
2593 #define IXGBE_TSIM_SYS_WRAP             0x00000001
2594 #define IXGBE_TSIM_TXTS                 0x00000002
2595 #define IXGBE_TSIM_TADJ                 0x00000080
2596
2597 #define IXGBE_TSICR_SYS_WRAP            IXGBE_TSIM_SYS_WRAP
2598 #define IXGBE_TSICR_TXTS                IXGBE_TSIM_TXTS
2599 #define IXGBE_TSICR_TADJ                IXGBE_TSIM_TADJ
2600
2601 #define IXGBE_RXMTRL_V1_CTRLT_MASK      0x000000FF
2602 #define IXGBE_RXMTRL_V1_SYNC_MSG        0x00
2603 #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG   0x01
2604 #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG    0x02
2605 #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG  0x03
2606 #define IXGBE_RXMTRL_V1_MGMT_MSG        0x04
2607
2608 #define IXGBE_RXMTRL_V2_MSGID_MASK      0x0000FF00
2609 #define IXGBE_RXMTRL_V2_SYNC_MSG        0x0000
2610 #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG   0x0100
2611 #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG  0x0200
2612 #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300
2613 #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG    0x0800
2614 #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG  0x0900
2615 #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00
2616 #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG    0x0B00
2617 #define IXGBE_RXMTRL_V2_SIGNALLING_MSG  0x0C00
2618 #define IXGBE_RXMTRL_V2_MGMT_MSG        0x0D00
2619
2620 #define IXGBE_FCTRL_SBP         0x00000002 /* Store Bad Packet */
2621 #define IXGBE_FCTRL_MPE         0x00000100 /* Multicast Promiscuous Ena*/
2622 #define IXGBE_FCTRL_UPE         0x00000200 /* Unicast Promiscuous Ena */
2623 #define IXGBE_FCTRL_BAM         0x00000400 /* Broadcast Accept Mode */
2624 #define IXGBE_FCTRL_PMCF        0x00001000 /* Pass MAC Control Frames */
2625 #define IXGBE_FCTRL_DPF         0x00002000 /* Discard Pause Frame */
2626 /* Receive Priority Flow Control Enable */
2627 #define IXGBE_FCTRL_RPFCE       0x00004000
2628 #define IXGBE_FCTRL_RFCE        0x00008000 /* Receive Flow Control Ena */
2629 #define IXGBE_MFLCN_PMCF        0x00000001 /* Pass MAC Control Frames */
2630 #define IXGBE_MFLCN_DPF         0x00000002 /* Discard Pause Frame */
2631 #define IXGBE_MFLCN_RPFCE       0x00000004 /* Receive Priority FC Enable */
2632 #define IXGBE_MFLCN_RFCE        0x00000008 /* Receive FC Enable */
2633 #define IXGBE_MFLCN_RPFCE_MASK  0x00000FF4 /* Rx Priority FC bitmap mask */
2634 #define IXGBE_MFLCN_RPFCE_SHIFT 4 /* Rx Priority FC bitmap shift */
2635
2636 /* Multiple Receive Queue Control */
2637 #define IXGBE_MRQC_RSSEN        0x00000001  /* RSS Enable */
2638 #define IXGBE_MRQC_MRQE_MASK    0xF /* Bits 3:0 */
2639 #define IXGBE_MRQC_RT8TCEN      0x00000002 /* 8 TC no RSS */
2640 #define IXGBE_MRQC_RT4TCEN      0x00000003 /* 4 TC no RSS */
2641 #define IXGBE_MRQC_RTRSS8TCEN   0x00000004 /* 8 TC w/ RSS */
2642 #define IXGBE_MRQC_RTRSS4TCEN   0x00000005 /* 4 TC w/ RSS */
2643 #define IXGBE_MRQC_VMDQEN       0x00000008 /* VMDq2 64 pools no RSS */
2644 #define IXGBE_MRQC_VMDQRSS32EN  0x0000000A /* VMDq2 32 pools w/ RSS */
2645 #define IXGBE_MRQC_VMDQRSS64EN  0x0000000B /* VMDq2 64 pools w/ RSS */
2646 #define IXGBE_MRQC_VMDQRT8TCEN  0x0000000C /* VMDq2/RT 16 pool 8 TC */
2647 #define IXGBE_MRQC_VMDQRT4TCEN  0x0000000D /* VMDq2/RT 32 pool 4 TC */
2648 #define IXGBE_MRQC_L3L4TXSWEN   0x00008000 /* Enable L3/L4 Tx switch */
2649 #define IXGBE_MRQC_RSS_FIELD_MASK       0xFFFF0000
2650 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP   0x00010000
2651 #define IXGBE_MRQC_RSS_FIELD_IPV4       0x00020000
2652 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
2653 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX    0x00080000
2654 #define IXGBE_MRQC_RSS_FIELD_IPV6       0x00100000
2655 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP   0x00200000
2656 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP   0x00400000
2657 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP   0x00800000
2658 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
2659 #define IXGBE_MRQC_MULTIPLE_RSS         0x00002000
2660 #define IXGBE_MRQC_L3L4TXSWEN           0x00008000
2661
2662 /* Queue Drop Enable */
2663 #define IXGBE_QDE_ENABLE        0x00000001
2664 #define IXGBE_QDE_HIDE_VLAN     0x00000002
2665 #define IXGBE_QDE_IDX_MASK      0x00007F00
2666 #define IXGBE_QDE_IDX_SHIFT     8
2667 #define IXGBE_QDE_WRITE         0x00010000
2668 #define IXGBE_QDE_READ          0x00020000
2669
2670 #define IXGBE_TXD_POPTS_IXSM    0x01 /* Insert IP checksum */
2671 #define IXGBE_TXD_POPTS_TXSM    0x02 /* Insert TCP/UDP checksum */
2672 #define IXGBE_TXD_CMD_EOP       0x01000000 /* End of Packet */
2673 #define IXGBE_TXD_CMD_IFCS      0x02000000 /* Insert FCS (Ethernet CRC) */
2674 #define IXGBE_TXD_CMD_IC        0x04000000 /* Insert Checksum */
2675 #define IXGBE_TXD_CMD_RS        0x08000000 /* Report Status */
2676 #define IXGBE_TXD_CMD_DEXT      0x20000000 /* Desc extension (0 = legacy) */
2677 #define IXGBE_TXD_CMD_VLE       0x40000000 /* Add VLAN tag */
2678 #define IXGBE_TXD_STAT_DD       0x00000001 /* Descriptor Done */
2679
2680 #define IXGBE_RXDADV_IPSEC_STATUS_SECP          0x00020000
2681 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
2682 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
2683 #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED    0x18000000
2684 #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK       0x18000000
2685 /* Multiple Transmit Queue Command Register */
2686 #define IXGBE_MTQC_RT_ENA       0x1 /* DCB Enable */
2687 #define IXGBE_MTQC_VT_ENA       0x2 /* VMDQ2 Enable */
2688 #define IXGBE_MTQC_64Q_1PB      0x0 /* 64 queues 1 pack buffer */
2689 #define IXGBE_MTQC_32VF         0x8 /* 4 TX Queues per pool w/32VF's */
2690 #define IXGBE_MTQC_64VF         0x4 /* 2 TX Queues per pool w/64VF's */
2691 #define IXGBE_MTQC_4TC_4TQ      0x8 /* 4 TC if RT_ENA and VT_ENA */
2692 #define IXGBE_MTQC_8TC_8TQ      0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
2693
2694 /* Receive Descriptor bit definitions */
2695 #define IXGBE_RXD_STAT_DD       0x01 /* Descriptor Done */
2696 #define IXGBE_RXD_STAT_EOP      0x02 /* End of Packet */
2697 #define IXGBE_RXD_STAT_FLM      0x04 /* FDir Match */
2698 #define IXGBE_RXD_STAT_VP       0x08 /* IEEE VLAN Packet */
2699 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
2700 #define IXGBE_RXDADV_NEXTP_SHIFT        0x00000004
2701 #define IXGBE_RXD_STAT_UDPCS    0x10 /* UDP xsum calculated */
2702 #define IXGBE_RXD_STAT_L4CS     0x20 /* L4 xsum calculated */
2703 #define IXGBE_RXD_STAT_IPCS     0x40 /* IP xsum calculated */
2704 #define IXGBE_RXD_STAT_PIF      0x80 /* passed in-exact filter */
2705 #define IXGBE_RXD_STAT_CRCV     0x100 /* Speculative CRC Valid */
2706 #define IXGBE_RXD_STAT_OUTERIPCS        0x100 /* Cloud IP xsum calculated */
2707 #define IXGBE_RXD_STAT_VEXT     0x200 /* 1st VLAN found */
2708 #define IXGBE_RXD_STAT_UDPV     0x400 /* Valid UDP checksum */
2709 #define IXGBE_RXD_STAT_DYNINT   0x800 /* Pkt caused INT via DYNINT */
2710 #define IXGBE_RXD_STAT_LLINT    0x800 /* Pkt caused Low Latency Interrupt */
2711 #define IXGBE_RXD_STAT_TSIP     0x08000 /* Time Stamp in packet buffer */
2712 #define IXGBE_RXD_STAT_TS       0x10000 /* Time Stamp */
2713 #define IXGBE_RXD_STAT_SECP     0x20000 /* Security Processing */
2714 #define IXGBE_RXD_STAT_LB       0x40000 /* Loopback Status */
2715 #define IXGBE_RXD_STAT_ACK      0x8000 /* ACK Packet indication */
2716 #define IXGBE_RXD_ERR_CE        0x01 /* CRC Error */
2717 #define IXGBE_RXD_ERR_LE        0x02 /* Length Error */
2718 #define IXGBE_RXD_ERR_PE        0x08 /* Packet Error */
2719 #define IXGBE_RXD_ERR_OSE       0x10 /* Oversize Error */
2720 #define IXGBE_RXD_ERR_USE       0x20 /* Undersize Error */
2721 #define IXGBE_RXD_ERR_TCPE      0x40 /* TCP/UDP Checksum Error */
2722 #define IXGBE_RXD_ERR_IPE       0x80 /* IP Checksum Error */
2723 #define IXGBE_RXDADV_ERR_MASK           0xfff00000 /* RDESC.ERRORS mask */
2724 #define IXGBE_RXDADV_ERR_SHIFT          20 /* RDESC.ERRORS shift */
2725 #define IXGBE_RXDADV_ERR_OUTERIPER      0x04000000 /* CRC IP Header error */
2726 #define IXGBE_RXDADV_ERR_RXE            0x20000000 /* Any MAC Error */
2727 #define IXGBE_RXDADV_ERR_FCEOFE         0x80000000 /* FCEOFe/IPE */
2728 #define IXGBE_RXDADV_ERR_FCERR          0x00700000 /* FCERR/FDIRERR */
2729 #define IXGBE_RXDADV_ERR_FDIR_LEN       0x00100000 /* FDIR Length error */
2730 #define IXGBE_RXDADV_ERR_FDIR_DROP      0x00200000 /* FDIR Drop error */
2731 #define IXGBE_RXDADV_ERR_FDIR_COLL      0x00400000 /* FDIR Collision error */
2732 #define IXGBE_RXDADV_ERR_HBO    0x00800000 /*Header Buffer Overflow */
2733 #define IXGBE_RXDADV_ERR_CE     0x01000000 /* CRC Error */
2734 #define IXGBE_RXDADV_ERR_LE     0x02000000 /* Length Error */
2735 #define IXGBE_RXDADV_ERR_PE     0x08000000 /* Packet Error */
2736 #define IXGBE_RXDADV_ERR_OSE    0x10000000 /* Oversize Error */
2737 #define IXGBE_RXDADV_ERR_USE    0x20000000 /* Undersize Error */
2738 #define IXGBE_RXDADV_ERR_TCPE   0x40000000 /* TCP/UDP Checksum Error */
2739 #define IXGBE_RXDADV_ERR_IPE    0x80000000 /* IP Checksum Error */
2740 #define IXGBE_RXD_VLAN_ID_MASK  0x0FFF  /* VLAN ID is in lower 12 bits */
2741 #define IXGBE_RXD_PRI_MASK      0xE000  /* Priority is in upper 3 bits */
2742 #define IXGBE_RXD_PRI_SHIFT     13
2743 #define IXGBE_RXD_CFI_MASK      0x1000  /* CFI is bit 12 */
2744 #define IXGBE_RXD_CFI_SHIFT     12
2745
2746 #define IXGBE_RXDADV_STAT_DD            IXGBE_RXD_STAT_DD  /* Done */
2747 #define IXGBE_RXDADV_STAT_EOP           IXGBE_RXD_STAT_EOP /* End of Packet */
2748 #define IXGBE_RXDADV_STAT_FLM           IXGBE_RXD_STAT_FLM /* FDir Match */
2749 #define IXGBE_RXDADV_STAT_VP            IXGBE_RXD_STAT_VP  /* IEEE VLAN Pkt */
2750 #define IXGBE_RXDADV_STAT_MASK          0x000fffff /* Stat/NEXTP: bit 0-19 */
2751 #define IXGBE_RXDADV_STAT_FCEOFS        0x00000040 /* FCoE EOF/SOF Stat */
2752 #define IXGBE_RXDADV_STAT_FCSTAT        0x00000030 /* FCoE Pkt Stat */
2753 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
2754 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP  0x00000010 /* 01: Ctxt w/o DDP */
2755 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
2756 #define IXGBE_RXDADV_STAT_FCSTAT_DDP    0x00000030 /* 11: Ctxt w/ DDP */
2757 #define IXGBE_RXDADV_STAT_TS            0x00010000 /* IEEE1588 Time Stamp */
2758 #define IXGBE_RXDADV_STAT_TSIP          0x00008000 /* Time Stamp in packet buffer */
2759
2760 /* PSRTYPE bit definitions */
2761 #define IXGBE_PSRTYPE_TCPHDR    0x00000010
2762 #define IXGBE_PSRTYPE_UDPHDR    0x00000020
2763 #define IXGBE_PSRTYPE_IPV4HDR   0x00000100
2764 #define IXGBE_PSRTYPE_IPV6HDR   0x00000200
2765 #define IXGBE_PSRTYPE_L2HDR     0x00001000
2766
2767 /* SRRCTL bit definitions */
2768 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT     10 /* so many KBs */
2769 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* 64byte resolution (>> 6)
2770                                            * + at bit 8 offset (<< 8)
2771                                            *  = (<< 2)
2772                                            */
2773 #define IXGBE_SRRCTL_RDMTS_SHIFT        22
2774 #define IXGBE_SRRCTL_RDMTS_MASK         0x01C00000
2775 #define IXGBE_SRRCTL_DROP_EN            0x10000000
2776 #define IXGBE_SRRCTL_BSIZEPKT_MASK      0x0000007F
2777 #define IXGBE_SRRCTL_BSIZEHDR_MASK      0x00003F00
2778 #define IXGBE_SRRCTL_DESCTYPE_LEGACY    0x00000000
2779 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
2780 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
2781 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
2782 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
2783 #define IXGBE_SRRCTL_DESCTYPE_MASK      0x0E000000
2784
2785 #define IXGBE_RXDPS_HDRSTAT_HDRSP       0x00008000
2786 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
2787
2788 #define IXGBE_RXDADV_RSSTYPE_MASK       0x0000000F
2789 #define IXGBE_RXDADV_PKTTYPE_MASK       0x0000FFF0
2790 #define IXGBE_RXDADV_PKTTYPE_MASK_EX    0x0001FFF0
2791 #define IXGBE_RXDADV_HDRBUFLEN_MASK     0x00007FE0
2792 #define IXGBE_RXDADV_RSCCNT_MASK        0x001E0000
2793 #define IXGBE_RXDADV_RSCCNT_SHIFT       17
2794 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT    5
2795 #define IXGBE_RXDADV_SPLITHEADER_EN     0x00001000
2796 #define IXGBE_RXDADV_SPH                0x8000
2797
2798 /* RSS Hash results */
2799 #define IXGBE_RXDADV_RSSTYPE_NONE       0x00000000
2800 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP   0x00000001
2801 #define IXGBE_RXDADV_RSSTYPE_IPV4       0x00000002
2802 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP   0x00000003
2803 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX    0x00000004
2804 #define IXGBE_RXDADV_RSSTYPE_IPV6       0x00000005
2805 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
2806 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP   0x00000007
2807 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP   0x00000008
2808 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
2809
2810 /* RSS Packet Types as indicated in the receive descriptor. */
2811 #define IXGBE_RXDADV_PKTTYPE_NONE       0x00000000
2812 #define IXGBE_RXDADV_PKTTYPE_IPV4       0x00000010 /* IPv4 hdr present */
2813 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX    0x00000020 /* IPv4 hdr + extensions */
2814 #define IXGBE_RXDADV_PKTTYPE_IPV6       0x00000040 /* IPv6 hdr present */
2815 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX    0x00000080 /* IPv6 hdr + extensions */
2816 #define IXGBE_RXDADV_PKTTYPE_TCP        0x00000100 /* TCP hdr present */
2817 #define IXGBE_RXDADV_PKTTYPE_UDP        0x00000200 /* UDP hdr present */
2818 #define IXGBE_RXDADV_PKTTYPE_SCTP       0x00000400 /* SCTP hdr present */
2819 #define IXGBE_RXDADV_PKTTYPE_NFS        0x00000800 /* NFS hdr present */
2820 #define IXGBE_RXDADV_PKTTYPE_GENEVE     0x00000800 /* GENEVE hdr present */
2821 #define IXGBE_RXDADV_PKTTYPE_VXLAN      0x00000800 /* VXLAN hdr present */
2822 #define IXGBE_RXDADV_PKTTYPE_TUNNEL     0x00010000 /* Tunnel type */
2823 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP  0x00001000 /* IPSec ESP */
2824 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH   0x00002000 /* IPSec AH */
2825 #define IXGBE_RXDADV_PKTTYPE_LINKSEC    0x00004000 /* LinkSec Encap */
2826 #define IXGBE_RXDADV_PKTTYPE_ETQF       0x00008000 /* PKTTYPE is ETQF index */
2827 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK  0x00000070 /* ETQF has 8 indices */
2828 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
2829
2830 /* Security Processing bit Indication */
2831 #define IXGBE_RXDADV_LNKSEC_STATUS_SECP         0x00020000
2832 #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
2833 #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
2834 #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
2835 #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
2836
2837 /* Masks to determine if packets should be dropped due to frame errors */
2838 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
2839                                 IXGBE_RXD_ERR_CE | \
2840                                 IXGBE_RXD_ERR_LE | \
2841                                 IXGBE_RXD_ERR_PE | \
2842                                 IXGBE_RXD_ERR_OSE | \
2843                                 IXGBE_RXD_ERR_USE)
2844
2845 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
2846                                 IXGBE_RXDADV_ERR_CE | \
2847                                 IXGBE_RXDADV_ERR_LE | \
2848                                 IXGBE_RXDADV_ERR_PE | \
2849                                 IXGBE_RXDADV_ERR_OSE | \
2850                                 IXGBE_RXDADV_ERR_USE)
2851
2852 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK_82599   IXGBE_RXDADV_ERR_RXE
2853
2854 /* Multicast bit mask */
2855 #define IXGBE_MCSTCTRL_MFE      0x4
2856
2857 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2858 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE        8
2859 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE        8
2860 #define IXGBE_REQ_TX_BUFFER_GRANULARITY         1024
2861
2862 /* Vlan-specific macros */
2863 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
2864 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK  0xE000 /* Priority in upper 3 bits */
2865 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
2866 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2867
2868 /* SR-IOV specific macros */
2869 #define IXGBE_MBVFICR_INDEX(vf_number)  (vf_number >> 4)
2870 #define IXGBE_MBVFICR(_i)               (0x00710 + ((_i) * 4))
2871 #define IXGBE_VFLRE(_i)                 (((_i & 1) ? 0x001C0 : 0x00600))
2872 #define IXGBE_VFLREC(_i)                 (0x00700 + ((_i) * 4))
2873 /* Translated register #defines */
2874 #define IXGBE_PVFCTRL(P)        (0x00300 + (4 * (P)))
2875 #define IXGBE_PVFSTATUS(P)      (0x00008 + (0 * (P)))
2876 #define IXGBE_PVFLINKS(P)       (0x042A4 + (0 * (P)))
2877 #define IXGBE_PVFRTIMER(P)      (0x00048 + (0 * (P)))
2878 #define IXGBE_PVFMAILBOX(P)     (0x04C00 + (4 * (P)))
2879 #define IXGBE_PVFRXMEMWRAP(P)   (0x03190 + (0 * (P)))
2880 #define IXGBE_PVTEICR(P)        (0x00B00 + (4 * (P)))
2881 #define IXGBE_PVTEICS(P)        (0x00C00 + (4 * (P)))
2882 #define IXGBE_PVTEIMS(P)        (0x00D00 + (4 * (P)))
2883 #define IXGBE_PVTEIMC(P)        (0x00E00 + (4 * (P)))
2884 #define IXGBE_PVTEIAC(P)        (0x00F00 + (4 * (P)))
2885 #define IXGBE_PVTEIAM(P)        (0x04D00 + (4 * (P)))
2886 #define IXGBE_PVTEITR(P)        (((P) < 24) ? (0x00820 + ((P) * 4)) : \
2887                                  (0x012300 + (((P) - 24) * 4)))
2888 #define IXGBE_PVTIVAR(P)        (0x12500 + (4 * (P)))
2889 #define IXGBE_PVTIVAR_MISC(P)   (0x04E00 + (4 * (P)))
2890 #define IXGBE_PVTRSCINT(P)      (0x12000 + (4 * (P)))
2891 #define IXGBE_VFPBACL(P)        (0x110C8 + (4 * (P)))
2892 #define IXGBE_PVFRDBAL(P)       ((P < 64) ? (0x01000 + (0x40 * (P))) \
2893                                  : (0x0D000 + (0x40 * ((P) - 64))))
2894 #define IXGBE_PVFRDBAH(P)       ((P < 64) ? (0x01004 + (0x40 * (P))) \
2895                                  : (0x0D004 + (0x40 * ((P) - 64))))
2896 #define IXGBE_PVFRDLEN(P)       ((P < 64) ? (0x01008 + (0x40 * (P))) \
2897                                  : (0x0D008 + (0x40 * ((P) - 64))))
2898 #define IXGBE_PVFRDH(P)         ((P < 64) ? (0x01010 + (0x40 * (P))) \
2899                                  : (0x0D010 + (0x40 * ((P) - 64))))
2900 #define IXGBE_PVFRDT(P)         ((P < 64) ? (0x01018 + (0x40 * (P))) \
2901                                  : (0x0D018 + (0x40 * ((P) - 64))))
2902 #define IXGBE_PVFRXDCTL(P)      ((P < 64) ? (0x01028 + (0x40 * (P))) \
2903                                  : (0x0D028 + (0x40 * ((P) - 64))))
2904 #define IXGBE_PVFSRRCTL(P)      ((P < 64) ? (0x01014 + (0x40 * (P))) \
2905                                  : (0x0D014 + (0x40 * ((P) - 64))))
2906 #define IXGBE_PVFPSRTYPE(P)     (0x0EA00 + (4 * (P)))
2907 #define IXGBE_PVFTDBAL(P)       (0x06000 + (0x40 * (P)))
2908 #define IXGBE_PVFTDBAH(P)       (0x06004 + (0x40 * (P)))
2909 #define IXGBE_PVFTDLEN(P)       (0x06008 + (0x40 * (P)))
2910 #define IXGBE_PVFTDH(P)         (0x06010 + (0x40 * (P)))
2911 #define IXGBE_PVFTDT(P)         (0x06018 + (0x40 * (P)))
2912 #define IXGBE_PVFTXDCTL(P)      (0x06028 + (0x40 * (P)))
2913 #define IXGBE_PVFTDWBAL(P)      (0x06038 + (0x40 * (P)))
2914 #define IXGBE_PVFTDWBAH(P)      (0x0603C + (0x40 * (P)))
2915 #define IXGBE_PVFDCA_RXCTRL(P)  (((P) < 64) ? (0x0100C + (0x40 * (P))) \
2916                                  : (0x0D00C + (0x40 * ((P) - 64))))
2917 #define IXGBE_PVFDCA_TXCTRL(P)  (0x0600C + (0x40 * (P)))
2918 #define IXGBE_PVFGPRC(x)        (0x0101C + (0x40 * (x)))
2919 #define IXGBE_PVFGPTC(x)        (0x08300 + (0x04 * (x)))
2920 #define IXGBE_PVFGORC_LSB(x)    (0x01020 + (0x40 * (x)))
2921 #define IXGBE_PVFGORC_MSB(x)    (0x0D020 + (0x40 * (x)))
2922 #define IXGBE_PVFGOTC_LSB(x)    (0x08400 + (0x08 * (x)))
2923 #define IXGBE_PVFGOTC_MSB(x)    (0x08404 + (0x08 * (x)))
2924 #define IXGBE_PVFMPRC(x)        (0x0D01C + (0x40 * (x)))
2925
2926 #define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \
2927                 (IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))
2928 #define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \
2929                 (IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))
2930
2931 #define IXGBE_PVFTDHn(q_per_pool, vf_number, vf_q_index) \
2932                 (IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))
2933 #define IXGBE_PVFTDTn(q_per_pool, vf_number, vf_q_index) \
2934                 (IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))
2935
2936 /* Little Endian defines */
2937 #ifndef __le16
2938 #define __le16  u16
2939 #endif
2940 #ifndef __le32
2941 #define __le32  u32
2942 #endif
2943 #ifndef __le64
2944 #define __le64  u64
2945
2946 #endif
2947 #ifndef __be16
2948 /* Big Endian defines */
2949 #define __be16  u16
2950 #define __be32  u32
2951 #define __be64  u64
2952
2953 #endif
2954 enum ixgbe_fdir_pballoc_type {
2955         IXGBE_FDIR_PBALLOC_NONE = 0,
2956         IXGBE_FDIR_PBALLOC_64K  = 1,
2957         IXGBE_FDIR_PBALLOC_128K = 2,
2958         IXGBE_FDIR_PBALLOC_256K = 3,
2959 };
2960
2961 /* Flow Director register values */
2962 #define IXGBE_FDIRCTRL_PBALLOC_64K              0x00000001
2963 #define IXGBE_FDIRCTRL_PBALLOC_128K             0x00000002
2964 #define IXGBE_FDIRCTRL_PBALLOC_256K             0x00000003
2965 #define IXGBE_FDIRCTRL_INIT_DONE                0x00000008
2966 #define IXGBE_FDIRCTRL_PERFECT_MATCH            0x00000010
2967 #define IXGBE_FDIRCTRL_REPORT_STATUS            0x00000020
2968 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS     0x00000080
2969 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT             8
2970 #define IXGBE_FDIRCTRL_DROP_Q_MASK              0x00007F00
2971 #define IXGBE_FDIRCTRL_FLEX_SHIFT               16
2972 #define IXGBE_FDIRCTRL_DROP_NO_MATCH            0x00008000
2973 #define IXGBE_FDIRCTRL_FILTERMODE_SHIFT         21
2974 #define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN       0x0001 /* bit 23:21, 001b */
2975 #define IXGBE_FDIRCTRL_FILTERMODE_CLOUD         0x0002 /* bit 23:21, 010b */
2976 #define IXGBE_FDIRCTRL_SEARCHLIM                0x00800000
2977 #define IXGBE_FDIRCTRL_FILTERMODE_MASK          0x00E00000
2978 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT         24
2979 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK         0xF0000000
2980 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT        28
2981
2982 #define IXGBE_FDIRTCPM_DPORTM_SHIFT             16
2983 #define IXGBE_FDIRUDPM_DPORTM_SHIFT             16
2984 #define IXGBE_FDIRIP6M_DIPM_SHIFT               16
2985 #define IXGBE_FDIRM_VLANID                      0x00000001
2986 #define IXGBE_FDIRM_VLANP                       0x00000002
2987 #define IXGBE_FDIRM_POOL                        0x00000004
2988 #define IXGBE_FDIRM_L4P                         0x00000008
2989 #define IXGBE_FDIRM_FLEX                        0x00000010
2990 #define IXGBE_FDIRM_DIPv6                       0x00000020
2991 #define IXGBE_FDIRM_L3P                         0x00000040
2992
2993 #define IXGBE_FDIRIP6M_INNER_MAC        0x03F0 /* bit 9:4 */
2994 #define IXGBE_FDIRIP6M_TUNNEL_TYPE      0x0800 /* bit 11 */
2995 #define IXGBE_FDIRIP6M_TNI_VNI          0xF000 /* bit 15:12 */
2996 #define IXGBE_FDIRIP6M_TNI_VNI_24       0x1000 /* bit 12 */
2997 #define IXGBE_FDIRIP6M_ALWAYS_MASK      0x040F /* bit 10, 3:0 */
2998
2999 #define IXGBE_FDIRFREE_FREE_MASK                0xFFFF
3000 #define IXGBE_FDIRFREE_FREE_SHIFT               0
3001 #define IXGBE_FDIRFREE_COLL_MASK                0x7FFF0000
3002 #define IXGBE_FDIRFREE_COLL_SHIFT               16
3003 #define IXGBE_FDIRLEN_MAXLEN_MASK               0x3F
3004 #define IXGBE_FDIRLEN_MAXLEN_SHIFT              0
3005 #define IXGBE_FDIRLEN_MAXHASH_MASK              0x7FFF0000
3006 #define IXGBE_FDIRLEN_MAXHASH_SHIFT             16
3007 #define IXGBE_FDIRUSTAT_ADD_MASK                0xFFFF
3008 #define IXGBE_FDIRUSTAT_ADD_SHIFT               0
3009 #define IXGBE_FDIRUSTAT_REMOVE_MASK             0xFFFF0000
3010 #define IXGBE_FDIRUSTAT_REMOVE_SHIFT            16
3011 #define IXGBE_FDIRFSTAT_FADD_MASK               0x00FF
3012 #define IXGBE_FDIRFSTAT_FADD_SHIFT              0
3013 #define IXGBE_FDIRFSTAT_FREMOVE_MASK            0xFF00
3014 #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT           8
3015 #define IXGBE_FDIRPORT_DESTINATION_SHIFT        16
3016 #define IXGBE_FDIRVLAN_FLEX_SHIFT               16
3017 #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT       15
3018 #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT       16
3019
3020 #define IXGBE_FDIRCMD_CMD_MASK                  0x00000003
3021 #define IXGBE_FDIRCMD_CMD_ADD_FLOW              0x00000001
3022 #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW           0x00000002
3023 #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT        0x00000003
3024 #define IXGBE_FDIRCMD_FILTER_VALID              0x00000004
3025 #define IXGBE_FDIRCMD_FILTER_UPDATE             0x00000008
3026 #define IXGBE_FDIRCMD_IPv6DMATCH                0x00000010
3027 #define IXGBE_FDIRCMD_L4TYPE_UDP                0x00000020
3028 #define IXGBE_FDIRCMD_L4TYPE_TCP                0x00000040
3029 #define IXGBE_FDIRCMD_L4TYPE_SCTP               0x00000060
3030 #define IXGBE_FDIRCMD_IPV6                      0x00000080
3031 #define IXGBE_FDIRCMD_CLEARHT                   0x00000100
3032 #define IXGBE_FDIRCMD_DROP                      0x00000200
3033 #define IXGBE_FDIRCMD_INT                       0x00000400
3034 #define IXGBE_FDIRCMD_LAST                      0x00000800
3035 #define IXGBE_FDIRCMD_COLLISION                 0x00001000
3036 #define IXGBE_FDIRCMD_QUEUE_EN                  0x00008000
3037 #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT           5
3038 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT            16
3039 #define IXGBE_FDIRCMD_TUNNEL_FILTER_SHIFT       23
3040 #define IXGBE_FDIRCMD_VT_POOL_SHIFT             24
3041 #define IXGBE_FDIR_INIT_DONE_POLL               10
3042 #define IXGBE_FDIRCMD_CMD_POLL                  10
3043 #define IXGBE_FDIRCMD_TUNNEL_FILTER             0x00800000
3044 #define IXGBE_FDIR_DROP_QUEUE                   127
3045
3046
3047 /* Manageablility Host Interface defines */
3048 #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH  1792 /* Num of bytes in range */
3049 #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
3050 #define IXGBE_HI_COMMAND_TIMEOUT        500 /* Process HI command limit */
3051 #define IXGBE_HI_FLASH_ERASE_TIMEOUT    1000 /* Process Erase command limit */
3052 #define IXGBE_HI_FLASH_UPDATE_TIMEOUT   5000 /* Process Update command limit */
3053 #define IXGBE_HI_FLASH_APPLY_TIMEOUT    0 /* Process Apply command limit */
3054 #define IXGBE_HI_PHY_MGMT_REQ_TIMEOUT   2000 /* Wait up to 2 seconds */
3055
3056 /* CEM Support */
3057 #define FW_CEM_HDR_LEN                  0x4
3058 #define FW_CEM_CMD_DRIVER_INFO          0xDD
3059 #define FW_CEM_CMD_DRIVER_INFO_LEN      0x5
3060 #define FW_CEM_CMD_RESERVED             0X0
3061 #define FW_CEM_UNUSED_VER               0x0
3062 #define FW_CEM_MAX_RETRIES              3
3063 #define FW_CEM_RESP_STATUS_SUCCESS      0x1
3064 #define FW_CEM_DRIVER_VERSION_SIZE      39 /* +9 would send 48 bytes to fw */
3065 #define FW_READ_SHADOW_RAM_CMD          0x31
3066 #define FW_READ_SHADOW_RAM_LEN          0x6
3067 #define FW_WRITE_SHADOW_RAM_CMD         0x33
3068 #define FW_WRITE_SHADOW_RAM_LEN         0xA /* 8 plus 1 WORD to write */
3069 #define FW_SHADOW_RAM_DUMP_CMD          0x36
3070 #define FW_SHADOW_RAM_DUMP_LEN          0
3071 #define FW_DEFAULT_CHECKSUM             0xFF /* checksum always 0xFF */
3072 #define FW_NVM_DATA_OFFSET              3
3073 #define FW_MAX_READ_BUFFER_SIZE         1024
3074 #define FW_DISABLE_RXEN_CMD             0xDE
3075 #define FW_DISABLE_RXEN_LEN             0x1
3076 #define FW_PHY_MGMT_REQ_CMD             0x20
3077 #define FW_PHY_TOKEN_REQ_CMD            0xA
3078 #define FW_PHY_TOKEN_REQ_LEN            2
3079 #define FW_PHY_TOKEN_REQ                0
3080 #define FW_PHY_TOKEN_REL                1
3081 #define FW_PHY_TOKEN_OK                 1
3082 #define FW_PHY_TOKEN_RETRY              0x80
3083 #define FW_PHY_TOKEN_DELAY              5       /* milliseconds */
3084 #define FW_PHY_TOKEN_WAIT               5       /* seconds */
3085 #define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY)
3086 #define FW_INT_PHY_REQ_CMD              0xB
3087 #define FW_INT_PHY_REQ_LEN              10
3088 #define FW_INT_PHY_REQ_READ             0
3089 #define FW_INT_PHY_REQ_WRITE            1
3090 #define FW_PHY_ACT_REQ_CMD              5
3091 #define FW_PHY_ACT_DATA_COUNT           4
3092 #define FW_PHY_ACT_REQ_LEN              (4 + 4 * FW_PHY_ACT_DATA_COUNT)
3093 #define FW_PHY_ACT_INIT_PHY             1
3094 #define FW_PHY_ACT_SETUP_LINK           2
3095 #define FW_PHY_ACT_LINK_SPEED_10        (1u << 0)
3096 #define FW_PHY_ACT_LINK_SPEED_100       (1u << 1)
3097 #define FW_PHY_ACT_LINK_SPEED_1G        (1u << 2)
3098 #define FW_PHY_ACT_LINK_SPEED_2_5G      (1u << 3)
3099 #define FW_PHY_ACT_LINK_SPEED_5G        (1u << 4)
3100 #define FW_PHY_ACT_LINK_SPEED_10G       (1u << 5)
3101 #define FW_PHY_ACT_LINK_SPEED_20G       (1u << 6)
3102 #define FW_PHY_ACT_LINK_SPEED_25G       (1u << 7)
3103 #define FW_PHY_ACT_LINK_SPEED_40G       (1u << 8)
3104 #define FW_PHY_ACT_LINK_SPEED_50G       (1u << 9)
3105 #define FW_PHY_ACT_LINK_SPEED_100G      (1u << 10)
3106 #define FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT 16
3107 #define FW_PHY_ACT_SETUP_LINK_PAUSE_MASK (3u << \
3108                                           FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT)
3109 #define FW_PHY_ACT_SETUP_LINK_PAUSE_NONE 0u
3110 #define FW_PHY_ACT_SETUP_LINK_PAUSE_TX  1u
3111 #define FW_PHY_ACT_SETUP_LINK_PAUSE_RX  2u
3112 #define FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 3u
3113 #define FW_PHY_ACT_SETUP_LINK_LP        (1u << 18)
3114 #define FW_PHY_ACT_SETUP_LINK_HP        (1u << 19)
3115 #define FW_PHY_ACT_SETUP_LINK_EEE       (1u << 20)
3116 #define FW_PHY_ACT_SETUP_LINK_AN        (1u << 22)
3117 #define FW_PHY_ACT_SETUP_LINK_RSP_DOWN  (1u << 0)
3118 #define FW_PHY_ACT_GET_LINK_INFO        3
3119 #define FW_PHY_ACT_GET_LINK_INFO_EEE    (1u << 19)
3120 #define FW_PHY_ACT_GET_LINK_INFO_FC_TX  (1u << 20)
3121 #define FW_PHY_ACT_GET_LINK_INFO_FC_RX  (1u << 21)
3122 #define FW_PHY_ACT_GET_LINK_INFO_POWER  (1u << 22)
3123 #define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE    (1u << 24)
3124 #define FW_PHY_ACT_GET_LINK_INFO_TEMP   (1u << 25)
3125 #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX       (1u << 28)
3126 #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX       (1u << 29)
3127 #define FW_PHY_ACT_FORCE_LINK_DOWN      4
3128 #define FW_PHY_ACT_FORCE_LINK_DOWN_OFF  (1u << 0)
3129 #define FW_PHY_ACT_PHY_SW_RESET         5
3130 #define FW_PHY_ACT_PHY_HW_RESET         6
3131 #define FW_PHY_ACT_GET_PHY_INFO         7
3132 #define FW_PHY_ACT_UD_2                 0x1002
3133 #define FW_PHY_ACT_UD_2_10G_KR_EEE      (1u << 6)
3134 #define FW_PHY_ACT_UD_2_10G_KX4_EEE     (1u << 5)
3135 #define FW_PHY_ACT_UD_2_1G_KX_EEE       (1u << 4)
3136 #define FW_PHY_ACT_UD_2_10G_T_EEE       (1u << 3)
3137 #define FW_PHY_ACT_UD_2_1G_T_EEE        (1u << 2)
3138 #define FW_PHY_ACT_UD_2_100M_TX_EEE     (1u << 1)
3139 #define FW_PHY_ACT_RETRIES              50
3140 #define FW_PHY_INFO_SPEED_MASK          0xFFFu
3141 #define FW_PHY_INFO_ID_HI_MASK          0xFFFF0000u
3142 #define FW_PHY_INFO_ID_LO_MASK          0x0000FFFFu
3143
3144 /* Host Interface Command Structures */
3145
3146 #ifdef C99
3147 #pragma pack(push, 1)
3148 #else
3149 #pragma pack (1)
3150 #endif /* C99 */
3151
3152 struct ixgbe_hic_hdr {
3153         u8 cmd;
3154         u8 buf_len;
3155         union {
3156                 u8 cmd_resv;
3157                 u8 ret_status;
3158         } cmd_or_resp;
3159         u8 checksum;
3160 };
3161
3162 struct ixgbe_hic_hdr2_req {
3163         u8 cmd;
3164         u8 buf_lenh;
3165         u8 buf_lenl;
3166         u8 checksum;
3167 };
3168
3169 struct ixgbe_hic_hdr2_rsp {
3170         u8 cmd;
3171         u8 buf_lenl;
3172         u8 buf_lenh_status;     /* 7-5: high bits of buf_len, 4-0: status */
3173         u8 checksum;
3174 };
3175
3176 union ixgbe_hic_hdr2 {
3177         struct ixgbe_hic_hdr2_req req;
3178         struct ixgbe_hic_hdr2_rsp rsp;
3179 };
3180
3181 struct ixgbe_hic_drv_info {
3182         struct ixgbe_hic_hdr hdr;
3183         u8 port_num;
3184         u8 ver_sub;
3185         u8 ver_build;
3186         u8 ver_min;
3187         u8 ver_maj;
3188         u8 pad; /* end spacing to ensure length is mult. of dword */
3189         u16 pad2; /* end spacing to ensure length is mult. of dword2 */
3190 };
3191
3192 struct ixgbe_hic_drv_info2 {
3193         struct ixgbe_hic_hdr hdr;
3194         u8 port_num;
3195         u8 ver_sub;
3196         u8 ver_build;
3197         u8 ver_min;
3198         u8 ver_maj;
3199         char driver_string[FW_CEM_DRIVER_VERSION_SIZE];
3200 };
3201
3202 /* These need to be dword aligned */
3203 struct ixgbe_hic_read_shadow_ram {
3204         union ixgbe_hic_hdr2 hdr;
3205         u32 address;
3206         u16 length;
3207         u16 pad2;
3208         u16 data;
3209         u16 pad3;
3210 };
3211
3212 struct ixgbe_hic_write_shadow_ram {
3213         union ixgbe_hic_hdr2 hdr;
3214         u32 address;
3215         u16 length;
3216         u16 pad2;
3217         u16 data;
3218         u16 pad3;
3219 };
3220
3221 struct ixgbe_hic_disable_rxen {
3222         struct ixgbe_hic_hdr hdr;
3223         u8  port_number;
3224         u8  pad2;
3225         u16 pad3;
3226 };
3227
3228 struct ixgbe_hic_phy_token_req {
3229         struct ixgbe_hic_hdr hdr;
3230         u8 port_number;
3231         u8 command_type;
3232         u16 pad;
3233 };
3234
3235 struct ixgbe_hic_internal_phy_req {
3236         struct ixgbe_hic_hdr hdr;
3237         u8 port_number;
3238         u8 command_type;
3239         __be16 address;
3240         u16 rsv1;
3241         __be32 write_data;
3242         u16 pad;
3243 };
3244
3245 struct ixgbe_hic_internal_phy_resp {
3246         struct ixgbe_hic_hdr hdr;
3247         __be32 read_data;
3248 };
3249
3250 struct ixgbe_hic_phy_activity_req {
3251         struct ixgbe_hic_hdr hdr;
3252         u8 port_number;
3253         u8 pad;
3254         __le16 activity_id;
3255         __be32 data[FW_PHY_ACT_DATA_COUNT];
3256 };
3257
3258 struct ixgbe_hic_phy_activity_resp {
3259         struct ixgbe_hic_hdr hdr;
3260         __be32 data[FW_PHY_ACT_DATA_COUNT];
3261 };
3262
3263 #ifdef C99
3264 #pragma pack(pop)
3265 #else
3266 #pragma pack()
3267 #endif /* C99 */
3268
3269 /* Transmit Descriptor - Legacy */
3270 struct ixgbe_legacy_tx_desc {
3271         u64 buffer_addr; /* Address of the descriptor's data buffer */
3272         union {
3273                 __le32 data;
3274                 struct {
3275                         __le16 length; /* Data buffer length */
3276                         u8 cso; /* Checksum offset */
3277                         u8 cmd; /* Descriptor control */
3278                 } flags;
3279         } lower;
3280         union {
3281                 __le32 data;
3282                 struct {
3283                         u8 status; /* Descriptor status */
3284                         u8 css; /* Checksum start */
3285                         __le16 vlan;
3286                 } fields;
3287         } upper;
3288 };
3289
3290 /* Transmit Descriptor - Advanced */
3291 union ixgbe_adv_tx_desc {
3292         struct {
3293                 __le64 buffer_addr; /* Address of descriptor's data buf */
3294                 __le32 cmd_type_len;
3295                 __le32 olinfo_status;
3296         } read;
3297         struct {
3298                 __le64 rsvd; /* Reserved */
3299                 __le32 nxtseq_seed;
3300                 __le32 status;
3301         } wb;
3302 };
3303
3304 /* Receive Descriptor - Legacy */
3305 struct ixgbe_legacy_rx_desc {
3306         __le64 buffer_addr; /* Address of the descriptor's data buffer */
3307         __le16 length; /* Length of data DMAed into data buffer */
3308         __le16 csum; /* Packet checksum */
3309         u8 status;   /* Descriptor status */
3310         u8 errors;   /* Descriptor Errors */
3311         __le16 vlan;
3312 };
3313
3314 /* Receive Descriptor - Advanced */
3315 union ixgbe_adv_rx_desc {
3316         struct {
3317                 __le64 pkt_addr; /* Packet buffer address */
3318                 __le64 hdr_addr; /* Header buffer address */
3319         } read;
3320         struct {
3321                 struct {
3322                         union {
3323                                 __le32 data;
3324                                 struct {
3325                                         __le16 pkt_info; /* RSS, Pkt type */
3326                                         __le16 hdr_info; /* Splithdr, hdrlen */
3327                                 } hs_rss;
3328                         } lo_dword;
3329                         union {
3330                                 __le32 rss; /* RSS Hash */
3331                                 struct {
3332                                         __le16 ip_id; /* IP id */
3333                                         __le16 csum; /* Packet Checksum */
3334                                 } csum_ip;
3335                         } hi_dword;
3336                 } lower;
3337                 struct {
3338                         __le32 status_error; /* ext status/error */
3339                         __le16 length; /* Packet length */
3340                         __le16 vlan; /* VLAN tag */
3341                 } upper;
3342         } wb;  /* writeback */
3343 };
3344
3345 /* Context descriptors */
3346 struct ixgbe_adv_tx_context_desc {
3347         __le32 vlan_macip_lens;
3348         __le32 seqnum_seed;
3349         __le32 type_tucmd_mlhl;
3350         __le32 mss_l4len_idx;
3351 };
3352
3353 /* Adv Transmit Descriptor Config Masks */
3354 #define IXGBE_ADVTXD_DTALEN_MASK        0x0000FFFF /* Data buf length(bytes) */
3355 #define IXGBE_ADVTXD_MAC_LINKSEC        0x00040000 /* Insert LinkSec */
3356 #define IXGBE_ADVTXD_MAC_TSTAMP         0x00080000 /* IEEE1588 time stamp */
3357 #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */
3358 #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */
3359 #define IXGBE_ADVTXD_DTYP_MASK          0x00F00000 /* DTYP mask */
3360 #define IXGBE_ADVTXD_DTYP_CTXT          0x00200000 /* Adv Context Desc */
3361 #define IXGBE_ADVTXD_DTYP_DATA          0x00300000 /* Adv Data Descriptor */
3362 #define IXGBE_ADVTXD_DCMD_EOP           IXGBE_TXD_CMD_EOP  /* End of Packet */
3363 #define IXGBE_ADVTXD_DCMD_IFCS          IXGBE_TXD_CMD_IFCS /* Insert FCS */
3364 #define IXGBE_ADVTXD_DCMD_RS            IXGBE_TXD_CMD_RS /* Report Status */
3365 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI   0x10000000 /* DDP hdr type or iSCSI */
3366 #define IXGBE_ADVTXD_DCMD_DEXT          IXGBE_TXD_CMD_DEXT /* Desc ext 1=Adv */
3367 #define IXGBE_ADVTXD_DCMD_VLE           IXGBE_TXD_CMD_VLE  /* VLAN pkt enable */
3368 #define IXGBE_ADVTXD_DCMD_TSE           0x80000000 /* TCP Seg enable */
3369 #define IXGBE_ADVTXD_STAT_DD            IXGBE_TXD_STAT_DD  /* Descriptor Done */
3370 #define IXGBE_ADVTXD_STAT_SN_CRC        0x00000002 /* NXTSEQ/SEED pres in WB */
3371 #define IXGBE_ADVTXD_STAT_RSV           0x0000000C /* STA Reserved */
3372 #define IXGBE_ADVTXD_IDX_SHIFT          4 /* Adv desc Index shift */
3373 #define IXGBE_ADVTXD_CC                 0x00000080 /* Check Context */
3374 #define IXGBE_ADVTXD_POPTS_SHIFT        8  /* Adv desc POPTS shift */
3375 #define IXGBE_ADVTXD_POPTS_IXSM         (IXGBE_TXD_POPTS_IXSM << \
3376                                          IXGBE_ADVTXD_POPTS_SHIFT)
3377 #define IXGBE_ADVTXD_POPTS_TXSM         (IXGBE_TXD_POPTS_TXSM << \
3378                                          IXGBE_ADVTXD_POPTS_SHIFT)
3379 #define IXGBE_ADVTXD_POPTS_ISCO_1ST     0x00000000 /* 1st TSO of iSCSI PDU */
3380 #define IXGBE_ADVTXD_POPTS_ISCO_MDL     0x00000800 /* Middle TSO of iSCSI PDU */
3381 #define IXGBE_ADVTXD_POPTS_ISCO_LAST    0x00001000 /* Last TSO of iSCSI PDU */
3382 /* 1st&Last TSO-full iSCSI PDU */
3383 #define IXGBE_ADVTXD_POPTS_ISCO_FULL    0x00001800
3384 #define IXGBE_ADVTXD_POPTS_RSV          0x00002000 /* POPTS Reserved */
3385 #define IXGBE_ADVTXD_PAYLEN_SHIFT       14 /* Adv desc PAYLEN shift */
3386 #define IXGBE_ADVTXD_MACLEN_SHIFT       9  /* Adv ctxt desc mac len shift */
3387 #define IXGBE_ADVTXD_VLAN_SHIFT         16  /* Adv ctxt vlan tag shift */
3388 #define IXGBE_ADVTXD_TUCMD_IPV4         0x00000400 /* IP Packet Type: 1=IPv4 */
3389 #define IXGBE_ADVTXD_TUCMD_IPV6         0x00000000 /* IP Packet Type: 0=IPv6 */
3390 #define IXGBE_ADVTXD_TUCMD_L4T_UDP      0x00000000 /* L4 Packet TYPE of UDP */
3391 #define IXGBE_ADVTXD_TUCMD_L4T_TCP      0x00000800 /* L4 Packet TYPE of TCP */
3392 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP     0x00001000 /* L4 Packet TYPE of SCTP */
3393 #define IXGBE_ADVTXD_TUCMD_L4T_RSV      0x00001800 /* RSV L4 Packet TYPE */
3394 #define IXGBE_ADVTXD_TUCMD_MKRREQ       0x00002000 /* req Markers and CRC */
3395 #define IXGBE_ADVTXD_POPTS_IPSEC        0x00000400 /* IPSec offload request */
3396 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
3397 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
3398 #define IXGBE_ADVTXT_TUCMD_FCOE         0x00008000 /* FCoE Frame Type */
3399 #define IXGBE_ADVTXD_FCOEF_EOF_MASK     (0x3 << 10) /* FC EOF index */
3400 #define IXGBE_ADVTXD_FCOEF_SOF          ((1 << 2) << 10) /* FC SOF index */
3401 #define IXGBE_ADVTXD_FCOEF_PARINC       ((1 << 3) << 10) /* Rel_Off in F_CTL */
3402 #define IXGBE_ADVTXD_FCOEF_ORIE         ((1 << 4) << 10) /* Orientation End */
3403 #define IXGBE_ADVTXD_FCOEF_ORIS         ((1 << 5) << 10) /* Orientation Start */
3404 #define IXGBE_ADVTXD_FCOEF_EOF_N        (0x0 << 10) /* 00: EOFn */
3405 #define IXGBE_ADVTXD_FCOEF_EOF_T        (0x1 << 10) /* 01: EOFt */
3406 #define IXGBE_ADVTXD_FCOEF_EOF_NI       (0x2 << 10) /* 10: EOFni */
3407 #define IXGBE_ADVTXD_FCOEF_EOF_A        (0x3 << 10) /* 11: EOFa */
3408 #define IXGBE_ADVTXD_L4LEN_SHIFT        8  /* Adv ctxt L4LEN shift */
3409 #define IXGBE_ADVTXD_MSS_SHIFT          16  /* Adv ctxt MSS shift */
3410
3411 #define IXGBE_ADVTXD_OUTER_IPLEN        16 /* Adv ctxt OUTERIPLEN shift */
3412 #define IXGBE_ADVTXD_TUNNEL_LEN         24 /* Adv ctxt TUNNELLEN shift */
3413 #define IXGBE_ADVTXD_TUNNEL_TYPE_SHIFT  16 /* Adv Tx Desc Tunnel Type shift */
3414 #define IXGBE_ADVTXD_OUTERIPCS_SHIFT    17 /* Adv Tx Desc OUTERIPCS Shift */
3415 #define IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE  1  /* Adv Tx Desc Tunnel Type NVGRE */
3416 /* Adv Tx Desc OUTERIPCS Shift for X550EM_a */
3417 #define IXGBE_ADVTXD_OUTERIPCS_SHIFT_X550EM_a   26
3418 /* Autonegotiation advertised speeds */
3419 typedef u32 ixgbe_autoneg_advertised;
3420 /* Link speed */
3421 typedef u32 ixgbe_link_speed;
3422 #define IXGBE_LINK_SPEED_UNKNOWN        0
3423 #define IXGBE_LINK_SPEED_10_FULL        0x0002
3424 #define IXGBE_LINK_SPEED_100_FULL       0x0008
3425 #define IXGBE_LINK_SPEED_1GB_FULL       0x0020
3426 #define IXGBE_LINK_SPEED_2_5GB_FULL     0x0400
3427 #define IXGBE_LINK_SPEED_5GB_FULL       0x0800
3428 #define IXGBE_LINK_SPEED_10GB_FULL      0x0080
3429 #define IXGBE_LINK_SPEED_82598_AUTONEG  (IXGBE_LINK_SPEED_1GB_FULL | \
3430                                          IXGBE_LINK_SPEED_10GB_FULL)
3431 #define IXGBE_LINK_SPEED_82599_AUTONEG  (IXGBE_LINK_SPEED_100_FULL | \
3432                                          IXGBE_LINK_SPEED_1GB_FULL | \
3433                                          IXGBE_LINK_SPEED_10GB_FULL)
3434
3435 /* Physical layer type */
3436 typedef u64 ixgbe_physical_layer;
3437 #define IXGBE_PHYSICAL_LAYER_UNKNOWN            0
3438 #define IXGBE_PHYSICAL_LAYER_10GBASE_T          0x00001
3439 #define IXGBE_PHYSICAL_LAYER_1000BASE_T         0x00002
3440 #define IXGBE_PHYSICAL_LAYER_100BASE_TX         0x00004
3441 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU        0x00008
3442 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR         0x00010
3443 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM        0x00020
3444 #define IXGBE_PHYSICAL_LAYER_10GBASE_SR         0x00040
3445 #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4        0x00080
3446 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4        0x00100
3447 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX        0x00200
3448 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX        0x00400
3449 #define IXGBE_PHYSICAL_LAYER_10GBASE_KR         0x00800
3450 #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI       0x01000
3451 #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA      0x02000
3452 #define IXGBE_PHYSICAL_LAYER_1000BASE_SX        0x04000
3453 #define IXGBE_PHYSICAL_LAYER_10BASE_T           0x08000
3454 #define IXGBE_PHYSICAL_LAYER_2500BASE_KX        0x10000
3455
3456 /* Flow Control Data Sheet defined values
3457  * Calculation and defines taken from 802.1bb Annex O
3458  */
3459
3460 /* BitTimes (BT) conversion */
3461 #define IXGBE_BT2KB(BT)         ((BT + (8 * 1024 - 1)) / (8 * 1024))
3462 #define IXGBE_B2BT(BT)          (BT * 8)
3463
3464 /* Calculate Delay to respond to PFC */
3465 #define IXGBE_PFC_D     672
3466
3467 /* Calculate Cable Delay */
3468 #define IXGBE_CABLE_DC  5556 /* Delay Copper */
3469 #define IXGBE_CABLE_DO  5000 /* Delay Optical */
3470
3471 /* Calculate Interface Delay X540 */
3472 #define IXGBE_PHY_DC    25600 /* Delay 10G BASET */
3473 #define IXGBE_MAC_DC    8192  /* Delay Copper XAUI interface */
3474 #define IXGBE_XAUI_DC   (2 * 2048) /* Delay Copper Phy */
3475
3476 #define IXGBE_ID_X540   (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)
3477
3478 /* Calculate Interface Delay 82598, 82599 */
3479 #define IXGBE_PHY_D     12800
3480 #define IXGBE_MAC_D     4096
3481 #define IXGBE_XAUI_D    (2 * 1024)
3482
3483 #define IXGBE_ID        (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)
3484
3485 /* Calculate Delay incurred from higher layer */
3486 #define IXGBE_HD        6144
3487
3488 /* Calculate PCI Bus delay for low thresholds */
3489 #define IXGBE_PCI_DELAY 10000
3490
3491 /* Calculate X540 delay value in bit times */
3492 #define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
3493                         ((36 * \
3494                           (IXGBE_B2BT(_max_frame_link) + \
3495                            IXGBE_PFC_D + \
3496                            (2 * IXGBE_CABLE_DC) + \
3497                            (2 * IXGBE_ID_X540) + \
3498                            IXGBE_HD) / 25 + 1) + \
3499                          2 * IXGBE_B2BT(_max_frame_tc))
3500
3501 /* Calculate 82599, 82598 delay value in bit times */
3502 #define IXGBE_DV(_max_frame_link, _max_frame_tc) \
3503                         ((36 * \
3504                           (IXGBE_B2BT(_max_frame_link) + \
3505                            IXGBE_PFC_D + \
3506                            (2 * IXGBE_CABLE_DC) + \
3507                            (2 * IXGBE_ID) + \
3508                            IXGBE_HD) / 25 + 1) + \
3509                          2 * IXGBE_B2BT(_max_frame_tc))
3510
3511 /* Calculate low threshold delay values */
3512 #define IXGBE_LOW_DV_X540(_max_frame_tc) \
3513                         (2 * IXGBE_B2BT(_max_frame_tc) + \
3514                         (36 * IXGBE_PCI_DELAY / 25) + 1)
3515 #define IXGBE_LOW_DV(_max_frame_tc) \
3516                         (2 * IXGBE_LOW_DV_X540(_max_frame_tc))
3517
3518 /* Software ATR hash keys */
3519 #define IXGBE_ATR_BUCKET_HASH_KEY       0x3DAD14E2
3520 #define IXGBE_ATR_SIGNATURE_HASH_KEY    0x174D3614
3521
3522 /* Software ATR input stream values and masks */
3523 #define IXGBE_ATR_HASH_MASK             0x7fff
3524 #define IXGBE_ATR_L4TYPE_MASK           0x3
3525 #define IXGBE_ATR_L4TYPE_UDP            0x1
3526 #define IXGBE_ATR_L4TYPE_TCP            0x2
3527 #define IXGBE_ATR_L4TYPE_SCTP           0x3
3528 #define IXGBE_ATR_L4TYPE_IPV6_MASK      0x4
3529 #define IXGBE_ATR_L4TYPE_TUNNEL_MASK    0x10
3530 enum ixgbe_atr_flow_type {
3531         IXGBE_ATR_FLOW_TYPE_IPV4        = 0x0,
3532         IXGBE_ATR_FLOW_TYPE_UDPV4       = 0x1,
3533         IXGBE_ATR_FLOW_TYPE_TCPV4       = 0x2,
3534         IXGBE_ATR_FLOW_TYPE_SCTPV4      = 0x3,
3535         IXGBE_ATR_FLOW_TYPE_IPV6        = 0x4,
3536         IXGBE_ATR_FLOW_TYPE_UDPV6       = 0x5,
3537         IXGBE_ATR_FLOW_TYPE_TCPV6       = 0x6,
3538         IXGBE_ATR_FLOW_TYPE_SCTPV6      = 0x7,
3539         IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4       = 0x10,
3540         IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4      = 0x11,
3541         IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4      = 0x12,
3542         IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4     = 0x13,
3543         IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6       = 0x14,
3544         IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6      = 0x15,
3545         IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6      = 0x16,
3546         IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6     = 0x17,
3547 };
3548
3549 /* Flow Director ATR input struct. */
3550 union ixgbe_atr_input {
3551         /*
3552          * Byte layout in order, all values with MSB first:
3553          *
3554          * vm_pool      - 1 byte
3555          * flow_type    - 1 byte
3556          * vlan_id      - 2 bytes
3557          * src_ip       - 16 bytes
3558          * inner_mac    - 6 bytes
3559          * cloud_mode   - 2 bytes
3560          * tni_vni      - 4 bytes
3561          * dst_ip       - 16 bytes
3562          * src_port     - 2 bytes
3563          * dst_port     - 2 bytes
3564          * flex_bytes   - 2 bytes
3565          * bkt_hash     - 2 bytes
3566          */
3567         struct {
3568                 u8 vm_pool;
3569                 u8 flow_type;
3570                 __be16 vlan_id;
3571                 __be32 dst_ip[4];
3572                 __be32 src_ip[4];
3573                 u8 inner_mac[6];
3574                 __be16 tunnel_type;
3575                 __be32 tni_vni;
3576                 __be16 src_port;
3577                 __be16 dst_port;
3578                 __be16 flex_bytes;
3579                 __be16 bkt_hash;
3580         } formatted;
3581         __be32 dword_stream[14];
3582 };
3583
3584 /* Flow Director compressed ATR hash input struct */
3585 union ixgbe_atr_hash_dword {
3586         struct {
3587                 u8 vm_pool;
3588                 u8 flow_type;
3589                 __be16 vlan_id;
3590         } formatted;
3591         __be32 ip;
3592         struct {
3593                 __be16 src;
3594                 __be16 dst;
3595         } port;
3596         __be16 flex_bytes;
3597         __be32 dword;
3598 };
3599
3600
3601 #define IXGBE_MVALS_INIT(m)     \
3602         IXGBE_CAT(EEC, m),              \
3603         IXGBE_CAT(FLA, m),              \
3604         IXGBE_CAT(GRC, m),              \
3605         IXGBE_CAT(SRAMREL, m),          \
3606         IXGBE_CAT(FACTPS, m),           \
3607         IXGBE_CAT(SWSM, m),             \
3608         IXGBE_CAT(SWFW_SYNC, m),        \
3609         IXGBE_CAT(FWSM, m),             \
3610         IXGBE_CAT(SDP0_GPIEN, m),       \
3611         IXGBE_CAT(SDP1_GPIEN, m),       \
3612         IXGBE_CAT(SDP2_GPIEN, m),       \
3613         IXGBE_CAT(EICR_GPI_SDP0, m),    \
3614         IXGBE_CAT(EICR_GPI_SDP1, m),    \
3615         IXGBE_CAT(EICR_GPI_SDP2, m),    \
3616         IXGBE_CAT(CIAA, m),             \
3617         IXGBE_CAT(CIAD, m),             \
3618         IXGBE_CAT(I2C_CLK_IN, m),       \
3619         IXGBE_CAT(I2C_CLK_OUT, m),      \
3620         IXGBE_CAT(I2C_DATA_IN, m),      \
3621         IXGBE_CAT(I2C_DATA_OUT, m),     \
3622         IXGBE_CAT(I2C_DATA_OE_N_EN, m), \
3623         IXGBE_CAT(I2C_BB_EN, m),        \
3624         IXGBE_CAT(I2C_CLK_OE_N_EN, m),  \
3625         IXGBE_CAT(I2CCTL, m)
3626
3627 enum ixgbe_mvals {
3628         IXGBE_MVALS_INIT(_IDX),
3629         IXGBE_MVALS_IDX_LIMIT
3630 };
3631
3632 /*
3633  * Unavailable: The FCoE Boot Option ROM is not present in the flash.
3634  * Disabled: Present; boot order is not set for any targets on the port.
3635  * Enabled: Present; boot order is set for at least one target on the port.
3636  */
3637 enum ixgbe_fcoe_boot_status {
3638         ixgbe_fcoe_bootstatus_disabled = 0,
3639         ixgbe_fcoe_bootstatus_enabled = 1,
3640         ixgbe_fcoe_bootstatus_unavailable = 0xFFFF
3641 };
3642
3643 enum ixgbe_eeprom_type {
3644         ixgbe_eeprom_uninitialized = 0,
3645         ixgbe_eeprom_spi,
3646         ixgbe_flash,
3647         ixgbe_eeprom_none /* No NVM support */
3648 };
3649
3650 enum ixgbe_mac_type {
3651         ixgbe_mac_unknown = 0,
3652         ixgbe_mac_82598EB,
3653         ixgbe_mac_82599EB,
3654         ixgbe_mac_82599_vf,
3655         ixgbe_mac_X540,
3656         ixgbe_mac_X540_vf,
3657         ixgbe_mac_X550,
3658         ixgbe_mac_X550EM_x,
3659         ixgbe_mac_X550EM_a,
3660         ixgbe_mac_X550_vf,
3661         ixgbe_mac_X550EM_x_vf,
3662         ixgbe_mac_X550EM_a_vf,
3663         ixgbe_num_macs
3664 };
3665
3666 enum ixgbe_phy_type {
3667         ixgbe_phy_unknown = 0,
3668         ixgbe_phy_none,
3669         ixgbe_phy_tn,
3670         ixgbe_phy_aq,
3671         ixgbe_phy_x550em_kr,
3672         ixgbe_phy_x550em_kx4,
3673         ixgbe_phy_x550em_xfi,
3674         ixgbe_phy_x550em_ext_t,
3675         ixgbe_phy_ext_1g_t,
3676         ixgbe_phy_cu_unknown,
3677         ixgbe_phy_qt,
3678         ixgbe_phy_xaui,
3679         ixgbe_phy_nl,
3680         ixgbe_phy_sfp_passive_tyco,
3681         ixgbe_phy_sfp_passive_unknown,
3682         ixgbe_phy_sfp_active_unknown,
3683         ixgbe_phy_sfp_avago,
3684         ixgbe_phy_sfp_ftl,
3685         ixgbe_phy_sfp_ftl_active,
3686         ixgbe_phy_sfp_unknown,
3687         ixgbe_phy_sfp_intel,
3688         ixgbe_phy_qsfp_passive_unknown,
3689         ixgbe_phy_qsfp_active_unknown,
3690         ixgbe_phy_qsfp_intel,
3691         ixgbe_phy_qsfp_unknown,
3692         ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/
3693         ixgbe_phy_sgmii,
3694         ixgbe_phy_fw,
3695         ixgbe_phy_generic
3696 };
3697
3698 /*
3699  * SFP+ module type IDs:
3700  *
3701  * ID   Module Type
3702  * =============
3703  * 0    SFP_DA_CU
3704  * 1    SFP_SR
3705  * 2    SFP_LR
3706  * 3    SFP_DA_CU_CORE0 - 82599-specific
3707  * 4    SFP_DA_CU_CORE1 - 82599-specific
3708  * 5    SFP_SR/LR_CORE0 - 82599-specific
3709  * 6    SFP_SR/LR_CORE1 - 82599-specific
3710  */
3711 enum ixgbe_sfp_type {
3712         ixgbe_sfp_type_da_cu = 0,
3713         ixgbe_sfp_type_sr = 1,
3714         ixgbe_sfp_type_lr = 2,
3715         ixgbe_sfp_type_da_cu_core0 = 3,
3716         ixgbe_sfp_type_da_cu_core1 = 4,
3717         ixgbe_sfp_type_srlr_core0 = 5,
3718         ixgbe_sfp_type_srlr_core1 = 6,
3719         ixgbe_sfp_type_da_act_lmt_core0 = 7,
3720         ixgbe_sfp_type_da_act_lmt_core1 = 8,
3721         ixgbe_sfp_type_1g_cu_core0 = 9,
3722         ixgbe_sfp_type_1g_cu_core1 = 10,
3723         ixgbe_sfp_type_1g_sx_core0 = 11,
3724         ixgbe_sfp_type_1g_sx_core1 = 12,
3725         ixgbe_sfp_type_1g_lx_core0 = 13,
3726         ixgbe_sfp_type_1g_lx_core1 = 14,
3727         ixgbe_sfp_type_1g_lha_core0 = 15,
3728         ixgbe_sfp_type_1g_lha_core1 = 16,
3729         ixgbe_sfp_type_not_present = 0xFFFE,
3730         ixgbe_sfp_type_unknown = 0xFFFF
3731 };
3732
3733 enum ixgbe_media_type {
3734         ixgbe_media_type_unknown = 0,
3735         ixgbe_media_type_fiber,
3736         ixgbe_media_type_fiber_qsfp,
3737         ixgbe_media_type_copper,
3738         ixgbe_media_type_backplane,
3739         ixgbe_media_type_cx4,
3740         ixgbe_media_type_virtual
3741 };
3742
3743 /* Flow Control Settings */
3744 enum ixgbe_fc_mode {
3745         ixgbe_fc_none = 0,
3746         ixgbe_fc_rx_pause,
3747         ixgbe_fc_tx_pause,
3748         ixgbe_fc_full,
3749         ixgbe_fc_default
3750 };
3751
3752 /* Smart Speed Settings */
3753 #define IXGBE_SMARTSPEED_MAX_RETRIES    3
3754 enum ixgbe_smart_speed {
3755         ixgbe_smart_speed_auto = 0,
3756         ixgbe_smart_speed_on,
3757         ixgbe_smart_speed_off
3758 };
3759
3760 /* PCI bus types */
3761 enum ixgbe_bus_type {
3762         ixgbe_bus_type_unknown = 0,
3763         ixgbe_bus_type_pci,
3764         ixgbe_bus_type_pcix,
3765         ixgbe_bus_type_pci_express,
3766         ixgbe_bus_type_internal,
3767         ixgbe_bus_type_reserved
3768 };
3769
3770 /* PCI bus speeds */
3771 enum ixgbe_bus_speed {
3772         ixgbe_bus_speed_unknown = 0,
3773         ixgbe_bus_speed_33      = 33,
3774         ixgbe_bus_speed_66      = 66,
3775         ixgbe_bus_speed_100     = 100,
3776         ixgbe_bus_speed_120     = 120,
3777         ixgbe_bus_speed_133     = 133,
3778         ixgbe_bus_speed_2500    = 2500,
3779         ixgbe_bus_speed_5000    = 5000,
3780         ixgbe_bus_speed_8000    = 8000,
3781         ixgbe_bus_speed_reserved
3782 };
3783
3784 /* PCI bus widths */
3785 enum ixgbe_bus_width {
3786         ixgbe_bus_width_unknown = 0,
3787         ixgbe_bus_width_pcie_x1 = 1,
3788         ixgbe_bus_width_pcie_x2 = 2,
3789         ixgbe_bus_width_pcie_x4 = 4,
3790         ixgbe_bus_width_pcie_x8 = 8,
3791         ixgbe_bus_width_32      = 32,
3792         ixgbe_bus_width_64      = 64,
3793         ixgbe_bus_width_reserved
3794 };
3795
3796 struct ixgbe_addr_filter_info {
3797         u32 num_mc_addrs;
3798         u32 rar_used_count;
3799         u32 mta_in_use;
3800         u32 overflow_promisc;
3801         bool user_set_promisc;
3802 };
3803
3804 /* Bus parameters */
3805 struct ixgbe_bus_info {
3806         enum ixgbe_bus_speed speed;
3807         enum ixgbe_bus_width width;
3808         enum ixgbe_bus_type type;
3809
3810         u16 func;
3811         u8 lan_id;
3812         u16 instance_id;
3813 };
3814
3815 /* Flow control parameters */
3816 struct ixgbe_fc_info {
3817         u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */
3818         u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */
3819         u16 pause_time; /* Flow Control Pause timer */
3820         bool send_xon; /* Flow control send XON */
3821         bool strict_ieee; /* Strict IEEE mode */
3822         bool disable_fc_autoneg; /* Do not autonegotiate FC */
3823         bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
3824         enum ixgbe_fc_mode current_mode; /* FC mode in effect */
3825         enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
3826 };
3827
3828 /* Statistics counters collected by the MAC */
3829 struct ixgbe_hw_stats {
3830         u64 crcerrs;
3831         u64 illerrc;
3832         u64 errbc;
3833         u64 mspdc;
3834         u64 mpctotal;
3835         u64 mpc[8];
3836         u64 mlfc;
3837         u64 mrfc;
3838         u64 rlec;
3839         u64 lxontxc;
3840         u64 lxonrxc;
3841         u64 lxofftxc;
3842         u64 lxoffrxc;
3843         u64 pxontxc[8];
3844         u64 pxonrxc[8];
3845         u64 pxofftxc[8];
3846         u64 pxoffrxc[8];
3847         u64 prc64;
3848         u64 prc127;
3849         u64 prc255;
3850         u64 prc511;
3851         u64 prc1023;
3852         u64 prc1522;
3853         u64 gprc;
3854         u64 bprc;
3855         u64 mprc;
3856         u64 gptc;
3857         u64 gorc;
3858         u64 gotc;
3859         u64 rnbc[8];
3860         u64 ruc;
3861         u64 rfc;
3862         u64 roc;
3863         u64 rjc;
3864         u64 mngprc;
3865         u64 mngpdc;
3866         u64 mngptc;
3867         u64 tor;
3868         u64 tpr;
3869         u64 tpt;
3870         u64 ptc64;
3871         u64 ptc127;
3872         u64 ptc255;
3873         u64 ptc511;
3874         u64 ptc1023;
3875         u64 ptc1522;
3876         u64 mptc;
3877         u64 bptc;
3878         u64 xec;
3879         u64 qprc[16];
3880         u64 qptc[16];
3881         u64 qbrc[16];
3882         u64 qbtc[16];
3883         u64 qprdc[16];
3884         u64 pxon2offc[8];
3885         u64 fdirustat_add;
3886         u64 fdirustat_remove;
3887         u64 fdirfstat_fadd;
3888         u64 fdirfstat_fremove;
3889         u64 fdirmatch;
3890         u64 fdirmiss;
3891         u64 fccrc;
3892         u64 fclast;
3893         u64 fcoerpdc;
3894         u64 fcoeprc;
3895         u64 fcoeptc;
3896         u64 fcoedwrc;
3897         u64 fcoedwtc;
3898         u64 fcoe_noddp;
3899         u64 fcoe_noddp_ext_buff;
3900         u64 ldpcec;
3901         u64 pcrc8ec;
3902         u64 b2ospc;
3903         u64 b2ogprc;
3904         u64 o2bgptc;
3905         u64 o2bspc;
3906 };
3907
3908 /* forward declaration */
3909 struct ixgbe_hw;
3910
3911 /* iterator type for walking multicast address lists */
3912 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
3913                                   u32 *vmdq);
3914
3915 /* Function pointer table */
3916 struct ixgbe_eeprom_operations {
3917         s32 (*init_params)(struct ixgbe_hw *);
3918         s32 (*read)(struct ixgbe_hw *, u16, u16 *);
3919         s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
3920         s32 (*write)(struct ixgbe_hw *, u16, u16);
3921         s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
3922         s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
3923         s32 (*update_checksum)(struct ixgbe_hw *);
3924         s32 (*calc_checksum)(struct ixgbe_hw *);
3925 };
3926
3927 struct ixgbe_mac_operations {
3928         s32 (*init_hw)(struct ixgbe_hw *);
3929         s32 (*reset_hw)(struct ixgbe_hw *);
3930         s32 (*start_hw)(struct ixgbe_hw *);
3931         s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
3932         void (*enable_relaxed_ordering)(struct ixgbe_hw *);
3933         enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
3934         u64 (*get_supported_physical_layer)(struct ixgbe_hw *);
3935         s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
3936         s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
3937         s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *);
3938         s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
3939         s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
3940         s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *);
3941         s32 (*stop_adapter)(struct ixgbe_hw *);
3942         s32 (*get_bus_info)(struct ixgbe_hw *);
3943         void (*set_lan_id)(struct ixgbe_hw *);
3944         s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
3945         s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
3946         s32 (*setup_sfp)(struct ixgbe_hw *);
3947         s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
3948         s32 (*disable_sec_rx_path)(struct ixgbe_hw *);
3949         s32 (*enable_sec_rx_path)(struct ixgbe_hw *);
3950         s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32);
3951         void (*release_swfw_sync)(struct ixgbe_hw *, u32);
3952         void (*init_swfw_sync)(struct ixgbe_hw *);
3953         s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
3954         s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
3955         s32 (*negotiate_api_version)(struct ixgbe_hw *hw, int api);
3956
3957         /* Link */
3958         void (*disable_tx_laser)(struct ixgbe_hw *);
3959         void (*enable_tx_laser)(struct ixgbe_hw *);
3960         void (*flap_tx_laser)(struct ixgbe_hw *);
3961         s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3962         s32 (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3963         s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
3964         s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
3965                                      bool *);
3966         void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed);
3967
3968         /* Packet Buffer manipulation */
3969         void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int);
3970
3971         /* LED */
3972         s32 (*led_on)(struct ixgbe_hw *, u32);
3973         s32 (*led_off)(struct ixgbe_hw *, u32);
3974         s32 (*blink_led_start)(struct ixgbe_hw *, u32);
3975         s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
3976         s32 (*init_led_link_act)(struct ixgbe_hw *);
3977
3978         /* RAR, Multicast, VLAN */
3979         s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
3980         s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);
3981         s32 (*clear_rar)(struct ixgbe_hw *, u32);
3982         s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);
3983         s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
3984         s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
3985         s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
3986         s32 (*init_rx_addrs)(struct ixgbe_hw *);
3987         s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
3988                                    ixgbe_mc_addr_itr);
3989         s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
3990                                    ixgbe_mc_addr_itr, bool clear);
3991         s32 (*enable_mc)(struct ixgbe_hw *);
3992         s32 (*disable_mc)(struct ixgbe_hw *);
3993         s32 (*clear_vfta)(struct ixgbe_hw *);
3994         s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool);
3995         s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, u32 *, u32,
3996                         bool);
3997         s32 (*init_uta_tables)(struct ixgbe_hw *);
3998         void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
3999         void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
4000         s32 (*update_xcast_mode)(struct ixgbe_hw *, int);
4001         s32 (*set_rlpml)(struct ixgbe_hw *, u16);
4002
4003         /* Flow Control */
4004         s32 (*fc_enable)(struct ixgbe_hw *);
4005         s32 (*setup_fc)(struct ixgbe_hw *);
4006         void (*fc_autoneg)(struct ixgbe_hw *);
4007
4008         /* Manageability interface */
4009         s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8, u16,
4010                               const char *);
4011         s32 (*get_thermal_sensor_data)(struct ixgbe_hw *);
4012         s32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw);
4013         void (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map);
4014         void (*disable_rx)(struct ixgbe_hw *hw);
4015         void (*enable_rx)(struct ixgbe_hw *hw);
4016         void (*set_source_address_pruning)(struct ixgbe_hw *, bool,
4017                                            unsigned int);
4018         void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int);
4019         s32 (*dmac_update_tcs)(struct ixgbe_hw *hw);
4020         s32 (*dmac_config_tcs)(struct ixgbe_hw *hw);
4021         s32 (*dmac_config)(struct ixgbe_hw *hw);
4022         s32 (*setup_eee)(struct ixgbe_hw *hw, bool enable_eee);
4023         s32 (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *);
4024         s32 (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32);
4025         void (*disable_mdd)(struct ixgbe_hw *hw);
4026         void (*enable_mdd)(struct ixgbe_hw *hw);
4027         void (*mdd_event)(struct ixgbe_hw *hw, u32 *vf_bitmap);
4028         void (*restore_mdd_vf)(struct ixgbe_hw *hw, u32 vf);
4029         bool (*fw_recovery_mode)(struct ixgbe_hw *hw);
4030 };
4031
4032 struct ixgbe_phy_operations {
4033         s32 (*identify)(struct ixgbe_hw *);
4034         s32 (*identify_sfp)(struct ixgbe_hw *);
4035         s32 (*init)(struct ixgbe_hw *);
4036         s32 (*reset)(struct ixgbe_hw *);
4037         s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
4038         s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
4039         s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);
4040         s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);
4041         s32 (*setup_link)(struct ixgbe_hw *);
4042         s32 (*setup_internal_link)(struct ixgbe_hw *);
4043         s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
4044         s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
4045         s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
4046         s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
4047         s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
4048         s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);
4049         s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
4050         s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
4051         void (*i2c_bus_clear)(struct ixgbe_hw *);
4052         s32 (*check_overtemp)(struct ixgbe_hw *);
4053         s32 (*set_phy_power)(struct ixgbe_hw *, bool on);
4054         s32 (*enter_lplu)(struct ixgbe_hw *);
4055         s32 (*handle_lasi)(struct ixgbe_hw *hw);
4056         s32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
4057                                       u8 *value);
4058         s32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
4059                                        u8 value);
4060 };
4061
4062 struct ixgbe_link_operations {
4063         s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);
4064         s32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
4065                                   u16 *val);
4066         s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);
4067         s32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
4068                                    u16 val);
4069 };
4070
4071 struct ixgbe_link_info {
4072         struct ixgbe_link_operations ops;
4073         u8 addr;
4074 };
4075
4076 struct ixgbe_eeprom_info {
4077         struct ixgbe_eeprom_operations ops;
4078         enum ixgbe_eeprom_type type;
4079         u32 semaphore_delay;
4080         u16 word_size;
4081         u16 address_bits;
4082         u16 word_page_size;
4083         u16 ctrl_word_3;
4084 };
4085
4086 #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED       0x01
4087 struct ixgbe_mac_info {
4088         struct ixgbe_mac_operations ops;
4089         enum ixgbe_mac_type type;
4090         u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
4091         u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
4092         u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
4093         /* prefix for World Wide Node Name (WWNN) */
4094         u16 wwnn_prefix;
4095         /* prefix for World Wide Port Name (WWPN) */
4096         u16 wwpn_prefix;
4097 #define IXGBE_MAX_MTA                   128
4098         u32 mta_shadow[IXGBE_MAX_MTA];
4099         s32 mc_filter_type;
4100         u32 mcft_size;
4101         u32 vft_size;
4102         u32 num_rar_entries;
4103         u32 rar_highwater;
4104         u32 rx_pb_size;
4105         u32 max_tx_queues;
4106         u32 max_rx_queues;
4107         u32 orig_autoc;
4108         u8  san_mac_rar_index;
4109         bool get_link_status;
4110         u32 orig_autoc2;
4111         u16 max_msix_vectors;
4112         bool arc_subsystem_valid;
4113         bool orig_link_settings_stored;
4114         bool autotry_restart;
4115         u8 flags;
4116         struct ixgbe_thermal_sensor_data  thermal_sensor_data;
4117         bool thermal_sensor_enabled;
4118         struct ixgbe_dmac_config dmac_config;
4119         bool set_lben;
4120         u32  max_link_up_time;
4121         u8   led_link_act;
4122 };
4123
4124 struct ixgbe_phy_info {
4125         struct ixgbe_phy_operations ops;
4126         enum ixgbe_phy_type type;
4127         u32 addr;
4128         u32 id;
4129         enum ixgbe_sfp_type sfp_type;
4130         bool sfp_setup_needed;
4131         u32 revision;
4132         enum ixgbe_media_type media_type;
4133         u32 phy_semaphore_mask;
4134         bool reset_disable;
4135         ixgbe_autoneg_advertised autoneg_advertised;
4136         ixgbe_link_speed speeds_supported;
4137         ixgbe_link_speed eee_speeds_supported;
4138         ixgbe_link_speed eee_speeds_advertised;
4139         enum ixgbe_smart_speed smart_speed;
4140         bool smart_speed_active;
4141         bool multispeed_fiber;
4142         bool reset_if_overtemp;
4143         bool qsfp_shared_i2c_bus;
4144         u32 nw_mng_if_sel;
4145 };
4146
4147 #include "ixgbe_mbx.h"
4148
4149 struct ixgbe_mbx_operations {
4150         void (*init_params)(struct ixgbe_hw *hw);
4151         s32  (*read)(struct ixgbe_hw *, u32 *, u16,  u16);
4152         s32  (*write)(struct ixgbe_hw *, u32 *, u16, u16);
4153         s32  (*read_posted)(struct ixgbe_hw *, u32 *, u16,  u16);
4154         s32  (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
4155         s32  (*check_for_msg)(struct ixgbe_hw *, u16);
4156         s32  (*check_for_ack)(struct ixgbe_hw *, u16);
4157         s32  (*check_for_rst)(struct ixgbe_hw *, u16);
4158 };
4159
4160 struct ixgbe_mbx_stats {
4161         u32 msgs_tx;
4162         u32 msgs_rx;
4163
4164         u32 acks;
4165         u32 reqs;
4166         u32 rsts;
4167 };
4168
4169 struct ixgbe_mbx_info {
4170         struct ixgbe_mbx_operations ops;
4171         struct ixgbe_mbx_stats stats;
4172         u32 timeout;
4173         u32 usec_delay;
4174         u32 v2p_mailbox;
4175         u16 size;
4176 };
4177
4178 struct ixgbe_hw {
4179         u8 IOMEM *hw_addr;
4180         void *back;
4181         struct ixgbe_mac_info mac;
4182         struct ixgbe_addr_filter_info addr_ctrl;
4183         struct ixgbe_fc_info fc;
4184         struct ixgbe_phy_info phy;
4185         struct ixgbe_link_info link;
4186         struct ixgbe_eeprom_info eeprom;
4187         struct ixgbe_bus_info bus;
4188         struct ixgbe_mbx_info mbx;
4189         const u32 *mvals;
4190         u16 device_id;
4191         u16 vendor_id;
4192         u16 subsystem_device_id;
4193         u16 subsystem_vendor_id;
4194         u8 revision_id;
4195         bool adapter_stopped;
4196         int api_version;
4197         bool force_full_reset;
4198         bool allow_unsupported_sfp;
4199         bool wol_enabled;
4200         bool need_crosstalk_fix;
4201 };
4202
4203 #define ixgbe_call_func(hw, func, params, error) \
4204                 (func != NULL) ? func params : error
4205
4206
4207 /* Error Codes */
4208 #define IXGBE_SUCCESS                           0
4209 #define IXGBE_ERR_EEPROM                        -1
4210 #define IXGBE_ERR_EEPROM_CHECKSUM               -2
4211 #define IXGBE_ERR_PHY                           -3
4212 #define IXGBE_ERR_CONFIG                        -4
4213 #define IXGBE_ERR_PARAM                         -5
4214 #define IXGBE_ERR_MAC_TYPE                      -6
4215 #define IXGBE_ERR_UNKNOWN_PHY                   -7
4216 #define IXGBE_ERR_LINK_SETUP                    -8
4217 #define IXGBE_ERR_ADAPTER_STOPPED               -9
4218 #define IXGBE_ERR_INVALID_MAC_ADDR              -10
4219 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED          -11
4220 #define IXGBE_ERR_MASTER_REQUESTS_PENDING       -12
4221 #define IXGBE_ERR_INVALID_LINK_SETTINGS         -13
4222 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE          -14
4223 #define IXGBE_ERR_RESET_FAILED                  -15
4224 #define IXGBE_ERR_SWFW_SYNC                     -16
4225 #define IXGBE_ERR_PHY_ADDR_INVALID              -17
4226 #define IXGBE_ERR_I2C                           -18
4227 #define IXGBE_ERR_SFP_NOT_SUPPORTED             -19
4228 #define IXGBE_ERR_SFP_NOT_PRESENT               -20
4229 #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT       -21
4230 #define IXGBE_ERR_NO_SAN_ADDR_PTR               -22
4231 #define IXGBE_ERR_FDIR_REINIT_FAILED            -23
4232 #define IXGBE_ERR_EEPROM_VERSION                -24
4233 #define IXGBE_ERR_NO_SPACE                      -25
4234 #define IXGBE_ERR_OVERTEMP                      -26
4235 #define IXGBE_ERR_FC_NOT_NEGOTIATED             -27
4236 #define IXGBE_ERR_FC_NOT_SUPPORTED              -28
4237 #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE        -30
4238 #define IXGBE_ERR_PBA_SECTION                   -31
4239 #define IXGBE_ERR_INVALID_ARGUMENT              -32
4240 #define IXGBE_ERR_HOST_INTERFACE_COMMAND        -33
4241 #define IXGBE_ERR_OUT_OF_MEM                    -34
4242 #define IXGBE_ERR_FEATURE_NOT_SUPPORTED         -36
4243 #define IXGBE_ERR_EEPROM_PROTECTED_REGION       -37
4244 #define IXGBE_ERR_FDIR_CMD_INCOMPLETE           -38
4245 #define IXGBE_ERR_FW_RESP_INVALID               -39
4246 #define IXGBE_ERR_TOKEN_RETRY                   -40
4247
4248 #define IXGBE_NOT_IMPLEMENTED                   0x7FFFFFFF
4249
4250 #define IXGBE_FUSES0_GROUP(_i)          (0x11158 + ((_i) * 4))
4251 #define IXGBE_FUSES0_300MHZ             (1 << 5)
4252 #define IXGBE_FUSES0_REV_MASK           (3 << 6)
4253
4254 #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P)  ((P) ? 0x8010 : 0x4010)
4255 #define IXGBE_KRM_LINK_S1(P)            ((P) ? 0x8200 : 0x4200)
4256 #define IXGBE_KRM_LINK_CTRL_1(P)        ((P) ? 0x820C : 0x420C)
4257 #define IXGBE_KRM_AN_CNTL_1(P)          ((P) ? 0x822C : 0x422C)
4258 #define IXGBE_KRM_AN_CNTL_4(P)          ((P) ? 0x8238 : 0x4238)
4259 #define IXGBE_KRM_AN_CNTL_8(P)          ((P) ? 0x8248 : 0x4248)
4260 #define IXGBE_KRM_PCS_KX_AN(P)          ((P) ? 0x9918 : 0x5918)
4261 #define IXGBE_KRM_PCS_KX_AN_LP(P)       ((P) ? 0x991C : 0x591C)
4262 #define IXGBE_KRM_SGMII_CTRL(P)         ((P) ? 0x82A0 : 0x42A0)
4263 #define IXGBE_KRM_LP_BASE_PAGE_HIGH(P)  ((P) ? 0x836C : 0x436C)
4264 #define IXGBE_KRM_DSP_TXFFE_STATE_4(P)  ((P) ? 0x8634 : 0x4634)
4265 #define IXGBE_KRM_DSP_TXFFE_STATE_5(P)  ((P) ? 0x8638 : 0x4638)
4266 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00)
4267 #define IXGBE_KRM_PMD_DFX_BURNIN(P)     ((P) ? 0x8E00 : 0x4E00)
4268 #define IXGBE_KRM_PMD_FLX_MASK_ST20(P)  ((P) ? 0x9054 : 0x5054)
4269 #define IXGBE_KRM_TX_COEFF_CTRL_1(P)    ((P) ? 0x9520 : 0x5520)
4270 #define IXGBE_KRM_RX_ANA_CTL(P)         ((P) ? 0x9A00 : 0x5A00)
4271
4272 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA          ~(0x3 << 20)
4273 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR          (1u << 20)
4274 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_LR          (0x2 << 20)
4275 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN            (1u << 25)
4276 #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN             (1u << 26)
4277 #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN               (1u << 27)
4278 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M           ~(0x7 << 28)
4279 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M          (1u << 28)
4280 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G            (0x2 << 28)
4281 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G           (0x3 << 28)
4282 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN            (0x4 << 28)
4283 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G          (0x7 << 28)
4284 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK          (0x7 << 28)
4285 #define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART       (1u << 31)
4286
4287 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B            (1 << 9)
4288 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS          (1 << 11)
4289
4290 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK     (0x7 << 8)
4291 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G       (2 << 8)
4292 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G      (4 << 8)
4293 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN          (1 << 12)
4294 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN      (1 << 13)
4295 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ           (1 << 14)
4296 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC           (1 << 15)
4297 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX            (1 << 16)
4298 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR            (1 << 18)
4299 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX           (1 << 24)
4300 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR           (1 << 26)
4301 #define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE               (1 << 28)
4302 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE            (1 << 29)
4303 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART           (1 << 31)
4304
4305 #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE                   (1 << 28)
4306 #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE                   (1 << 29)
4307 #define IXGBE_KRM_PCS_KX_AN_SYM_PAUSE                   (1 << 1)
4308 #define IXGBE_KRM_PCS_KX_AN_ASM_PAUSE                   (1 << 2)
4309 #define IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE                (1 << 2)
4310 #define IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE                (1 << 3)
4311 #define IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73           (1 << 29)
4312 #define IXGBE_KRM_AN_CNTL_8_LINEAR                      (1 << 0)
4313 #define IXGBE_KRM_AN_CNTL_8_LIMITING                    (1 << 1)
4314
4315 #define IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE           (1 << 10)
4316 #define IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE           (1 << 11)
4317
4318 #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D        (1 << 12)
4319 #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D         (1 << 19)
4320
4321 #define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN                 (1 << 6)
4322 #define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN            (1 << 15)
4323 #define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN           (1 << 16)
4324
4325 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL   (1 << 4)
4326 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS    (1 << 2)
4327
4328 #define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK       (0x3 << 16)
4329
4330 #define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN      (1 << 1)
4331 #define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN       (1 << 2)
4332 #define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN              (1 << 3)
4333 #define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN              (1 << 31)
4334
4335 #define IXGBE_SB_IOSF_INDIRECT_CTRL     0x00011144
4336 #define IXGBE_SB_IOSF_INDIRECT_DATA     0x00011148
4337
4338 #define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT           0
4339 #define IXGBE_SB_IOSF_CTRL_ADDR_MASK            0xFF
4340 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT      18
4341 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK       \
4342                                 (0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT)
4343 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT       20
4344 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK        \
4345                                 (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
4346 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT  28
4347 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK   0x7
4348 #define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT           31
4349 #define IXGBE_SB_IOSF_CTRL_BUSY         (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
4350 #define IXGBE_SB_IOSF_TARGET_KR_PHY     0
4351
4352 #define IXGBE_NW_MNG_IF_SEL             0x00011178
4353 #define IXGBE_NW_MNG_IF_SEL_MDIO_ACT    (1u << 1)
4354 #define IXGBE_NW_MNG_IF_SEL_MDIO_IF_MODE        (1u << 2)
4355 #define IXGBE_NW_MNG_IF_SEL_EN_SHARED_MDIO      (1u << 13)
4356 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M       (1u << 17)
4357 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M      (1u << 18)
4358 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G        (1u << 19)
4359 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G      (1u << 20)
4360 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G       (1u << 21)
4361 #define IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE        (1u << 25)
4362 #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24) /* X552 reg field only */
4363 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3
4364 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD        \
4365                                 (0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)
4366
4367 #endif /* _IXGBE_TYPE_H_ */