ceph/src/seastar/dpdk/drivers/net/liquidio/base/lio_23xx_reg.h

   1 /*
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2017 Cavium, Inc.. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Cavium, Inc. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #ifndef _LIO_23XX_REG_H_
  35 #define _LIO_23XX_REG_H_
  36
  37 /* ###################### REQUEST QUEUE ######################### */
  38
  39 /* 64 registers for Input Queues Start Addr - SLI_PKT(0..63)_INSTR_BADDR */
  40 #define CN23XX_SLI_PKT_INSTR_BADDR_START64      0x10010
  41
  42 /* 64 registers for Input Doorbell - SLI_PKT(0..63)_INSTR_BAOFF_DBELL */
  43 #define CN23XX_SLI_PKT_INSTR_BADDR_DBELL_START  0x10020
  44
  45 /* 64 registers for Input Queue size - SLI_PKT(0..63)_INSTR_FIFO_RSIZE */
  46 #define CN23XX_SLI_PKT_INSTR_FIFO_RSIZE_START   0x10030
  47
  48 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE(0..63)_CNTS */
  49 #define CN23XX_SLI_PKT_IN_DONE_CNTS_START64     0x10040
  50
  51 /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data &
  52  * gather list fetches. SLI_PKT(0..63)_INPUT_CONTROL.
  53  */
  54 #define CN23XX_SLI_PKT_INPUT_CONTROL_START64    0x10000
  55
  56 /* ------- Request Queue Macros --------- */
  57
  58 /* Each Input Queue register is at a 16-byte Offset in BAR0 */
  59 #define CN23XX_IQ_OFFSET                        0x20000
  60
  61 #define CN23XX_SLI_IQ_PKT_CONTROL64(iq)                                 \
  62         (CN23XX_SLI_PKT_INPUT_CONTROL_START64 + ((iq) * CN23XX_IQ_OFFSET))
  63
  64 #define CN23XX_SLI_IQ_BASE_ADDR64(iq)                                   \
  65         (CN23XX_SLI_PKT_INSTR_BADDR_START64 + ((iq) * CN23XX_IQ_OFFSET))
  66
  67 #define CN23XX_SLI_IQ_SIZE(iq)                                          \
  68         (CN23XX_SLI_PKT_INSTR_FIFO_RSIZE_START + ((iq) * CN23XX_IQ_OFFSET))
  69
  70 #define CN23XX_SLI_IQ_DOORBELL(iq)                                      \
  71         (CN23XX_SLI_PKT_INSTR_BADDR_DBELL_START + ((iq) * CN23XX_IQ_OFFSET))
  72
  73 #define CN23XX_SLI_IQ_INSTR_COUNT64(iq)                                 \
  74         (CN23XX_SLI_PKT_IN_DONE_CNTS_START64 + ((iq) * CN23XX_IQ_OFFSET))
  75
  76 /* Number of instructions to be read in one MAC read request.
  77  * setting to Max value(4)
  78  */
  79 #define CN23XX_PKT_INPUT_CTL_RDSIZE                     (3 << 25)
  80 #define CN23XX_PKT_INPUT_CTL_IS_64B                     (1 << 24)
  81 #define CN23XX_PKT_INPUT_CTL_RST                        (1 << 23)
  82 #define CN23XX_PKT_INPUT_CTL_QUIET                      (1 << 28)
  83 #define CN23XX_PKT_INPUT_CTL_RING_ENB                   (1 << 22)
  84 #define CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP           (1 << 6)
  85 #define CN23XX_PKT_INPUT_CTL_USE_CSR                    (1 << 4)
  86 #define CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP         (2)
  87
  88 /* These bits[47:44] select the Physical function number within the MAC */
  89 #define CN23XX_PKT_INPUT_CTL_PF_NUM_POS         45
  90 /* These bits[43:32] select the function number within the PF */
  91 #define CN23XX_PKT_INPUT_CTL_VF_NUM_POS         32
  92
  93 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
  94 #define CN23XX_PKT_INPUT_CTL_MASK                       \
  95         (CN23XX_PKT_INPUT_CTL_RDSIZE |                  \
  96          CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP |        \
  97          CN23XX_PKT_INPUT_CTL_USE_CSR)
  98 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
  99 #define CN23XX_PKT_INPUT_CTL_MASK                       \
 100         (CN23XX_PKT_INPUT_CTL_RDSIZE |                  \
 101          CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP |        \
 102          CN23XX_PKT_INPUT_CTL_USE_CSR |                 \
 103          CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP)
 104 #endif
 105
 106 /* ############################ OUTPUT QUEUE ######################### */
 107
 108 /* 64 registers for Output queue control - SLI_PKT(0..63)_OUTPUT_CONTROL */
 109 #define CN23XX_SLI_PKT_OUTPUT_CONTROL_START     0x10050
 110
 111 /* 64 registers for Output queue buffer and info size
 112  * SLI_PKT(0..63)_OUT_SIZE
 113  */
 114 #define CN23XX_SLI_PKT_OUT_SIZE                 0x10060
 115
 116 /* 64 registers for Output Queue Start Addr - SLI_PKT(0..63)_SLIST_BADDR */
 117 #define CN23XX_SLI_SLIST_BADDR_START64          0x10070
 118
 119 /* 64 registers for Output Queue Packet Credits
 120  * SLI_PKT(0..63)_SLIST_BAOFF_DBELL
 121  */
 122 #define CN23XX_SLI_PKT_SLIST_BAOFF_DBELL_START  0x10080
 123
 124 /* 64 registers for Output Queue size - SLI_PKT(0..63)_SLIST_FIFO_RSIZE */
 125 #define CN23XX_SLI_PKT_SLIST_FIFO_RSIZE_START   0x10090
 126
 127 /* 64 registers for Output Queue Packet Count - SLI_PKT(0..63)_CNTS */
 128 #define CN23XX_SLI_PKT_CNTS_START               0x100B0
 129
 130 /* Each Output Queue register is at a 16-byte Offset in BAR0 */
 131 #define CN23XX_OQ_OFFSET                        0x20000
 132
 133 /* ------- Output Queue Macros --------- */
 134
 135 #define CN23XX_SLI_OQ_PKT_CONTROL(oq)                                   \
 136         (CN23XX_SLI_PKT_OUTPUT_CONTROL_START + ((oq) * CN23XX_OQ_OFFSET))
 137
 138 #define CN23XX_SLI_OQ_BASE_ADDR64(oq)                                   \
 139         (CN23XX_SLI_SLIST_BADDR_START64 + ((oq) * CN23XX_OQ_OFFSET))
 140
 141 #define CN23XX_SLI_OQ_SIZE(oq)                                          \
 142         (CN23XX_SLI_PKT_SLIST_FIFO_RSIZE_START + ((oq) * CN23XX_OQ_OFFSET))
 143
 144 #define CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq)                                \
 145         (CN23XX_SLI_PKT_OUT_SIZE + ((oq) * CN23XX_OQ_OFFSET))
 146
 147 #define CN23XX_SLI_OQ_PKTS_SENT(oq)                                     \
 148         (CN23XX_SLI_PKT_CNTS_START + ((oq) * CN23XX_OQ_OFFSET))
 149
 150 #define CN23XX_SLI_OQ_PKTS_CREDIT(oq)                                   \
 151         (CN23XX_SLI_PKT_SLIST_BAOFF_DBELL_START + ((oq) * CN23XX_OQ_OFFSET))
 152
 153 /* ------------------ Masks ---------------- */
 154 #define CN23XX_PKT_OUTPUT_CTL_IPTR              (1 << 11)
 155 #define CN23XX_PKT_OUTPUT_CTL_ES                (1 << 9)
 156 #define CN23XX_PKT_OUTPUT_CTL_NSR               (1 << 8)
 157 #define CN23XX_PKT_OUTPUT_CTL_ROR               (1 << 7)
 158 #define CN23XX_PKT_OUTPUT_CTL_DPTR              (1 << 6)
 159 #define CN23XX_PKT_OUTPUT_CTL_BMODE             (1 << 5)
 160 #define CN23XX_PKT_OUTPUT_CTL_ES_P              (1 << 3)
 161 #define CN23XX_PKT_OUTPUT_CTL_NSR_P             (1 << 2)
 162 #define CN23XX_PKT_OUTPUT_CTL_ROR_P             (1 << 1)
 163 #define CN23XX_PKT_OUTPUT_CTL_RING_ENB          (1 << 0)
 164
 165 /* Rings per Virtual Function [RO] */
 166 #define CN23XX_PKT_INPUT_CTL_RPVF_MASK          0x3F
 167 #define CN23XX_PKT_INPUT_CTL_RPVF_POS           48
 168
 169 /* These bits[47:44][RO] give the Physical function
 170  * number info within the MAC
 171  */
 172 #define CN23XX_PKT_INPUT_CTL_PF_NUM_MASK        0x7
 173
 174 /* These bits[43:32][RO] give the virtual function
 175  * number info within the PF
 176  */
 177 #define CN23XX_PKT_INPUT_CTL_VF_NUM_MASK        0x1FFF
 178
 179 /* ######################### Mailbox Reg Macros ######################## */
 180 #define CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START     0x10200
 181 #define CN23XX_VF_SLI_PKT_MBOX_INT_START        0x10210
 182
 183 #define CN23XX_SLI_MBOX_OFFSET                  0x20000
 184 #define CN23XX_SLI_MBOX_SIG_IDX_OFFSET          0x8
 185
 186 #define CN23XX_SLI_PKT_PF_VF_MBOX_SIG(q, idx)                           \
 187         (CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START +                          \
 188          ((q) * CN23XX_SLI_MBOX_OFFSET +                                \
 189           (idx) * CN23XX_SLI_MBOX_SIG_IDX_OFFSET))
 190
 191 #define CN23XX_VF_SLI_PKT_MBOX_INT(q)                                   \
 192         (CN23XX_VF_SLI_PKT_MBOX_INT_START + ((q) * CN23XX_SLI_MBOX_OFFSET))
 193
 194 #endif /* _LIO_23XX_REG_H_ */