ceph/src/seastar/dpdk/drivers/net/liquidio/base/lio_23xx_vf.c

   1 /*
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2017 Cavium, Inc.. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Cavium, Inc. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <string.h>
  35
  36 #include <rte_ethdev.h>
  37 #include <rte_cycles.h>
  38 #include <rte_malloc.h>
  39
  40 #include "lio_logs.h"
  41 #include "lio_23xx_vf.h"
  42 #include "lio_23xx_reg.h"
  43 #include "lio_mbox.h"
  44
  45 static int
  46 cn23xx_vf_reset_io_queues(struct lio_device *lio_dev, uint32_t num_queues)
  47 {
  48         uint32_t loop = CN23XX_VF_BUSY_READING_REG_LOOP_COUNT;
  49         uint64_t d64, q_no;
  50         int ret_val = 0;
  51
  52         PMD_INIT_FUNC_TRACE();
  53
  54         for (q_no = 0; q_no < num_queues; q_no++) {
  55                 /* set RST bit to 1. This bit applies to both IQ and OQ */
  56                 d64 = lio_read_csr64(lio_dev,
  57                                      CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
  58                 d64 = d64 | CN23XX_PKT_INPUT_CTL_RST;
  59                 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
  60                                 d64);
  61         }
  62
  63         /* wait until the RST bit is clear or the RST and QUIET bits are set */
  64         for (q_no = 0; q_no < num_queues; q_no++) {
  65                 volatile uint64_t reg_val;
  66
  67                 reg_val = lio_read_csr64(lio_dev,
  68                                          CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
  69                 while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) &&
  70                                 !(reg_val & CN23XX_PKT_INPUT_CTL_QUIET) &&
  71                                 loop) {
  72                         reg_val = lio_read_csr64(
  73                                         lio_dev,
  74                                         CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
  75                         loop = loop - 1;
  76                 }
  77
  78                 if (loop == 0) {
  79                         lio_dev_err(lio_dev,
  80                                     "clearing the reset reg failed or setting the quiet reg failed for qno: %lu\n",
  81                                     (unsigned long)q_no);
  82                         return -1;
  83                 }
  84
  85                 reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
  86                 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
  87                                 reg_val);
  88
  89                 reg_val = lio_read_csr64(
  90                     lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
  91                 if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
  92                         lio_dev_err(lio_dev,
  93                                     "clearing the reset failed for qno: %lu\n",
  94                                     (unsigned long)q_no);
  95                         ret_val = -1;
  96                 }
  97         }
  98
  99         return ret_val;
 100 }
 101
 102 static int
 103 cn23xx_vf_setup_global_input_regs(struct lio_device *lio_dev)
 104 {
 105         uint64_t q_no;
 106         uint64_t d64;
 107
 108         PMD_INIT_FUNC_TRACE();
 109
 110         if (cn23xx_vf_reset_io_queues(lio_dev,
 111                                       lio_dev->sriov_info.rings_per_vf))
 112                 return -1;
 113
 114         for (q_no = 0; q_no < (lio_dev->sriov_info.rings_per_vf); q_no++) {
 115                 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_DOORBELL(q_no),
 116                                 0xFFFFFFFF);
 117
 118                 d64 = lio_read_csr64(lio_dev,
 119                                      CN23XX_SLI_IQ_INSTR_COUNT64(q_no));
 120
 121                 d64 &= 0xEFFFFFFFFFFFFFFFL;
 122
 123                 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_INSTR_COUNT64(q_no),
 124                                 d64);
 125
 126                 /* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for
 127                  * the Input Queues
 128                  */
 129                 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
 130                                 CN23XX_PKT_INPUT_CTL_MASK);
 131         }
 132
 133         return 0;
 134 }
 135
 136 static void
 137 cn23xx_vf_setup_global_output_regs(struct lio_device *lio_dev)
 138 {
 139         uint32_t reg_val;
 140         uint32_t q_no;
 141
 142         PMD_INIT_FUNC_TRACE();
 143
 144         for (q_no = 0; q_no < lio_dev->sriov_info.rings_per_vf; q_no++) {
 145                 lio_write_csr(lio_dev, CN23XX_SLI_OQ_PKTS_CREDIT(q_no),
 146                               0xFFFFFFFF);
 147
 148                 reg_val =
 149                     lio_read_csr(lio_dev, CN23XX_SLI_OQ_PKTS_SENT(q_no));
 150
 151                 reg_val &= 0xEFFFFFFFFFFFFFFFL;
 152
 153                 reg_val =
 154                     lio_read_csr(lio_dev, CN23XX_SLI_OQ_PKT_CONTROL(q_no));
 155
 156                 /* set IPTR & DPTR */
 157                 reg_val |=
 158                     (CN23XX_PKT_OUTPUT_CTL_IPTR | CN23XX_PKT_OUTPUT_CTL_DPTR);
 159
 160                 /* reset BMODE */
 161                 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE);
 162
 163                 /* No Relaxed Ordering, No Snoop, 64-bit Byte swap
 164                  * for Output Queue Scatter List
 165                  * reset ROR_P, NSR_P
 166                  */
 167                 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P);
 168                 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P);
 169
 170 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
 171                 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P);
 172 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
 173                 reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P);
 174 #endif
 175                 /* No Relaxed Ordering, No Snoop, 64-bit Byte swap
 176                  * for Output Queue Data
 177                  * reset ROR, NSR
 178                  */
 179                 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR);
 180                 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR);
 181                 /* set the ES bit */
 182                 reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES);
 183
 184                 /* write all the selected settings */
 185                 lio_write_csr(lio_dev, CN23XX_SLI_OQ_PKT_CONTROL(q_no),
 186                               reg_val);
 187         }
 188 }
 189
 190 static int
 191 cn23xx_vf_setup_device_regs(struct lio_device *lio_dev)
 192 {
 193         PMD_INIT_FUNC_TRACE();
 194
 195         if (cn23xx_vf_setup_global_input_regs(lio_dev))
 196                 return -1;
 197
 198         cn23xx_vf_setup_global_output_regs(lio_dev);
 199
 200         return 0;
 201 }
 202
 203 static void
 204 cn23xx_vf_setup_iq_regs(struct lio_device *lio_dev, uint32_t iq_no)
 205 {
 206         struct lio_instr_queue *iq = lio_dev->instr_queue[iq_no];
 207         uint64_t pkt_in_done = 0;
 208
 209         PMD_INIT_FUNC_TRACE();
 210
 211         /* Write the start of the input queue's ring and its size */
 212         lio_write_csr64(lio_dev, CN23XX_SLI_IQ_BASE_ADDR64(iq_no),
 213                         iq->base_addr_dma);
 214         lio_write_csr(lio_dev, CN23XX_SLI_IQ_SIZE(iq_no), iq->max_count);
 215
 216         /* Remember the doorbell & instruction count register addr
 217          * for this queue
 218          */
 219         iq->doorbell_reg = (uint8_t *)lio_dev->hw_addr +
 220                                 CN23XX_SLI_IQ_DOORBELL(iq_no);
 221         iq->inst_cnt_reg = (uint8_t *)lio_dev->hw_addr +
 222                                 CN23XX_SLI_IQ_INSTR_COUNT64(iq_no);
 223         lio_dev_dbg(lio_dev, "InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n",
 224                     iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
 225
 226         /* Store the current instruction counter (used in flush_iq
 227          * calculation)
 228          */
 229         pkt_in_done = rte_read64(iq->inst_cnt_reg);
 230
 231         /* Clear the count by writing back what we read, but don't
 232          * enable data traffic here
 233          */
 234         rte_write64(pkt_in_done, iq->inst_cnt_reg);
 235 }
 236
 237 static void
 238 cn23xx_vf_setup_oq_regs(struct lio_device *lio_dev, uint32_t oq_no)
 239 {
 240         struct lio_droq *droq = lio_dev->droq[oq_no];
 241
 242         PMD_INIT_FUNC_TRACE();
 243
 244         lio_write_csr64(lio_dev, CN23XX_SLI_OQ_BASE_ADDR64(oq_no),
 245                         droq->desc_ring_dma);
 246         lio_write_csr(lio_dev, CN23XX_SLI_OQ_SIZE(oq_no), droq->max_count);
 247
 248         lio_write_csr(lio_dev, CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq_no),
 249                       (droq->buffer_size | (OCTEON_RH_SIZE << 16)));
 250
 251         /* Get the mapped address of the pkt_sent and pkts_credit regs */
 252         droq->pkts_sent_reg = (uint8_t *)lio_dev->hw_addr +
 253                                         CN23XX_SLI_OQ_PKTS_SENT(oq_no);
 254         droq->pkts_credit_reg = (uint8_t *)lio_dev->hw_addr +
 255                                         CN23XX_SLI_OQ_PKTS_CREDIT(oq_no);
 256 }
 257
 258 static void
 259 cn23xx_vf_free_mbox(struct lio_device *lio_dev)
 260 {
 261         PMD_INIT_FUNC_TRACE();
 262
 263         rte_free(lio_dev->mbox[0]);
 264         lio_dev->mbox[0] = NULL;
 265
 266         rte_free(lio_dev->mbox);
 267         lio_dev->mbox = NULL;
 268 }
 269
 270 static int
 271 cn23xx_vf_setup_mbox(struct lio_device *lio_dev)
 272 {
 273         struct lio_mbox *mbox;
 274
 275         PMD_INIT_FUNC_TRACE();
 276
 277         if (lio_dev->mbox == NULL) {
 278                 lio_dev->mbox = rte_zmalloc(NULL, sizeof(void *), 0);
 279                 if (lio_dev->mbox == NULL)
 280                         return -ENOMEM;
 281         }
 282
 283         mbox = rte_zmalloc(NULL, sizeof(struct lio_mbox), 0);
 284         if (mbox == NULL) {
 285                 rte_free(lio_dev->mbox);
 286                 lio_dev->mbox = NULL;
 287                 return -ENOMEM;
 288         }
 289
 290         rte_spinlock_init(&mbox->lock);
 291
 292         mbox->lio_dev = lio_dev;
 293
 294         mbox->q_no = 0;
 295
 296         mbox->state = LIO_MBOX_STATE_IDLE;
 297
 298         /* VF mbox interrupt reg */
 299         mbox->mbox_int_reg = (uint8_t *)lio_dev->hw_addr +
 300                                 CN23XX_VF_SLI_PKT_MBOX_INT(0);
 301         /* VF reads from SIG0 reg */
 302         mbox->mbox_read_reg = (uint8_t *)lio_dev->hw_addr +
 303                                 CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 0);
 304         /* VF writes into SIG1 reg */
 305         mbox->mbox_write_reg = (uint8_t *)lio_dev->hw_addr +
 306                                 CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 1);
 307
 308         lio_dev->mbox[0] = mbox;
 309
 310         rte_write64(LIO_PFVFSIG, mbox->mbox_read_reg);
 311
 312         return 0;
 313 }
 314
 315 static int
 316 cn23xx_vf_enable_io_queues(struct lio_device *lio_dev)
 317 {
 318         uint32_t q_no;
 319
 320         PMD_INIT_FUNC_TRACE();
 321
 322         for (q_no = 0; q_no < lio_dev->num_iqs; q_no++) {
 323                 uint64_t reg_val;
 324
 325                 /* set the corresponding IQ IS_64B bit */
 326                 if (lio_dev->io_qmask.iq64B & (1ULL << q_no)) {
 327                         reg_val = lio_read_csr64(
 328                                         lio_dev,
 329                                         CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
 330                         reg_val = reg_val | CN23XX_PKT_INPUT_CTL_IS_64B;
 331                         lio_write_csr64(lio_dev,
 332                                         CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
 333                                         reg_val);
 334                 }
 335
 336                 /* set the corresponding IQ ENB bit */
 337                 if (lio_dev->io_qmask.iq & (1ULL << q_no)) {
 338                         reg_val = lio_read_csr64(
 339                                         lio_dev,
 340                                         CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
 341                         reg_val = reg_val | CN23XX_PKT_INPUT_CTL_RING_ENB;
 342                         lio_write_csr64(lio_dev,
 343                                         CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
 344                                         reg_val);
 345                 }
 346         }
 347         for (q_no = 0; q_no < lio_dev->num_oqs; q_no++) {
 348                 uint32_t reg_val;
 349
 350                 /* set the corresponding OQ ENB bit */
 351                 if (lio_dev->io_qmask.oq & (1ULL << q_no)) {
 352                         reg_val = lio_read_csr(
 353                                         lio_dev,
 354                                         CN23XX_SLI_OQ_PKT_CONTROL(q_no));
 355                         reg_val = reg_val | CN23XX_PKT_OUTPUT_CTL_RING_ENB;
 356                         lio_write_csr(lio_dev,
 357                                       CN23XX_SLI_OQ_PKT_CONTROL(q_no),
 358                                       reg_val);
 359                 }
 360         }
 361
 362         return 0;
 363 }
 364
 365 static void
 366 cn23xx_vf_disable_io_queues(struct lio_device *lio_dev)
 367 {
 368         uint32_t num_queues;
 369
 370         PMD_INIT_FUNC_TRACE();
 371
 372         /* per HRM, rings can only be disabled via reset operation,
 373          * NOT via SLI_PKT()_INPUT/OUTPUT_CONTROL[ENB]
 374          */
 375         num_queues = lio_dev->num_iqs;
 376         if (num_queues < lio_dev->num_oqs)
 377                 num_queues = lio_dev->num_oqs;
 378
 379         cn23xx_vf_reset_io_queues(lio_dev, num_queues);
 380 }
 381
 382 void
 383 cn23xx_vf_ask_pf_to_do_flr(struct lio_device *lio_dev)
 384 {
 385         struct lio_mbox_cmd mbox_cmd;
 386
 387         memset(&mbox_cmd, 0, sizeof(struct lio_mbox_cmd));
 388         mbox_cmd.msg.s.type = LIO_MBOX_REQUEST;
 389         mbox_cmd.msg.s.resp_needed = 0;
 390         mbox_cmd.msg.s.cmd = LIO_VF_FLR_REQUEST;
 391         mbox_cmd.msg.s.len = 1;
 392         mbox_cmd.q_no = 0;
 393         mbox_cmd.recv_len = 0;
 394         mbox_cmd.recv_status = 0;
 395         mbox_cmd.fn = NULL;
 396         mbox_cmd.fn_arg = 0;
 397
 398         lio_mbox_write(lio_dev, &mbox_cmd);
 399 }
 400
 401 static void
 402 cn23xx_pfvf_hs_callback(struct lio_device *lio_dev,
 403                         struct lio_mbox_cmd *cmd, void *arg)
 404 {
 405         uint32_t major = 0;
 406
 407         PMD_INIT_FUNC_TRACE();
 408
 409         rte_memcpy((uint8_t *)&lio_dev->pfvf_hsword, cmd->msg.s.params, 6);
 410         if (cmd->recv_len > 1) {
 411                 struct lio_version *lio_ver = (struct lio_version *)cmd->data;
 412
 413                 major = lio_ver->major;
 414                 major = major << 16;
 415         }
 416
 417         rte_atomic64_set((rte_atomic64_t *)arg, major | 1);
 418 }
 419
 420 int
 421 cn23xx_pfvf_handshake(struct lio_device *lio_dev)
 422 {
 423         struct lio_mbox_cmd mbox_cmd;
 424         struct lio_version *lio_ver = (struct lio_version *)&mbox_cmd.data[0];
 425         uint32_t q_no, count = 0;
 426         rte_atomic64_t status;
 427         uint32_t pfmajor;
 428         uint32_t vfmajor;
 429         uint32_t ret;
 430
 431         PMD_INIT_FUNC_TRACE();
 432
 433         /* Sending VF_ACTIVE indication to the PF driver */
 434         lio_dev_dbg(lio_dev, "requesting info from PF\n");
 435
 436         mbox_cmd.msg.mbox_msg64 = 0;
 437         mbox_cmd.msg.s.type = LIO_MBOX_REQUEST;
 438         mbox_cmd.msg.s.resp_needed = 1;
 439         mbox_cmd.msg.s.cmd = LIO_VF_ACTIVE;
 440         mbox_cmd.msg.s.len = 2;
 441         mbox_cmd.data[0] = 0;
 442         lio_ver->major = LIO_BASE_MAJOR_VERSION;
 443         lio_ver->minor = LIO_BASE_MINOR_VERSION;
 444         lio_ver->micro = LIO_BASE_MICRO_VERSION;
 445         mbox_cmd.q_no = 0;
 446         mbox_cmd.recv_len = 0;
 447         mbox_cmd.recv_status = 0;
 448         mbox_cmd.fn = (lio_mbox_callback)cn23xx_pfvf_hs_callback;
 449         mbox_cmd.fn_arg = (void *)&status;
 450
 451         if (lio_mbox_write(lio_dev, &mbox_cmd)) {
 452                 lio_dev_err(lio_dev, "Write to mailbox failed\n");
 453                 return -1;
 454         }
 455
 456         rte_atomic64_set(&status, 0);
 457
 458         do {
 459                 rte_delay_ms(1);
 460         } while ((rte_atomic64_read(&status) == 0) && (count++ < 10000));
 461
 462         ret = rte_atomic64_read(&status);
 463         if (ret == 0) {
 464                 lio_dev_err(lio_dev, "cn23xx_pfvf_handshake timeout\n");
 465                 return -1;
 466         }
 467
 468         for (q_no = 0; q_no < lio_dev->num_iqs; q_no++)
 469                 lio_dev->instr_queue[q_no]->txpciq.s.pkind =
 470                                                 lio_dev->pfvf_hsword.pkind;
 471
 472         vfmajor = LIO_BASE_MAJOR_VERSION;
 473         pfmajor = ret >> 16;
 474         if (pfmajor != vfmajor) {
 475                 lio_dev_err(lio_dev,
 476                             "VF LiquidIO driver (major version %d) is not compatible with LiquidIO PF driver (major version %d)\n",
 477                             vfmajor, pfmajor);
 478                 ret = -EPERM;
 479         } else {
 480                 lio_dev_dbg(lio_dev,
 481                             "VF LiquidIO driver (major version %d), LiquidIO PF driver (major version %d)\n",
 482                             vfmajor, pfmajor);
 483                 ret = 0;
 484         }
 485
 486         lio_dev_dbg(lio_dev, "got data from PF pkind is %d\n",
 487                     lio_dev->pfvf_hsword.pkind);
 488
 489         return ret;
 490 }
 491
 492 void
 493 cn23xx_vf_handle_mbox(struct lio_device *lio_dev)
 494 {
 495         uint64_t mbox_int_val;
 496
 497         /* read and clear by writing 1 */
 498         mbox_int_val = rte_read64(lio_dev->mbox[0]->mbox_int_reg);
 499         rte_write64(mbox_int_val, lio_dev->mbox[0]->mbox_int_reg);
 500         if (lio_mbox_read(lio_dev->mbox[0]))
 501                 lio_mbox_process_message(lio_dev->mbox[0]);
 502 }
 503
 504 int
 505 cn23xx_vf_setup_device(struct lio_device *lio_dev)
 506 {
 507         uint64_t reg_val;
 508
 509         PMD_INIT_FUNC_TRACE();
 510
 511         /* INPUT_CONTROL[RPVF] gives the VF IOq count */
 512         reg_val = lio_read_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(0));
 513
 514         lio_dev->pf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_PF_NUM_POS) &
 515                                 CN23XX_PKT_INPUT_CTL_PF_NUM_MASK;
 516         lio_dev->vf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_VF_NUM_POS) &
 517                                 CN23XX_PKT_INPUT_CTL_VF_NUM_MASK;
 518
 519         reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS;
 520
 521         lio_dev->sriov_info.rings_per_vf =
 522                                 reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK;
 523
 524         lio_dev->default_config = lio_get_conf(lio_dev);
 525         if (lio_dev->default_config == NULL)
 526                 return -1;
 527
 528         lio_dev->fn_list.setup_iq_regs          = cn23xx_vf_setup_iq_regs;
 529         lio_dev->fn_list.setup_oq_regs          = cn23xx_vf_setup_oq_regs;
 530         lio_dev->fn_list.setup_mbox             = cn23xx_vf_setup_mbox;
 531         lio_dev->fn_list.free_mbox              = cn23xx_vf_free_mbox;
 532
 533         lio_dev->fn_list.setup_device_regs      = cn23xx_vf_setup_device_regs;
 534
 535         lio_dev->fn_list.enable_io_queues       = cn23xx_vf_enable_io_queues;
 536         lio_dev->fn_list.disable_io_queues      = cn23xx_vf_disable_io_queues;
 537
 538         return 0;
 539 }
 540
 541 int
 542 cn23xx_vf_set_io_queues_off(struct lio_device *lio_dev)
 543 {
 544         uint32_t loop = CN23XX_VF_BUSY_READING_REG_LOOP_COUNT;
 545         uint64_t q_no;
 546
 547         /* Disable the i/p and o/p queues for this Octeon.
 548          * IOQs will already be in reset.
 549          * If RST bit is set, wait for Quiet bit to be set
 550          * Once Quiet bit is set, clear the RST bit
 551          */
 552         PMD_INIT_FUNC_TRACE();
 553
 554         for (q_no = 0; q_no < lio_dev->sriov_info.rings_per_vf; q_no++) {
 555                 volatile uint64_t reg_val;
 556
 557                 reg_val = lio_read_csr64(lio_dev,
 558                                          CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
 559                 while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) && !(reg_val &
 560                                          CN23XX_PKT_INPUT_CTL_QUIET) && loop) {
 561                         reg_val = lio_read_csr64(
 562                                         lio_dev,
 563                                         CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
 564                         loop = loop - 1;
 565                 }
 566
 567                 if (loop == 0) {
 568                         lio_dev_err(lio_dev,
 569                                     "clearing the reset reg failed or setting the quiet reg failed for qno %lu\n",
 570                                     (unsigned long)q_no);
 571                         return -1;
 572                 }
 573
 574                 reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
 575                 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
 576                                 reg_val);
 577
 578                 reg_val = lio_read_csr64(lio_dev,
 579                                          CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
 580                 if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
 581                         lio_dev_err(lio_dev, "unable to reset qno %lu\n",
 582                                     (unsigned long)q_no);
 583                         return -1;
 584                 }
 585         }
 586
 587         return 0;
 588 }