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1 /*-
2 * BSD LICENSE
3 *
4 * Copyright 2012-2017 6WIND S.A.
5 * Copyright 2012-2017 Mellanox.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * Known limitations:
36 * - RSS hash key and options cannot be modified.
37 * - Hardware counters aren't implemented.
38 */
39
40 /* System headers. */
41 #include <stddef.h>
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <stdint.h>
45 #include <inttypes.h>
46 #include <string.h>
47 #include <errno.h>
48 #include <unistd.h>
49 #include <limits.h>
50 #include <assert.h>
51 #include <arpa/inet.h>
52 #include <net/if.h>
53 #include <dirent.h>
54 #include <sys/ioctl.h>
55 #include <sys/socket.h>
56 #include <netinet/in.h>
57 #include <linux/ethtool.h>
58 #include <linux/sockios.h>
59 #include <fcntl.h>
60
61 #include <rte_ether.h>
62 #include <rte_ethdev.h>
63 #include <rte_ethdev_pci.h>
64 #include <rte_dev.h>
65 #include <rte_mbuf.h>
66 #include <rte_errno.h>
67 #include <rte_mempool.h>
68 #include <rte_prefetch.h>
69 #include <rte_malloc.h>
70 #include <rte_spinlock.h>
71 #include <rte_atomic.h>
72 #include <rte_version.h>
73 #include <rte_log.h>
74 #include <rte_alarm.h>
75 #include <rte_memory.h>
76 #include <rte_flow.h>
77 #include <rte_kvargs.h>
78
79 /* Generated configuration header. */
80 #include "mlx4_autoconf.h"
81
82 /* PMD headers. */
83 #include "mlx4.h"
84 #include "mlx4_flow.h"
85
86 /* Convenience macros for accessing mbuf fields. */
87 #define NEXT(m) ((m)->next)
88 #define DATA_LEN(m) ((m)->data_len)
89 #define PKT_LEN(m) ((m)->pkt_len)
90 #define DATA_OFF(m) ((m)->data_off)
91 #define SET_DATA_OFF(m, o) ((m)->data_off = (o))
92 #define NB_SEGS(m) ((m)->nb_segs)
93 #define PORT(m) ((m)->port)
94
95 /* Work Request ID data type (64 bit). */
96 typedef union {
97 struct {
98 uint32_t id;
99 uint16_t offset;
100 } data;
101 uint64_t raw;
102 } wr_id_t;
103
104 #define WR_ID(o) (((wr_id_t *)&(o))->data)
105
106 /* Transpose flags. Useful to convert IBV to DPDK flags. */
107 #define TRANSPOSE(val, from, to) \
108 (((from) >= (to)) ? \
109 (((val) & (from)) / ((from) / (to))) : \
110 (((val) & (from)) * ((to) / (from))))
111
112 /* Local storage for secondary process data. */
113 struct mlx4_secondary_data {
114 struct rte_eth_dev_data data; /* Local device data. */
115 struct priv *primary_priv; /* Private structure from primary. */
116 struct rte_eth_dev_data *shared_dev_data; /* Shared device data. */
117 rte_spinlock_t lock; /* Port configuration lock. */
118 } mlx4_secondary_data[RTE_MAX_ETHPORTS];
119
120 struct mlx4_conf {
121 uint8_t active_ports;
122 };
123
124 /* Available parameters list. */
125 const char *pmd_mlx4_init_params[] = {
126 MLX4_PMD_PORT_KVARG,
127 NULL,
128 };
129
130 /**
131 * Check if running as a secondary process.
132 *
133 * @return
134 * Nonzero if running as a secondary process.
135 */
136 static inline int
137 mlx4_is_secondary(void)
138 {
139 return rte_eal_process_type() != RTE_PROC_PRIMARY;
140 }
141
142 /**
143 * Return private structure associated with an Ethernet device.
144 *
145 * @param dev
146 * Pointer to Ethernet device structure.
147 *
148 * @return
149 * Pointer to private structure.
150 */
151 static struct priv *
152 mlx4_get_priv(struct rte_eth_dev *dev)
153 {
154 struct mlx4_secondary_data *sd;
155
156 if (!mlx4_is_secondary())
157 return dev->data->dev_private;
158 sd = &mlx4_secondary_data[dev->data->port_id];
159 return sd->data.dev_private;
160 }
161
162 /**
163 * Lock private structure to protect it from concurrent access in the
164 * control path.
165 *
166 * @param priv
167 * Pointer to private structure.
168 */
169 void priv_lock(struct priv *priv)
170 {
171 rte_spinlock_lock(&priv->lock);
172 }
173
174 /**
175 * Unlock private structure.
176 *
177 * @param priv
178 * Pointer to private structure.
179 */
180 void priv_unlock(struct priv *priv)
181 {
182 rte_spinlock_unlock(&priv->lock);
183 }
184
185 /* Allocate a buffer on the stack and fill it with a printf format string. */
186 #define MKSTR(name, ...) \
187 char name[snprintf(NULL, 0, __VA_ARGS__) + 1]; \
188 \
189 snprintf(name, sizeof(name), __VA_ARGS__)
190
191 /**
192 * Get interface name from private structure.
193 *
194 * @param[in] priv
195 * Pointer to private structure.
196 * @param[out] ifname
197 * Interface name output buffer.
198 *
199 * @return
200 * 0 on success, -1 on failure and errno is set.
201 */
202 static int
203 priv_get_ifname(const struct priv *priv, char (*ifname)[IF_NAMESIZE])
204 {
205 DIR *dir;
206 struct dirent *dent;
207 unsigned int dev_type = 0;
208 unsigned int dev_port_prev = ~0u;
209 char match[IF_NAMESIZE] = "";
210
211 {
212 MKSTR(path, "%s/device/net", priv->ctx->device->ibdev_path);
213
214 dir = opendir(path);
215 if (dir == NULL)
216 return -1;
217 }
218 while ((dent = readdir(dir)) != NULL) {
219 char *name = dent->d_name;
220 FILE *file;
221 unsigned int dev_port;
222 int r;
223
224 if ((name[0] == '.') &&
225 ((name[1] == '\0') ||
226 ((name[1] == '.') && (name[2] == '\0'))))
227 continue;
228
229 MKSTR(path, "%s/device/net/%s/%s",
230 priv->ctx->device->ibdev_path, name,
231 (dev_type ? "dev_id" : "dev_port"));
232
233 file = fopen(path, "rb");
234 if (file == NULL) {
235 if (errno != ENOENT)
236 continue;
237 /*
238 * Switch to dev_id when dev_port does not exist as
239 * is the case with Linux kernel versions < 3.15.
240 */
241 try_dev_id:
242 match[0] = '\0';
243 if (dev_type)
244 break;
245 dev_type = 1;
246 dev_port_prev = ~0u;
247 rewinddir(dir);
248 continue;
249 }
250 r = fscanf(file, (dev_type ? "%x" : "%u"), &dev_port);
251 fclose(file);
252 if (r != 1)
253 continue;
254 /*
255 * Switch to dev_id when dev_port returns the same value for
256 * all ports. May happen when using a MOFED release older than
257 * 3.0 with a Linux kernel >= 3.15.
258 */
259 if (dev_port == dev_port_prev)
260 goto try_dev_id;
261 dev_port_prev = dev_port;
262 if (dev_port == (priv->port - 1u))
263 snprintf(match, sizeof(match), "%s", name);
264 }
265 closedir(dir);
266 if (match[0] == '\0')
267 return -1;
268 strncpy(*ifname, match, sizeof(*ifname));
269 return 0;
270 }
271
272 /**
273 * Read from sysfs entry.
274 *
275 * @param[in] priv
276 * Pointer to private structure.
277 * @param[in] entry
278 * Entry name relative to sysfs path.
279 * @param[out] buf
280 * Data output buffer.
281 * @param size
282 * Buffer size.
283 *
284 * @return
285 * 0 on success, -1 on failure and errno is set.
286 */
287 static int
288 priv_sysfs_read(const struct priv *priv, const char *entry,
289 char *buf, size_t size)
290 {
291 char ifname[IF_NAMESIZE];
292 FILE *file;
293 int ret;
294 int err;
295
296 if (priv_get_ifname(priv, &ifname))
297 return -1;
298
299 MKSTR(path, "%s/device/net/%s/%s", priv->ctx->device->ibdev_path,
300 ifname, entry);
301
302 file = fopen(path, "rb");
303 if (file == NULL)
304 return -1;
305 ret = fread(buf, 1, size, file);
306 err = errno;
307 if (((size_t)ret < size) && (ferror(file)))
308 ret = -1;
309 else
310 ret = size;
311 fclose(file);
312 errno = err;
313 return ret;
314 }
315
316 /**
317 * Write to sysfs entry.
318 *
319 * @param[in] priv
320 * Pointer to private structure.
321 * @param[in] entry
322 * Entry name relative to sysfs path.
323 * @param[in] buf
324 * Data buffer.
325 * @param size
326 * Buffer size.
327 *
328 * @return
329 * 0 on success, -1 on failure and errno is set.
330 */
331 static int
332 priv_sysfs_write(const struct priv *priv, const char *entry,
333 char *buf, size_t size)
334 {
335 char ifname[IF_NAMESIZE];
336 FILE *file;
337 int ret;
338 int err;
339
340 if (priv_get_ifname(priv, &ifname))
341 return -1;
342
343 MKSTR(path, "%s/device/net/%s/%s", priv->ctx->device->ibdev_path,
344 ifname, entry);
345
346 file = fopen(path, "wb");
347 if (file == NULL)
348 return -1;
349 ret = fwrite(buf, 1, size, file);
350 err = errno;
351 if (((size_t)ret < size) || (ferror(file)))
352 ret = -1;
353 else
354 ret = size;
355 fclose(file);
356 errno = err;
357 return ret;
358 }
359
360 /**
361 * Get unsigned long sysfs property.
362 *
363 * @param priv
364 * Pointer to private structure.
365 * @param[in] name
366 * Entry name relative to sysfs path.
367 * @param[out] value
368 * Value output buffer.
369 *
370 * @return
371 * 0 on success, -1 on failure and errno is set.
372 */
373 static int
374 priv_get_sysfs_ulong(struct priv *priv, const char *name, unsigned long *value)
375 {
376 int ret;
377 unsigned long value_ret;
378 char value_str[32];
379
380 ret = priv_sysfs_read(priv, name, value_str, (sizeof(value_str) - 1));
381 if (ret == -1) {
382 DEBUG("cannot read %s value from sysfs: %s",
383 name, strerror(errno));
384 return -1;
385 }
386 value_str[ret] = '\0';
387 errno = 0;
388 value_ret = strtoul(value_str, NULL, 0);
389 if (errno) {
390 DEBUG("invalid %s value `%s': %s", name, value_str,
391 strerror(errno));
392 return -1;
393 }
394 *value = value_ret;
395 return 0;
396 }
397
398 /**
399 * Set unsigned long sysfs property.
400 *
401 * @param priv
402 * Pointer to private structure.
403 * @param[in] name
404 * Entry name relative to sysfs path.
405 * @param value
406 * Value to set.
407 *
408 * @return
409 * 0 on success, -1 on failure and errno is set.
410 */
411 static int
412 priv_set_sysfs_ulong(struct priv *priv, const char *name, unsigned long value)
413 {
414 int ret;
415 MKSTR(value_str, "%lu", value);
416
417 ret = priv_sysfs_write(priv, name, value_str, (sizeof(value_str) - 1));
418 if (ret == -1) {
419 DEBUG("cannot write %s `%s' (%lu) to sysfs: %s",
420 name, value_str, value, strerror(errno));
421 return -1;
422 }
423 return 0;
424 }
425
426 /**
427 * Perform ifreq ioctl() on associated Ethernet device.
428 *
429 * @param[in] priv
430 * Pointer to private structure.
431 * @param req
432 * Request number to pass to ioctl().
433 * @param[out] ifr
434 * Interface request structure output buffer.
435 *
436 * @return
437 * 0 on success, -1 on failure and errno is set.
438 */
439 static int
440 priv_ifreq(const struct priv *priv, int req, struct ifreq *ifr)
441 {
442 int sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_IP);
443 int ret = -1;
444
445 if (sock == -1)
446 return ret;
447 if (priv_get_ifname(priv, &ifr->ifr_name) == 0)
448 ret = ioctl(sock, req, ifr);
449 close(sock);
450 return ret;
451 }
452
453 /**
454 * Get device MTU.
455 *
456 * @param priv
457 * Pointer to private structure.
458 * @param[out] mtu
459 * MTU value output buffer.
460 *
461 * @return
462 * 0 on success, -1 on failure and errno is set.
463 */
464 static int
465 priv_get_mtu(struct priv *priv, uint16_t *mtu)
466 {
467 unsigned long ulong_mtu;
468
469 if (priv_get_sysfs_ulong(priv, "mtu", &ulong_mtu) == -1)
470 return -1;
471 *mtu = ulong_mtu;
472 return 0;
473 }
474
475 /**
476 * Set device MTU.
477 *
478 * @param priv
479 * Pointer to private structure.
480 * @param mtu
481 * MTU value to set.
482 *
483 * @return
484 * 0 on success, -1 on failure and errno is set.
485 */
486 static int
487 priv_set_mtu(struct priv *priv, uint16_t mtu)
488 {
489 uint16_t new_mtu;
490
491 if (priv_set_sysfs_ulong(priv, "mtu", mtu) ||
492 priv_get_mtu(priv, &new_mtu))
493 return -1;
494 if (new_mtu == mtu)
495 return 0;
496 errno = EINVAL;
497 return -1;
498 }
499
500 /**
501 * Set device flags.
502 *
503 * @param priv
504 * Pointer to private structure.
505 * @param keep
506 * Bitmask for flags that must remain untouched.
507 * @param flags
508 * Bitmask for flags to modify.
509 *
510 * @return
511 * 0 on success, -1 on failure and errno is set.
512 */
513 static int
514 priv_set_flags(struct priv *priv, unsigned int keep, unsigned int flags)
515 {
516 unsigned long tmp;
517
518 if (priv_get_sysfs_ulong(priv, "flags", &tmp) == -1)
519 return -1;
520 tmp &= keep;
521 tmp |= (flags & (~keep));
522 return priv_set_sysfs_ulong(priv, "flags", tmp);
523 }
524
525 /* Device configuration. */
526
527 static int
528 txq_setup(struct rte_eth_dev *dev, struct txq *txq, uint16_t desc,
529 unsigned int socket, const struct rte_eth_txconf *conf);
530
531 static void
532 txq_cleanup(struct txq *txq);
533
534 static int
535 rxq_setup(struct rte_eth_dev *dev, struct rxq *rxq, uint16_t desc,
536 unsigned int socket, int inactive, const struct rte_eth_rxconf *conf,
537 struct rte_mempool *mp);
538
539 static void
540 rxq_cleanup(struct rxq *rxq);
541
542 /**
543 * Ethernet device configuration.
544 *
545 * Prepare the driver for a given number of TX and RX queues.
546 * Allocate parent RSS queue when several RX queues are requested.
547 *
548 * @param dev
549 * Pointer to Ethernet device structure.
550 *
551 * @return
552 * 0 on success, errno value on failure.
553 */
554 static int
555 dev_configure(struct rte_eth_dev *dev)
556 {
557 struct priv *priv = dev->data->dev_private;
558 unsigned int rxqs_n = dev->data->nb_rx_queues;
559 unsigned int txqs_n = dev->data->nb_tx_queues;
560 unsigned int tmp;
561 int ret;
562
563 priv->rxqs = (void *)dev->data->rx_queues;
564 priv->txqs = (void *)dev->data->tx_queues;
565 if (txqs_n != priv->txqs_n) {
566 INFO("%p: TX queues number update: %u -> %u",
567 (void *)dev, priv->txqs_n, txqs_n);
568 priv->txqs_n = txqs_n;
569 }
570 if (rxqs_n == priv->rxqs_n)
571 return 0;
572 if (!rte_is_power_of_2(rxqs_n)) {
573 unsigned n_active;
574
575 n_active = rte_align32pow2(rxqs_n + 1) >> 1;
576 WARN("%p: number of RX queues must be a power"
577 " of 2: %u queues among %u will be active",
578 (void *)dev, n_active, rxqs_n);
579 }
580
581 INFO("%p: RX queues number update: %u -> %u",
582 (void *)dev, priv->rxqs_n, rxqs_n);
583 /* If RSS is enabled, disable it first. */
584 if (priv->rss) {
585 unsigned int i;
586
587 /* Only if there are no remaining child RX queues. */
588 for (i = 0; (i != priv->rxqs_n); ++i)
589 if ((*priv->rxqs)[i] != NULL)
590 return EINVAL;
591 rxq_cleanup(&priv->rxq_parent);
592 priv->rss = 0;
593 priv->rxqs_n = 0;
594 }
595 if (rxqs_n <= 1) {
596 /* Nothing else to do. */
597 priv->rxqs_n = rxqs_n;
598 return 0;
599 }
600 /* Allocate a new RSS parent queue if supported by hardware. */
601 if (!priv->hw_rss) {
602 ERROR("%p: only a single RX queue can be configured when"
603 " hardware doesn't support RSS",
604 (void *)dev);
605 return EINVAL;
606 }
607 /* Fail if hardware doesn't support that many RSS queues. */
608 if (rxqs_n >= priv->max_rss_tbl_sz) {
609 ERROR("%p: only %u RX queues can be configured for RSS",
610 (void *)dev, priv->max_rss_tbl_sz);
611 return EINVAL;
612 }
613 priv->rss = 1;
614 tmp = priv->rxqs_n;
615 priv->rxqs_n = rxqs_n;
616 ret = rxq_setup(dev, &priv->rxq_parent, 0, 0, 0, NULL, NULL);
617 if (!ret)
618 return 0;
619 /* Failure, rollback. */
620 priv->rss = 0;
621 priv->rxqs_n = tmp;
622 assert(ret > 0);
623 return ret;
624 }
625
626 /**
627 * DPDK callback for Ethernet device configuration.
628 *
629 * @param dev
630 * Pointer to Ethernet device structure.
631 *
632 * @return
633 * 0 on success, negative errno value on failure.
634 */
635 static int
636 mlx4_dev_configure(struct rte_eth_dev *dev)
637 {
638 struct priv *priv = dev->data->dev_private;
639 int ret;
640
641 if (mlx4_is_secondary())
642 return -E_RTE_SECONDARY;
643 priv_lock(priv);
644 ret = dev_configure(dev);
645 assert(ret >= 0);
646 priv_unlock(priv);
647 return -ret;
648 }
649
650 static uint16_t mlx4_tx_burst(void *, struct rte_mbuf **, uint16_t);
651 static uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
652
653 /**
654 * Configure secondary process queues from a private data pointer (primary
655 * or secondary) and update burst callbacks. Can take place only once.
656 *
657 * All queues must have been previously created by the primary process to
658 * avoid undefined behavior.
659 *
660 * @param priv
661 * Private data pointer from either primary or secondary process.
662 *
663 * @return
664 * Private data pointer from secondary process, NULL in case of error.
665 */
666 static struct priv *
667 mlx4_secondary_data_setup(struct priv *priv)
668 {
669 unsigned int port_id = 0;
670 struct mlx4_secondary_data *sd;
671 void **tx_queues;
672 void **rx_queues;
673 unsigned int nb_tx_queues;
674 unsigned int nb_rx_queues;
675 unsigned int i;
676
677 /* priv must be valid at this point. */
678 assert(priv != NULL);
679 /* priv->dev must also be valid but may point to local memory from
680 * another process, possibly with the same address and must not
681 * be dereferenced yet. */
682 assert(priv->dev != NULL);
683 /* Determine port ID by finding out where priv comes from. */
684 while (1) {
685 sd = &mlx4_secondary_data[port_id];
686 rte_spinlock_lock(&sd->lock);
687 /* Primary process? */
688 if (sd->primary_priv == priv)
689 break;
690 /* Secondary process? */
691 if (sd->data.dev_private == priv)
692 break;
693 rte_spinlock_unlock(&sd->lock);
694 if (++port_id == RTE_DIM(mlx4_secondary_data))
695 port_id = 0;
696 }
697 /* Switch to secondary private structure. If private data has already
698 * been updated by another thread, there is nothing else to do. */
699 priv = sd->data.dev_private;
700 if (priv->dev->data == &sd->data)
701 goto end;
702 /* Sanity checks. Secondary private structure is supposed to point
703 * to local eth_dev, itself still pointing to the shared device data
704 * structure allocated by the primary process. */
705 assert(sd->shared_dev_data != &sd->data);
706 assert(sd->data.nb_tx_queues == 0);
707 assert(sd->data.tx_queues == NULL);
708 assert(sd->data.nb_rx_queues == 0);
709 assert(sd->data.rx_queues == NULL);
710 assert(priv != sd->primary_priv);
711 assert(priv->dev->data == sd->shared_dev_data);
712 assert(priv->txqs_n == 0);
713 assert(priv->txqs == NULL);
714 assert(priv->rxqs_n == 0);
715 assert(priv->rxqs == NULL);
716 nb_tx_queues = sd->shared_dev_data->nb_tx_queues;
717 nb_rx_queues = sd->shared_dev_data->nb_rx_queues;
718 /* Allocate local storage for queues. */
719 tx_queues = rte_zmalloc("secondary ethdev->tx_queues",
720 sizeof(sd->data.tx_queues[0]) * nb_tx_queues,
721 RTE_CACHE_LINE_SIZE);
722 rx_queues = rte_zmalloc("secondary ethdev->rx_queues",
723 sizeof(sd->data.rx_queues[0]) * nb_rx_queues,
724 RTE_CACHE_LINE_SIZE);
725 if (tx_queues == NULL || rx_queues == NULL)
726 goto error;
727 /* Lock to prevent control operations during setup. */
728 priv_lock(priv);
729 /* TX queues. */
730 for (i = 0; i != nb_tx_queues; ++i) {
731 struct txq *primary_txq = (*sd->primary_priv->txqs)[i];
732 struct txq *txq;
733
734 if (primary_txq == NULL)
735 continue;
736 txq = rte_calloc_socket("TXQ", 1, sizeof(*txq), 0,
737 primary_txq->socket);
738 if (txq != NULL) {
739 if (txq_setup(priv->dev,
740 txq,
741 primary_txq->elts_n * MLX4_PMD_SGE_WR_N,
742 primary_txq->socket,
743 NULL) == 0) {
744 txq->stats.idx = primary_txq->stats.idx;
745 tx_queues[i] = txq;
746 continue;
747 }
748 rte_free(txq);
749 }
750 while (i) {
751 txq = tx_queues[--i];
752 txq_cleanup(txq);
753 rte_free(txq);
754 }
755 goto error;
756 }
757 /* RX queues. */
758 for (i = 0; i != nb_rx_queues; ++i) {
759 struct rxq *primary_rxq = (*sd->primary_priv->rxqs)[i];
760
761 if (primary_rxq == NULL)
762 continue;
763 /* Not supported yet. */
764 rx_queues[i] = NULL;
765 }
766 /* Update everything. */
767 priv->txqs = (void *)tx_queues;
768 priv->txqs_n = nb_tx_queues;
769 priv->rxqs = (void *)rx_queues;
770 priv->rxqs_n = nb_rx_queues;
771 sd->data.rx_queues = rx_queues;
772 sd->data.tx_queues = tx_queues;
773 sd->data.nb_rx_queues = nb_rx_queues;
774 sd->data.nb_tx_queues = nb_tx_queues;
775 sd->data.dev_link = sd->shared_dev_data->dev_link;
776 sd->data.mtu = sd->shared_dev_data->mtu;
777 memcpy(sd->data.rx_queue_state, sd->shared_dev_data->rx_queue_state,
778 sizeof(sd->data.rx_queue_state));
779 memcpy(sd->data.tx_queue_state, sd->shared_dev_data->tx_queue_state,
780 sizeof(sd->data.tx_queue_state));
781 sd->data.dev_flags = sd->shared_dev_data->dev_flags;
782 /* Use local data from now on. */
783 rte_mb();
784 priv->dev->data = &sd->data;
785 rte_mb();
786 priv->dev->tx_pkt_burst = mlx4_tx_burst;
787 priv->dev->rx_pkt_burst = removed_rx_burst;
788 priv_unlock(priv);
789 end:
790 /* More sanity checks. */
791 assert(priv->dev->tx_pkt_burst == mlx4_tx_burst);
792 assert(priv->dev->rx_pkt_burst == removed_rx_burst);
793 assert(priv->dev->data == &sd->data);
794 rte_spinlock_unlock(&sd->lock);
795 return priv;
796 error:
797 priv_unlock(priv);
798 rte_free(tx_queues);
799 rte_free(rx_queues);
800 rte_spinlock_unlock(&sd->lock);
801 return NULL;
802 }
803
804 /* TX queues handling. */
805
806 /**
807 * Allocate TX queue elements.
808 *
809 * @param txq
810 * Pointer to TX queue structure.
811 * @param elts_n
812 * Number of elements to allocate.
813 *
814 * @return
815 * 0 on success, errno value on failure.
816 */
817 static int
818 txq_alloc_elts(struct txq *txq, unsigned int elts_n)
819 {
820 unsigned int i;
821 struct txq_elt (*elts)[elts_n] =
822 rte_calloc_socket("TXQ", 1, sizeof(*elts), 0, txq->socket);
823 linear_t (*elts_linear)[elts_n] =
824 rte_calloc_socket("TXQ", 1, sizeof(*elts_linear), 0,
825 txq->socket);
826 struct ibv_mr *mr_linear = NULL;
827 int ret = 0;
828
829 if ((elts == NULL) || (elts_linear == NULL)) {
830 ERROR("%p: can't allocate packets array", (void *)txq);
831 ret = ENOMEM;
832 goto error;
833 }
834 mr_linear =
835 ibv_reg_mr(txq->priv->pd, elts_linear, sizeof(*elts_linear),
836 IBV_ACCESS_LOCAL_WRITE);
837 if (mr_linear == NULL) {
838 ERROR("%p: unable to configure MR, ibv_reg_mr() failed",
839 (void *)txq);
840 ret = EINVAL;
841 goto error;
842 }
843 for (i = 0; (i != elts_n); ++i) {
844 struct txq_elt *elt = &(*elts)[i];
845
846 elt->buf = NULL;
847 }
848 DEBUG("%p: allocated and configured %u WRs", (void *)txq, elts_n);
849 txq->elts_n = elts_n;
850 txq->elts = elts;
851 txq->elts_head = 0;
852 txq->elts_tail = 0;
853 txq->elts_comp = 0;
854 /* Request send completion every MLX4_PMD_TX_PER_COMP_REQ packets or
855 * at least 4 times per ring. */
856 txq->elts_comp_cd_init =
857 ((MLX4_PMD_TX_PER_COMP_REQ < (elts_n / 4)) ?
858 MLX4_PMD_TX_PER_COMP_REQ : (elts_n / 4));
859 txq->elts_comp_cd = txq->elts_comp_cd_init;
860 txq->elts_linear = elts_linear;
861 txq->mr_linear = mr_linear;
862 assert(ret == 0);
863 return 0;
864 error:
865 if (mr_linear != NULL)
866 claim_zero(ibv_dereg_mr(mr_linear));
867
868 rte_free(elts_linear);
869 rte_free(elts);
870
871 DEBUG("%p: failed, freed everything", (void *)txq);
872 assert(ret > 0);
873 return ret;
874 }
875
876 /**
877 * Free TX queue elements.
878 *
879 * @param txq
880 * Pointer to TX queue structure.
881 */
882 static void
883 txq_free_elts(struct txq *txq)
884 {
885 unsigned int elts_n = txq->elts_n;
886 unsigned int elts_head = txq->elts_head;
887 unsigned int elts_tail = txq->elts_tail;
888 struct txq_elt (*elts)[elts_n] = txq->elts;
889 linear_t (*elts_linear)[elts_n] = txq->elts_linear;
890 struct ibv_mr *mr_linear = txq->mr_linear;
891
892 DEBUG("%p: freeing WRs", (void *)txq);
893 txq->elts_n = 0;
894 txq->elts_head = 0;
895 txq->elts_tail = 0;
896 txq->elts_comp = 0;
897 txq->elts_comp_cd = 0;
898 txq->elts_comp_cd_init = 0;
899 txq->elts = NULL;
900 txq->elts_linear = NULL;
901 txq->mr_linear = NULL;
902 if (mr_linear != NULL)
903 claim_zero(ibv_dereg_mr(mr_linear));
904
905 rte_free(elts_linear);
906 if (elts == NULL)
907 return;
908 while (elts_tail != elts_head) {
909 struct txq_elt *elt = &(*elts)[elts_tail];
910
911 assert(elt->buf != NULL);
912 rte_pktmbuf_free(elt->buf);
913 #ifndef NDEBUG
914 /* Poisoning. */
915 memset(elt, 0x77, sizeof(*elt));
916 #endif
917 if (++elts_tail == elts_n)
918 elts_tail = 0;
919 }
920 rte_free(elts);
921 }
922
923
924 /**
925 * Clean up a TX queue.
926 *
927 * Destroy objects, free allocated memory and reset the structure for reuse.
928 *
929 * @param txq
930 * Pointer to TX queue structure.
931 */
932 static void
933 txq_cleanup(struct txq *txq)
934 {
935 struct ibv_exp_release_intf_params params;
936 size_t i;
937
938 DEBUG("cleaning up %p", (void *)txq);
939 txq_free_elts(txq);
940 if (txq->if_qp != NULL) {
941 assert(txq->priv != NULL);
942 assert(txq->priv->ctx != NULL);
943 assert(txq->qp != NULL);
944 params = (struct ibv_exp_release_intf_params){
945 .comp_mask = 0,
946 };
947 claim_zero(ibv_exp_release_intf(txq->priv->ctx,
948 txq->if_qp,
949 &params));
950 }
951 if (txq->if_cq != NULL) {
952 assert(txq->priv != NULL);
953 assert(txq->priv->ctx != NULL);
954 assert(txq->cq != NULL);
955 params = (struct ibv_exp_release_intf_params){
956 .comp_mask = 0,
957 };
958 claim_zero(ibv_exp_release_intf(txq->priv->ctx,
959 txq->if_cq,
960 &params));
961 }
962 if (txq->qp != NULL)
963 claim_zero(ibv_destroy_qp(txq->qp));
964 if (txq->cq != NULL)
965 claim_zero(ibv_destroy_cq(txq->cq));
966 if (txq->rd != NULL) {
967 struct ibv_exp_destroy_res_domain_attr attr = {
968 .comp_mask = 0,
969 };
970
971 assert(txq->priv != NULL);
972 assert(txq->priv->ctx != NULL);
973 claim_zero(ibv_exp_destroy_res_domain(txq->priv->ctx,
974 txq->rd,
975 &attr));
976 }
977 for (i = 0; (i != elemof(txq->mp2mr)); ++i) {
978 if (txq->mp2mr[i].mp == NULL)
979 break;
980 assert(txq->mp2mr[i].mr != NULL);
981 claim_zero(ibv_dereg_mr(txq->mp2mr[i].mr));
982 }
983 memset(txq, 0, sizeof(*txq));
984 }
985
986 /**
987 * Manage TX completions.
988 *
989 * When sending a burst, mlx4_tx_burst() posts several WRs.
990 * To improve performance, a completion event is only required once every
991 * MLX4_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information
992 * for other WRs, but this information would not be used anyway.
993 *
994 * @param txq
995 * Pointer to TX queue structure.
996 *
997 * @return
998 * 0 on success, -1 on failure.
999 */
1000 static int
1001 txq_complete(struct txq *txq)
1002 {
1003 unsigned int elts_comp = txq->elts_comp;
1004 unsigned int elts_tail = txq->elts_tail;
1005 const unsigned int elts_n = txq->elts_n;
1006 int wcs_n;
1007
1008 if (unlikely(elts_comp == 0))
1009 return 0;
1010 #ifdef DEBUG_SEND
1011 DEBUG("%p: processing %u work requests completions",
1012 (void *)txq, elts_comp);
1013 #endif
1014 wcs_n = txq->if_cq->poll_cnt(txq->cq, elts_comp);
1015 if (unlikely(wcs_n == 0))
1016 return 0;
1017 if (unlikely(wcs_n < 0)) {
1018 DEBUG("%p: ibv_poll_cq() failed (wcs_n=%d)",
1019 (void *)txq, wcs_n);
1020 return -1;
1021 }
1022 elts_comp -= wcs_n;
1023 assert(elts_comp <= txq->elts_comp);
1024 /*
1025 * Assume WC status is successful as nothing can be done about it
1026 * anyway.
1027 */
1028 elts_tail += wcs_n * txq->elts_comp_cd_init;
1029 if (elts_tail >= elts_n)
1030 elts_tail -= elts_n;
1031 txq->elts_tail = elts_tail;
1032 txq->elts_comp = elts_comp;
1033 return 0;
1034 }
1035
1036 struct mlx4_check_mempool_data {
1037 int ret;
1038 char *start;
1039 char *end;
1040 };
1041
1042 /* Called by mlx4_check_mempool() when iterating the memory chunks. */
1043 static void mlx4_check_mempool_cb(struct rte_mempool *mp,
1044 void *opaque, struct rte_mempool_memhdr *memhdr,
1045 unsigned mem_idx)
1046 {
1047 struct mlx4_check_mempool_data *data = opaque;
1048
1049 (void)mp;
1050 (void)mem_idx;
1051
1052 /* It already failed, skip the next chunks. */
1053 if (data->ret != 0)
1054 return;
1055 /* It is the first chunk. */
1056 if (data->start == NULL && data->end == NULL) {
1057 data->start = memhdr->addr;
1058 data->end = data->start + memhdr->len;
1059 return;
1060 }
1061 if (data->end == memhdr->addr) {
1062 data->end += memhdr->len;
1063 return;
1064 }
1065 if (data->start == (char *)memhdr->addr + memhdr->len) {
1066 data->start -= memhdr->len;
1067 return;
1068 }
1069 /* Error, mempool is not virtually contigous. */
1070 data->ret = -1;
1071 }
1072
1073 /**
1074 * Check if a mempool can be used: it must be virtually contiguous.
1075 *
1076 * @param[in] mp
1077 * Pointer to memory pool.
1078 * @param[out] start
1079 * Pointer to the start address of the mempool virtual memory area
1080 * @param[out] end
1081 * Pointer to the end address of the mempool virtual memory area
1082 *
1083 * @return
1084 * 0 on success (mempool is virtually contiguous), -1 on error.
1085 */
1086 static int mlx4_check_mempool(struct rte_mempool *mp, uintptr_t *start,
1087 uintptr_t *end)
1088 {
1089 struct mlx4_check_mempool_data data;
1090
1091 memset(&data, 0, sizeof(data));
1092 rte_mempool_mem_iter(mp, mlx4_check_mempool_cb, &data);
1093 *start = (uintptr_t)data.start;
1094 *end = (uintptr_t)data.end;
1095
1096 return data.ret;
1097 }
1098
1099 /* For best performance, this function should not be inlined. */
1100 static struct ibv_mr *mlx4_mp2mr(struct ibv_pd *, struct rte_mempool *)
1101 __attribute__((noinline));
1102
1103 /**
1104 * Register mempool as a memory region.
1105 *
1106 * @param pd
1107 * Pointer to protection domain.
1108 * @param mp
1109 * Pointer to memory pool.
1110 *
1111 * @return
1112 * Memory region pointer, NULL in case of error.
1113 */
1114 static struct ibv_mr *
1115 mlx4_mp2mr(struct ibv_pd *pd, struct rte_mempool *mp)
1116 {
1117 const struct rte_memseg *ms = rte_eal_get_physmem_layout();
1118 uintptr_t start;
1119 uintptr_t end;
1120 unsigned int i;
1121
1122 if (mlx4_check_mempool(mp, &start, &end) != 0) {
1123 ERROR("mempool %p: not virtually contiguous",
1124 (void *)mp);
1125 return NULL;
1126 }
1127
1128 DEBUG("mempool %p area start=%p end=%p size=%zu",
1129 (void *)mp, (void *)start, (void *)end,
1130 (size_t)(end - start));
1131 /* Round start and end to page boundary if found in memory segments. */
1132 for (i = 0; (i < RTE_MAX_MEMSEG) && (ms[i].addr != NULL); ++i) {
1133 uintptr_t addr = (uintptr_t)ms[i].addr;
1134 size_t len = ms[i].len;
1135 unsigned int align = ms[i].hugepage_sz;
1136
1137 if ((start > addr) && (start < addr + len))
1138 start = RTE_ALIGN_FLOOR(start, align);
1139 if ((end > addr) && (end < addr + len))
1140 end = RTE_ALIGN_CEIL(end, align);
1141 }
1142 DEBUG("mempool %p using start=%p end=%p size=%zu for MR",
1143 (void *)mp, (void *)start, (void *)end,
1144 (size_t)(end - start));
1145 return ibv_reg_mr(pd,
1146 (void *)start,
1147 end - start,
1148 IBV_ACCESS_LOCAL_WRITE);
1149 }
1150
1151 /**
1152 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
1153 * the cloned mbuf is allocated is returned instead.
1154 *
1155 * @param buf
1156 * Pointer to mbuf.
1157 *
1158 * @return
1159 * Memory pool where data is located for given mbuf.
1160 */
1161 static struct rte_mempool *
1162 txq_mb2mp(struct rte_mbuf *buf)
1163 {
1164 if (unlikely(RTE_MBUF_INDIRECT(buf)))
1165 return rte_mbuf_from_indirect(buf)->pool;
1166 return buf->pool;
1167 }
1168
1169 /**
1170 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
1171 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
1172 * remove an entry first.
1173 *
1174 * @param txq
1175 * Pointer to TX queue structure.
1176 * @param[in] mp
1177 * Memory Pool for which a Memory Region lkey must be returned.
1178 *
1179 * @return
1180 * mr->lkey on success, (uint32_t)-1 on failure.
1181 */
1182 static uint32_t
1183 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
1184 {
1185 unsigned int i;
1186 struct ibv_mr *mr;
1187
1188 for (i = 0; (i != elemof(txq->mp2mr)); ++i) {
1189 if (unlikely(txq->mp2mr[i].mp == NULL)) {
1190 /* Unknown MP, add a new MR for it. */
1191 break;
1192 }
1193 if (txq->mp2mr[i].mp == mp) {
1194 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
1195 assert(txq->mp2mr[i].mr->lkey == txq->mp2mr[i].lkey);
1196 return txq->mp2mr[i].lkey;
1197 }
1198 }
1199 /* Add a new entry, register MR first. */
1200 DEBUG("%p: discovered new memory pool \"%s\" (%p)",
1201 (void *)txq, mp->name, (void *)mp);
1202 mr = mlx4_mp2mr(txq->priv->pd, mp);
1203 if (unlikely(mr == NULL)) {
1204 DEBUG("%p: unable to configure MR, ibv_reg_mr() failed.",
1205 (void *)txq);
1206 return (uint32_t)-1;
1207 }
1208 if (unlikely(i == elemof(txq->mp2mr))) {
1209 /* Table is full, remove oldest entry. */
1210 DEBUG("%p: MR <-> MP table full, dropping oldest entry.",
1211 (void *)txq);
1212 --i;
1213 claim_zero(ibv_dereg_mr(txq->mp2mr[0].mr));
1214 memmove(&txq->mp2mr[0], &txq->mp2mr[1],
1215 (sizeof(txq->mp2mr) - sizeof(txq->mp2mr[0])));
1216 }
1217 /* Store the new entry. */
1218 txq->mp2mr[i].mp = mp;
1219 txq->mp2mr[i].mr = mr;
1220 txq->mp2mr[i].lkey = mr->lkey;
1221 DEBUG("%p: new MR lkey for MP \"%s\" (%p): 0x%08" PRIu32,
1222 (void *)txq, mp->name, (void *)mp, txq->mp2mr[i].lkey);
1223 return txq->mp2mr[i].lkey;
1224 }
1225
1226 struct txq_mp2mr_mbuf_check_data {
1227 int ret;
1228 };
1229
1230 /**
1231 * Callback function for rte_mempool_obj_iter() to check whether a given
1232 * mempool object looks like a mbuf.
1233 *
1234 * @param[in] mp
1235 * The mempool pointer
1236 * @param[in] arg
1237 * Context data (struct txq_mp2mr_mbuf_check_data). Contains the
1238 * return value.
1239 * @param[in] obj
1240 * Object address.
1241 * @param index
1242 * Object index, unused.
1243 */
1244 static void
1245 txq_mp2mr_mbuf_check(struct rte_mempool *mp, void *arg, void *obj,
1246 uint32_t index __rte_unused)
1247 {
1248 struct txq_mp2mr_mbuf_check_data *data = arg;
1249 struct rte_mbuf *buf = obj;
1250
1251 /* Check whether mbuf structure fits element size and whether mempool
1252 * pointer is valid. */
1253 if (sizeof(*buf) > mp->elt_size || buf->pool != mp)
1254 data->ret = -1;
1255 }
1256
1257 /**
1258 * Iterator function for rte_mempool_walk() to register existing mempools and
1259 * fill the MP to MR cache of a TX queue.
1260 *
1261 * @param[in] mp
1262 * Memory Pool to register.
1263 * @param *arg
1264 * Pointer to TX queue structure.
1265 */
1266 static void
1267 txq_mp2mr_iter(struct rte_mempool *mp, void *arg)
1268 {
1269 struct txq *txq = arg;
1270 struct txq_mp2mr_mbuf_check_data data = {
1271 .ret = 0,
1272 };
1273
1274 /* Register mempool only if the first element looks like a mbuf. */
1275 if (rte_mempool_obj_iter(mp, txq_mp2mr_mbuf_check, &data) == 0 ||
1276 data.ret == -1)
1277 return;
1278 txq_mp2mr(txq, mp);
1279 }
1280
1281 #if MLX4_PMD_SGE_WR_N > 1
1282
1283 /**
1284 * Copy scattered mbuf contents to a single linear buffer.
1285 *
1286 * @param[out] linear
1287 * Linear output buffer.
1288 * @param[in] buf
1289 * Scattered input buffer.
1290 *
1291 * @return
1292 * Number of bytes copied to the output buffer or 0 if not large enough.
1293 */
1294 static unsigned int
1295 linearize_mbuf(linear_t *linear, struct rte_mbuf *buf)
1296 {
1297 unsigned int size = 0;
1298 unsigned int offset;
1299
1300 do {
1301 unsigned int len = DATA_LEN(buf);
1302
1303 offset = size;
1304 size += len;
1305 if (unlikely(size > sizeof(*linear)))
1306 return 0;
1307 memcpy(&(*linear)[offset],
1308 rte_pktmbuf_mtod(buf, uint8_t *),
1309 len);
1310 buf = NEXT(buf);
1311 } while (buf != NULL);
1312 return size;
1313 }
1314
1315 /**
1316 * Handle scattered buffers for mlx4_tx_burst().
1317 *
1318 * @param txq
1319 * TX queue structure.
1320 * @param segs
1321 * Number of segments in buf.
1322 * @param elt
1323 * TX queue element to fill.
1324 * @param[in] buf
1325 * Buffer to process.
1326 * @param elts_head
1327 * Index of the linear buffer to use if necessary (normally txq->elts_head).
1328 * @param[out] sges
1329 * Array filled with SGEs on success.
1330 *
1331 * @return
1332 * A structure containing the processed packet size in bytes and the
1333 * number of SGEs. Both fields are set to (unsigned int)-1 in case of
1334 * failure.
1335 */
1336 static struct tx_burst_sg_ret {
1337 unsigned int length;
1338 unsigned int num;
1339 }
1340 tx_burst_sg(struct txq *txq, unsigned int segs, struct txq_elt *elt,
1341 struct rte_mbuf *buf, unsigned int elts_head,
1342 struct ibv_sge (*sges)[MLX4_PMD_SGE_WR_N])
1343 {
1344 unsigned int sent_size = 0;
1345 unsigned int j;
1346 int linearize = 0;
1347
1348 /* When there are too many segments, extra segments are
1349 * linearized in the last SGE. */
1350 if (unlikely(segs > elemof(*sges))) {
1351 segs = (elemof(*sges) - 1);
1352 linearize = 1;
1353 }
1354 /* Update element. */
1355 elt->buf = buf;
1356 /* Register segments as SGEs. */
1357 for (j = 0; (j != segs); ++j) {
1358 struct ibv_sge *sge = &(*sges)[j];
1359 uint32_t lkey;
1360
1361 /* Retrieve Memory Region key for this memory pool. */
1362 lkey = txq_mp2mr(txq, txq_mb2mp(buf));
1363 if (unlikely(lkey == (uint32_t)-1)) {
1364 /* MR does not exist. */
1365 DEBUG("%p: unable to get MP <-> MR association",
1366 (void *)txq);
1367 /* Clean up TX element. */
1368 elt->buf = NULL;
1369 goto stop;
1370 }
1371 /* Update SGE. */
1372 sge->addr = rte_pktmbuf_mtod(buf, uintptr_t);
1373 if (txq->priv->vf)
1374 rte_prefetch0((volatile void *)
1375 (uintptr_t)sge->addr);
1376 sge->length = DATA_LEN(buf);
1377 sge->lkey = lkey;
1378 sent_size += sge->length;
1379 buf = NEXT(buf);
1380 }
1381 /* If buf is not NULL here and is not going to be linearized,
1382 * nb_segs is not valid. */
1383 assert(j == segs);
1384 assert((buf == NULL) || (linearize));
1385 /* Linearize extra segments. */
1386 if (linearize) {
1387 struct ibv_sge *sge = &(*sges)[segs];
1388 linear_t *linear = &(*txq->elts_linear)[elts_head];
1389 unsigned int size = linearize_mbuf(linear, buf);
1390
1391 assert(segs == (elemof(*sges) - 1));
1392 if (size == 0) {
1393 /* Invalid packet. */
1394 DEBUG("%p: packet too large to be linearized.",
1395 (void *)txq);
1396 /* Clean up TX element. */
1397 elt->buf = NULL;
1398 goto stop;
1399 }
1400 /* If MLX4_PMD_SGE_WR_N is 1, free mbuf immediately. */
1401 if (elemof(*sges) == 1) {
1402 do {
1403 struct rte_mbuf *next = NEXT(buf);
1404
1405 rte_pktmbuf_free_seg(buf);
1406 buf = next;
1407 } while (buf != NULL);
1408 elt->buf = NULL;
1409 }
1410 /* Update SGE. */
1411 sge->addr = (uintptr_t)&(*linear)[0];
1412 sge->length = size;
1413 sge->lkey = txq->mr_linear->lkey;
1414 sent_size += size;
1415 /* Include last segment. */
1416 segs++;
1417 }
1418 return (struct tx_burst_sg_ret){
1419 .length = sent_size,
1420 .num = segs,
1421 };
1422 stop:
1423 return (struct tx_burst_sg_ret){
1424 .length = -1,
1425 .num = -1,
1426 };
1427 }
1428
1429 #endif /* MLX4_PMD_SGE_WR_N > 1 */
1430
1431 /**
1432 * DPDK callback for TX.
1433 *
1434 * @param dpdk_txq
1435 * Generic pointer to TX queue structure.
1436 * @param[in] pkts
1437 * Packets to transmit.
1438 * @param pkts_n
1439 * Number of packets in array.
1440 *
1441 * @return
1442 * Number of packets successfully transmitted (<= pkts_n).
1443 */
1444 static uint16_t
1445 mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1446 {
1447 struct txq *txq = (struct txq *)dpdk_txq;
1448 unsigned int elts_head = txq->elts_head;
1449 const unsigned int elts_n = txq->elts_n;
1450 unsigned int elts_comp_cd = txq->elts_comp_cd;
1451 unsigned int elts_comp = 0;
1452 unsigned int i;
1453 unsigned int max;
1454 int err;
1455
1456 assert(elts_comp_cd != 0);
1457 txq_complete(txq);
1458 max = (elts_n - (elts_head - txq->elts_tail));
1459 if (max > elts_n)
1460 max -= elts_n;
1461 assert(max >= 1);
1462 assert(max <= elts_n);
1463 /* Always leave one free entry in the ring. */
1464 --max;
1465 if (max == 0)
1466 return 0;
1467 if (max > pkts_n)
1468 max = pkts_n;
1469 for (i = 0; (i != max); ++i) {
1470 struct rte_mbuf *buf = pkts[i];
1471 unsigned int elts_head_next =
1472 (((elts_head + 1) == elts_n) ? 0 : elts_head + 1);
1473 struct txq_elt *elt_next = &(*txq->elts)[elts_head_next];
1474 struct txq_elt *elt = &(*txq->elts)[elts_head];
1475 unsigned int segs = NB_SEGS(buf);
1476 #ifdef MLX4_PMD_SOFT_COUNTERS
1477 unsigned int sent_size = 0;
1478 #endif
1479 uint32_t send_flags = 0;
1480
1481 /* Clean up old buffer. */
1482 if (likely(elt->buf != NULL)) {
1483 struct rte_mbuf *tmp = elt->buf;
1484
1485 #ifndef NDEBUG
1486 /* Poisoning. */
1487 memset(elt, 0x66, sizeof(*elt));
1488 #endif
1489 /* Faster than rte_pktmbuf_free(). */
1490 do {
1491 struct rte_mbuf *next = NEXT(tmp);
1492
1493 rte_pktmbuf_free_seg(tmp);
1494 tmp = next;
1495 } while (tmp != NULL);
1496 }
1497 /* Request TX completion. */
1498 if (unlikely(--elts_comp_cd == 0)) {
1499 elts_comp_cd = txq->elts_comp_cd_init;
1500 ++elts_comp;
1501 send_flags |= IBV_EXP_QP_BURST_SIGNALED;
1502 }
1503 /* Should we enable HW CKSUM offload */
1504 if (buf->ol_flags &
1505 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
1506 send_flags |= IBV_EXP_QP_BURST_IP_CSUM;
1507 /* HW does not support checksum offloads at arbitrary
1508 * offsets but automatically recognizes the packet
1509 * type. For inner L3/L4 checksums, only VXLAN (UDP)
1510 * tunnels are currently supported. */
1511 if (RTE_ETH_IS_TUNNEL_PKT(buf->packet_type))
1512 send_flags |= IBV_EXP_QP_BURST_TUNNEL;
1513 }
1514 if (likely(segs == 1)) {
1515 uintptr_t addr;
1516 uint32_t length;
1517 uint32_t lkey;
1518
1519 /* Retrieve buffer information. */
1520 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1521 length = DATA_LEN(buf);
1522 /* Retrieve Memory Region key for this memory pool. */
1523 lkey = txq_mp2mr(txq, txq_mb2mp(buf));
1524 if (unlikely(lkey == (uint32_t)-1)) {
1525 /* MR does not exist. */
1526 DEBUG("%p: unable to get MP <-> MR"
1527 " association", (void *)txq);
1528 /* Clean up TX element. */
1529 elt->buf = NULL;
1530 goto stop;
1531 }
1532 /* Update element. */
1533 elt->buf = buf;
1534 if (txq->priv->vf)
1535 rte_prefetch0((volatile void *)
1536 (uintptr_t)addr);
1537 RTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);
1538 /* Put packet into send queue. */
1539 #if MLX4_PMD_MAX_INLINE > 0
1540 if (length <= txq->max_inline)
1541 err = txq->if_qp->send_pending_inline
1542 (txq->qp,
1543 (void *)addr,
1544 length,
1545 send_flags);
1546 else
1547 #endif
1548 err = txq->if_qp->send_pending
1549 (txq->qp,
1550 addr,
1551 length,
1552 lkey,
1553 send_flags);
1554 if (unlikely(err))
1555 goto stop;
1556 #ifdef MLX4_PMD_SOFT_COUNTERS
1557 sent_size += length;
1558 #endif
1559 } else {
1560 #if MLX4_PMD_SGE_WR_N > 1
1561 struct ibv_sge sges[MLX4_PMD_SGE_WR_N];
1562 struct tx_burst_sg_ret ret;
1563
1564 ret = tx_burst_sg(txq, segs, elt, buf, elts_head,
1565 &sges);
1566 if (ret.length == (unsigned int)-1)
1567 goto stop;
1568 RTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);
1569 /* Put SG list into send queue. */
1570 err = txq->if_qp->send_pending_sg_list
1571 (txq->qp,
1572 sges,
1573 ret.num,
1574 send_flags);
1575 if (unlikely(err))
1576 goto stop;
1577 #ifdef MLX4_PMD_SOFT_COUNTERS
1578 sent_size += ret.length;
1579 #endif
1580 #else /* MLX4_PMD_SGE_WR_N > 1 */
1581 DEBUG("%p: TX scattered buffers support not"
1582 " compiled in", (void *)txq);
1583 goto stop;
1584 #endif /* MLX4_PMD_SGE_WR_N > 1 */
1585 }
1586 elts_head = elts_head_next;
1587 #ifdef MLX4_PMD_SOFT_COUNTERS
1588 /* Increment sent bytes counter. */
1589 txq->stats.obytes += sent_size;
1590 #endif
1591 }
1592 stop:
1593 /* Take a shortcut if nothing must be sent. */
1594 if (unlikely(i == 0))
1595 return 0;
1596 #ifdef MLX4_PMD_SOFT_COUNTERS
1597 /* Increment sent packets counter. */
1598 txq->stats.opackets += i;
1599 #endif
1600 /* Ring QP doorbell. */
1601 err = txq->if_qp->send_flush(txq->qp);
1602 if (unlikely(err)) {
1603 /* A nonzero value is not supposed to be returned.
1604 * Nothing can be done about it. */
1605 DEBUG("%p: send_flush() failed with error %d",
1606 (void *)txq, err);
1607 }
1608 txq->elts_head = elts_head;
1609 txq->elts_comp += elts_comp;
1610 txq->elts_comp_cd = elts_comp_cd;
1611 return i;
1612 }
1613
1614 /**
1615 * DPDK callback for TX in secondary processes.
1616 *
1617 * This function configures all queues from primary process information
1618 * if necessary before reverting to the normal TX burst callback.
1619 *
1620 * @param dpdk_txq
1621 * Generic pointer to TX queue structure.
1622 * @param[in] pkts
1623 * Packets to transmit.
1624 * @param pkts_n
1625 * Number of packets in array.
1626 *
1627 * @return
1628 * Number of packets successfully transmitted (<= pkts_n).
1629 */
1630 static uint16_t
1631 mlx4_tx_burst_secondary_setup(void *dpdk_txq, struct rte_mbuf **pkts,
1632 uint16_t pkts_n)
1633 {
1634 struct txq *txq = dpdk_txq;
1635 struct priv *priv = mlx4_secondary_data_setup(txq->priv);
1636 struct priv *primary_priv;
1637 unsigned int index;
1638
1639 if (priv == NULL)
1640 return 0;
1641 primary_priv =
1642 mlx4_secondary_data[priv->dev->data->port_id].primary_priv;
1643 /* Look for queue index in both private structures. */
1644 for (index = 0; index != priv->txqs_n; ++index)
1645 if (((*primary_priv->txqs)[index] == txq) ||
1646 ((*priv->txqs)[index] == txq))
1647 break;
1648 if (index == priv->txqs_n)
1649 return 0;
1650 txq = (*priv->txqs)[index];
1651 return priv->dev->tx_pkt_burst(txq, pkts, pkts_n);
1652 }
1653
1654 /**
1655 * Configure a TX queue.
1656 *
1657 * @param dev
1658 * Pointer to Ethernet device structure.
1659 * @param txq
1660 * Pointer to TX queue structure.
1661 * @param desc
1662 * Number of descriptors to configure in queue.
1663 * @param socket
1664 * NUMA socket on which memory must be allocated.
1665 * @param[in] conf
1666 * Thresholds parameters.
1667 *
1668 * @return
1669 * 0 on success, errno value on failure.
1670 */
1671 static int
1672 txq_setup(struct rte_eth_dev *dev, struct txq *txq, uint16_t desc,
1673 unsigned int socket, const struct rte_eth_txconf *conf)
1674 {
1675 struct priv *priv = mlx4_get_priv(dev);
1676 struct txq tmpl = {
1677 .priv = priv,
1678 .socket = socket
1679 };
1680 union {
1681 struct ibv_exp_query_intf_params params;
1682 struct ibv_exp_qp_init_attr init;
1683 struct ibv_exp_res_domain_init_attr rd;
1684 struct ibv_exp_cq_init_attr cq;
1685 struct ibv_exp_qp_attr mod;
1686 } attr;
1687 enum ibv_exp_query_intf_status status;
1688 int ret = 0;
1689
1690 (void)conf; /* Thresholds configuration (ignored). */
1691 if (priv == NULL)
1692 return EINVAL;
1693 if ((desc == 0) || (desc % MLX4_PMD_SGE_WR_N)) {
1694 ERROR("%p: invalid number of TX descriptors (must be a"
1695 " multiple of %d)", (void *)dev, MLX4_PMD_SGE_WR_N);
1696 return EINVAL;
1697 }
1698 desc /= MLX4_PMD_SGE_WR_N;
1699 /* MRs will be registered in mp2mr[] later. */
1700 attr.rd = (struct ibv_exp_res_domain_init_attr){
1701 .comp_mask = (IBV_EXP_RES_DOMAIN_THREAD_MODEL |
1702 IBV_EXP_RES_DOMAIN_MSG_MODEL),
1703 .thread_model = IBV_EXP_THREAD_SINGLE,
1704 .msg_model = IBV_EXP_MSG_HIGH_BW,
1705 };
1706 tmpl.rd = ibv_exp_create_res_domain(priv->ctx, &attr.rd);
1707 if (tmpl.rd == NULL) {
1708 ret = ENOMEM;
1709 ERROR("%p: RD creation failure: %s",
1710 (void *)dev, strerror(ret));
1711 goto error;
1712 }
1713 attr.cq = (struct ibv_exp_cq_init_attr){
1714 .comp_mask = IBV_EXP_CQ_INIT_ATTR_RES_DOMAIN,
1715 .res_domain = tmpl.rd,
1716 };
1717 tmpl.cq = ibv_exp_create_cq(priv->ctx, desc, NULL, NULL, 0, &attr.cq);
1718 if (tmpl.cq == NULL) {
1719 ret = ENOMEM;
1720 ERROR("%p: CQ creation failure: %s",
1721 (void *)dev, strerror(ret));
1722 goto error;
1723 }
1724 DEBUG("priv->device_attr.max_qp_wr is %d",
1725 priv->device_attr.max_qp_wr);
1726 DEBUG("priv->device_attr.max_sge is %d",
1727 priv->device_attr.max_sge);
1728 attr.init = (struct ibv_exp_qp_init_attr){
1729 /* CQ to be associated with the send queue. */
1730 .send_cq = tmpl.cq,
1731 /* CQ to be associated with the receive queue. */
1732 .recv_cq = tmpl.cq,
1733 .cap = {
1734 /* Max number of outstanding WRs. */
1735 .max_send_wr = ((priv->device_attr.max_qp_wr < desc) ?
1736 priv->device_attr.max_qp_wr :
1737 desc),
1738 /* Max number of scatter/gather elements in a WR. */
1739 .max_send_sge = ((priv->device_attr.max_sge <
1740 MLX4_PMD_SGE_WR_N) ?
1741 priv->device_attr.max_sge :
1742 MLX4_PMD_SGE_WR_N),
1743 #if MLX4_PMD_MAX_INLINE > 0
1744 .max_inline_data = MLX4_PMD_MAX_INLINE,
1745 #endif
1746 },
1747 .qp_type = IBV_QPT_RAW_PACKET,
1748 /* Do *NOT* enable this, completions events are managed per
1749 * TX burst. */
1750 .sq_sig_all = 0,
1751 .pd = priv->pd,
1752 .res_domain = tmpl.rd,
1753 .comp_mask = (IBV_EXP_QP_INIT_ATTR_PD |
1754 IBV_EXP_QP_INIT_ATTR_RES_DOMAIN),
1755 };
1756 tmpl.qp = ibv_exp_create_qp(priv->ctx, &attr.init);
1757 if (tmpl.qp == NULL) {
1758 ret = (errno ? errno : EINVAL);
1759 ERROR("%p: QP creation failure: %s",
1760 (void *)dev, strerror(ret));
1761 goto error;
1762 }
1763 #if MLX4_PMD_MAX_INLINE > 0
1764 /* ibv_create_qp() updates this value. */
1765 tmpl.max_inline = attr.init.cap.max_inline_data;
1766 #endif
1767 attr.mod = (struct ibv_exp_qp_attr){
1768 /* Move the QP to this state. */
1769 .qp_state = IBV_QPS_INIT,
1770 /* Primary port number. */
1771 .port_num = priv->port
1772 };
1773 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod,
1774 (IBV_EXP_QP_STATE | IBV_EXP_QP_PORT));
1775 if (ret) {
1776 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
1777 (void *)dev, strerror(ret));
1778 goto error;
1779 }
1780 ret = txq_alloc_elts(&tmpl, desc);
1781 if (ret) {
1782 ERROR("%p: TXQ allocation failed: %s",
1783 (void *)dev, strerror(ret));
1784 goto error;
1785 }
1786 attr.mod = (struct ibv_exp_qp_attr){
1787 .qp_state = IBV_QPS_RTR
1788 };
1789 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);
1790 if (ret) {
1791 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
1792 (void *)dev, strerror(ret));
1793 goto error;
1794 }
1795 attr.mod.qp_state = IBV_QPS_RTS;
1796 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);
1797 if (ret) {
1798 ERROR("%p: QP state to IBV_QPS_RTS failed: %s",
1799 (void *)dev, strerror(ret));
1800 goto error;
1801 }
1802 attr.params = (struct ibv_exp_query_intf_params){
1803 .intf_scope = IBV_EXP_INTF_GLOBAL,
1804 .intf = IBV_EXP_INTF_CQ,
1805 .obj = tmpl.cq,
1806 };
1807 tmpl.if_cq = ibv_exp_query_intf(priv->ctx, &attr.params, &status);
1808 if (tmpl.if_cq == NULL) {
1809 ERROR("%p: CQ interface family query failed with status %d",
1810 (void *)dev, status);
1811 goto error;
1812 }
1813 attr.params = (struct ibv_exp_query_intf_params){
1814 .intf_scope = IBV_EXP_INTF_GLOBAL,
1815 .intf = IBV_EXP_INTF_QP_BURST,
1816 .obj = tmpl.qp,
1817 #ifdef HAVE_EXP_QP_BURST_CREATE_DISABLE_ETH_LOOPBACK
1818 /* MC loopback must be disabled when not using a VF. */
1819 .family_flags =
1820 (!priv->vf ?
1821 IBV_EXP_QP_BURST_CREATE_DISABLE_ETH_LOOPBACK :
1822 0),
1823 #endif
1824 };
1825 tmpl.if_qp = ibv_exp_query_intf(priv->ctx, &attr.params, &status);
1826 if (tmpl.if_qp == NULL) {
1827 ERROR("%p: QP interface family query failed with status %d",
1828 (void *)dev, status);
1829 goto error;
1830 }
1831 /* Clean up txq in case we're reinitializing it. */
1832 DEBUG("%p: cleaning-up old txq just in case", (void *)txq);
1833 txq_cleanup(txq);
1834 *txq = tmpl;
1835 DEBUG("%p: txq updated with %p", (void *)txq, (void *)&tmpl);
1836 /* Pre-register known mempools. */
1837 rte_mempool_walk(txq_mp2mr_iter, txq);
1838 assert(ret == 0);
1839 return 0;
1840 error:
1841 txq_cleanup(&tmpl);
1842 assert(ret > 0);
1843 return ret;
1844 }
1845
1846 /**
1847 * DPDK callback to configure a TX queue.
1848 *
1849 * @param dev
1850 * Pointer to Ethernet device structure.
1851 * @param idx
1852 * TX queue index.
1853 * @param desc
1854 * Number of descriptors to configure in queue.
1855 * @param socket
1856 * NUMA socket on which memory must be allocated.
1857 * @param[in] conf
1858 * Thresholds parameters.
1859 *
1860 * @return
1861 * 0 on success, negative errno value on failure.
1862 */
1863 static int
1864 mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1865 unsigned int socket, const struct rte_eth_txconf *conf)
1866 {
1867 struct priv *priv = dev->data->dev_private;
1868 struct txq *txq = (*priv->txqs)[idx];
1869 int ret;
1870
1871 if (mlx4_is_secondary())
1872 return -E_RTE_SECONDARY;
1873 priv_lock(priv);
1874 DEBUG("%p: configuring queue %u for %u descriptors",
1875 (void *)dev, idx, desc);
1876 if (idx >= priv->txqs_n) {
1877 ERROR("%p: queue index out of range (%u >= %u)",
1878 (void *)dev, idx, priv->txqs_n);
1879 priv_unlock(priv);
1880 return -EOVERFLOW;
1881 }
1882 if (txq != NULL) {
1883 DEBUG("%p: reusing already allocated queue index %u (%p)",
1884 (void *)dev, idx, (void *)txq);
1885 if (priv->started) {
1886 priv_unlock(priv);
1887 return -EEXIST;
1888 }
1889 (*priv->txqs)[idx] = NULL;
1890 txq_cleanup(txq);
1891 } else {
1892 txq = rte_calloc_socket("TXQ", 1, sizeof(*txq), 0, socket);
1893 if (txq == NULL) {
1894 ERROR("%p: unable to allocate queue index %u",
1895 (void *)dev, idx);
1896 priv_unlock(priv);
1897 return -ENOMEM;
1898 }
1899 }
1900 ret = txq_setup(dev, txq, desc, socket, conf);
1901 if (ret)
1902 rte_free(txq);
1903 else {
1904 txq->stats.idx = idx;
1905 DEBUG("%p: adding TX queue %p to list",
1906 (void *)dev, (void *)txq);
1907 (*priv->txqs)[idx] = txq;
1908 /* Update send callback. */
1909 dev->tx_pkt_burst = mlx4_tx_burst;
1910 }
1911 priv_unlock(priv);
1912 return -ret;
1913 }
1914
1915 /**
1916 * DPDK callback to release a TX queue.
1917 *
1918 * @param dpdk_txq
1919 * Generic TX queue pointer.
1920 */
1921 static void
1922 mlx4_tx_queue_release(void *dpdk_txq)
1923 {
1924 struct txq *txq = (struct txq *)dpdk_txq;
1925 struct priv *priv;
1926 unsigned int i;
1927
1928 if (mlx4_is_secondary())
1929 return;
1930 if (txq == NULL)
1931 return;
1932 priv = txq->priv;
1933 priv_lock(priv);
1934 for (i = 0; (i != priv->txqs_n); ++i)
1935 if ((*priv->txqs)[i] == txq) {
1936 DEBUG("%p: removing TX queue %p from list",
1937 (void *)priv->dev, (void *)txq);
1938 (*priv->txqs)[i] = NULL;
1939 break;
1940 }
1941 txq_cleanup(txq);
1942 rte_free(txq);
1943 priv_unlock(priv);
1944 }
1945
1946 /* RX queues handling. */
1947
1948 /**
1949 * Allocate RX queue elements with scattered packets support.
1950 *
1951 * @param rxq
1952 * Pointer to RX queue structure.
1953 * @param elts_n
1954 * Number of elements to allocate.
1955 * @param[in] pool
1956 * If not NULL, fetch buffers from this array instead of allocating them
1957 * with rte_pktmbuf_alloc().
1958 *
1959 * @return
1960 * 0 on success, errno value on failure.
1961 */
1962 static int
1963 rxq_alloc_elts_sp(struct rxq *rxq, unsigned int elts_n,
1964 struct rte_mbuf **pool)
1965 {
1966 unsigned int i;
1967 struct rxq_elt_sp (*elts)[elts_n] =
1968 rte_calloc_socket("RXQ elements", 1, sizeof(*elts), 0,
1969 rxq->socket);
1970 int ret = 0;
1971
1972 if (elts == NULL) {
1973 ERROR("%p: can't allocate packets array", (void *)rxq);
1974 ret = ENOMEM;
1975 goto error;
1976 }
1977 /* For each WR (packet). */
1978 for (i = 0; (i != elts_n); ++i) {
1979 unsigned int j;
1980 struct rxq_elt_sp *elt = &(*elts)[i];
1981 struct ibv_recv_wr *wr = &elt->wr;
1982 struct ibv_sge (*sges)[(elemof(elt->sges))] = &elt->sges;
1983
1984 /* These two arrays must have the same size. */
1985 assert(elemof(elt->sges) == elemof(elt->bufs));
1986 /* Configure WR. */
1987 wr->wr_id = i;
1988 wr->next = &(*elts)[(i + 1)].wr;
1989 wr->sg_list = &(*sges)[0];
1990 wr->num_sge = elemof(*sges);
1991 /* For each SGE (segment). */
1992 for (j = 0; (j != elemof(elt->bufs)); ++j) {
1993 struct ibv_sge *sge = &(*sges)[j];
1994 struct rte_mbuf *buf;
1995
1996 if (pool != NULL) {
1997 buf = *(pool++);
1998 assert(buf != NULL);
1999 rte_pktmbuf_reset(buf);
2000 } else
2001 buf = rte_pktmbuf_alloc(rxq->mp);
2002 if (buf == NULL) {
2003 assert(pool == NULL);
2004 ERROR("%p: empty mbuf pool", (void *)rxq);
2005 ret = ENOMEM;
2006 goto error;
2007 }
2008 elt->bufs[j] = buf;
2009 /* Headroom is reserved by rte_pktmbuf_alloc(). */
2010 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
2011 /* Buffer is supposed to be empty. */
2012 assert(rte_pktmbuf_data_len(buf) == 0);
2013 assert(rte_pktmbuf_pkt_len(buf) == 0);
2014 /* sge->addr must be able to store a pointer. */
2015 assert(sizeof(sge->addr) >= sizeof(uintptr_t));
2016 if (j == 0) {
2017 /* The first SGE keeps its headroom. */
2018 sge->addr = rte_pktmbuf_mtod(buf, uintptr_t);
2019 sge->length = (buf->buf_len -
2020 RTE_PKTMBUF_HEADROOM);
2021 } else {
2022 /* Subsequent SGEs lose theirs. */
2023 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
2024 SET_DATA_OFF(buf, 0);
2025 sge->addr = (uintptr_t)buf->buf_addr;
2026 sge->length = buf->buf_len;
2027 }
2028 sge->lkey = rxq->mr->lkey;
2029 /* Redundant check for tailroom. */
2030 assert(sge->length == rte_pktmbuf_tailroom(buf));
2031 }
2032 }
2033 /* The last WR pointer must be NULL. */
2034 (*elts)[(i - 1)].wr.next = NULL;
2035 DEBUG("%p: allocated and configured %u WRs (%zu segments)",
2036 (void *)rxq, elts_n, (elts_n * elemof((*elts)[0].sges)));
2037 rxq->elts_n = elts_n;
2038 rxq->elts_head = 0;
2039 rxq->elts.sp = elts;
2040 assert(ret == 0);
2041 return 0;
2042 error:
2043 if (elts != NULL) {
2044 assert(pool == NULL);
2045 for (i = 0; (i != elemof(*elts)); ++i) {
2046 unsigned int j;
2047 struct rxq_elt_sp *elt = &(*elts)[i];
2048
2049 for (j = 0; (j != elemof(elt->bufs)); ++j) {
2050 struct rte_mbuf *buf = elt->bufs[j];
2051
2052 if (buf != NULL)
2053 rte_pktmbuf_free_seg(buf);
2054 }
2055 }
2056 rte_free(elts);
2057 }
2058 DEBUG("%p: failed, freed everything", (void *)rxq);
2059 assert(ret > 0);
2060 return ret;
2061 }
2062
2063 /**
2064 * Free RX queue elements with scattered packets support.
2065 *
2066 * @param rxq
2067 * Pointer to RX queue structure.
2068 */
2069 static void
2070 rxq_free_elts_sp(struct rxq *rxq)
2071 {
2072 unsigned int i;
2073 unsigned int elts_n = rxq->elts_n;
2074 struct rxq_elt_sp (*elts)[elts_n] = rxq->elts.sp;
2075
2076 DEBUG("%p: freeing WRs", (void *)rxq);
2077 rxq->elts_n = 0;
2078 rxq->elts.sp = NULL;
2079 if (elts == NULL)
2080 return;
2081 for (i = 0; (i != elemof(*elts)); ++i) {
2082 unsigned int j;
2083 struct rxq_elt_sp *elt = &(*elts)[i];
2084
2085 for (j = 0; (j != elemof(elt->bufs)); ++j) {
2086 struct rte_mbuf *buf = elt->bufs[j];
2087
2088 if (buf != NULL)
2089 rte_pktmbuf_free_seg(buf);
2090 }
2091 }
2092 rte_free(elts);
2093 }
2094
2095 /**
2096 * Allocate RX queue elements.
2097 *
2098 * @param rxq
2099 * Pointer to RX queue structure.
2100 * @param elts_n
2101 * Number of elements to allocate.
2102 * @param[in] pool
2103 * If not NULL, fetch buffers from this array instead of allocating them
2104 * with rte_pktmbuf_alloc().
2105 *
2106 * @return
2107 * 0 on success, errno value on failure.
2108 */
2109 static int
2110 rxq_alloc_elts(struct rxq *rxq, unsigned int elts_n, struct rte_mbuf **pool)
2111 {
2112 unsigned int i;
2113 struct rxq_elt (*elts)[elts_n] =
2114 rte_calloc_socket("RXQ elements", 1, sizeof(*elts), 0,
2115 rxq->socket);
2116 int ret = 0;
2117
2118 if (elts == NULL) {
2119 ERROR("%p: can't allocate packets array", (void *)rxq);
2120 ret = ENOMEM;
2121 goto error;
2122 }
2123 /* For each WR (packet). */
2124 for (i = 0; (i != elts_n); ++i) {
2125 struct rxq_elt *elt = &(*elts)[i];
2126 struct ibv_recv_wr *wr = &elt->wr;
2127 struct ibv_sge *sge = &(*elts)[i].sge;
2128 struct rte_mbuf *buf;
2129
2130 if (pool != NULL) {
2131 buf = *(pool++);
2132 assert(buf != NULL);
2133 rte_pktmbuf_reset(buf);
2134 } else
2135 buf = rte_pktmbuf_alloc(rxq->mp);
2136 if (buf == NULL) {
2137 assert(pool == NULL);
2138 ERROR("%p: empty mbuf pool", (void *)rxq);
2139 ret = ENOMEM;
2140 goto error;
2141 }
2142 /* Configure WR. Work request ID contains its own index in
2143 * the elts array and the offset between SGE buffer header and
2144 * its data. */
2145 WR_ID(wr->wr_id).id = i;
2146 WR_ID(wr->wr_id).offset =
2147 (((uintptr_t)buf->buf_addr + RTE_PKTMBUF_HEADROOM) -
2148 (uintptr_t)buf);
2149 wr->next = &(*elts)[(i + 1)].wr;
2150 wr->sg_list = sge;
2151 wr->num_sge = 1;
2152 /* Headroom is reserved by rte_pktmbuf_alloc(). */
2153 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
2154 /* Buffer is supposed to be empty. */
2155 assert(rte_pktmbuf_data_len(buf) == 0);
2156 assert(rte_pktmbuf_pkt_len(buf) == 0);
2157 /* sge->addr must be able to store a pointer. */
2158 assert(sizeof(sge->addr) >= sizeof(uintptr_t));
2159 /* SGE keeps its headroom. */
2160 sge->addr = (uintptr_t)
2161 ((uint8_t *)buf->buf_addr + RTE_PKTMBUF_HEADROOM);
2162 sge->length = (buf->buf_len - RTE_PKTMBUF_HEADROOM);
2163 sge->lkey = rxq->mr->lkey;
2164 /* Redundant check for tailroom. */
2165 assert(sge->length == rte_pktmbuf_tailroom(buf));
2166 /* Make sure elts index and SGE mbuf pointer can be deduced
2167 * from WR ID. */
2168 if ((WR_ID(wr->wr_id).id != i) ||
2169 ((void *)((uintptr_t)sge->addr -
2170 WR_ID(wr->wr_id).offset) != buf)) {
2171 ERROR("%p: cannot store index and offset in WR ID",
2172 (void *)rxq);
2173 sge->addr = 0;
2174 rte_pktmbuf_free(buf);
2175 ret = EOVERFLOW;
2176 goto error;
2177 }
2178 }
2179 /* The last WR pointer must be NULL. */
2180 (*elts)[(i - 1)].wr.next = NULL;
2181 DEBUG("%p: allocated and configured %u single-segment WRs",
2182 (void *)rxq, elts_n);
2183 rxq->elts_n = elts_n;
2184 rxq->elts_head = 0;
2185 rxq->elts.no_sp = elts;
2186 assert(ret == 0);
2187 return 0;
2188 error:
2189 if (elts != NULL) {
2190 assert(pool == NULL);
2191 for (i = 0; (i != elemof(*elts)); ++i) {
2192 struct rxq_elt *elt = &(*elts)[i];
2193 struct rte_mbuf *buf;
2194
2195 if (elt->sge.addr == 0)
2196 continue;
2197 assert(WR_ID(elt->wr.wr_id).id == i);
2198 buf = (void *)((uintptr_t)elt->sge.addr -
2199 WR_ID(elt->wr.wr_id).offset);
2200 rte_pktmbuf_free_seg(buf);
2201 }
2202 rte_free(elts);
2203 }
2204 DEBUG("%p: failed, freed everything", (void *)rxq);
2205 assert(ret > 0);
2206 return ret;
2207 }
2208
2209 /**
2210 * Free RX queue elements.
2211 *
2212 * @param rxq
2213 * Pointer to RX queue structure.
2214 */
2215 static void
2216 rxq_free_elts(struct rxq *rxq)
2217 {
2218 unsigned int i;
2219 unsigned int elts_n = rxq->elts_n;
2220 struct rxq_elt (*elts)[elts_n] = rxq->elts.no_sp;
2221
2222 DEBUG("%p: freeing WRs", (void *)rxq);
2223 rxq->elts_n = 0;
2224 rxq->elts.no_sp = NULL;
2225 if (elts == NULL)
2226 return;
2227 for (i = 0; (i != elemof(*elts)); ++i) {
2228 struct rxq_elt *elt = &(*elts)[i];
2229 struct rte_mbuf *buf;
2230
2231 if (elt->sge.addr == 0)
2232 continue;
2233 assert(WR_ID(elt->wr.wr_id).id == i);
2234 buf = (void *)((uintptr_t)elt->sge.addr -
2235 WR_ID(elt->wr.wr_id).offset);
2236 rte_pktmbuf_free_seg(buf);
2237 }
2238 rte_free(elts);
2239 }
2240
2241 /**
2242 * Delete flow steering rule.
2243 *
2244 * @param rxq
2245 * Pointer to RX queue structure.
2246 * @param mac_index
2247 * MAC address index.
2248 * @param vlan_index
2249 * VLAN index.
2250 */
2251 static void
2252 rxq_del_flow(struct rxq *rxq, unsigned int mac_index, unsigned int vlan_index)
2253 {
2254 #ifndef NDEBUG
2255 struct priv *priv = rxq->priv;
2256 const uint8_t (*mac)[ETHER_ADDR_LEN] =
2257 (const uint8_t (*)[ETHER_ADDR_LEN])
2258 priv->mac[mac_index].addr_bytes;
2259 #endif
2260 assert(rxq->mac_flow[mac_index][vlan_index] != NULL);
2261 DEBUG("%p: removing MAC address %02x:%02x:%02x:%02x:%02x:%02x index %u"
2262 " (VLAN ID %" PRIu16 ")",
2263 (void *)rxq,
2264 (*mac)[0], (*mac)[1], (*mac)[2], (*mac)[3], (*mac)[4], (*mac)[5],
2265 mac_index, priv->vlan_filter[vlan_index].id);
2266 claim_zero(ibv_destroy_flow(rxq->mac_flow[mac_index][vlan_index]));
2267 rxq->mac_flow[mac_index][vlan_index] = NULL;
2268 }
2269
2270 /**
2271 * Unregister a MAC address from a RX queue.
2272 *
2273 * @param rxq
2274 * Pointer to RX queue structure.
2275 * @param mac_index
2276 * MAC address index.
2277 */
2278 static void
2279 rxq_mac_addr_del(struct rxq *rxq, unsigned int mac_index)
2280 {
2281 struct priv *priv = rxq->priv;
2282 unsigned int i;
2283 unsigned int vlans = 0;
2284
2285 assert(mac_index < elemof(priv->mac));
2286 if (!BITFIELD_ISSET(rxq->mac_configured, mac_index))
2287 return;
2288 for (i = 0; (i != elemof(priv->vlan_filter)); ++i) {
2289 if (!priv->vlan_filter[i].enabled)
2290 continue;
2291 rxq_del_flow(rxq, mac_index, i);
2292 vlans++;
2293 }
2294 if (!vlans) {
2295 rxq_del_flow(rxq, mac_index, 0);
2296 }
2297 BITFIELD_RESET(rxq->mac_configured, mac_index);
2298 }
2299
2300 /**
2301 * Unregister all MAC addresses from a RX queue.
2302 *
2303 * @param rxq
2304 * Pointer to RX queue structure.
2305 */
2306 static void
2307 rxq_mac_addrs_del(struct rxq *rxq)
2308 {
2309 struct priv *priv = rxq->priv;
2310 unsigned int i;
2311
2312 for (i = 0; (i != elemof(priv->mac)); ++i)
2313 rxq_mac_addr_del(rxq, i);
2314 }
2315
2316 static int rxq_promiscuous_enable(struct rxq *);
2317 static void rxq_promiscuous_disable(struct rxq *);
2318
2319 /**
2320 * Add single flow steering rule.
2321 *
2322 * @param rxq
2323 * Pointer to RX queue structure.
2324 * @param mac_index
2325 * MAC address index to register.
2326 * @param vlan_index
2327 * VLAN index. Use -1 for a flow without VLAN.
2328 *
2329 * @return
2330 * 0 on success, errno value on failure.
2331 */
2332 static int
2333 rxq_add_flow(struct rxq *rxq, unsigned int mac_index, unsigned int vlan_index)
2334 {
2335 struct ibv_flow *flow;
2336 struct priv *priv = rxq->priv;
2337 const uint8_t (*mac)[ETHER_ADDR_LEN] =
2338 (const uint8_t (*)[ETHER_ADDR_LEN])
2339 priv->mac[mac_index].addr_bytes;
2340
2341 /* Allocate flow specification on the stack. */
2342 struct __attribute__((packed)) {
2343 struct ibv_flow_attr attr;
2344 struct ibv_flow_spec_eth spec;
2345 } data;
2346 struct ibv_flow_attr *attr = &data.attr;
2347 struct ibv_flow_spec_eth *spec = &data.spec;
2348
2349 assert(mac_index < elemof(priv->mac));
2350 assert((vlan_index < elemof(priv->vlan_filter)) || (vlan_index == -1u));
2351 /*
2352 * No padding must be inserted by the compiler between attr and spec.
2353 * This layout is expected by libibverbs.
2354 */
2355 assert(((uint8_t *)attr + sizeof(*attr)) == (uint8_t *)spec);
2356 *attr = (struct ibv_flow_attr){
2357 .type = IBV_FLOW_ATTR_NORMAL,
2358 .priority = 3,
2359 .num_of_specs = 1,
2360 .port = priv->port,
2361 .flags = 0
2362 };
2363 *spec = (struct ibv_flow_spec_eth){
2364 .type = IBV_FLOW_SPEC_ETH,
2365 .size = sizeof(*spec),
2366 .val = {
2367 .dst_mac = {
2368 (*mac)[0], (*mac)[1], (*mac)[2],
2369 (*mac)[3], (*mac)[4], (*mac)[5]
2370 },
2371 .vlan_tag = ((vlan_index != -1u) ?
2372 htons(priv->vlan_filter[vlan_index].id) :
2373 0),
2374 },
2375 .mask = {
2376 .dst_mac = "\xff\xff\xff\xff\xff\xff",
2377 .vlan_tag = ((vlan_index != -1u) ? htons(0xfff) : 0),
2378 }
2379 };
2380 DEBUG("%p: adding MAC address %02x:%02x:%02x:%02x:%02x:%02x index %u"
2381 " (VLAN %s %" PRIu16 ")",
2382 (void *)rxq,
2383 (*mac)[0], (*mac)[1], (*mac)[2], (*mac)[3], (*mac)[4], (*mac)[5],
2384 mac_index,
2385 ((vlan_index != -1u) ? "ID" : "index"),
2386 ((vlan_index != -1u) ? priv->vlan_filter[vlan_index].id : -1u));
2387 /* Create related flow. */
2388 errno = 0;
2389 flow = ibv_create_flow(rxq->qp, attr);
2390 if (flow == NULL) {
2391 /* It's not clear whether errno is always set in this case. */
2392 ERROR("%p: flow configuration failed, errno=%d: %s",
2393 (void *)rxq, errno,
2394 (errno ? strerror(errno) : "Unknown error"));
2395 if (errno)
2396 return errno;
2397 return EINVAL;
2398 }
2399 if (vlan_index == -1u)
2400 vlan_index = 0;
2401 assert(rxq->mac_flow[mac_index][vlan_index] == NULL);
2402 rxq->mac_flow[mac_index][vlan_index] = flow;
2403 return 0;
2404 }
2405
2406 /**
2407 * Register a MAC address in a RX queue.
2408 *
2409 * @param rxq
2410 * Pointer to RX queue structure.
2411 * @param mac_index
2412 * MAC address index to register.
2413 *
2414 * @return
2415 * 0 on success, errno value on failure.
2416 */
2417 static int
2418 rxq_mac_addr_add(struct rxq *rxq, unsigned int mac_index)
2419 {
2420 struct priv *priv = rxq->priv;
2421 unsigned int i;
2422 unsigned int vlans = 0;
2423 int ret;
2424
2425 assert(mac_index < elemof(priv->mac));
2426 if (BITFIELD_ISSET(rxq->mac_configured, mac_index))
2427 rxq_mac_addr_del(rxq, mac_index);
2428 /* Fill VLAN specifications. */
2429 for (i = 0; (i != elemof(priv->vlan_filter)); ++i) {
2430 if (!priv->vlan_filter[i].enabled)
2431 continue;
2432 /* Create related flow. */
2433 ret = rxq_add_flow(rxq, mac_index, i);
2434 if (!ret) {
2435 vlans++;
2436 continue;
2437 }
2438 /* Failure, rollback. */
2439 while (i != 0)
2440 if (priv->vlan_filter[--i].enabled)
2441 rxq_del_flow(rxq, mac_index, i);
2442 assert(ret > 0);
2443 return ret;
2444 }
2445 /* In case there is no VLAN filter. */
2446 if (!vlans) {
2447 ret = rxq_add_flow(rxq, mac_index, -1);
2448 if (ret)
2449 return ret;
2450 }
2451 BITFIELD_SET(rxq->mac_configured, mac_index);
2452 return 0;
2453 }
2454
2455 /**
2456 * Register all MAC addresses in a RX queue.
2457 *
2458 * @param rxq
2459 * Pointer to RX queue structure.
2460 *
2461 * @return
2462 * 0 on success, errno value on failure.
2463 */
2464 static int
2465 rxq_mac_addrs_add(struct rxq *rxq)
2466 {
2467 struct priv *priv = rxq->priv;
2468 unsigned int i;
2469 int ret;
2470
2471 for (i = 0; (i != elemof(priv->mac)); ++i) {
2472 if (!BITFIELD_ISSET(priv->mac_configured, i))
2473 continue;
2474 ret = rxq_mac_addr_add(rxq, i);
2475 if (!ret)
2476 continue;
2477 /* Failure, rollback. */
2478 while (i != 0)
2479 rxq_mac_addr_del(rxq, --i);
2480 assert(ret > 0);
2481 return ret;
2482 }
2483 return 0;
2484 }
2485
2486 /**
2487 * Unregister a MAC address.
2488 *
2489 * In RSS mode, the MAC address is unregistered from the parent queue,
2490 * otherwise it is unregistered from each queue directly.
2491 *
2492 * @param priv
2493 * Pointer to private structure.
2494 * @param mac_index
2495 * MAC address index.
2496 */
2497 static void
2498 priv_mac_addr_del(struct priv *priv, unsigned int mac_index)
2499 {
2500 unsigned int i;
2501
2502 assert(mac_index < elemof(priv->mac));
2503 if (!BITFIELD_ISSET(priv->mac_configured, mac_index))
2504 return;
2505 if (priv->rss) {
2506 rxq_mac_addr_del(&priv->rxq_parent, mac_index);
2507 goto end;
2508 }
2509 for (i = 0; (i != priv->dev->data->nb_rx_queues); ++i)
2510 rxq_mac_addr_del((*priv->rxqs)[i], mac_index);
2511 end:
2512 BITFIELD_RESET(priv->mac_configured, mac_index);
2513 }
2514
2515 /**
2516 * Register a MAC address.
2517 *
2518 * In RSS mode, the MAC address is registered in the parent queue,
2519 * otherwise it is registered in each queue directly.
2520 *
2521 * @param priv
2522 * Pointer to private structure.
2523 * @param mac_index
2524 * MAC address index to use.
2525 * @param mac
2526 * MAC address to register.
2527 *
2528 * @return
2529 * 0 on success, errno value on failure.
2530 */
2531 static int
2532 priv_mac_addr_add(struct priv *priv, unsigned int mac_index,
2533 const uint8_t (*mac)[ETHER_ADDR_LEN])
2534 {
2535 unsigned int i;
2536 int ret;
2537
2538 assert(mac_index < elemof(priv->mac));
2539 /* First, make sure this address isn't already configured. */
2540 for (i = 0; (i != elemof(priv->mac)); ++i) {
2541 /* Skip this index, it's going to be reconfigured. */
2542 if (i == mac_index)
2543 continue;
2544 if (!BITFIELD_ISSET(priv->mac_configured, i))
2545 continue;
2546 if (memcmp(priv->mac[i].addr_bytes, *mac, sizeof(*mac)))
2547 continue;
2548 /* Address already configured elsewhere, return with error. */
2549 return EADDRINUSE;
2550 }
2551 if (BITFIELD_ISSET(priv->mac_configured, mac_index))
2552 priv_mac_addr_del(priv, mac_index);
2553 priv->mac[mac_index] = (struct ether_addr){
2554 {
2555 (*mac)[0], (*mac)[1], (*mac)[2],
2556 (*mac)[3], (*mac)[4], (*mac)[5]
2557 }
2558 };
2559 /* If device isn't started, this is all we need to do. */
2560 if (!priv->started) {
2561 #ifndef NDEBUG
2562 /* Verify that all queues have this index disabled. */
2563 for (i = 0; (i != priv->rxqs_n); ++i) {
2564 if ((*priv->rxqs)[i] == NULL)
2565 continue;
2566 assert(!BITFIELD_ISSET
2567 ((*priv->rxqs)[i]->mac_configured, mac_index));
2568 }
2569 #endif
2570 goto end;
2571 }
2572 if (priv->rss) {
2573 ret = rxq_mac_addr_add(&priv->rxq_parent, mac_index);
2574 if (ret)
2575 return ret;
2576 goto end;
2577 }
2578 for (i = 0; (i != priv->rxqs_n); ++i) {
2579 if ((*priv->rxqs)[i] == NULL)
2580 continue;
2581 ret = rxq_mac_addr_add((*priv->rxqs)[i], mac_index);
2582 if (!ret)
2583 continue;
2584 /* Failure, rollback. */
2585 while (i != 0)
2586 if ((*priv->rxqs)[(--i)] != NULL)
2587 rxq_mac_addr_del((*priv->rxqs)[i], mac_index);
2588 return ret;
2589 }
2590 end:
2591 BITFIELD_SET(priv->mac_configured, mac_index);
2592 return 0;
2593 }
2594
2595 /**
2596 * Enable allmulti mode in a RX queue.
2597 *
2598 * @param rxq
2599 * Pointer to RX queue structure.
2600 *
2601 * @return
2602 * 0 on success, errno value on failure.
2603 */
2604 static int
2605 rxq_allmulticast_enable(struct rxq *rxq)
2606 {
2607 struct ibv_flow *flow;
2608 struct ibv_flow_attr attr = {
2609 .type = IBV_FLOW_ATTR_MC_DEFAULT,
2610 .num_of_specs = 0,
2611 .port = rxq->priv->port,
2612 .flags = 0
2613 };
2614
2615 DEBUG("%p: enabling allmulticast mode", (void *)rxq);
2616 if (rxq->allmulti_flow != NULL)
2617 return EBUSY;
2618 errno = 0;
2619 flow = ibv_create_flow(rxq->qp, &attr);
2620 if (flow == NULL) {
2621 /* It's not clear whether errno is always set in this case. */
2622 ERROR("%p: flow configuration failed, errno=%d: %s",
2623 (void *)rxq, errno,
2624 (errno ? strerror(errno) : "Unknown error"));
2625 if (errno)
2626 return errno;
2627 return EINVAL;
2628 }
2629 rxq->allmulti_flow = flow;
2630 DEBUG("%p: allmulticast mode enabled", (void *)rxq);
2631 return 0;
2632 }
2633
2634 /**
2635 * Disable allmulti mode in a RX queue.
2636 *
2637 * @param rxq
2638 * Pointer to RX queue structure.
2639 */
2640 static void
2641 rxq_allmulticast_disable(struct rxq *rxq)
2642 {
2643 DEBUG("%p: disabling allmulticast mode", (void *)rxq);
2644 if (rxq->allmulti_flow == NULL)
2645 return;
2646 claim_zero(ibv_destroy_flow(rxq->allmulti_flow));
2647 rxq->allmulti_flow = NULL;
2648 DEBUG("%p: allmulticast mode disabled", (void *)rxq);
2649 }
2650
2651 /**
2652 * Enable promiscuous mode in a RX queue.
2653 *
2654 * @param rxq
2655 * Pointer to RX queue structure.
2656 *
2657 * @return
2658 * 0 on success, errno value on failure.
2659 */
2660 static int
2661 rxq_promiscuous_enable(struct rxq *rxq)
2662 {
2663 struct ibv_flow *flow;
2664 struct ibv_flow_attr attr = {
2665 .type = IBV_FLOW_ATTR_ALL_DEFAULT,
2666 .num_of_specs = 0,
2667 .port = rxq->priv->port,
2668 .flags = 0
2669 };
2670
2671 if (rxq->priv->vf)
2672 return 0;
2673 DEBUG("%p: enabling promiscuous mode", (void *)rxq);
2674 if (rxq->promisc_flow != NULL)
2675 return EBUSY;
2676 errno = 0;
2677 flow = ibv_create_flow(rxq->qp, &attr);
2678 if (flow == NULL) {
2679 /* It's not clear whether errno is always set in this case. */
2680 ERROR("%p: flow configuration failed, errno=%d: %s",
2681 (void *)rxq, errno,
2682 (errno ? strerror(errno) : "Unknown error"));
2683 if (errno)
2684 return errno;
2685 return EINVAL;
2686 }
2687 rxq->promisc_flow = flow;
2688 DEBUG("%p: promiscuous mode enabled", (void *)rxq);
2689 return 0;
2690 }
2691
2692 /**
2693 * Disable promiscuous mode in a RX queue.
2694 *
2695 * @param rxq
2696 * Pointer to RX queue structure.
2697 */
2698 static void
2699 rxq_promiscuous_disable(struct rxq *rxq)
2700 {
2701 if (rxq->priv->vf)
2702 return;
2703 DEBUG("%p: disabling promiscuous mode", (void *)rxq);
2704 if (rxq->promisc_flow == NULL)
2705 return;
2706 claim_zero(ibv_destroy_flow(rxq->promisc_flow));
2707 rxq->promisc_flow = NULL;
2708 DEBUG("%p: promiscuous mode disabled", (void *)rxq);
2709 }
2710
2711 /**
2712 * Clean up a RX queue.
2713 *
2714 * Destroy objects, free allocated memory and reset the structure for reuse.
2715 *
2716 * @param rxq
2717 * Pointer to RX queue structure.
2718 */
2719 static void
2720 rxq_cleanup(struct rxq *rxq)
2721 {
2722 struct ibv_exp_release_intf_params params;
2723
2724 DEBUG("cleaning up %p", (void *)rxq);
2725 if (rxq->sp)
2726 rxq_free_elts_sp(rxq);
2727 else
2728 rxq_free_elts(rxq);
2729 if (rxq->if_qp != NULL) {
2730 assert(rxq->priv != NULL);
2731 assert(rxq->priv->ctx != NULL);
2732 assert(rxq->qp != NULL);
2733 params = (struct ibv_exp_release_intf_params){
2734 .comp_mask = 0,
2735 };
2736 claim_zero(ibv_exp_release_intf(rxq->priv->ctx,
2737 rxq->if_qp,
2738 &params));
2739 }
2740 if (rxq->if_cq != NULL) {
2741 assert(rxq->priv != NULL);
2742 assert(rxq->priv->ctx != NULL);
2743 assert(rxq->cq != NULL);
2744 params = (struct ibv_exp_release_intf_params){
2745 .comp_mask = 0,
2746 };
2747 claim_zero(ibv_exp_release_intf(rxq->priv->ctx,
2748 rxq->if_cq,
2749 &params));
2750 }
2751 if (rxq->qp != NULL) {
2752 rxq_promiscuous_disable(rxq);
2753 rxq_allmulticast_disable(rxq);
2754 rxq_mac_addrs_del(rxq);
2755 claim_zero(ibv_destroy_qp(rxq->qp));
2756 }
2757 if (rxq->cq != NULL)
2758 claim_zero(ibv_destroy_cq(rxq->cq));
2759 if (rxq->rd != NULL) {
2760 struct ibv_exp_destroy_res_domain_attr attr = {
2761 .comp_mask = 0,
2762 };
2763
2764 assert(rxq->priv != NULL);
2765 assert(rxq->priv->ctx != NULL);
2766 claim_zero(ibv_exp_destroy_res_domain(rxq->priv->ctx,
2767 rxq->rd,
2768 &attr));
2769 }
2770 if (rxq->mr != NULL)
2771 claim_zero(ibv_dereg_mr(rxq->mr));
2772 memset(rxq, 0, sizeof(*rxq));
2773 }
2774
2775 /**
2776 * Translate RX completion flags to packet type.
2777 *
2778 * @param flags
2779 * RX completion flags returned by poll_length_flags().
2780 *
2781 * @note: fix mlx4_dev_supported_ptypes_get() if any change here.
2782 *
2783 * @return
2784 * Packet type for struct rte_mbuf.
2785 */
2786 static inline uint32_t
2787 rxq_cq_to_pkt_type(uint32_t flags)
2788 {
2789 uint32_t pkt_type;
2790
2791 if (flags & IBV_EXP_CQ_RX_TUNNEL_PACKET)
2792 pkt_type =
2793 TRANSPOSE(flags,
2794 IBV_EXP_CQ_RX_OUTER_IPV4_PACKET,
2795 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN) |
2796 TRANSPOSE(flags,
2797 IBV_EXP_CQ_RX_OUTER_IPV6_PACKET,
2798 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
2799 TRANSPOSE(flags,
2800 IBV_EXP_CQ_RX_IPV4_PACKET,
2801 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
2802 TRANSPOSE(flags,
2803 IBV_EXP_CQ_RX_IPV6_PACKET,
2804 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
2805 else
2806 pkt_type =
2807 TRANSPOSE(flags,
2808 IBV_EXP_CQ_RX_IPV4_PACKET,
2809 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN) |
2810 TRANSPOSE(flags,
2811 IBV_EXP_CQ_RX_IPV6_PACKET,
2812 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN);
2813 return pkt_type;
2814 }
2815
2816 /**
2817 * Translate RX completion flags to offload flags.
2818 *
2819 * @param[in] rxq
2820 * Pointer to RX queue structure.
2821 * @param flags
2822 * RX completion flags returned by poll_length_flags().
2823 *
2824 * @return
2825 * Offload flags (ol_flags) for struct rte_mbuf.
2826 */
2827 static inline uint32_t
2828 rxq_cq_to_ol_flags(const struct rxq *rxq, uint32_t flags)
2829 {
2830 uint32_t ol_flags = 0;
2831
2832 if (rxq->csum)
2833 ol_flags |=
2834 TRANSPOSE(flags,
2835 IBV_EXP_CQ_RX_IP_CSUM_OK,
2836 PKT_RX_IP_CKSUM_GOOD) |
2837 TRANSPOSE(flags,
2838 IBV_EXP_CQ_RX_TCP_UDP_CSUM_OK,
2839 PKT_RX_L4_CKSUM_GOOD);
2840 if ((flags & IBV_EXP_CQ_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
2841 ol_flags |=
2842 TRANSPOSE(flags,
2843 IBV_EXP_CQ_RX_OUTER_IP_CSUM_OK,
2844 PKT_RX_IP_CKSUM_GOOD) |
2845 TRANSPOSE(flags,
2846 IBV_EXP_CQ_RX_OUTER_TCP_UDP_CSUM_OK,
2847 PKT_RX_L4_CKSUM_GOOD);
2848 return ol_flags;
2849 }
2850
2851 static uint16_t
2852 mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
2853
2854 /**
2855 * DPDK callback for RX with scattered packets support.
2856 *
2857 * @param dpdk_rxq
2858 * Generic pointer to RX queue structure.
2859 * @param[out] pkts
2860 * Array to store received packets.
2861 * @param pkts_n
2862 * Maximum number of packets in array.
2863 *
2864 * @return
2865 * Number of packets successfully received (<= pkts_n).
2866 */
2867 static uint16_t
2868 mlx4_rx_burst_sp(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2869 {
2870 struct rxq *rxq = (struct rxq *)dpdk_rxq;
2871 struct rxq_elt_sp (*elts)[rxq->elts_n] = rxq->elts.sp;
2872 const unsigned int elts_n = rxq->elts_n;
2873 unsigned int elts_head = rxq->elts_head;
2874 struct ibv_recv_wr head;
2875 struct ibv_recv_wr **next = &head.next;
2876 struct ibv_recv_wr *bad_wr;
2877 unsigned int i;
2878 unsigned int pkts_ret = 0;
2879 int ret;
2880
2881 if (unlikely(!rxq->sp))
2882 return mlx4_rx_burst(dpdk_rxq, pkts, pkts_n);
2883 if (unlikely(elts == NULL)) /* See RTE_DEV_CMD_SET_MTU. */
2884 return 0;
2885 for (i = 0; (i != pkts_n); ++i) {
2886 struct rxq_elt_sp *elt = &(*elts)[elts_head];
2887 struct ibv_recv_wr *wr = &elt->wr;
2888 uint64_t wr_id = wr->wr_id;
2889 unsigned int len;
2890 unsigned int pkt_buf_len;
2891 struct rte_mbuf *pkt_buf = NULL; /* Buffer returned in pkts. */
2892 struct rte_mbuf **pkt_buf_next = &pkt_buf;
2893 unsigned int seg_headroom = RTE_PKTMBUF_HEADROOM;
2894 unsigned int j = 0;
2895 uint32_t flags;
2896
2897 /* Sanity checks. */
2898 #ifdef NDEBUG
2899 (void)wr_id;
2900 #endif
2901 assert(wr_id < rxq->elts_n);
2902 assert(wr->sg_list == elt->sges);
2903 assert(wr->num_sge == elemof(elt->sges));
2904 assert(elts_head < rxq->elts_n);
2905 assert(rxq->elts_head < rxq->elts_n);
2906 ret = rxq->if_cq->poll_length_flags(rxq->cq, NULL, NULL,
2907 &flags);
2908 if (unlikely(ret < 0)) {
2909 struct ibv_wc wc;
2910 int wcs_n;
2911
2912 DEBUG("rxq=%p, poll_length() failed (ret=%d)",
2913 (void *)rxq, ret);
2914 /* ibv_poll_cq() must be used in case of failure. */
2915 wcs_n = ibv_poll_cq(rxq->cq, 1, &wc);
2916 if (unlikely(wcs_n == 0))
2917 break;
2918 if (unlikely(wcs_n < 0)) {
2919 DEBUG("rxq=%p, ibv_poll_cq() failed (wcs_n=%d)",
2920 (void *)rxq, wcs_n);
2921 break;
2922 }
2923 assert(wcs_n == 1);
2924 if (unlikely(wc.status != IBV_WC_SUCCESS)) {
2925 /* Whatever, just repost the offending WR. */
2926 DEBUG("rxq=%p, wr_id=%" PRIu64 ": bad work"
2927 " completion status (%d): %s",
2928 (void *)rxq, wc.wr_id, wc.status,
2929 ibv_wc_status_str(wc.status));
2930 #ifdef MLX4_PMD_SOFT_COUNTERS
2931 /* Increment dropped packets counter. */
2932 ++rxq->stats.idropped;
2933 #endif
2934 /* Link completed WRs together for repost. */
2935 *next = wr;
2936 next = &wr->next;
2937 goto repost;
2938 }
2939 ret = wc.byte_len;
2940 }
2941 if (ret == 0)
2942 break;
2943 len = ret;
2944 pkt_buf_len = len;
2945 /* Link completed WRs together for repost. */
2946 *next = wr;
2947 next = &wr->next;
2948 /*
2949 * Replace spent segments with new ones, concatenate and
2950 * return them as pkt_buf.
2951 */
2952 while (1) {
2953 struct ibv_sge *sge = &elt->sges[j];
2954 struct rte_mbuf *seg = elt->bufs[j];
2955 struct rte_mbuf *rep;
2956 unsigned int seg_tailroom;
2957
2958 /*
2959 * Fetch initial bytes of packet descriptor into a
2960 * cacheline while allocating rep.
2961 */
2962 rte_prefetch0(seg);
2963 rep = rte_mbuf_raw_alloc(rxq->mp);
2964 if (unlikely(rep == NULL)) {
2965 /*
2966 * Unable to allocate a replacement mbuf,
2967 * repost WR.
2968 */
2969 DEBUG("rxq=%p, wr_id=%" PRIu64 ":"
2970 " can't allocate a new mbuf",
2971 (void *)rxq, wr_id);
2972 if (pkt_buf != NULL) {
2973 *pkt_buf_next = NULL;
2974 rte_pktmbuf_free(pkt_buf);
2975 }
2976 /* Increase out of memory counters. */
2977 ++rxq->stats.rx_nombuf;
2978 ++rxq->priv->dev->data->rx_mbuf_alloc_failed;
2979 goto repost;
2980 }
2981 #ifndef NDEBUG
2982 /* Poison user-modifiable fields in rep. */
2983 NEXT(rep) = (void *)((uintptr_t)-1);
2984 SET_DATA_OFF(rep, 0xdead);
2985 DATA_LEN(rep) = 0xd00d;
2986 PKT_LEN(rep) = 0xdeadd00d;
2987 NB_SEGS(rep) = 0x2a;
2988 PORT(rep) = 0x2a;
2989 rep->ol_flags = -1;
2990 #endif
2991 assert(rep->buf_len == seg->buf_len);
2992 /* Reconfigure sge to use rep instead of seg. */
2993 assert(sge->lkey == rxq->mr->lkey);
2994 sge->addr = ((uintptr_t)rep->buf_addr + seg_headroom);
2995 elt->bufs[j] = rep;
2996 ++j;
2997 /* Update pkt_buf if it's the first segment, or link
2998 * seg to the previous one and update pkt_buf_next. */
2999 *pkt_buf_next = seg;
3000 pkt_buf_next = &NEXT(seg);
3001 /* Update seg information. */
3002 seg_tailroom = (seg->buf_len - seg_headroom);
3003 assert(sge->length == seg_tailroom);
3004 SET_DATA_OFF(seg, seg_headroom);
3005 if (likely(len <= seg_tailroom)) {
3006 /* Last segment. */
3007 DATA_LEN(seg) = len;
3008 PKT_LEN(seg) = len;
3009 /* Sanity check. */
3010 assert(rte_pktmbuf_headroom(seg) ==
3011 seg_headroom);
3012 assert(rte_pktmbuf_tailroom(seg) ==
3013 (seg_tailroom - len));
3014 break;
3015 }
3016 DATA_LEN(seg) = seg_tailroom;
3017 PKT_LEN(seg) = seg_tailroom;
3018 /* Sanity check. */
3019 assert(rte_pktmbuf_headroom(seg) == seg_headroom);
3020 assert(rte_pktmbuf_tailroom(seg) == 0);
3021 /* Fix len and clear headroom for next segments. */
3022 len -= seg_tailroom;
3023 seg_headroom = 0;
3024 }
3025 /* Update head and tail segments. */
3026 *pkt_buf_next = NULL;
3027 assert(pkt_buf != NULL);
3028 assert(j != 0);
3029 NB_SEGS(pkt_buf) = j;
3030 PORT(pkt_buf) = rxq->port_id;
3031 PKT_LEN(pkt_buf) = pkt_buf_len;
3032 pkt_buf->packet_type = rxq_cq_to_pkt_type(flags);
3033 pkt_buf->ol_flags = rxq_cq_to_ol_flags(rxq, flags);
3034
3035 /* Return packet. */
3036 *(pkts++) = pkt_buf;
3037 ++pkts_ret;
3038 #ifdef MLX4_PMD_SOFT_COUNTERS
3039 /* Increase bytes counter. */
3040 rxq->stats.ibytes += pkt_buf_len;
3041 #endif
3042 repost:
3043 if (++elts_head >= elts_n)
3044 elts_head = 0;
3045 continue;
3046 }
3047 if (unlikely(i == 0))
3048 return 0;
3049 *next = NULL;
3050 /* Repost WRs. */
3051 #ifdef DEBUG_RECV
3052 DEBUG("%p: reposting %d WRs", (void *)rxq, i);
3053 #endif
3054 ret = ibv_post_recv(rxq->qp, head.next, &bad_wr);
3055 if (unlikely(ret)) {
3056 /* Inability to repost WRs is fatal. */
3057 DEBUG("%p: ibv_post_recv(): failed for WR %p: %s",
3058 (void *)rxq->priv,
3059 (void *)bad_wr,
3060 strerror(ret));
3061 abort();
3062 }
3063 rxq->elts_head = elts_head;
3064 #ifdef MLX4_PMD_SOFT_COUNTERS
3065 /* Increase packets counter. */
3066 rxq->stats.ipackets += pkts_ret;
3067 #endif
3068 return pkts_ret;
3069 }
3070
3071 /**
3072 * DPDK callback for RX.
3073 *
3074 * The following function is the same as mlx4_rx_burst_sp(), except it doesn't
3075 * manage scattered packets. Improves performance when MRU is lower than the
3076 * size of the first segment.
3077 *
3078 * @param dpdk_rxq
3079 * Generic pointer to RX queue structure.
3080 * @param[out] pkts
3081 * Array to store received packets.
3082 * @param pkts_n
3083 * Maximum number of packets in array.
3084 *
3085 * @return
3086 * Number of packets successfully received (<= pkts_n).
3087 */
3088 static uint16_t
3089 mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
3090 {
3091 struct rxq *rxq = (struct rxq *)dpdk_rxq;
3092 struct rxq_elt (*elts)[rxq->elts_n] = rxq->elts.no_sp;
3093 const unsigned int elts_n = rxq->elts_n;
3094 unsigned int elts_head = rxq->elts_head;
3095 struct ibv_sge sges[pkts_n];
3096 unsigned int i;
3097 unsigned int pkts_ret = 0;
3098 int ret;
3099
3100 if (unlikely(rxq->sp))
3101 return mlx4_rx_burst_sp(dpdk_rxq, pkts, pkts_n);
3102 for (i = 0; (i != pkts_n); ++i) {
3103 struct rxq_elt *elt = &(*elts)[elts_head];
3104 struct ibv_recv_wr *wr = &elt->wr;
3105 uint64_t wr_id = wr->wr_id;
3106 unsigned int len;
3107 struct rte_mbuf *seg = (void *)((uintptr_t)elt->sge.addr -
3108 WR_ID(wr_id).offset);
3109 struct rte_mbuf *rep;
3110 uint32_t flags;
3111
3112 /* Sanity checks. */
3113 assert(WR_ID(wr_id).id < rxq->elts_n);
3114 assert(wr->sg_list == &elt->sge);
3115 assert(wr->num_sge == 1);
3116 assert(elts_head < rxq->elts_n);
3117 assert(rxq->elts_head < rxq->elts_n);
3118 /*
3119 * Fetch initial bytes of packet descriptor into a
3120 * cacheline while allocating rep.
3121 */
3122 rte_mbuf_prefetch_part1(seg);
3123 rte_mbuf_prefetch_part2(seg);
3124 ret = rxq->if_cq->poll_length_flags(rxq->cq, NULL, NULL,
3125 &flags);
3126 if (unlikely(ret < 0)) {
3127 struct ibv_wc wc;
3128 int wcs_n;
3129
3130 DEBUG("rxq=%p, poll_length() failed (ret=%d)",
3131 (void *)rxq, ret);
3132 /* ibv_poll_cq() must be used in case of failure. */
3133 wcs_n = ibv_poll_cq(rxq->cq, 1, &wc);
3134 if (unlikely(wcs_n == 0))
3135 break;
3136 if (unlikely(wcs_n < 0)) {
3137 DEBUG("rxq=%p, ibv_poll_cq() failed (wcs_n=%d)",
3138 (void *)rxq, wcs_n);
3139 break;
3140 }
3141 assert(wcs_n == 1);
3142 if (unlikely(wc.status != IBV_WC_SUCCESS)) {
3143 /* Whatever, just repost the offending WR. */
3144 DEBUG("rxq=%p, wr_id=%" PRIu64 ": bad work"
3145 " completion status (%d): %s",
3146 (void *)rxq, wc.wr_id, wc.status,
3147 ibv_wc_status_str(wc.status));
3148 #ifdef MLX4_PMD_SOFT_COUNTERS
3149 /* Increment dropped packets counter. */
3150 ++rxq->stats.idropped;
3151 #endif
3152 /* Add SGE to array for repost. */
3153 sges[i] = elt->sge;
3154 goto repost;
3155 }
3156 ret = wc.byte_len;
3157 }
3158 if (ret == 0)
3159 break;
3160 len = ret;
3161 rep = rte_mbuf_raw_alloc(rxq->mp);
3162 if (unlikely(rep == NULL)) {
3163 /*
3164 * Unable to allocate a replacement mbuf,
3165 * repost WR.
3166 */
3167 DEBUG("rxq=%p, wr_id=%" PRIu32 ":"
3168 " can't allocate a new mbuf",
3169 (void *)rxq, WR_ID(wr_id).id);
3170 /* Increase out of memory counters. */
3171 ++rxq->stats.rx_nombuf;
3172 ++rxq->priv->dev->data->rx_mbuf_alloc_failed;
3173 /* Add SGE to array for repost. */
3174 sges[i] = elt->sge;
3175 goto repost;
3176 }
3177
3178 /* Reconfigure sge to use rep instead of seg. */
3179 elt->sge.addr = (uintptr_t)rep->buf_addr + RTE_PKTMBUF_HEADROOM;
3180 assert(elt->sge.lkey == rxq->mr->lkey);
3181 WR_ID(wr->wr_id).offset =
3182 (((uintptr_t)rep->buf_addr + RTE_PKTMBUF_HEADROOM) -
3183 (uintptr_t)rep);
3184 assert(WR_ID(wr->wr_id).id == WR_ID(wr_id).id);
3185
3186 /* Add SGE to array for repost. */
3187 sges[i] = elt->sge;
3188
3189 /* Update seg information. */
3190 SET_DATA_OFF(seg, RTE_PKTMBUF_HEADROOM);
3191 NB_SEGS(seg) = 1;
3192 PORT(seg) = rxq->port_id;
3193 NEXT(seg) = NULL;
3194 PKT_LEN(seg) = len;
3195 DATA_LEN(seg) = len;
3196 seg->packet_type = rxq_cq_to_pkt_type(flags);
3197 seg->ol_flags = rxq_cq_to_ol_flags(rxq, flags);
3198
3199 /* Return packet. */
3200 *(pkts++) = seg;
3201 ++pkts_ret;
3202 #ifdef MLX4_PMD_SOFT_COUNTERS
3203 /* Increase bytes counter. */
3204 rxq->stats.ibytes += len;
3205 #endif
3206 repost:
3207 if (++elts_head >= elts_n)
3208 elts_head = 0;
3209 continue;
3210 }
3211 if (unlikely(i == 0))
3212 return 0;
3213 /* Repost WRs. */
3214 #ifdef DEBUG_RECV
3215 DEBUG("%p: reposting %u WRs", (void *)rxq, i);
3216 #endif
3217 ret = rxq->if_qp->recv_burst(rxq->qp, sges, i);
3218 if (unlikely(ret)) {
3219 /* Inability to repost WRs is fatal. */
3220 DEBUG("%p: recv_burst(): failed (ret=%d)",
3221 (void *)rxq->priv,
3222 ret);
3223 abort();
3224 }
3225 rxq->elts_head = elts_head;
3226 #ifdef MLX4_PMD_SOFT_COUNTERS
3227 /* Increase packets counter. */
3228 rxq->stats.ipackets += pkts_ret;
3229 #endif
3230 return pkts_ret;
3231 }
3232
3233 /**
3234 * DPDK callback for RX in secondary processes.
3235 *
3236 * This function configures all queues from primary process information
3237 * if necessary before reverting to the normal RX burst callback.
3238 *
3239 * @param dpdk_rxq
3240 * Generic pointer to RX queue structure.
3241 * @param[out] pkts
3242 * Array to store received packets.
3243 * @param pkts_n
3244 * Maximum number of packets in array.
3245 *
3246 * @return
3247 * Number of packets successfully received (<= pkts_n).
3248 */
3249 static uint16_t
3250 mlx4_rx_burst_secondary_setup(void *dpdk_rxq, struct rte_mbuf **pkts,
3251 uint16_t pkts_n)
3252 {
3253 struct rxq *rxq = dpdk_rxq;
3254 struct priv *priv = mlx4_secondary_data_setup(rxq->priv);
3255 struct priv *primary_priv;
3256 unsigned int index;
3257
3258 if (priv == NULL)
3259 return 0;
3260 primary_priv =
3261 mlx4_secondary_data[priv->dev->data->port_id].primary_priv;
3262 /* Look for queue index in both private structures. */
3263 for (index = 0; index != priv->rxqs_n; ++index)
3264 if (((*primary_priv->rxqs)[index] == rxq) ||
3265 ((*priv->rxqs)[index] == rxq))
3266 break;
3267 if (index == priv->rxqs_n)
3268 return 0;
3269 rxq = (*priv->rxqs)[index];
3270 return priv->dev->rx_pkt_burst(rxq, pkts, pkts_n);
3271 }
3272
3273 /**
3274 * Allocate a Queue Pair.
3275 * Optionally setup inline receive if supported.
3276 *
3277 * @param priv
3278 * Pointer to private structure.
3279 * @param cq
3280 * Completion queue to associate with QP.
3281 * @param desc
3282 * Number of descriptors in QP (hint only).
3283 *
3284 * @return
3285 * QP pointer or NULL in case of error.
3286 */
3287 static struct ibv_qp *
3288 rxq_setup_qp(struct priv *priv, struct ibv_cq *cq, uint16_t desc,
3289 struct ibv_exp_res_domain *rd)
3290 {
3291 struct ibv_exp_qp_init_attr attr = {
3292 /* CQ to be associated with the send queue. */
3293 .send_cq = cq,
3294 /* CQ to be associated with the receive queue. */
3295 .recv_cq = cq,
3296 .cap = {
3297 /* Max number of outstanding WRs. */
3298 .max_recv_wr = ((priv->device_attr.max_qp_wr < desc) ?
3299 priv->device_attr.max_qp_wr :
3300 desc),
3301 /* Max number of scatter/gather elements in a WR. */
3302 .max_recv_sge = ((priv->device_attr.max_sge <
3303 MLX4_PMD_SGE_WR_N) ?
3304 priv->device_attr.max_sge :
3305 MLX4_PMD_SGE_WR_N),
3306 },
3307 .qp_type = IBV_QPT_RAW_PACKET,
3308 .comp_mask = (IBV_EXP_QP_INIT_ATTR_PD |
3309 IBV_EXP_QP_INIT_ATTR_RES_DOMAIN),
3310 .pd = priv->pd,
3311 .res_domain = rd,
3312 };
3313
3314 #ifdef INLINE_RECV
3315 attr.max_inl_recv = priv->inl_recv_size;
3316 attr.comp_mask |= IBV_EXP_QP_INIT_ATTR_INL_RECV;
3317 #endif
3318 return ibv_exp_create_qp(priv->ctx, &attr);
3319 }
3320
3321 #ifdef RSS_SUPPORT
3322
3323 /**
3324 * Allocate a RSS Queue Pair.
3325 * Optionally setup inline receive if supported.
3326 *
3327 * @param priv
3328 * Pointer to private structure.
3329 * @param cq
3330 * Completion queue to associate with QP.
3331 * @param desc
3332 * Number of descriptors in QP (hint only).
3333 * @param parent
3334 * If nonzero, create a parent QP, otherwise a child.
3335 *
3336 * @return
3337 * QP pointer or NULL in case of error.
3338 */
3339 static struct ibv_qp *
3340 rxq_setup_qp_rss(struct priv *priv, struct ibv_cq *cq, uint16_t desc,
3341 int parent, struct ibv_exp_res_domain *rd)
3342 {
3343 struct ibv_exp_qp_init_attr attr = {
3344 /* CQ to be associated with the send queue. */
3345 .send_cq = cq,
3346 /* CQ to be associated with the receive queue. */
3347 .recv_cq = cq,
3348 .cap = {
3349 /* Max number of outstanding WRs. */
3350 .max_recv_wr = ((priv->device_attr.max_qp_wr < desc) ?
3351 priv->device_attr.max_qp_wr :
3352 desc),
3353 /* Max number of scatter/gather elements in a WR. */
3354 .max_recv_sge = ((priv->device_attr.max_sge <
3355 MLX4_PMD_SGE_WR_N) ?
3356 priv->device_attr.max_sge :
3357 MLX4_PMD_SGE_WR_N),
3358 },
3359 .qp_type = IBV_QPT_RAW_PACKET,
3360 .comp_mask = (IBV_EXP_QP_INIT_ATTR_PD |
3361 IBV_EXP_QP_INIT_ATTR_RES_DOMAIN |
3362 IBV_EXP_QP_INIT_ATTR_QPG),
3363 .pd = priv->pd,
3364 .res_domain = rd,
3365 };
3366
3367 #ifdef INLINE_RECV
3368 attr.max_inl_recv = priv->inl_recv_size,
3369 attr.comp_mask |= IBV_EXP_QP_INIT_ATTR_INL_RECV;
3370 #endif
3371 if (parent) {
3372 attr.qpg.qpg_type = IBV_EXP_QPG_PARENT;
3373 /* TSS isn't necessary. */
3374 attr.qpg.parent_attrib.tss_child_count = 0;
3375 attr.qpg.parent_attrib.rss_child_count =
3376 rte_align32pow2(priv->rxqs_n + 1) >> 1;
3377 DEBUG("initializing parent RSS queue");
3378 } else {
3379 attr.qpg.qpg_type = IBV_EXP_QPG_CHILD_RX;
3380 attr.qpg.qpg_parent = priv->rxq_parent.qp;
3381 DEBUG("initializing child RSS queue");
3382 }
3383 return ibv_exp_create_qp(priv->ctx, &attr);
3384 }
3385
3386 #endif /* RSS_SUPPORT */
3387
3388 /**
3389 * Reconfigure a RX queue with new parameters.
3390 *
3391 * rxq_rehash() does not allocate mbufs, which, if not done from the right
3392 * thread (such as a control thread), may corrupt the pool.
3393 * In case of failure, the queue is left untouched.
3394 *
3395 * @param dev
3396 * Pointer to Ethernet device structure.
3397 * @param rxq
3398 * RX queue pointer.
3399 *
3400 * @return
3401 * 0 on success, errno value on failure.
3402 */
3403 static int
3404 rxq_rehash(struct rte_eth_dev *dev, struct rxq *rxq)
3405 {
3406 struct priv *priv = rxq->priv;
3407 struct rxq tmpl = *rxq;
3408 unsigned int mbuf_n;
3409 unsigned int desc_n;
3410 struct rte_mbuf **pool;
3411 unsigned int i, k;
3412 struct ibv_exp_qp_attr mod;
3413 struct ibv_recv_wr *bad_wr;
3414 unsigned int mb_len;
3415 int err;
3416 int parent = (rxq == &priv->rxq_parent);
3417
3418 if (parent) {
3419 ERROR("%p: cannot rehash parent queue %p",
3420 (void *)dev, (void *)rxq);
3421 return EINVAL;
3422 }
3423 mb_len = rte_pktmbuf_data_room_size(rxq->mp);
3424 DEBUG("%p: rehashing queue %p", (void *)dev, (void *)rxq);
3425 /* Number of descriptors and mbufs currently allocated. */
3426 desc_n = (tmpl.elts_n * (tmpl.sp ? MLX4_PMD_SGE_WR_N : 1));
3427 mbuf_n = desc_n;
3428 /* Toggle RX checksum offload if hardware supports it. */
3429 if (priv->hw_csum) {
3430 tmpl.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;
3431 rxq->csum = tmpl.csum;
3432 }
3433 if (priv->hw_csum_l2tun) {
3434 tmpl.csum_l2tun = !!dev->data->dev_conf.rxmode.hw_ip_checksum;
3435 rxq->csum_l2tun = tmpl.csum_l2tun;
3436 }
3437 /* Enable scattered packets support for this queue if necessary. */
3438 assert(mb_len >= RTE_PKTMBUF_HEADROOM);
3439 if (dev->data->dev_conf.rxmode.enable_scatter &&
3440 (dev->data->dev_conf.rxmode.max_rx_pkt_len >
3441 (mb_len - RTE_PKTMBUF_HEADROOM))) {
3442 tmpl.sp = 1;
3443 desc_n /= MLX4_PMD_SGE_WR_N;
3444 } else
3445 tmpl.sp = 0;
3446 DEBUG("%p: %s scattered packets support (%u WRs)",
3447 (void *)dev, (tmpl.sp ? "enabling" : "disabling"), desc_n);
3448 /* If scatter mode is the same as before, nothing to do. */
3449 if (tmpl.sp == rxq->sp) {
3450 DEBUG("%p: nothing to do", (void *)dev);
3451 return 0;
3452 }
3453 /* Remove attached flows if RSS is disabled (no parent queue). */
3454 if (!priv->rss) {
3455 rxq_allmulticast_disable(&tmpl);
3456 rxq_promiscuous_disable(&tmpl);
3457 rxq_mac_addrs_del(&tmpl);
3458 /* Update original queue in case of failure. */
3459 rxq->allmulti_flow = tmpl.allmulti_flow;
3460 rxq->promisc_flow = tmpl.promisc_flow;
3461 memcpy(rxq->mac_configured, tmpl.mac_configured,
3462 sizeof(rxq->mac_configured));
3463 memcpy(rxq->mac_flow, tmpl.mac_flow, sizeof(rxq->mac_flow));
3464 }
3465 /* From now on, any failure will render the queue unusable.
3466 * Reinitialize QP. */
3467 mod = (struct ibv_exp_qp_attr){ .qp_state = IBV_QPS_RESET };
3468 err = ibv_exp_modify_qp(tmpl.qp, &mod, IBV_EXP_QP_STATE);
3469 if (err) {
3470 ERROR("%p: cannot reset QP: %s", (void *)dev, strerror(err));
3471 assert(err > 0);
3472 return err;
3473 }
3474 err = ibv_resize_cq(tmpl.cq, desc_n);
3475 if (err) {
3476 ERROR("%p: cannot resize CQ: %s", (void *)dev, strerror(err));
3477 assert(err > 0);
3478 return err;
3479 }
3480 mod = (struct ibv_exp_qp_attr){
3481 /* Move the QP to this state. */
3482 .qp_state = IBV_QPS_INIT,
3483 /* Primary port number. */
3484 .port_num = priv->port
3485 };
3486 err = ibv_exp_modify_qp(tmpl.qp, &mod,
3487 (IBV_EXP_QP_STATE |
3488 #ifdef RSS_SUPPORT
3489 (parent ? IBV_EXP_QP_GROUP_RSS : 0) |
3490 #endif /* RSS_SUPPORT */
3491 IBV_EXP_QP_PORT));
3492 if (err) {
3493 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
3494 (void *)dev, strerror(err));
3495 assert(err > 0);
3496 return err;
3497 };
3498 /* Reconfigure flows. Do not care for errors. */
3499 if (!priv->rss) {
3500 rxq_mac_addrs_add(&tmpl);
3501 if (priv->promisc)
3502 rxq_promiscuous_enable(&tmpl);
3503 if (priv->allmulti)
3504 rxq_allmulticast_enable(&tmpl);
3505 /* Update original queue in case of failure. */
3506 rxq->allmulti_flow = tmpl.allmulti_flow;
3507 rxq->promisc_flow = tmpl.promisc_flow;
3508 memcpy(rxq->mac_configured, tmpl.mac_configured,
3509 sizeof(rxq->mac_configured));
3510 memcpy(rxq->mac_flow, tmpl.mac_flow, sizeof(rxq->mac_flow));
3511 }
3512 /* Allocate pool. */
3513 pool = rte_malloc(__func__, (mbuf_n * sizeof(*pool)), 0);
3514 if (pool == NULL) {
3515 ERROR("%p: cannot allocate memory", (void *)dev);
3516 return ENOBUFS;
3517 }
3518 /* Snatch mbufs from original queue. */
3519 k = 0;
3520 if (rxq->sp) {
3521 struct rxq_elt_sp (*elts)[rxq->elts_n] = rxq->elts.sp;
3522
3523 for (i = 0; (i != elemof(*elts)); ++i) {
3524 struct rxq_elt_sp *elt = &(*elts)[i];
3525 unsigned int j;
3526
3527 for (j = 0; (j != elemof(elt->bufs)); ++j) {
3528 assert(elt->bufs[j] != NULL);
3529 pool[k++] = elt->bufs[j];
3530 }
3531 }
3532 } else {
3533 struct rxq_elt (*elts)[rxq->elts_n] = rxq->elts.no_sp;
3534
3535 for (i = 0; (i != elemof(*elts)); ++i) {
3536 struct rxq_elt *elt = &(*elts)[i];
3537 struct rte_mbuf *buf = (void *)
3538 ((uintptr_t)elt->sge.addr -
3539 WR_ID(elt->wr.wr_id).offset);
3540
3541 assert(WR_ID(elt->wr.wr_id).id == i);
3542 pool[k++] = buf;
3543 }
3544 }
3545 assert(k == mbuf_n);
3546 tmpl.elts_n = 0;
3547 tmpl.elts.sp = NULL;
3548 assert((void *)&tmpl.elts.sp == (void *)&tmpl.elts.no_sp);
3549 err = ((tmpl.sp) ?
3550 rxq_alloc_elts_sp(&tmpl, desc_n, pool) :
3551 rxq_alloc_elts(&tmpl, desc_n, pool));
3552 if (err) {
3553 ERROR("%p: cannot reallocate WRs, aborting", (void *)dev);
3554 rte_free(pool);
3555 assert(err > 0);
3556 return err;
3557 }
3558 assert(tmpl.elts_n == desc_n);
3559 assert(tmpl.elts.sp != NULL);
3560 rte_free(pool);
3561 /* Clean up original data. */
3562 rxq->elts_n = 0;
3563 rte_free(rxq->elts.sp);
3564 rxq->elts.sp = NULL;
3565 /* Post WRs. */
3566 err = ibv_post_recv(tmpl.qp,
3567 (tmpl.sp ?
3568 &(*tmpl.elts.sp)[0].wr :
3569 &(*tmpl.elts.no_sp)[0].wr),
3570 &bad_wr);
3571 if (err) {
3572 ERROR("%p: ibv_post_recv() failed for WR %p: %s",
3573 (void *)dev,
3574 (void *)bad_wr,
3575 strerror(err));
3576 goto skip_rtr;
3577 }
3578 mod = (struct ibv_exp_qp_attr){
3579 .qp_state = IBV_QPS_RTR
3580 };
3581 err = ibv_exp_modify_qp(tmpl.qp, &mod, IBV_EXP_QP_STATE);
3582 if (err)
3583 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
3584 (void *)dev, strerror(err));
3585 skip_rtr:
3586 *rxq = tmpl;
3587 assert(err >= 0);
3588 return err;
3589 }
3590
3591 /**
3592 * Configure a RX queue.
3593 *
3594 * @param dev
3595 * Pointer to Ethernet device structure.
3596 * @param rxq
3597 * Pointer to RX queue structure.
3598 * @param desc
3599 * Number of descriptors to configure in queue.
3600 * @param socket
3601 * NUMA socket on which memory must be allocated.
3602 * @param inactive
3603 * If true, the queue is disabled because its index is higher or
3604 * equal to the real number of queues, which must be a power of 2.
3605 * @param[in] conf
3606 * Thresholds parameters.
3607 * @param mp
3608 * Memory pool for buffer allocations.
3609 *
3610 * @return
3611 * 0 on success, errno value on failure.
3612 */
3613 static int
3614 rxq_setup(struct rte_eth_dev *dev, struct rxq *rxq, uint16_t desc,
3615 unsigned int socket, int inactive, const struct rte_eth_rxconf *conf,
3616 struct rte_mempool *mp)
3617 {
3618 struct priv *priv = dev->data->dev_private;
3619 struct rxq tmpl = {
3620 .priv = priv,
3621 .mp = mp,
3622 .socket = socket
3623 };
3624 struct ibv_exp_qp_attr mod;
3625 union {
3626 struct ibv_exp_query_intf_params params;
3627 struct ibv_exp_cq_init_attr cq;
3628 struct ibv_exp_res_domain_init_attr rd;
3629 } attr;
3630 enum ibv_exp_query_intf_status status;
3631 struct ibv_recv_wr *bad_wr;
3632 unsigned int mb_len;
3633 int ret = 0;
3634 int parent = (rxq == &priv->rxq_parent);
3635
3636 (void)conf; /* Thresholds configuration (ignored). */
3637 /*
3638 * If this is a parent queue, hardware must support RSS and
3639 * RSS must be enabled.
3640 */
3641 assert((!parent) || ((priv->hw_rss) && (priv->rss)));
3642 if (parent) {
3643 /* Even if unused, ibv_create_cq() requires at least one
3644 * descriptor. */
3645 desc = 1;
3646 goto skip_mr;
3647 }
3648 mb_len = rte_pktmbuf_data_room_size(mp);
3649 if ((desc == 0) || (desc % MLX4_PMD_SGE_WR_N)) {
3650 ERROR("%p: invalid number of RX descriptors (must be a"
3651 " multiple of %d)", (void *)dev, MLX4_PMD_SGE_WR_N);
3652 return EINVAL;
3653 }
3654 /* Toggle RX checksum offload if hardware supports it. */
3655 if (priv->hw_csum)
3656 tmpl.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;
3657 if (priv->hw_csum_l2tun)
3658 tmpl.csum_l2tun = !!dev->data->dev_conf.rxmode.hw_ip_checksum;
3659 /* Enable scattered packets support for this queue if necessary. */
3660 assert(mb_len >= RTE_PKTMBUF_HEADROOM);
3661 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
3662 (mb_len - RTE_PKTMBUF_HEADROOM)) {
3663 tmpl.sp = 0;
3664 } else if (dev->data->dev_conf.rxmode.enable_scatter) {
3665 tmpl.sp = 1;
3666 desc /= MLX4_PMD_SGE_WR_N;
3667 } else {
3668 WARN("%p: the requested maximum Rx packet size (%u) is"
3669 " larger than a single mbuf (%u) and scattered"
3670 " mode has not been requested",
3671 (void *)dev,
3672 dev->data->dev_conf.rxmode.max_rx_pkt_len,
3673 mb_len - RTE_PKTMBUF_HEADROOM);
3674 }
3675 DEBUG("%p: %s scattered packets support (%u WRs)",
3676 (void *)dev, (tmpl.sp ? "enabling" : "disabling"), desc);
3677 /* Use the entire RX mempool as the memory region. */
3678 tmpl.mr = mlx4_mp2mr(priv->pd, mp);
3679 if (tmpl.mr == NULL) {
3680 ret = EINVAL;
3681 ERROR("%p: MR creation failure: %s",
3682 (void *)dev, strerror(ret));
3683 goto error;
3684 }
3685 skip_mr:
3686 attr.rd = (struct ibv_exp_res_domain_init_attr){
3687 .comp_mask = (IBV_EXP_RES_DOMAIN_THREAD_MODEL |
3688 IBV_EXP_RES_DOMAIN_MSG_MODEL),
3689 .thread_model = IBV_EXP_THREAD_SINGLE,
3690 .msg_model = IBV_EXP_MSG_HIGH_BW,
3691 };
3692 tmpl.rd = ibv_exp_create_res_domain(priv->ctx, &attr.rd);
3693 if (tmpl.rd == NULL) {
3694 ret = ENOMEM;
3695 ERROR("%p: RD creation failure: %s",
3696 (void *)dev, strerror(ret));
3697 goto error;
3698 }
3699 attr.cq = (struct ibv_exp_cq_init_attr){
3700 .comp_mask = IBV_EXP_CQ_INIT_ATTR_RES_DOMAIN,
3701 .res_domain = tmpl.rd,
3702 };
3703 tmpl.cq = ibv_exp_create_cq(priv->ctx, desc, NULL, NULL, 0, &attr.cq);
3704 if (tmpl.cq == NULL) {
3705 ret = ENOMEM;
3706 ERROR("%p: CQ creation failure: %s",
3707 (void *)dev, strerror(ret));
3708 goto error;
3709 }
3710 DEBUG("priv->device_attr.max_qp_wr is %d",
3711 priv->device_attr.max_qp_wr);
3712 DEBUG("priv->device_attr.max_sge is %d",
3713 priv->device_attr.max_sge);
3714 #ifdef RSS_SUPPORT
3715 if (priv->rss && !inactive)
3716 tmpl.qp = rxq_setup_qp_rss(priv, tmpl.cq, desc, parent,
3717 tmpl.rd);
3718 else
3719 #endif /* RSS_SUPPORT */
3720 tmpl.qp = rxq_setup_qp(priv, tmpl.cq, desc, tmpl.rd);
3721 if (tmpl.qp == NULL) {
3722 ret = (errno ? errno : EINVAL);
3723 ERROR("%p: QP creation failure: %s",
3724 (void *)dev, strerror(ret));
3725 goto error;
3726 }
3727 mod = (struct ibv_exp_qp_attr){
3728 /* Move the QP to this state. */
3729 .qp_state = IBV_QPS_INIT,
3730 /* Primary port number. */
3731 .port_num = priv->port
3732 };
3733 ret = ibv_exp_modify_qp(tmpl.qp, &mod,
3734 (IBV_EXP_QP_STATE |
3735 #ifdef RSS_SUPPORT
3736 (parent ? IBV_EXP_QP_GROUP_RSS : 0) |
3737 #endif /* RSS_SUPPORT */
3738 IBV_EXP_QP_PORT));
3739 if (ret) {
3740 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
3741 (void *)dev, strerror(ret));
3742 goto error;
3743 }
3744 if ((parent) || (!priv->rss)) {
3745 /* Configure MAC and broadcast addresses. */
3746 ret = rxq_mac_addrs_add(&tmpl);
3747 if (ret) {
3748 ERROR("%p: QP flow attachment failed: %s",
3749 (void *)dev, strerror(ret));
3750 goto error;
3751 }
3752 }
3753 /* Allocate descriptors for RX queues, except for the RSS parent. */
3754 if (parent)
3755 goto skip_alloc;
3756 if (tmpl.sp)
3757 ret = rxq_alloc_elts_sp(&tmpl, desc, NULL);
3758 else
3759 ret = rxq_alloc_elts(&tmpl, desc, NULL);
3760 if (ret) {
3761 ERROR("%p: RXQ allocation failed: %s",
3762 (void *)dev, strerror(ret));
3763 goto error;
3764 }
3765 ret = ibv_post_recv(tmpl.qp,
3766 (tmpl.sp ?
3767 &(*tmpl.elts.sp)[0].wr :
3768 &(*tmpl.elts.no_sp)[0].wr),
3769 &bad_wr);
3770 if (ret) {
3771 ERROR("%p: ibv_post_recv() failed for WR %p: %s",
3772 (void *)dev,
3773 (void *)bad_wr,
3774 strerror(ret));
3775 goto error;
3776 }
3777 skip_alloc:
3778 mod = (struct ibv_exp_qp_attr){
3779 .qp_state = IBV_QPS_RTR
3780 };
3781 ret = ibv_exp_modify_qp(tmpl.qp, &mod, IBV_EXP_QP_STATE);
3782 if (ret) {
3783 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
3784 (void *)dev, strerror(ret));
3785 goto error;
3786 }
3787 /* Save port ID. */
3788 tmpl.port_id = dev->data->port_id;
3789 DEBUG("%p: RTE port ID: %u", (void *)rxq, tmpl.port_id);
3790 attr.params = (struct ibv_exp_query_intf_params){
3791 .intf_scope = IBV_EXP_INTF_GLOBAL,
3792 .intf = IBV_EXP_INTF_CQ,
3793 .obj = tmpl.cq,
3794 };
3795 tmpl.if_cq = ibv_exp_query_intf(priv->ctx, &attr.params, &status);
3796 if (tmpl.if_cq == NULL) {
3797 ERROR("%p: CQ interface family query failed with status %d",
3798 (void *)dev, status);
3799 goto error;
3800 }
3801 attr.params = (struct ibv_exp_query_intf_params){
3802 .intf_scope = IBV_EXP_INTF_GLOBAL,
3803 .intf = IBV_EXP_INTF_QP_BURST,
3804 .obj = tmpl.qp,
3805 };
3806 tmpl.if_qp = ibv_exp_query_intf(priv->ctx, &attr.params, &status);
3807 if (tmpl.if_qp == NULL) {
3808 ERROR("%p: QP interface family query failed with status %d",
3809 (void *)dev, status);
3810 goto error;
3811 }
3812 /* Clean up rxq in case we're reinitializing it. */
3813 DEBUG("%p: cleaning-up old rxq just in case", (void *)rxq);
3814 rxq_cleanup(rxq);
3815 *rxq = tmpl;
3816 DEBUG("%p: rxq updated with %p", (void *)rxq, (void *)&tmpl);
3817 assert(ret == 0);
3818 return 0;
3819 error:
3820 rxq_cleanup(&tmpl);
3821 assert(ret > 0);
3822 return ret;
3823 }
3824
3825 /**
3826 * DPDK callback to configure a RX queue.
3827 *
3828 * @param dev
3829 * Pointer to Ethernet device structure.
3830 * @param idx
3831 * RX queue index.
3832 * @param desc
3833 * Number of descriptors to configure in queue.
3834 * @param socket
3835 * NUMA socket on which memory must be allocated.
3836 * @param[in] conf
3837 * Thresholds parameters.
3838 * @param mp
3839 * Memory pool for buffer allocations.
3840 *
3841 * @return
3842 * 0 on success, negative errno value on failure.
3843 */
3844 static int
3845 mlx4_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
3846 unsigned int socket, const struct rte_eth_rxconf *conf,
3847 struct rte_mempool *mp)
3848 {
3849 struct priv *priv = dev->data->dev_private;
3850 struct rxq *rxq = (*priv->rxqs)[idx];
3851 int inactive = 0;
3852 int ret;
3853
3854 if (mlx4_is_secondary())
3855 return -E_RTE_SECONDARY;
3856 priv_lock(priv);
3857 DEBUG("%p: configuring queue %u for %u descriptors",
3858 (void *)dev, idx, desc);
3859 if (idx >= priv->rxqs_n) {
3860 ERROR("%p: queue index out of range (%u >= %u)",
3861 (void *)dev, idx, priv->rxqs_n);
3862 priv_unlock(priv);
3863 return -EOVERFLOW;
3864 }
3865 if (rxq != NULL) {
3866 DEBUG("%p: reusing already allocated queue index %u (%p)",
3867 (void *)dev, idx, (void *)rxq);
3868 if (priv->started) {
3869 priv_unlock(priv);
3870 return -EEXIST;
3871 }
3872 (*priv->rxqs)[idx] = NULL;
3873 rxq_cleanup(rxq);
3874 } else {
3875 rxq = rte_calloc_socket("RXQ", 1, sizeof(*rxq), 0, socket);
3876 if (rxq == NULL) {
3877 ERROR("%p: unable to allocate queue index %u",
3878 (void *)dev, idx);
3879 priv_unlock(priv);
3880 return -ENOMEM;
3881 }
3882 }
3883 if (idx >= rte_align32pow2(priv->rxqs_n + 1) >> 1)
3884 inactive = 1;
3885 ret = rxq_setup(dev, rxq, desc, socket, inactive, conf, mp);
3886 if (ret)
3887 rte_free(rxq);
3888 else {
3889 rxq->stats.idx = idx;
3890 DEBUG("%p: adding RX queue %p to list",
3891 (void *)dev, (void *)rxq);
3892 (*priv->rxqs)[idx] = rxq;
3893 /* Update receive callback. */
3894 if (rxq->sp)
3895 dev->rx_pkt_burst = mlx4_rx_burst_sp;
3896 else
3897 dev->rx_pkt_burst = mlx4_rx_burst;
3898 }
3899 priv_unlock(priv);
3900 return -ret;
3901 }
3902
3903 /**
3904 * DPDK callback to release a RX queue.
3905 *
3906 * @param dpdk_rxq
3907 * Generic RX queue pointer.
3908 */
3909 static void
3910 mlx4_rx_queue_release(void *dpdk_rxq)
3911 {
3912 struct rxq *rxq = (struct rxq *)dpdk_rxq;
3913 struct priv *priv;
3914 unsigned int i;
3915
3916 if (mlx4_is_secondary())
3917 return;
3918 if (rxq == NULL)
3919 return;
3920 priv = rxq->priv;
3921 priv_lock(priv);
3922 assert(rxq != &priv->rxq_parent);
3923 for (i = 0; (i != priv->rxqs_n); ++i)
3924 if ((*priv->rxqs)[i] == rxq) {
3925 DEBUG("%p: removing RX queue %p from list",
3926 (void *)priv->dev, (void *)rxq);
3927 (*priv->rxqs)[i] = NULL;
3928 break;
3929 }
3930 rxq_cleanup(rxq);
3931 rte_free(rxq);
3932 priv_unlock(priv);
3933 }
3934
3935 static int
3936 priv_dev_interrupt_handler_install(struct priv *, struct rte_eth_dev *);
3937
3938 static int
3939 priv_dev_removal_interrupt_handler_install(struct priv *, struct rte_eth_dev *);
3940
3941 static int
3942 priv_dev_link_interrupt_handler_install(struct priv *, struct rte_eth_dev *);
3943
3944 /**
3945 * DPDK callback to start the device.
3946 *
3947 * Simulate device start by attaching all configured flows.
3948 *
3949 * @param dev
3950 * Pointer to Ethernet device structure.
3951 *
3952 * @return
3953 * 0 on success, negative errno value on failure.
3954 */
3955 static int
3956 mlx4_dev_start(struct rte_eth_dev *dev)
3957 {
3958 struct priv *priv = dev->data->dev_private;
3959 unsigned int i = 0;
3960 unsigned int r;
3961 struct rxq *rxq;
3962 int ret;
3963
3964 if (mlx4_is_secondary())
3965 return -E_RTE_SECONDARY;
3966 priv_lock(priv);
3967 if (priv->started) {
3968 priv_unlock(priv);
3969 return 0;
3970 }
3971 DEBUG("%p: attaching configured flows to all RX queues", (void *)dev);
3972 priv->started = 1;
3973 if (priv->rss) {
3974 rxq = &priv->rxq_parent;
3975 r = 1;
3976 } else {
3977 rxq = (*priv->rxqs)[0];
3978 r = priv->rxqs_n;
3979 }
3980 /* Iterate only once when RSS is enabled. */
3981 do {
3982 /* Ignore nonexistent RX queues. */
3983 if (rxq == NULL)
3984 continue;
3985 ret = rxq_mac_addrs_add(rxq);
3986 if (!ret && priv->promisc)
3987 ret = rxq_promiscuous_enable(rxq);
3988 if (!ret && priv->allmulti)
3989 ret = rxq_allmulticast_enable(rxq);
3990 if (!ret)
3991 continue;
3992 WARN("%p: QP flow attachment failed: %s",
3993 (void *)dev, strerror(ret));
3994 goto err;
3995 } while ((--r) && ((rxq = (*priv->rxqs)[++i]), i));
3996 ret = priv_dev_link_interrupt_handler_install(priv, dev);
3997 if (ret) {
3998 ERROR("%p: LSC handler install failed",
3999 (void *)dev);
4000 goto err;
4001 }
4002 ret = priv_dev_removal_interrupt_handler_install(priv, dev);
4003 if (ret) {
4004 ERROR("%p: RMV handler install failed",
4005 (void *)dev);
4006 goto err;
4007 }
4008 ret = mlx4_priv_flow_start(priv);
4009 if (ret) {
4010 ERROR("%p: flow start failed: %s",
4011 (void *)dev, strerror(ret));
4012 goto err;
4013 }
4014 priv_unlock(priv);
4015 return 0;
4016 err:
4017 /* Rollback. */
4018 while (i != 0) {
4019 rxq = (*priv->rxqs)[i--];
4020 if (rxq != NULL) {
4021 rxq_allmulticast_disable(rxq);
4022 rxq_promiscuous_disable(rxq);
4023 rxq_mac_addrs_del(rxq);
4024 }
4025 }
4026 priv->started = 0;
4027 priv_unlock(priv);
4028 return -ret;
4029 }
4030
4031 /**
4032 * DPDK callback to stop the device.
4033 *
4034 * Simulate device stop by detaching all configured flows.
4035 *
4036 * @param dev
4037 * Pointer to Ethernet device structure.
4038 */
4039 static void
4040 mlx4_dev_stop(struct rte_eth_dev *dev)
4041 {
4042 struct priv *priv = dev->data->dev_private;
4043 unsigned int i = 0;
4044 unsigned int r;
4045 struct rxq *rxq;
4046
4047 if (mlx4_is_secondary())
4048 return;
4049 priv_lock(priv);
4050 if (!priv->started) {
4051 priv_unlock(priv);
4052 return;
4053 }
4054 DEBUG("%p: detaching flows from all RX queues", (void *)dev);
4055 priv->started = 0;
4056 if (priv->rss) {
4057 rxq = &priv->rxq_parent;
4058 r = 1;
4059 } else {
4060 rxq = (*priv->rxqs)[0];
4061 r = priv->rxqs_n;
4062 }
4063 mlx4_priv_flow_stop(priv);
4064 /* Iterate only once when RSS is enabled. */
4065 do {
4066 /* Ignore nonexistent RX queues. */
4067 if (rxq == NULL)
4068 continue;
4069 rxq_allmulticast_disable(rxq);
4070 rxq_promiscuous_disable(rxq);
4071 rxq_mac_addrs_del(rxq);
4072 } while ((--r) && ((rxq = (*priv->rxqs)[++i]), i));
4073 priv_unlock(priv);
4074 }
4075
4076 /**
4077 * Dummy DPDK callback for TX.
4078 *
4079 * This function is used to temporarily replace the real callback during
4080 * unsafe control operations on the queue, or in case of error.
4081 *
4082 * @param dpdk_txq
4083 * Generic pointer to TX queue structure.
4084 * @param[in] pkts
4085 * Packets to transmit.
4086 * @param pkts_n
4087 * Number of packets in array.
4088 *
4089 * @return
4090 * Number of packets successfully transmitted (<= pkts_n).
4091 */
4092 static uint16_t
4093 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
4094 {
4095 (void)dpdk_txq;
4096 (void)pkts;
4097 (void)pkts_n;
4098 return 0;
4099 }
4100
4101 /**
4102 * Dummy DPDK callback for RX.
4103 *
4104 * This function is used to temporarily replace the real callback during
4105 * unsafe control operations on the queue, or in case of error.
4106 *
4107 * @param dpdk_rxq
4108 * Generic pointer to RX queue structure.
4109 * @param[out] pkts
4110 * Array to store received packets.
4111 * @param pkts_n
4112 * Maximum number of packets in array.
4113 *
4114 * @return
4115 * Number of packets successfully received (<= pkts_n).
4116 */
4117 static uint16_t
4118 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
4119 {
4120 (void)dpdk_rxq;
4121 (void)pkts;
4122 (void)pkts_n;
4123 return 0;
4124 }
4125
4126 static int
4127 priv_dev_interrupt_handler_uninstall(struct priv *, struct rte_eth_dev *);
4128
4129 static int
4130 priv_dev_removal_interrupt_handler_uninstall(struct priv *,
4131 struct rte_eth_dev *);
4132
4133 static int
4134 priv_dev_link_interrupt_handler_uninstall(struct priv *, struct rte_eth_dev *);
4135
4136 /**
4137 * DPDK callback to close the device.
4138 *
4139 * Destroy all queues and objects, free memory.
4140 *
4141 * @param dev
4142 * Pointer to Ethernet device structure.
4143 */
4144 static void
4145 mlx4_dev_close(struct rte_eth_dev *dev)
4146 {
4147 struct priv *priv = mlx4_get_priv(dev);
4148 void *tmp;
4149 unsigned int i;
4150
4151 if (priv == NULL)
4152 return;
4153 priv_lock(priv);
4154 DEBUG("%p: closing device \"%s\"",
4155 (void *)dev,
4156 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
4157 /* Prevent crashes when queues are still in use. This is unfortunately
4158 * still required for DPDK 1.3 because some programs (such as testpmd)
4159 * never release them before closing the device. */
4160 dev->rx_pkt_burst = removed_rx_burst;
4161 dev->tx_pkt_burst = removed_tx_burst;
4162 if (priv->rxqs != NULL) {
4163 /* XXX race condition if mlx4_rx_burst() is still running. */
4164 usleep(1000);
4165 for (i = 0; (i != priv->rxqs_n); ++i) {
4166 tmp = (*priv->rxqs)[i];
4167 if (tmp == NULL)
4168 continue;
4169 (*priv->rxqs)[i] = NULL;
4170 rxq_cleanup(tmp);
4171 rte_free(tmp);
4172 }
4173 priv->rxqs_n = 0;
4174 priv->rxqs = NULL;
4175 }
4176 if (priv->txqs != NULL) {
4177 /* XXX race condition if mlx4_tx_burst() is still running. */
4178 usleep(1000);
4179 for (i = 0; (i != priv->txqs_n); ++i) {
4180 tmp = (*priv->txqs)[i];
4181 if (tmp == NULL)
4182 continue;
4183 (*priv->txqs)[i] = NULL;
4184 txq_cleanup(tmp);
4185 rte_free(tmp);
4186 }
4187 priv->txqs_n = 0;
4188 priv->txqs = NULL;
4189 }
4190 if (priv->rss)
4191 rxq_cleanup(&priv->rxq_parent);
4192 if (priv->pd != NULL) {
4193 assert(priv->ctx != NULL);
4194 claim_zero(ibv_dealloc_pd(priv->pd));
4195 claim_zero(ibv_close_device(priv->ctx));
4196 } else
4197 assert(priv->ctx == NULL);
4198 priv_dev_removal_interrupt_handler_uninstall(priv, dev);
4199 priv_dev_link_interrupt_handler_uninstall(priv, dev);
4200 priv_unlock(priv);
4201 memset(priv, 0, sizeof(*priv));
4202 }
4203
4204 /**
4205 * Change the link state (UP / DOWN).
4206 *
4207 * @param priv
4208 * Pointer to Ethernet device private data.
4209 * @param up
4210 * Nonzero for link up, otherwise link down.
4211 *
4212 * @return
4213 * 0 on success, errno value on failure.
4214 */
4215 static int
4216 priv_set_link(struct priv *priv, int up)
4217 {
4218 struct rte_eth_dev *dev = priv->dev;
4219 int err;
4220 unsigned int i;
4221
4222 if (up) {
4223 err = priv_set_flags(priv, ~IFF_UP, IFF_UP);
4224 if (err)
4225 return err;
4226 for (i = 0; i < priv->rxqs_n; i++)
4227 if ((*priv->rxqs)[i]->sp)
4228 break;
4229 /* Check if an sp queue exists.
4230 * Note: Some old frames might be received.
4231 */
4232 if (i == priv->rxqs_n)
4233 dev->rx_pkt_burst = mlx4_rx_burst;
4234 else
4235 dev->rx_pkt_burst = mlx4_rx_burst_sp;
4236 dev->tx_pkt_burst = mlx4_tx_burst;
4237 } else {
4238 err = priv_set_flags(priv, ~IFF_UP, ~IFF_UP);
4239 if (err)
4240 return err;
4241 dev->rx_pkt_burst = removed_rx_burst;
4242 dev->tx_pkt_burst = removed_tx_burst;
4243 }
4244 return 0;
4245 }
4246
4247 /**
4248 * DPDK callback to bring the link DOWN.
4249 *
4250 * @param dev
4251 * Pointer to Ethernet device structure.
4252 *
4253 * @return
4254 * 0 on success, errno value on failure.
4255 */
4256 static int
4257 mlx4_set_link_down(struct rte_eth_dev *dev)
4258 {
4259 struct priv *priv = dev->data->dev_private;
4260 int err;
4261
4262 priv_lock(priv);
4263 err = priv_set_link(priv, 0);
4264 priv_unlock(priv);
4265 return err;
4266 }
4267
4268 /**
4269 * DPDK callback to bring the link UP.
4270 *
4271 * @param dev
4272 * Pointer to Ethernet device structure.
4273 *
4274 * @return
4275 * 0 on success, errno value on failure.
4276 */
4277 static int
4278 mlx4_set_link_up(struct rte_eth_dev *dev)
4279 {
4280 struct priv *priv = dev->data->dev_private;
4281 int err;
4282
4283 priv_lock(priv);
4284 err = priv_set_link(priv, 1);
4285 priv_unlock(priv);
4286 return err;
4287 }
4288 /**
4289 * DPDK callback to get information about the device.
4290 *
4291 * @param dev
4292 * Pointer to Ethernet device structure.
4293 * @param[out] info
4294 * Info structure output buffer.
4295 */
4296 static void
4297 mlx4_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
4298 {
4299 struct priv *priv = mlx4_get_priv(dev);
4300 unsigned int max;
4301 char ifname[IF_NAMESIZE];
4302
4303 info->pci_dev = RTE_DEV_TO_PCI(dev->device);
4304
4305 if (priv == NULL)
4306 return;
4307 priv_lock(priv);
4308 /* FIXME: we should ask the device for these values. */
4309 info->min_rx_bufsize = 32;
4310 info->max_rx_pktlen = 65536;
4311 /*
4312 * Since we need one CQ per QP, the limit is the minimum number
4313 * between the two values.
4314 */
4315 max = ((priv->device_attr.max_cq > priv->device_attr.max_qp) ?
4316 priv->device_attr.max_qp : priv->device_attr.max_cq);
4317 /* If max >= 65535 then max = 0, max_rx_queues is uint16_t. */
4318 if (max >= 65535)
4319 max = 65535;
4320 info->max_rx_queues = max;
4321 info->max_tx_queues = max;
4322 /* Last array entry is reserved for broadcast. */
4323 info->max_mac_addrs = (elemof(priv->mac) - 1);
4324 info->rx_offload_capa =
4325 (priv->hw_csum ?
4326 (DEV_RX_OFFLOAD_IPV4_CKSUM |
4327 DEV_RX_OFFLOAD_UDP_CKSUM |
4328 DEV_RX_OFFLOAD_TCP_CKSUM) :
4329 0);
4330 info->tx_offload_capa =
4331 (priv->hw_csum ?
4332 (DEV_TX_OFFLOAD_IPV4_CKSUM |
4333 DEV_TX_OFFLOAD_UDP_CKSUM |
4334 DEV_TX_OFFLOAD_TCP_CKSUM) :
4335 0);
4336 if (priv_get_ifname(priv, &ifname) == 0)
4337 info->if_index = if_nametoindex(ifname);
4338 info->speed_capa =
4339 ETH_LINK_SPEED_1G |
4340 ETH_LINK_SPEED_10G |
4341 ETH_LINK_SPEED_20G |
4342 ETH_LINK_SPEED_40G |
4343 ETH_LINK_SPEED_56G;
4344 priv_unlock(priv);
4345 }
4346
4347 static const uint32_t *
4348 mlx4_dev_supported_ptypes_get(struct rte_eth_dev *dev)
4349 {
4350 static const uint32_t ptypes[] = {
4351 /* refers to rxq_cq_to_pkt_type() */
4352 RTE_PTYPE_L3_IPV4,
4353 RTE_PTYPE_L3_IPV6,
4354 RTE_PTYPE_INNER_L3_IPV4,
4355 RTE_PTYPE_INNER_L3_IPV6,
4356 RTE_PTYPE_UNKNOWN
4357 };
4358
4359 if (dev->rx_pkt_burst == mlx4_rx_burst ||
4360 dev->rx_pkt_burst == mlx4_rx_burst_sp)
4361 return ptypes;
4362 return NULL;
4363 }
4364
4365 /**
4366 * DPDK callback to get device statistics.
4367 *
4368 * @param dev
4369 * Pointer to Ethernet device structure.
4370 * @param[out] stats
4371 * Stats structure output buffer.
4372 */
4373 static void
4374 mlx4_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4375 {
4376 struct priv *priv = mlx4_get_priv(dev);
4377 struct rte_eth_stats tmp = {0};
4378 unsigned int i;
4379 unsigned int idx;
4380
4381 if (priv == NULL)
4382 return;
4383 priv_lock(priv);
4384 /* Add software counters. */
4385 for (i = 0; (i != priv->rxqs_n); ++i) {
4386 struct rxq *rxq = (*priv->rxqs)[i];
4387
4388 if (rxq == NULL)
4389 continue;
4390 idx = rxq->stats.idx;
4391 if (idx < RTE_ETHDEV_QUEUE_STAT_CNTRS) {
4392 #ifdef MLX4_PMD_SOFT_COUNTERS
4393 tmp.q_ipackets[idx] += rxq->stats.ipackets;
4394 tmp.q_ibytes[idx] += rxq->stats.ibytes;
4395 #endif
4396 tmp.q_errors[idx] += (rxq->stats.idropped +
4397 rxq->stats.rx_nombuf);
4398 }
4399 #ifdef MLX4_PMD_SOFT_COUNTERS
4400 tmp.ipackets += rxq->stats.ipackets;
4401 tmp.ibytes += rxq->stats.ibytes;
4402 #endif
4403 tmp.ierrors += rxq->stats.idropped;
4404 tmp.rx_nombuf += rxq->stats.rx_nombuf;
4405 }
4406 for (i = 0; (i != priv->txqs_n); ++i) {
4407 struct txq *txq = (*priv->txqs)[i];
4408
4409 if (txq == NULL)
4410 continue;
4411 idx = txq->stats.idx;
4412 if (idx < RTE_ETHDEV_QUEUE_STAT_CNTRS) {
4413 #ifdef MLX4_PMD_SOFT_COUNTERS
4414 tmp.q_opackets[idx] += txq->stats.opackets;
4415 tmp.q_obytes[idx] += txq->stats.obytes;
4416 #endif
4417 tmp.q_errors[idx] += txq->stats.odropped;
4418 }
4419 #ifdef MLX4_PMD_SOFT_COUNTERS
4420 tmp.opackets += txq->stats.opackets;
4421 tmp.obytes += txq->stats.obytes;
4422 #endif
4423 tmp.oerrors += txq->stats.odropped;
4424 }
4425 #ifndef MLX4_PMD_SOFT_COUNTERS
4426 /* FIXME: retrieve and add hardware counters. */
4427 #endif
4428 *stats = tmp;
4429 priv_unlock(priv);
4430 }
4431
4432 /**
4433 * DPDK callback to clear device statistics.
4434 *
4435 * @param dev
4436 * Pointer to Ethernet device structure.
4437 */
4438 static void
4439 mlx4_stats_reset(struct rte_eth_dev *dev)
4440 {
4441 struct priv *priv = mlx4_get_priv(dev);
4442 unsigned int i;
4443 unsigned int idx;
4444
4445 if (priv == NULL)
4446 return;
4447 priv_lock(priv);
4448 for (i = 0; (i != priv->rxqs_n); ++i) {
4449 if ((*priv->rxqs)[i] == NULL)
4450 continue;
4451 idx = (*priv->rxqs)[i]->stats.idx;
4452 (*priv->rxqs)[i]->stats =
4453 (struct mlx4_rxq_stats){ .idx = idx };
4454 }
4455 for (i = 0; (i != priv->txqs_n); ++i) {
4456 if ((*priv->txqs)[i] == NULL)
4457 continue;
4458 idx = (*priv->txqs)[i]->stats.idx;
4459 (*priv->txqs)[i]->stats =
4460 (struct mlx4_txq_stats){ .idx = idx };
4461 }
4462 #ifndef MLX4_PMD_SOFT_COUNTERS
4463 /* FIXME: reset hardware counters. */
4464 #endif
4465 priv_unlock(priv);
4466 }
4467
4468 /**
4469 * DPDK callback to remove a MAC address.
4470 *
4471 * @param dev
4472 * Pointer to Ethernet device structure.
4473 * @param index
4474 * MAC address index.
4475 */
4476 static void
4477 mlx4_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
4478 {
4479 struct priv *priv = dev->data->dev_private;
4480
4481 if (mlx4_is_secondary())
4482 return;
4483 priv_lock(priv);
4484 DEBUG("%p: removing MAC address from index %" PRIu32,
4485 (void *)dev, index);
4486 /* Last array entry is reserved for broadcast. */
4487 if (index >= (elemof(priv->mac) - 1))
4488 goto end;
4489 priv_mac_addr_del(priv, index);
4490 end:
4491 priv_unlock(priv);
4492 }
4493
4494 /**
4495 * DPDK callback to add a MAC address.
4496 *
4497 * @param dev
4498 * Pointer to Ethernet device structure.
4499 * @param mac_addr
4500 * MAC address to register.
4501 * @param index
4502 * MAC address index.
4503 * @param vmdq
4504 * VMDq pool index to associate address with (ignored).
4505 */
4506 static int
4507 mlx4_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4508 uint32_t index, uint32_t vmdq)
4509 {
4510 struct priv *priv = dev->data->dev_private;
4511 int re;
4512
4513 if (mlx4_is_secondary())
4514 return -ENOTSUP;
4515 (void)vmdq;
4516 priv_lock(priv);
4517 DEBUG("%p: adding MAC address at index %" PRIu32,
4518 (void *)dev, index);
4519 /* Last array entry is reserved for broadcast. */
4520 if (index >= (elemof(priv->mac) - 1)) {
4521 re = EINVAL;
4522 goto end;
4523 }
4524 re = priv_mac_addr_add(priv, index,
4525 (const uint8_t (*)[ETHER_ADDR_LEN])
4526 mac_addr->addr_bytes);
4527 end:
4528 priv_unlock(priv);
4529 return -re;
4530 }
4531
4532 /**
4533 * DPDK callback to set the primary MAC address.
4534 *
4535 * @param dev
4536 * Pointer to Ethernet device structure.
4537 * @param mac_addr
4538 * MAC address to register.
4539 */
4540 static void
4541 mlx4_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
4542 {
4543 DEBUG("%p: setting primary MAC address", (void *)dev);
4544 mlx4_mac_addr_remove(dev, 0);
4545 mlx4_mac_addr_add(dev, mac_addr, 0, 0);
4546 }
4547
4548 /**
4549 * DPDK callback to enable promiscuous mode.
4550 *
4551 * @param dev
4552 * Pointer to Ethernet device structure.
4553 */
4554 static void
4555 mlx4_promiscuous_enable(struct rte_eth_dev *dev)
4556 {
4557 struct priv *priv = dev->data->dev_private;
4558 unsigned int i;
4559 int ret;
4560
4561 if (mlx4_is_secondary())
4562 return;
4563 priv_lock(priv);
4564 if (priv->promisc) {
4565 priv_unlock(priv);
4566 return;
4567 }
4568 /* If device isn't started, this is all we need to do. */
4569 if (!priv->started)
4570 goto end;
4571 if (priv->rss) {
4572 ret = rxq_promiscuous_enable(&priv->rxq_parent);
4573 if (ret) {
4574 priv_unlock(priv);
4575 return;
4576 }
4577 goto end;
4578 }
4579 for (i = 0; (i != priv->rxqs_n); ++i) {
4580 if ((*priv->rxqs)[i] == NULL)
4581 continue;
4582 ret = rxq_promiscuous_enable((*priv->rxqs)[i]);
4583 if (!ret)
4584 continue;
4585 /* Failure, rollback. */
4586 while (i != 0)
4587 if ((*priv->rxqs)[--i] != NULL)
4588 rxq_promiscuous_disable((*priv->rxqs)[i]);
4589 priv_unlock(priv);
4590 return;
4591 }
4592 end:
4593 priv->promisc = 1;
4594 priv_unlock(priv);
4595 }
4596
4597 /**
4598 * DPDK callback to disable promiscuous mode.
4599 *
4600 * @param dev
4601 * Pointer to Ethernet device structure.
4602 */
4603 static void
4604 mlx4_promiscuous_disable(struct rte_eth_dev *dev)
4605 {
4606 struct priv *priv = dev->data->dev_private;
4607 unsigned int i;
4608
4609 if (mlx4_is_secondary())
4610 return;
4611 priv_lock(priv);
4612 if (!priv->promisc) {
4613 priv_unlock(priv);
4614 return;
4615 }
4616 if (priv->rss) {
4617 rxq_promiscuous_disable(&priv->rxq_parent);
4618 goto end;
4619 }
4620 for (i = 0; (i != priv->rxqs_n); ++i)
4621 if ((*priv->rxqs)[i] != NULL)
4622 rxq_promiscuous_disable((*priv->rxqs)[i]);
4623 end:
4624 priv->promisc = 0;
4625 priv_unlock(priv);
4626 }
4627
4628 /**
4629 * DPDK callback to enable allmulti mode.
4630 *
4631 * @param dev
4632 * Pointer to Ethernet device structure.
4633 */
4634 static void
4635 mlx4_allmulticast_enable(struct rte_eth_dev *dev)
4636 {
4637 struct priv *priv = dev->data->dev_private;
4638 unsigned int i;
4639 int ret;
4640
4641 if (mlx4_is_secondary())
4642 return;
4643 priv_lock(priv);
4644 if (priv->allmulti) {
4645 priv_unlock(priv);
4646 return;
4647 }
4648 /* If device isn't started, this is all we need to do. */
4649 if (!priv->started)
4650 goto end;
4651 if (priv->rss) {
4652 ret = rxq_allmulticast_enable(&priv->rxq_parent);
4653 if (ret) {
4654 priv_unlock(priv);
4655 return;
4656 }
4657 goto end;
4658 }
4659 for (i = 0; (i != priv->rxqs_n); ++i) {
4660 if ((*priv->rxqs)[i] == NULL)
4661 continue;
4662 ret = rxq_allmulticast_enable((*priv->rxqs)[i]);
4663 if (!ret)
4664 continue;
4665 /* Failure, rollback. */
4666 while (i != 0)
4667 if ((*priv->rxqs)[--i] != NULL)
4668 rxq_allmulticast_disable((*priv->rxqs)[i]);
4669 priv_unlock(priv);
4670 return;
4671 }
4672 end:
4673 priv->allmulti = 1;
4674 priv_unlock(priv);
4675 }
4676
4677 /**
4678 * DPDK callback to disable allmulti mode.
4679 *
4680 * @param dev
4681 * Pointer to Ethernet device structure.
4682 */
4683 static void
4684 mlx4_allmulticast_disable(struct rte_eth_dev *dev)
4685 {
4686 struct priv *priv = dev->data->dev_private;
4687 unsigned int i;
4688
4689 if (mlx4_is_secondary())
4690 return;
4691 priv_lock(priv);
4692 if (!priv->allmulti) {
4693 priv_unlock(priv);
4694 return;
4695 }
4696 if (priv->rss) {
4697 rxq_allmulticast_disable(&priv->rxq_parent);
4698 goto end;
4699 }
4700 for (i = 0; (i != priv->rxqs_n); ++i)
4701 if ((*priv->rxqs)[i] != NULL)
4702 rxq_allmulticast_disable((*priv->rxqs)[i]);
4703 end:
4704 priv->allmulti = 0;
4705 priv_unlock(priv);
4706 }
4707
4708 /**
4709 * DPDK callback to retrieve physical link information.
4710 *
4711 * @param dev
4712 * Pointer to Ethernet device structure.
4713 * @param wait_to_complete
4714 * Wait for request completion (ignored).
4715 */
4716 static int
4717 mlx4_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4718 {
4719 const struct priv *priv = mlx4_get_priv(dev);
4720 struct ethtool_cmd edata = {
4721 .cmd = ETHTOOL_GSET
4722 };
4723 struct ifreq ifr;
4724 struct rte_eth_link dev_link;
4725 int link_speed = 0;
4726
4727 /* priv_lock() is not taken to allow concurrent calls. */
4728
4729 if (priv == NULL)
4730 return -EINVAL;
4731 (void)wait_to_complete;
4732 if (priv_ifreq(priv, SIOCGIFFLAGS, &ifr)) {
4733 WARN("ioctl(SIOCGIFFLAGS) failed: %s", strerror(errno));
4734 return -1;
4735 }
4736 memset(&dev_link, 0, sizeof(dev_link));
4737 dev_link.link_status = ((ifr.ifr_flags & IFF_UP) &&
4738 (ifr.ifr_flags & IFF_RUNNING));
4739 ifr.ifr_data = (void *)&edata;
4740 if (priv_ifreq(priv, SIOCETHTOOL, &ifr)) {
4741 WARN("ioctl(SIOCETHTOOL, ETHTOOL_GSET) failed: %s",
4742 strerror(errno));
4743 return -1;
4744 }
4745 link_speed = ethtool_cmd_speed(&edata);
4746 if (link_speed == -1)
4747 dev_link.link_speed = 0;
4748 else
4749 dev_link.link_speed = link_speed;
4750 dev_link.link_duplex = ((edata.duplex == DUPLEX_HALF) ?
4751 ETH_LINK_HALF_DUPLEX : ETH_LINK_FULL_DUPLEX);
4752 dev_link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4753 ETH_LINK_SPEED_FIXED);
4754 if (memcmp(&dev_link, &dev->data->dev_link, sizeof(dev_link))) {
4755 /* Link status changed. */
4756 dev->data->dev_link = dev_link;
4757 return 0;
4758 }
4759 /* Link status is still the same. */
4760 return -1;
4761 }
4762
4763 static int
4764 mlx4_ibv_device_to_pci_addr(const struct ibv_device *device,
4765 struct rte_pci_addr *pci_addr);
4766
4767 /**
4768 * DPDK callback to change the MTU.
4769 *
4770 * Setting the MTU affects hardware MRU (packets larger than the MTU cannot be
4771 * received). Use this as a hint to enable/disable scattered packets support
4772 * and improve performance when not needed.
4773 * Since failure is not an option, reconfiguring queues on the fly is not
4774 * recommended.
4775 *
4776 * @param dev
4777 * Pointer to Ethernet device structure.
4778 * @param in_mtu
4779 * New MTU.
4780 *
4781 * @return
4782 * 0 on success, negative errno value on failure.
4783 */
4784 static int
4785 mlx4_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4786 {
4787 struct priv *priv = dev->data->dev_private;
4788 int ret = 0;
4789 unsigned int i;
4790 uint16_t (*rx_func)(void *, struct rte_mbuf **, uint16_t) =
4791 mlx4_rx_burst;
4792
4793 if (mlx4_is_secondary())
4794 return -E_RTE_SECONDARY;
4795 priv_lock(priv);
4796 /* Set kernel interface MTU first. */
4797 if (priv_set_mtu(priv, mtu)) {
4798 ret = errno;
4799 WARN("cannot set port %u MTU to %u: %s", priv->port, mtu,
4800 strerror(ret));
4801 goto out;
4802 } else
4803 DEBUG("adapter port %u MTU set to %u", priv->port, mtu);
4804 priv->mtu = mtu;
4805 /* Temporarily replace RX handler with a fake one, assuming it has not
4806 * been copied elsewhere. */
4807 dev->rx_pkt_burst = removed_rx_burst;
4808 /* Make sure everyone has left mlx4_rx_burst() and uses
4809 * removed_rx_burst() instead. */
4810 rte_wmb();
4811 usleep(1000);
4812 /* Reconfigure each RX queue. */
4813 for (i = 0; (i != priv->rxqs_n); ++i) {
4814 struct rxq *rxq = (*priv->rxqs)[i];
4815 unsigned int max_frame_len;
4816
4817 if (rxq == NULL)
4818 continue;
4819 /* Calculate new maximum frame length according to MTU. */
4820 max_frame_len = (priv->mtu + ETHER_HDR_LEN +
4821 (ETHER_MAX_VLAN_FRAME_LEN - ETHER_MAX_LEN));
4822 /* Provide new values to rxq_setup(). */
4823 dev->data->dev_conf.rxmode.jumbo_frame =
4824 (max_frame_len > ETHER_MAX_LEN);
4825 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame_len;
4826 ret = rxq_rehash(dev, rxq);
4827 if (ret) {
4828 /* Force SP RX if that queue requires it and abort. */
4829 if (rxq->sp)
4830 rx_func = mlx4_rx_burst_sp;
4831 break;
4832 }
4833 /* Reenable non-RSS queue attributes. No need to check
4834 * for errors at this stage. */
4835 if (!priv->rss) {
4836 rxq_mac_addrs_add(rxq);
4837 if (priv->promisc)
4838 rxq_promiscuous_enable(rxq);
4839 if (priv->allmulti)
4840 rxq_allmulticast_enable(rxq);
4841 }
4842 /* Scattered burst function takes priority. */
4843 if (rxq->sp)
4844 rx_func = mlx4_rx_burst_sp;
4845 }
4846 /* Burst functions can now be called again. */
4847 rte_wmb();
4848 dev->rx_pkt_burst = rx_func;
4849 out:
4850 priv_unlock(priv);
4851 assert(ret >= 0);
4852 return -ret;
4853 }
4854
4855 /**
4856 * DPDK callback to get flow control status.
4857 *
4858 * @param dev
4859 * Pointer to Ethernet device structure.
4860 * @param[out] fc_conf
4861 * Flow control output buffer.
4862 *
4863 * @return
4864 * 0 on success, negative errno value on failure.
4865 */
4866 static int
4867 mlx4_dev_get_flow_ctrl(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4868 {
4869 struct priv *priv = dev->data->dev_private;
4870 struct ifreq ifr;
4871 struct ethtool_pauseparam ethpause = {
4872 .cmd = ETHTOOL_GPAUSEPARAM
4873 };
4874 int ret;
4875
4876 if (mlx4_is_secondary())
4877 return -E_RTE_SECONDARY;
4878 ifr.ifr_data = (void *)&ethpause;
4879 priv_lock(priv);
4880 if (priv_ifreq(priv, SIOCETHTOOL, &ifr)) {
4881 ret = errno;
4882 WARN("ioctl(SIOCETHTOOL, ETHTOOL_GPAUSEPARAM)"
4883 " failed: %s",
4884 strerror(ret));
4885 goto out;
4886 }
4887
4888 fc_conf->autoneg = ethpause.autoneg;
4889 if (ethpause.rx_pause && ethpause.tx_pause)
4890 fc_conf->mode = RTE_FC_FULL;
4891 else if (ethpause.rx_pause)
4892 fc_conf->mode = RTE_FC_RX_PAUSE;
4893 else if (ethpause.tx_pause)
4894 fc_conf->mode = RTE_FC_TX_PAUSE;
4895 else
4896 fc_conf->mode = RTE_FC_NONE;
4897 ret = 0;
4898
4899 out:
4900 priv_unlock(priv);
4901 assert(ret >= 0);
4902 return -ret;
4903 }
4904
4905 /**
4906 * DPDK callback to modify flow control parameters.
4907 *
4908 * @param dev
4909 * Pointer to Ethernet device structure.
4910 * @param[in] fc_conf
4911 * Flow control parameters.
4912 *
4913 * @return
4914 * 0 on success, negative errno value on failure.
4915 */
4916 static int
4917 mlx4_dev_set_flow_ctrl(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4918 {
4919 struct priv *priv = dev->data->dev_private;
4920 struct ifreq ifr;
4921 struct ethtool_pauseparam ethpause = {
4922 .cmd = ETHTOOL_SPAUSEPARAM
4923 };
4924 int ret;
4925
4926 if (mlx4_is_secondary())
4927 return -E_RTE_SECONDARY;
4928 ifr.ifr_data = (void *)&ethpause;
4929 ethpause.autoneg = fc_conf->autoneg;
4930 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
4931 (fc_conf->mode & RTE_FC_RX_PAUSE))
4932 ethpause.rx_pause = 1;
4933 else
4934 ethpause.rx_pause = 0;
4935
4936 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
4937 (fc_conf->mode & RTE_FC_TX_PAUSE))
4938 ethpause.tx_pause = 1;
4939 else
4940 ethpause.tx_pause = 0;
4941
4942 priv_lock(priv);
4943 if (priv_ifreq(priv, SIOCETHTOOL, &ifr)) {
4944 ret = errno;
4945 WARN("ioctl(SIOCETHTOOL, ETHTOOL_SPAUSEPARAM)"
4946 " failed: %s",
4947 strerror(ret));
4948 goto out;
4949 }
4950 ret = 0;
4951
4952 out:
4953 priv_unlock(priv);
4954 assert(ret >= 0);
4955 return -ret;
4956 }
4957
4958 /**
4959 * Configure a VLAN filter.
4960 *
4961 * @param dev
4962 * Pointer to Ethernet device structure.
4963 * @param vlan_id
4964 * VLAN ID to filter.
4965 * @param on
4966 * Toggle filter.
4967 *
4968 * @return
4969 * 0 on success, errno value on failure.
4970 */
4971 static int
4972 vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4973 {
4974 struct priv *priv = dev->data->dev_private;
4975 unsigned int i;
4976 unsigned int j = -1;
4977
4978 DEBUG("%p: %s VLAN filter ID %" PRIu16,
4979 (void *)dev, (on ? "enable" : "disable"), vlan_id);
4980 for (i = 0; (i != elemof(priv->vlan_filter)); ++i) {
4981 if (!priv->vlan_filter[i].enabled) {
4982 /* Unused index, remember it. */
4983 j = i;
4984 continue;
4985 }
4986 if (priv->vlan_filter[i].id != vlan_id)
4987 continue;
4988 /* This VLAN ID is already known, use its index. */
4989 j = i;
4990 break;
4991 }
4992 /* Check if there's room for another VLAN filter. */
4993 if (j == (unsigned int)-1)
4994 return ENOMEM;
4995 /*
4996 * VLAN filters apply to all configured MAC addresses, flow
4997 * specifications must be reconfigured accordingly.
4998 */
4999 priv->vlan_filter[j].id = vlan_id;
5000 if ((on) && (!priv->vlan_filter[j].enabled)) {
5001 /*
5002 * Filter is disabled, enable it.
5003 * Rehashing flows in all RX queues is necessary.
5004 */
5005 if (priv->rss)
5006 rxq_mac_addrs_del(&priv->rxq_parent);
5007 else
5008 for (i = 0; (i != priv->rxqs_n); ++i)
5009 if ((*priv->rxqs)[i] != NULL)
5010 rxq_mac_addrs_del((*priv->rxqs)[i]);
5011 priv->vlan_filter[j].enabled = 1;
5012 if (priv->started) {
5013 if (priv->rss)
5014 rxq_mac_addrs_add(&priv->rxq_parent);
5015 else
5016 for (i = 0; (i != priv->rxqs_n); ++i) {
5017 if ((*priv->rxqs)[i] == NULL)
5018 continue;
5019 rxq_mac_addrs_add((*priv->rxqs)[i]);
5020 }
5021 }
5022 } else if ((!on) && (priv->vlan_filter[j].enabled)) {
5023 /*
5024 * Filter is enabled, disable it.
5025 * Rehashing flows in all RX queues is necessary.
5026 */
5027 if (priv->rss)
5028 rxq_mac_addrs_del(&priv->rxq_parent);
5029 else
5030 for (i = 0; (i != priv->rxqs_n); ++i)
5031 if ((*priv->rxqs)[i] != NULL)
5032 rxq_mac_addrs_del((*priv->rxqs)[i]);
5033 priv->vlan_filter[j].enabled = 0;
5034 if (priv->started) {
5035 if (priv->rss)
5036 rxq_mac_addrs_add(&priv->rxq_parent);
5037 else
5038 for (i = 0; (i != priv->rxqs_n); ++i) {
5039 if ((*priv->rxqs)[i] == NULL)
5040 continue;
5041 rxq_mac_addrs_add((*priv->rxqs)[i]);
5042 }
5043 }
5044 }
5045 return 0;
5046 }
5047
5048 /**
5049 * DPDK callback to configure a VLAN filter.
5050 *
5051 * @param dev
5052 * Pointer to Ethernet device structure.
5053 * @param vlan_id
5054 * VLAN ID to filter.
5055 * @param on
5056 * Toggle filter.
5057 *
5058 * @return
5059 * 0 on success, negative errno value on failure.
5060 */
5061 static int
5062 mlx4_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5063 {
5064 struct priv *priv = dev->data->dev_private;
5065 int ret;
5066
5067 if (mlx4_is_secondary())
5068 return -E_RTE_SECONDARY;
5069 priv_lock(priv);
5070 ret = vlan_filter_set(dev, vlan_id, on);
5071 priv_unlock(priv);
5072 assert(ret >= 0);
5073 return -ret;
5074 }
5075
5076 const struct rte_flow_ops mlx4_flow_ops = {
5077 .validate = mlx4_flow_validate,
5078 .create = mlx4_flow_create,
5079 .destroy = mlx4_flow_destroy,
5080 .flush = mlx4_flow_flush,
5081 .query = NULL,
5082 };
5083
5084 /**
5085 * Manage filter operations.
5086 *
5087 * @param dev
5088 * Pointer to Ethernet device structure.
5089 * @param filter_type
5090 * Filter type.
5091 * @param filter_op
5092 * Operation to perform.
5093 * @param arg
5094 * Pointer to operation-specific structure.
5095 *
5096 * @return
5097 * 0 on success, negative errno value on failure.
5098 */
5099 static int
5100 mlx4_dev_filter_ctrl(struct rte_eth_dev *dev,
5101 enum rte_filter_type filter_type,
5102 enum rte_filter_op filter_op,
5103 void *arg)
5104 {
5105 int ret = EINVAL;
5106
5107 switch (filter_type) {
5108 case RTE_ETH_FILTER_GENERIC:
5109 if (filter_op != RTE_ETH_FILTER_GET)
5110 return -EINVAL;
5111 *(const void **)arg = &mlx4_flow_ops;
5112 return 0;
5113 case RTE_ETH_FILTER_FDIR:
5114 DEBUG("%p: filter type FDIR is not supported by this PMD",
5115 (void *)dev);
5116 break;
5117 default:
5118 ERROR("%p: filter type (%d) not supported",
5119 (void *)dev, filter_type);
5120 break;
5121 }
5122 return -ret;
5123 }
5124
5125 static const struct eth_dev_ops mlx4_dev_ops = {
5126 .dev_configure = mlx4_dev_configure,
5127 .dev_start = mlx4_dev_start,
5128 .dev_stop = mlx4_dev_stop,
5129 .dev_set_link_down = mlx4_set_link_down,
5130 .dev_set_link_up = mlx4_set_link_up,
5131 .dev_close = mlx4_dev_close,
5132 .promiscuous_enable = mlx4_promiscuous_enable,
5133 .promiscuous_disable = mlx4_promiscuous_disable,
5134 .allmulticast_enable = mlx4_allmulticast_enable,
5135 .allmulticast_disable = mlx4_allmulticast_disable,
5136 .link_update = mlx4_link_update,
5137 .stats_get = mlx4_stats_get,
5138 .stats_reset = mlx4_stats_reset,
5139 .queue_stats_mapping_set = NULL,
5140 .dev_infos_get = mlx4_dev_infos_get,
5141 .dev_supported_ptypes_get = mlx4_dev_supported_ptypes_get,
5142 .vlan_filter_set = mlx4_vlan_filter_set,
5143 .vlan_tpid_set = NULL,
5144 .vlan_strip_queue_set = NULL,
5145 .vlan_offload_set = NULL,
5146 .rx_queue_setup = mlx4_rx_queue_setup,
5147 .tx_queue_setup = mlx4_tx_queue_setup,
5148 .rx_queue_release = mlx4_rx_queue_release,
5149 .tx_queue_release = mlx4_tx_queue_release,
5150 .dev_led_on = NULL,
5151 .dev_led_off = NULL,
5152 .flow_ctrl_get = mlx4_dev_get_flow_ctrl,
5153 .flow_ctrl_set = mlx4_dev_set_flow_ctrl,
5154 .priority_flow_ctrl_set = NULL,
5155 .mac_addr_remove = mlx4_mac_addr_remove,
5156 .mac_addr_add = mlx4_mac_addr_add,
5157 .mac_addr_set = mlx4_mac_addr_set,
5158 .mtu_set = mlx4_dev_set_mtu,
5159 .filter_ctrl = mlx4_dev_filter_ctrl,
5160 };
5161
5162 /**
5163 * Get PCI information from struct ibv_device.
5164 *
5165 * @param device
5166 * Pointer to Ethernet device structure.
5167 * @param[out] pci_addr
5168 * PCI bus address output buffer.
5169 *
5170 * @return
5171 * 0 on success, -1 on failure and errno is set.
5172 */
5173 static int
5174 mlx4_ibv_device_to_pci_addr(const struct ibv_device *device,
5175 struct rte_pci_addr *pci_addr)
5176 {
5177 FILE *file;
5178 char line[32];
5179 MKSTR(path, "%s/device/uevent", device->ibdev_path);
5180
5181 file = fopen(path, "rb");
5182 if (file == NULL)
5183 return -1;
5184 while (fgets(line, sizeof(line), file) == line) {
5185 size_t len = strlen(line);
5186 int ret;
5187
5188 /* Truncate long lines. */
5189 if (len == (sizeof(line) - 1))
5190 while (line[(len - 1)] != '\n') {
5191 ret = fgetc(file);
5192 if (ret == EOF)
5193 break;
5194 line[(len - 1)] = ret;
5195 }
5196 /* Extract information. */
5197 if (sscanf(line,
5198 "PCI_SLOT_NAME="
5199 "%" SCNx16 ":%" SCNx8 ":%" SCNx8 ".%" SCNx8 "\n",
5200 &pci_addr->domain,
5201 &pci_addr->bus,
5202 &pci_addr->devid,
5203 &pci_addr->function) == 4) {
5204 ret = 0;
5205 break;
5206 }
5207 }
5208 fclose(file);
5209 return 0;
5210 }
5211
5212 /**
5213 * Get MAC address by querying netdevice.
5214 *
5215 * @param[in] priv
5216 * struct priv for the requested device.
5217 * @param[out] mac
5218 * MAC address output buffer.
5219 *
5220 * @return
5221 * 0 on success, -1 on failure and errno is set.
5222 */
5223 static int
5224 priv_get_mac(struct priv *priv, uint8_t (*mac)[ETHER_ADDR_LEN])
5225 {
5226 struct ifreq request;
5227
5228 if (priv_ifreq(priv, SIOCGIFHWADDR, &request))
5229 return -1;
5230 memcpy(mac, request.ifr_hwaddr.sa_data, ETHER_ADDR_LEN);
5231 return 0;
5232 }
5233
5234 /* Support up to 32 adapters. */
5235 static struct {
5236 struct rte_pci_addr pci_addr; /* associated PCI address */
5237 uint32_t ports; /* physical ports bitfield. */
5238 } mlx4_dev[32];
5239
5240 /**
5241 * Get device index in mlx4_dev[] from PCI bus address.
5242 *
5243 * @param[in] pci_addr
5244 * PCI bus address to look for.
5245 *
5246 * @return
5247 * mlx4_dev[] index on success, -1 on failure.
5248 */
5249 static int
5250 mlx4_dev_idx(struct rte_pci_addr *pci_addr)
5251 {
5252 unsigned int i;
5253 int ret = -1;
5254
5255 assert(pci_addr != NULL);
5256 for (i = 0; (i != elemof(mlx4_dev)); ++i) {
5257 if ((mlx4_dev[i].pci_addr.domain == pci_addr->domain) &&
5258 (mlx4_dev[i].pci_addr.bus == pci_addr->bus) &&
5259 (mlx4_dev[i].pci_addr.devid == pci_addr->devid) &&
5260 (mlx4_dev[i].pci_addr.function == pci_addr->function))
5261 return i;
5262 if ((mlx4_dev[i].ports == 0) && (ret == -1))
5263 ret = i;
5264 }
5265 return ret;
5266 }
5267
5268 /**
5269 * Retrieve integer value from environment variable.
5270 *
5271 * @param[in] name
5272 * Environment variable name.
5273 *
5274 * @return
5275 * Integer value, 0 if the variable is not set.
5276 */
5277 static int
5278 mlx4_getenv_int(const char *name)
5279 {
5280 const char *val = getenv(name);
5281
5282 if (val == NULL)
5283 return 0;
5284 return atoi(val);
5285 }
5286
5287 static void
5288 mlx4_dev_link_status_handler(void *);
5289 static void
5290 mlx4_dev_interrupt_handler(void *);
5291
5292 /**
5293 * Link/device status handler.
5294 *
5295 * @param priv
5296 * Pointer to private structure.
5297 * @param dev
5298 * Pointer to the rte_eth_dev structure.
5299 * @param events
5300 * Pointer to event flags holder.
5301 *
5302 * @return
5303 * Number of events
5304 */
5305 static int
5306 priv_dev_status_handler(struct priv *priv, struct rte_eth_dev *dev,
5307 uint32_t *events)
5308 {
5309 struct ibv_async_event event;
5310 int port_change = 0;
5311 int ret = 0;
5312
5313 *events = 0;
5314 /* Read all message and acknowledge them. */
5315 for (;;) {
5316 if (ibv_get_async_event(priv->ctx, &event))
5317 break;
5318 if ((event.event_type == IBV_EVENT_PORT_ACTIVE ||
5319 event.event_type == IBV_EVENT_PORT_ERR) &&
5320 (priv->intr_conf.lsc == 1)) {
5321 port_change = 1;
5322 ret++;
5323 } else if (event.event_type == IBV_EVENT_DEVICE_FATAL &&
5324 priv->intr_conf.rmv == 1) {
5325 *events |= (1 << RTE_ETH_EVENT_INTR_RMV);
5326 ret++;
5327 } else
5328 DEBUG("event type %d on port %d not handled",
5329 event.event_type, event.element.port_num);
5330 ibv_ack_async_event(&event);
5331 }
5332
5333 if (port_change ^ priv->pending_alarm) {
5334 struct rte_eth_link *link = &dev->data->dev_link;
5335
5336 priv->pending_alarm = 0;
5337 mlx4_link_update(dev, 0);
5338 if (((link->link_speed == 0) && link->link_status) ||
5339 ((link->link_speed != 0) && !link->link_status)) {
5340 /* Inconsistent status, check again later. */
5341 priv->pending_alarm = 1;
5342 rte_eal_alarm_set(MLX4_ALARM_TIMEOUT_US,
5343 mlx4_dev_link_status_handler,
5344 dev);
5345 } else {
5346 *events |= (1 << RTE_ETH_EVENT_INTR_LSC);
5347 }
5348 }
5349 return ret;
5350 }
5351
5352 /**
5353 * Handle delayed link status event.
5354 *
5355 * @param arg
5356 * Registered argument.
5357 */
5358 static void
5359 mlx4_dev_link_status_handler(void *arg)
5360 {
5361 struct rte_eth_dev *dev = arg;
5362 struct priv *priv = dev->data->dev_private;
5363 uint32_t events;
5364 int ret;
5365
5366 priv_lock(priv);
5367 assert(priv->pending_alarm == 1);
5368 ret = priv_dev_status_handler(priv, dev, &events);
5369 priv_unlock(priv);
5370 if (ret > 0 && events & (1 << RTE_ETH_EVENT_INTR_LSC))
5371 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
5372 }
5373
5374 /**
5375 * Handle interrupts from the NIC.
5376 *
5377 * @param[in] intr_handle
5378 * Interrupt handler.
5379 * @param cb_arg
5380 * Callback argument.
5381 */
5382 static void
5383 mlx4_dev_interrupt_handler(void *cb_arg)
5384 {
5385 struct rte_eth_dev *dev = cb_arg;
5386 struct priv *priv = dev->data->dev_private;
5387 int ret;
5388 uint32_t ev;
5389 int i;
5390
5391 priv_lock(priv);
5392 ret = priv_dev_status_handler(priv, dev, &ev);
5393 priv_unlock(priv);
5394 if (ret > 0) {
5395 for (i = RTE_ETH_EVENT_UNKNOWN;
5396 i < RTE_ETH_EVENT_MAX;
5397 i++) {
5398 if (ev & (1 << i)) {
5399 ev &= ~(1 << i);
5400 _rte_eth_dev_callback_process(dev, i, NULL);
5401 ret--;
5402 }
5403 }
5404 if (ret)
5405 WARN("%d event%s not processed", ret,
5406 (ret > 1 ? "s were" : " was"));
5407 }
5408 }
5409
5410 /**
5411 * Uninstall interrupt handler.
5412 *
5413 * @param priv
5414 * Pointer to private structure.
5415 * @param dev
5416 * Pointer to the rte_eth_dev structure.
5417 * @return
5418 * 0 on success, negative errno value on failure.
5419 */
5420 static int
5421 priv_dev_interrupt_handler_uninstall(struct priv *priv, struct rte_eth_dev *dev)
5422 {
5423 int ret;
5424
5425 if (priv->intr_conf.lsc ||
5426 priv->intr_conf.rmv)
5427 return 0;
5428 ret = rte_intr_callback_unregister(&priv->intr_handle,
5429 mlx4_dev_interrupt_handler,
5430 dev);
5431 if (ret < 0) {
5432 ERROR("rte_intr_callback_unregister failed with %d"
5433 "%s%s%s", ret,
5434 (errno ? " (errno: " : ""),
5435 (errno ? strerror(errno) : ""),
5436 (errno ? ")" : ""));
5437 }
5438 priv->intr_handle.fd = 0;
5439 priv->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
5440 return ret;
5441 }
5442
5443 /**
5444 * Install interrupt handler.
5445 *
5446 * @param priv
5447 * Pointer to private structure.
5448 * @param dev
5449 * Pointer to the rte_eth_dev structure.
5450 * @return
5451 * 0 on success, negative errno value on failure.
5452 */
5453 static int
5454 priv_dev_interrupt_handler_install(struct priv *priv,
5455 struct rte_eth_dev *dev)
5456 {
5457 int flags;
5458 int rc;
5459
5460 /* Check whether the interrupt handler has already been installed
5461 * for either type of interrupt
5462 */
5463 if (priv->intr_conf.lsc &&
5464 priv->intr_conf.rmv &&
5465 priv->intr_handle.fd)
5466 return 0;
5467 assert(priv->ctx->async_fd > 0);
5468 flags = fcntl(priv->ctx->async_fd, F_GETFL);
5469 rc = fcntl(priv->ctx->async_fd, F_SETFL, flags | O_NONBLOCK);
5470 if (rc < 0) {
5471 INFO("failed to change file descriptor async event queue");
5472 dev->data->dev_conf.intr_conf.lsc = 0;
5473 dev->data->dev_conf.intr_conf.rmv = 0;
5474 return -errno;
5475 } else {
5476 priv->intr_handle.fd = priv->ctx->async_fd;
5477 priv->intr_handle.type = RTE_INTR_HANDLE_EXT;
5478 rc = rte_intr_callback_register(&priv->intr_handle,
5479 mlx4_dev_interrupt_handler,
5480 dev);
5481 if (rc) {
5482 ERROR("rte_intr_callback_register failed "
5483 " (errno: %s)", strerror(errno));
5484 return rc;
5485 }
5486 }
5487 return 0;
5488 }
5489
5490 /**
5491 * Uninstall interrupt handler.
5492 *
5493 * @param priv
5494 * Pointer to private structure.
5495 * @param dev
5496 * Pointer to the rte_eth_dev structure.
5497 * @return
5498 * 0 on success, negative value on error.
5499 */
5500 static int
5501 priv_dev_removal_interrupt_handler_uninstall(struct priv *priv,
5502 struct rte_eth_dev *dev)
5503 {
5504 if (dev->data->dev_conf.intr_conf.rmv) {
5505 priv->intr_conf.rmv = 0;
5506 return priv_dev_interrupt_handler_uninstall(priv, dev);
5507 }
5508 return 0;
5509 }
5510
5511 /**
5512 * Uninstall interrupt handler.
5513 *
5514 * @param priv
5515 * Pointer to private structure.
5516 * @param dev
5517 * Pointer to the rte_eth_dev structure.
5518 * @return
5519 * 0 on success, negative value on error,
5520 */
5521 static int
5522 priv_dev_link_interrupt_handler_uninstall(struct priv *priv,
5523 struct rte_eth_dev *dev)
5524 {
5525 int ret = 0;
5526
5527 if (dev->data->dev_conf.intr_conf.lsc) {
5528 priv->intr_conf.lsc = 0;
5529 ret = priv_dev_interrupt_handler_uninstall(priv, dev);
5530 if (ret)
5531 return ret;
5532 }
5533 if (priv->pending_alarm)
5534 if (rte_eal_alarm_cancel(mlx4_dev_link_status_handler,
5535 dev)) {
5536 ERROR("rte_eal_alarm_cancel failed "
5537 " (errno: %s)", strerror(rte_errno));
5538 return -rte_errno;
5539 }
5540 priv->pending_alarm = 0;
5541 return 0;
5542 }
5543
5544 /**
5545 * Install link interrupt handler.
5546 *
5547 * @param priv
5548 * Pointer to private structure.
5549 * @param dev
5550 * Pointer to the rte_eth_dev structure.
5551 * @return
5552 * 0 on success, negative value on error.
5553 */
5554 static int
5555 priv_dev_link_interrupt_handler_install(struct priv *priv,
5556 struct rte_eth_dev *dev)
5557 {
5558 int ret;
5559
5560 if (dev->data->dev_conf.intr_conf.lsc) {
5561 ret = priv_dev_interrupt_handler_install(priv, dev);
5562 if (ret)
5563 return ret;
5564 priv->intr_conf.lsc = 1;
5565 }
5566 return 0;
5567 }
5568
5569 /**
5570 * Install removal interrupt handler.
5571 *
5572 * @param priv
5573 * Pointer to private structure.
5574 * @param dev
5575 * Pointer to the rte_eth_dev structure.
5576 * @return
5577 * 0 on success, negative value on error.
5578 */
5579 static int
5580 priv_dev_removal_interrupt_handler_install(struct priv *priv,
5581 struct rte_eth_dev *dev)
5582 {
5583 int ret;
5584
5585 if (dev->data->dev_conf.intr_conf.rmv) {
5586 ret = priv_dev_interrupt_handler_install(priv, dev);
5587 if (ret)
5588 return ret;
5589 priv->intr_conf.rmv = 1;
5590 }
5591 return 0;
5592 }
5593
5594 /**
5595 * Verify and store value for device argument.
5596 *
5597 * @param[in] key
5598 * Key argument to verify.
5599 * @param[in] val
5600 * Value associated with key.
5601 * @param out
5602 * User data.
5603 *
5604 * @return
5605 * 0 on success, negative errno value on failure.
5606 */
5607 static int
5608 mlx4_arg_parse(const char *key, const char *val, void *out)
5609 {
5610 struct mlx4_conf *conf = out;
5611 unsigned long tmp;
5612
5613 errno = 0;
5614 tmp = strtoul(val, NULL, 0);
5615 if (errno) {
5616 WARN("%s: \"%s\" is not a valid integer", key, val);
5617 return -errno;
5618 }
5619 if (strcmp(MLX4_PMD_PORT_KVARG, key) == 0) {
5620 if (tmp >= MLX4_PMD_MAX_PHYS_PORTS) {
5621 ERROR("invalid port index %lu (max: %u)",
5622 tmp, MLX4_PMD_MAX_PHYS_PORTS - 1);
5623 return -EINVAL;
5624 }
5625 conf->active_ports |= 1 << tmp;
5626 } else {
5627 WARN("%s: unknown parameter", key);
5628 return -EINVAL;
5629 }
5630 return 0;
5631 }
5632
5633 /**
5634 * Parse device parameters.
5635 *
5636 * @param devargs
5637 * Device arguments structure.
5638 *
5639 * @return
5640 * 0 on success, negative errno value on failure.
5641 */
5642 static int
5643 mlx4_args(struct rte_devargs *devargs, struct mlx4_conf *conf)
5644 {
5645 struct rte_kvargs *kvlist;
5646 unsigned int arg_count;
5647 int ret = 0;
5648 int i;
5649
5650 if (devargs == NULL)
5651 return 0;
5652 kvlist = rte_kvargs_parse(devargs->args, pmd_mlx4_init_params);
5653 if (kvlist == NULL) {
5654 ERROR("failed to parse kvargs");
5655 return -EINVAL;
5656 }
5657 /* Process parameters. */
5658 for (i = 0; pmd_mlx4_init_params[i]; ++i) {
5659 arg_count = rte_kvargs_count(kvlist, MLX4_PMD_PORT_KVARG);
5660 while (arg_count-- > 0) {
5661 ret = rte_kvargs_process(kvlist, MLX4_PMD_PORT_KVARG,
5662 mlx4_arg_parse, conf);
5663 if (ret != 0)
5664 goto free_kvlist;
5665 }
5666 }
5667 free_kvlist:
5668 rte_kvargs_free(kvlist);
5669 return ret;
5670 }
5671
5672 static struct rte_pci_driver mlx4_driver;
5673
5674 /**
5675 * DPDK callback to register a PCI device.
5676 *
5677 * This function creates an Ethernet device for each port of a given
5678 * PCI device.
5679 *
5680 * @param[in] pci_drv
5681 * PCI driver structure (mlx4_driver).
5682 * @param[in] pci_dev
5683 * PCI device information.
5684 *
5685 * @return
5686 * 0 on success, negative errno value on failure.
5687 */
5688 static int
5689 mlx4_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
5690 {
5691 struct ibv_device **list;
5692 struct ibv_device *ibv_dev;
5693 int err = 0;
5694 struct ibv_context *attr_ctx = NULL;
5695 struct ibv_device_attr device_attr;
5696 struct mlx4_conf conf = {
5697 .active_ports = 0,
5698 };
5699 unsigned int vf;
5700 int idx;
5701 int i;
5702
5703 (void)pci_drv;
5704 assert(pci_drv == &mlx4_driver);
5705 /* Get mlx4_dev[] index. */
5706 idx = mlx4_dev_idx(&pci_dev->addr);
5707 if (idx == -1) {
5708 ERROR("this driver cannot support any more adapters");
5709 return -ENOMEM;
5710 }
5711 DEBUG("using driver device index %d", idx);
5712
5713 /* Save PCI address. */
5714 mlx4_dev[idx].pci_addr = pci_dev->addr;
5715 list = ibv_get_device_list(&i);
5716 if (list == NULL) {
5717 assert(errno);
5718 if (errno == ENOSYS)
5719 ERROR("cannot list devices, is ib_uverbs loaded?");
5720 return -errno;
5721 }
5722 assert(i >= 0);
5723 /*
5724 * For each listed device, check related sysfs entry against
5725 * the provided PCI ID.
5726 */
5727 while (i != 0) {
5728 struct rte_pci_addr pci_addr;
5729
5730 --i;
5731 DEBUG("checking device \"%s\"", list[i]->name);
5732 if (mlx4_ibv_device_to_pci_addr(list[i], &pci_addr))
5733 continue;
5734 if ((pci_dev->addr.domain != pci_addr.domain) ||
5735 (pci_dev->addr.bus != pci_addr.bus) ||
5736 (pci_dev->addr.devid != pci_addr.devid) ||
5737 (pci_dev->addr.function != pci_addr.function))
5738 continue;
5739 vf = (pci_dev->id.device_id ==
5740 PCI_DEVICE_ID_MELLANOX_CONNECTX3VF);
5741 INFO("PCI information matches, using device \"%s\" (VF: %s)",
5742 list[i]->name, (vf ? "true" : "false"));
5743 attr_ctx = ibv_open_device(list[i]);
5744 err = errno;
5745 break;
5746 }
5747 if (attr_ctx == NULL) {
5748 ibv_free_device_list(list);
5749 switch (err) {
5750 case 0:
5751 ERROR("cannot access device, is mlx4_ib loaded?");
5752 return -ENODEV;
5753 case EINVAL:
5754 ERROR("cannot use device, are drivers up to date?");
5755 return -EINVAL;
5756 }
5757 assert(err > 0);
5758 return -err;
5759 }
5760 ibv_dev = list[i];
5761
5762 DEBUG("device opened");
5763 if (ibv_query_device(attr_ctx, &device_attr))
5764 goto error;
5765 INFO("%u port(s) detected", device_attr.phys_port_cnt);
5766
5767 if (mlx4_args(pci_dev->device.devargs, &conf)) {
5768 ERROR("failed to process device arguments");
5769 goto error;
5770 }
5771 /* Use all ports when none are defined */
5772 if (conf.active_ports == 0) {
5773 for (i = 0; i < MLX4_PMD_MAX_PHYS_PORTS; i++)
5774 conf.active_ports |= 1 << i;
5775 }
5776 for (i = 0; i < device_attr.phys_port_cnt; i++) {
5777 uint32_t port = i + 1; /* ports are indexed from one */
5778 uint32_t test = (1 << i);
5779 struct ibv_context *ctx = NULL;
5780 struct ibv_port_attr port_attr;
5781 struct ibv_pd *pd = NULL;
5782 struct priv *priv = NULL;
5783 struct rte_eth_dev *eth_dev = NULL;
5784 #ifdef HAVE_EXP_QUERY_DEVICE
5785 struct ibv_exp_device_attr exp_device_attr;
5786 #endif /* HAVE_EXP_QUERY_DEVICE */
5787 struct ether_addr mac;
5788
5789 /* If port is not active, skip. */
5790 if (!(conf.active_ports & (1 << i)))
5791 continue;
5792 #ifdef HAVE_EXP_QUERY_DEVICE
5793 exp_device_attr.comp_mask = IBV_EXP_DEVICE_ATTR_EXP_CAP_FLAGS;
5794 #ifdef RSS_SUPPORT
5795 exp_device_attr.comp_mask |= IBV_EXP_DEVICE_ATTR_RSS_TBL_SZ;
5796 #endif /* RSS_SUPPORT */
5797 #endif /* HAVE_EXP_QUERY_DEVICE */
5798
5799 DEBUG("using port %u (%08" PRIx32 ")", port, test);
5800
5801 ctx = ibv_open_device(ibv_dev);
5802 if (ctx == NULL)
5803 goto port_error;
5804
5805 /* Check port status. */
5806 err = ibv_query_port(ctx, port, &port_attr);
5807 if (err) {
5808 ERROR("port query failed: %s", strerror(err));
5809 goto port_error;
5810 }
5811
5812 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
5813 ERROR("port %d is not configured in Ethernet mode",
5814 port);
5815 goto port_error;
5816 }
5817
5818 if (port_attr.state != IBV_PORT_ACTIVE)
5819 DEBUG("port %d is not active: \"%s\" (%d)",
5820 port, ibv_port_state_str(port_attr.state),
5821 port_attr.state);
5822
5823 /* Allocate protection domain. */
5824 pd = ibv_alloc_pd(ctx);
5825 if (pd == NULL) {
5826 ERROR("PD allocation failure");
5827 err = ENOMEM;
5828 goto port_error;
5829 }
5830
5831 mlx4_dev[idx].ports |= test;
5832
5833 /* from rte_ethdev.c */
5834 priv = rte_zmalloc("ethdev private structure",
5835 sizeof(*priv),
5836 RTE_CACHE_LINE_SIZE);
5837 if (priv == NULL) {
5838 ERROR("priv allocation failure");
5839 err = ENOMEM;
5840 goto port_error;
5841 }
5842
5843 priv->ctx = ctx;
5844 priv->device_attr = device_attr;
5845 priv->port = port;
5846 priv->pd = pd;
5847 priv->mtu = ETHER_MTU;
5848 #ifdef HAVE_EXP_QUERY_DEVICE
5849 if (ibv_exp_query_device(ctx, &exp_device_attr)) {
5850 ERROR("ibv_exp_query_device() failed");
5851 goto port_error;
5852 }
5853 #ifdef RSS_SUPPORT
5854 if ((exp_device_attr.exp_device_cap_flags &
5855 IBV_EXP_DEVICE_QPG) &&
5856 (exp_device_attr.exp_device_cap_flags &
5857 IBV_EXP_DEVICE_UD_RSS) &&
5858 (exp_device_attr.comp_mask &
5859 IBV_EXP_DEVICE_ATTR_RSS_TBL_SZ) &&
5860 (exp_device_attr.max_rss_tbl_sz > 0)) {
5861 priv->hw_qpg = 1;
5862 priv->hw_rss = 1;
5863 priv->max_rss_tbl_sz = exp_device_attr.max_rss_tbl_sz;
5864 } else {
5865 priv->hw_qpg = 0;
5866 priv->hw_rss = 0;
5867 priv->max_rss_tbl_sz = 0;
5868 }
5869 priv->hw_tss = !!(exp_device_attr.exp_device_cap_flags &
5870 IBV_EXP_DEVICE_UD_TSS);
5871 DEBUG("device flags: %s%s%s",
5872 (priv->hw_qpg ? "IBV_DEVICE_QPG " : ""),
5873 (priv->hw_tss ? "IBV_DEVICE_TSS " : ""),
5874 (priv->hw_rss ? "IBV_DEVICE_RSS " : ""));
5875 if (priv->hw_rss)
5876 DEBUG("maximum RSS indirection table size: %u",
5877 exp_device_attr.max_rss_tbl_sz);
5878 #endif /* RSS_SUPPORT */
5879
5880 priv->hw_csum =
5881 ((exp_device_attr.exp_device_cap_flags &
5882 IBV_EXP_DEVICE_RX_CSUM_TCP_UDP_PKT) &&
5883 (exp_device_attr.exp_device_cap_flags &
5884 IBV_EXP_DEVICE_RX_CSUM_IP_PKT));
5885 DEBUG("checksum offloading is %ssupported",
5886 (priv->hw_csum ? "" : "not "));
5887
5888 priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags &
5889 IBV_EXP_DEVICE_VXLAN_SUPPORT);
5890 DEBUG("L2 tunnel checksum offloads are %ssupported",
5891 (priv->hw_csum_l2tun ? "" : "not "));
5892
5893 #ifdef INLINE_RECV
5894 priv->inl_recv_size = mlx4_getenv_int("MLX4_INLINE_RECV_SIZE");
5895
5896 if (priv->inl_recv_size) {
5897 exp_device_attr.comp_mask =
5898 IBV_EXP_DEVICE_ATTR_INLINE_RECV_SZ;
5899 if (ibv_exp_query_device(ctx, &exp_device_attr)) {
5900 INFO("Couldn't query device for inline-receive"
5901 " capabilities.");
5902 priv->inl_recv_size = 0;
5903 } else {
5904 if ((unsigned)exp_device_attr.inline_recv_sz <
5905 priv->inl_recv_size) {
5906 INFO("Max inline-receive (%d) <"
5907 " requested inline-receive (%u)",
5908 exp_device_attr.inline_recv_sz,
5909 priv->inl_recv_size);
5910 priv->inl_recv_size =
5911 exp_device_attr.inline_recv_sz;
5912 }
5913 }
5914 INFO("Set inline receive size to %u",
5915 priv->inl_recv_size);
5916 }
5917 #endif /* INLINE_RECV */
5918 #endif /* HAVE_EXP_QUERY_DEVICE */
5919
5920 (void)mlx4_getenv_int;
5921 priv->vf = vf;
5922 /* Configure the first MAC address by default. */
5923 if (priv_get_mac(priv, &mac.addr_bytes)) {
5924 ERROR("cannot get MAC address, is mlx4_en loaded?"
5925 " (errno: %s)", strerror(errno));
5926 goto port_error;
5927 }
5928 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
5929 priv->port,
5930 mac.addr_bytes[0], mac.addr_bytes[1],
5931 mac.addr_bytes[2], mac.addr_bytes[3],
5932 mac.addr_bytes[4], mac.addr_bytes[5]);
5933 /* Register MAC and broadcast addresses. */
5934 claim_zero(priv_mac_addr_add(priv, 0,
5935 (const uint8_t (*)[ETHER_ADDR_LEN])
5936 mac.addr_bytes));
5937 claim_zero(priv_mac_addr_add(priv, (elemof(priv->mac) - 1),
5938 &(const uint8_t [ETHER_ADDR_LEN])
5939 { "\xff\xff\xff\xff\xff\xff" }));
5940 #ifndef NDEBUG
5941 {
5942 char ifname[IF_NAMESIZE];
5943
5944 if (priv_get_ifname(priv, &ifname) == 0)
5945 DEBUG("port %u ifname is \"%s\"",
5946 priv->port, ifname);
5947 else
5948 DEBUG("port %u ifname is unknown", priv->port);
5949 }
5950 #endif
5951 /* Get actual MTU if possible. */
5952 priv_get_mtu(priv, &priv->mtu);
5953 DEBUG("port %u MTU is %u", priv->port, priv->mtu);
5954
5955 /* from rte_ethdev.c */
5956 {
5957 char name[RTE_ETH_NAME_MAX_LEN];
5958
5959 snprintf(name, sizeof(name), "%s port %u",
5960 ibv_get_device_name(ibv_dev), port);
5961 eth_dev = rte_eth_dev_allocate(name);
5962 }
5963 if (eth_dev == NULL) {
5964 ERROR("can not allocate rte ethdev");
5965 err = ENOMEM;
5966 goto port_error;
5967 }
5968
5969 /* Secondary processes have to use local storage for their
5970 * private data as well as a copy of eth_dev->data, but this
5971 * pointer must not be modified before burst functions are
5972 * actually called. */
5973 if (mlx4_is_secondary()) {
5974 struct mlx4_secondary_data *sd =
5975 &mlx4_secondary_data[eth_dev->data->port_id];
5976
5977 sd->primary_priv = eth_dev->data->dev_private;
5978 if (sd->primary_priv == NULL) {
5979 ERROR("no private data for port %u",
5980 eth_dev->data->port_id);
5981 err = EINVAL;
5982 goto port_error;
5983 }
5984 sd->shared_dev_data = eth_dev->data;
5985 rte_spinlock_init(&sd->lock);
5986 memcpy(sd->data.name, sd->shared_dev_data->name,
5987 sizeof(sd->data.name));
5988 sd->data.dev_private = priv;
5989 sd->data.rx_mbuf_alloc_failed = 0;
5990 sd->data.mtu = ETHER_MTU;
5991 sd->data.port_id = sd->shared_dev_data->port_id;
5992 sd->data.mac_addrs = priv->mac;
5993 eth_dev->tx_pkt_burst = mlx4_tx_burst_secondary_setup;
5994 eth_dev->rx_pkt_burst = mlx4_rx_burst_secondary_setup;
5995 } else {
5996 eth_dev->data->dev_private = priv;
5997 eth_dev->data->mac_addrs = priv->mac;
5998 }
5999 eth_dev->device = &pci_dev->device;
6000
6001 rte_eth_copy_pci_info(eth_dev, pci_dev);
6002
6003 eth_dev->device->driver = &mlx4_driver.driver;
6004
6005 priv->dev = eth_dev;
6006 eth_dev->dev_ops = &mlx4_dev_ops;
6007
6008 /* Bring Ethernet device up. */
6009 DEBUG("forcing Ethernet interface up");
6010 priv_set_flags(priv, ~IFF_UP, IFF_UP);
6011 /* Update link status once if waiting for LSC. */
6012 if (eth_dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
6013 mlx4_link_update(eth_dev, 0);
6014 continue;
6015
6016 port_error:
6017 rte_free(priv);
6018 if (pd)
6019 claim_zero(ibv_dealloc_pd(pd));
6020 if (ctx)
6021 claim_zero(ibv_close_device(ctx));
6022 if (eth_dev)
6023 rte_eth_dev_release_port(eth_dev);
6024 break;
6025 }
6026
6027 /*
6028 * XXX if something went wrong in the loop above, there is a resource
6029 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
6030 * long as the dpdk does not provide a way to deallocate a ethdev and a
6031 * way to enumerate the registered ethdevs to free the previous ones.
6032 */
6033
6034 /* no port found, complain */
6035 if (!mlx4_dev[idx].ports) {
6036 err = ENODEV;
6037 goto error;
6038 }
6039
6040 error:
6041 if (attr_ctx)
6042 claim_zero(ibv_close_device(attr_ctx));
6043 if (list)
6044 ibv_free_device_list(list);
6045 assert(err >= 0);
6046 return -err;
6047 }
6048
6049 static const struct rte_pci_id mlx4_pci_id_map[] = {
6050 {
6051 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
6052 PCI_DEVICE_ID_MELLANOX_CONNECTX3)
6053 },
6054 {
6055 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
6056 PCI_DEVICE_ID_MELLANOX_CONNECTX3PRO)
6057 },
6058 {
6059 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
6060 PCI_DEVICE_ID_MELLANOX_CONNECTX3VF)
6061 },
6062 {
6063 .vendor_id = 0
6064 }
6065 };
6066
6067 static struct rte_pci_driver mlx4_driver = {
6068 .driver = {
6069 .name = MLX4_DRIVER_NAME
6070 },
6071 .id_table = mlx4_pci_id_map,
6072 .probe = mlx4_pci_probe,
6073 .drv_flags = RTE_PCI_DRV_INTR_LSC |
6074 RTE_PCI_DRV_INTR_RMV,
6075 };
6076
6077 /**
6078 * Driver initialization routine.
6079 */
6080 RTE_INIT(rte_mlx4_pmd_init);
6081 static void
6082 rte_mlx4_pmd_init(void)
6083 {
6084 RTE_BUILD_BUG_ON(sizeof(wr_id_t) != sizeof(uint64_t));
6085 /*
6086 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
6087 * huge pages. Calling ibv_fork_init() during init allows
6088 * applications to use fork() safely for purposes other than
6089 * using this PMD, which is not supported in forked processes.
6090 */
6091 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
6092 ibv_fork_init();
6093 rte_pci_register(&mlx4_driver);
6094 }
6095
6096 RTE_PMD_EXPORT_NAME(net_mlx4, __COUNTER__);
6097 RTE_PMD_REGISTER_PCI_TABLE(net_mlx4, mlx4_pci_id_map);
6098 RTE_PMD_REGISTER_KMOD_DEP(net_mlx4,
6099 "* ib_uverbs & mlx4_en & mlx4_core & mlx4_ib");