2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
17 #define CONFIG_ECORE_BINARY_FW
18 #undef CONFIG_ECORE_ZIPPED_FW
20 #ifdef CONFIG_ECORE_ZIPPED_FW
24 #include "ecore_hsi_common.h"
25 #include "ecore_hsi_debug_tools.h"
26 #include "ecore_hsi_init_func.h"
27 #include "ecore_hsi_init_tool.h"
28 #include "ecore_proto_if.h"
29 #include "mcp_public.h"
31 #define ECORE_MAJOR_VERSION 8
32 #define ECORE_MINOR_VERSION 18
33 #define ECORE_REVISION_VERSION 7
34 #define ECORE_ENGINEERING_VERSION 0
36 #define ECORE_VERSION \
37 ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \
38 (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
40 #define STORM_FW_VERSION \
41 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
42 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
44 #define MAX_HWFNS_PER_DEVICE 2
45 #define NAME_SIZE 128 /* @DPDK */
46 #define ECORE_WFQ_UNIT 100
47 #include "../qede_logs.h" /* @DPDK */
49 #define ISCSI_BDQ_ID(_port_id) (_port_id)
50 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
52 #define ECORE_WID_SIZE (1024)
55 #define ECORE_PF_DEMS_SIZE (4)
58 enum ecore_coalescing_mode
{
59 ECORE_COAL_MODE_DISABLE
,
60 ECORE_COAL_MODE_ENABLE
64 ECORE_PUT_FILE_BEGIN
= DRV_MSG_CODE_NVM_PUT_FILE_BEGIN
,
65 ECORE_PUT_FILE_DATA
= DRV_MSG_CODE_NVM_PUT_FILE_DATA
,
66 ECORE_NVM_READ_NVRAM
= DRV_MSG_CODE_NVM_READ_NVRAM
,
67 ECORE_NVM_WRITE_NVRAM
= DRV_MSG_CODE_NVM_WRITE_NVRAM
,
68 ECORE_NVM_DEL_FILE
= DRV_MSG_CODE_NVM_DEL_FILE
,
69 ECORE_NVM_SET_SECURE_MODE
= DRV_MSG_CODE_SET_SECURE_MODE
,
70 ECORE_PHY_RAW_READ
= DRV_MSG_CODE_PHY_RAW_READ
,
71 ECORE_PHY_RAW_WRITE
= DRV_MSG_CODE_PHY_RAW_WRITE
,
72 ECORE_PHY_CORE_READ
= DRV_MSG_CODE_PHY_CORE_READ
,
73 ECORE_PHY_CORE_WRITE
= DRV_MSG_CODE_PHY_CORE_WRITE
,
74 ECORE_GET_MCP_NVM_RESP
= 0xFFFFFF00
78 #if !defined(CONFIG_ECORE_L2)
79 #define CONFIG_ECORE_L2
80 #define CONFIG_ECORE_SRIOV
85 #ifndef __EXTRACT__LINUX__
86 #define MASK_FIELD(_name, _value) \
87 ((_value) &= (_name##_MASK))
89 #define FIELD_VALUE(_name, _value) \
90 ((_value & _name##_MASK) << _name##_SHIFT)
92 #define SET_FIELD(value, name, flag) \
94 (value) &= ~(name##_MASK << name##_SHIFT); \
95 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
98 #define GET_FIELD(value, name) \
99 (((value) >> (name##_SHIFT)) & name##_MASK)
102 #define ECORE_MFW_GET_FIELD(name, field) \
103 (((name) & (field ## _MASK)) >> (field ## _SHIFT))
105 #define ECORE_MFW_SET_FIELD(name, field, value) \
107 (name) &= ~(field ## _MASK); \
108 (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK)); \
111 static OSAL_INLINE u32
DB_ADDR(u32 cid
, u32 DEMS
)
113 u32 db_addr
= FIELD_VALUE(DB_LEGACY_ADDR_DEMS
, DEMS
) |
114 (cid
* ECORE_PF_DEMS_SIZE
);
119 static OSAL_INLINE u32
DB_ADDR_VF(u32 cid
, u32 DEMS
)
121 u32 db_addr
= FIELD_VALUE(DB_LEGACY_ADDR_DEMS
, DEMS
) |
122 FIELD_VALUE(DB_LEGACY_ADDR_ICID
, cid
);
127 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
128 ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
129 ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
133 #define U64_HI(val) ((u32)(((u64)(val)) >> 32))
137 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
141 #ifndef __EXTRACT__LINUX__
143 ECORE_LEVEL_VERBOSE
= 0x0,
144 ECORE_LEVEL_INFO
= 0x1,
145 ECORE_LEVEL_NOTICE
= 0x2,
146 ECORE_LEVEL_ERR
= 0x3,
149 #define ECORE_LOG_LEVEL_SHIFT (30)
150 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff)
151 #define ECORE_LOG_INFO_MASK (0x40000000)
152 #define ECORE_LOG_NOTICE_MASK (0x80000000)
156 ECORE_MSG_DRV
= 0x0001,
157 ECORE_MSG_PROBE
= 0x0002,
158 ECORE_MSG_LINK
= 0x0004,
159 ECORE_MSG_TIMER
= 0x0008,
160 ECORE_MSG_IFDOWN
= 0x0010,
161 ECORE_MSG_IFUP
= 0x0020,
162 ECORE_MSG_RX_ERR
= 0x0040,
163 ECORE_MSG_TX_ERR
= 0x0080,
164 ECORE_MSG_TX_QUEUED
= 0x0100,
165 ECORE_MSG_INTR
= 0x0200,
166 ECORE_MSG_TX_DONE
= 0x0400,
167 ECORE_MSG_RX_STATUS
= 0x0800,
168 ECORE_MSG_PKTDATA
= 0x1000,
169 ECORE_MSG_HW
= 0x2000,
170 ECORE_MSG_WOL
= 0x4000,
172 ECORE_MSG_SPQ
= 0x10000,
173 ECORE_MSG_STATS
= 0x20000,
174 ECORE_MSG_DCB
= 0x40000,
175 ECORE_MSG_IOV
= 0x80000,
176 ECORE_MSG_SP
= 0x100000,
177 ECORE_MSG_STORAGE
= 0x200000,
178 ECORE_MSG_OOO
= 0x200000,
179 ECORE_MSG_CXT
= 0x800000,
180 ECORE_MSG_LL2
= 0x1000000,
181 ECORE_MSG_ILT
= 0x2000000,
182 ECORE_MSG_RDMA
= 0x4000000,
183 ECORE_MSG_DEBUG
= 0x8000000,
184 /* to be added...up to 0x8000000 */
188 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
190 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
191 (val == (cond1) ? true1 : \
192 (val == (cond2) ? true2 : def))
195 struct ecore_ptt_pool
;
197 struct ecore_sb_info
;
198 struct ecore_sb_attn_info
;
199 struct ecore_cxt_mngr
;
200 struct ecore_dma_mem
;
201 struct ecore_sb_sp_info
;
202 struct ecore_ll2_info
;
203 struct ecore_l2_info
;
204 struct ecore_igu_info
;
205 struct ecore_mcp_info
;
206 struct ecore_dcbx_info
;
208 struct ecore_rt_data
{
213 enum ecore_tunn_mode
{
214 ECORE_MODE_L2GENEVE_TUNN
,
215 ECORE_MODE_IPGENEVE_TUNN
,
216 ECORE_MODE_L2GRE_TUNN
,
217 ECORE_MODE_IPGRE_TUNN
,
218 ECORE_MODE_VXLAN_TUNN
,
221 enum ecore_tunn_clss
{
222 ECORE_TUNN_CLSS_MAC_VLAN
,
223 ECORE_TUNN_CLSS_MAC_VNI
,
224 ECORE_TUNN_CLSS_INNER_MAC_VLAN
,
225 ECORE_TUNN_CLSS_INNER_MAC_VNI
,
226 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE
,
230 struct ecore_tunn_update_type
{
233 enum ecore_tunn_clss tun_cls
;
236 struct ecore_tunn_update_udp_port
{
241 struct ecore_tunnel_info
{
242 struct ecore_tunn_update_type vxlan
;
243 struct ecore_tunn_update_type l2_geneve
;
244 struct ecore_tunn_update_type ip_geneve
;
245 struct ecore_tunn_update_type l2_gre
;
246 struct ecore_tunn_update_type ip_gre
;
248 struct ecore_tunn_update_udp_port vxlan_port
;
249 struct ecore_tunn_update_udp_port geneve_port
;
251 bool b_update_rx_cls
;
252 bool b_update_tx_cls
;
255 /* The PCI personality is not quite synonymous to protocol ID:
256 * 1. All personalities need CORE connections
257 * 2. The Ethernet personality may support also the RoCE/iWARP protocol
259 enum ecore_pci_personality
{
266 ECORE_PCI_DEFAULT
/* default in shmem */
269 /* All VFs are symmetric, all counters are PF + all VFs */
270 struct ecore_qm_iids
{
276 #define MAX_PF_PER_PORT 8
278 /* HW / FW resources, output of features supported below, most information
279 * is received from MFW.
281 enum ecore_resources
{
294 ECORE_RDMA_STATS_QUEUE
,
296 ECORE_MAX_RESC
, /* must be last */
299 /* Features that require resources, given as input to the resource management
300 * algorithm, the output are the resources above
315 enum ecore_port_mode
{
316 ECORE_PORT_MODE_DE_2X40G
,
317 ECORE_PORT_MODE_DE_2X50G
,
318 ECORE_PORT_MODE_DE_1X100G
,
319 ECORE_PORT_MODE_DE_4X10G_F
,
320 ECORE_PORT_MODE_DE_4X10G_E
,
321 ECORE_PORT_MODE_DE_4X20G
,
322 ECORE_PORT_MODE_DE_1X40G
,
323 ECORE_PORT_MODE_DE_2X25G
,
324 ECORE_PORT_MODE_DE_1X25G
,
325 ECORE_PORT_MODE_DE_4X25G
,
326 ECORE_PORT_MODE_DE_2X10G
,
337 #ifndef __EXTRACT__LINUX__
338 enum ecore_hw_err_type
{
339 ECORE_HW_ERR_FAN_FAIL
,
340 ECORE_HW_ERR_MFW_RESP_FAIL
,
341 ECORE_HW_ERR_HW_ATTN
,
342 ECORE_HW_ERR_DMAE_FAIL
,
343 ECORE_HW_ERR_RAMROD_FAIL
,
344 ECORE_HW_ERR_FW_ASSERT
,
348 struct ecore_hw_info
{
349 /* PCI personality */
350 enum ecore_pci_personality personality
;
351 #define ECORE_IS_RDMA_PERSONALITY(dev) \
352 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
353 (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
354 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
355 #define ECORE_IS_ROCE_PERSONALITY(dev) \
356 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
357 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
358 #define ECORE_IS_IWARP_PERSONALITY(dev) \
359 ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
360 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
361 #define ECORE_IS_L2_PERSONALITY(dev) \
362 ((dev)->hw_info.personality == ECORE_PCI_ETH || \
363 ECORE_IS_RDMA_PERSONALITY(dev))
365 /* Resource Allocation scheme results */
366 u32 resc_start
[ECORE_MAX_RESC
];
367 u32 resc_num
[ECORE_MAX_RESC
];
368 u32 feat_num
[ECORE_MAX_FEATURES
];
370 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
371 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
372 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
373 RESC_NUM(_p_hwfn, resc))
374 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
376 /* Amount of traffic classes HW supports */
379 /* Amount of TCs which should be active according to DCBx or upper layer driver
385 /* The traffic class used by PF for it's offloaded protocol */
393 unsigned char hw_mac_addr
[ETH_ALEN
];
394 u64 node_wwn
; /* For FCoE only */
395 u64 port_wwn
; /* For FCoE only */
400 struct ecore_igu_info
*p_igu_info
;
402 u8 max_chains_per_vf
;
406 unsigned long device_capabilities
;
408 /* Default DCBX mode */
414 /* maximun size of read/write commands (HW limit) */
415 #define DMAE_MAX_RW_SIZE 0x2000
417 struct ecore_dmae_info
{
418 /* Mutex for synchronizing access to functions */
423 dma_addr_t completion_word_phys_addr
;
425 /* The memory location where the DMAE writes the completion
426 * value when an operation is finished on this context.
428 u32
*p_completion_word
;
430 dma_addr_t intermediate_buffer_phys_addr
;
432 /* An intermediate buffer for DMAE operations that use virtual
433 * addresses - data is DMA'd to/from this buffer and then
434 * memcpy'd to/from the virtual address
436 u32
*p_intermediate_buffer
;
438 dma_addr_t dmae_cmd_phys_addr
;
439 struct dmae_cmd
*p_dmae_cmd
;
442 struct ecore_wfq_data
{
443 u32 default_min_speed
; /* When wfq feature is not configured */
444 u32 min_speed
; /* when feature is configured for any 1 vport */
448 struct ecore_qm_info
{
449 struct init_qm_pq_params
*qm_pq_params
;
450 struct init_qm_vport_params
*qm_vport_params
;
451 struct init_qm_port_params
*qm_port_params
;
464 u8 max_phys_tcs_per_port
;
472 struct ecore_wfq_data
*wfq_data
;
481 struct ecore_fw_data
{
482 #ifdef CONFIG_ECORE_BINARY_FW
483 struct fw_ver_info
*fw_ver_info
;
485 const u8
*modes_tree_buf
;
486 union init_op
*init_ops
;
492 struct ecore_dev
*p_dev
;
493 u8 my_id
; /* ID inside the PF */
494 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
495 u8 rel_pf_id
; /* Relative to engine*/
497 #define ECORE_PATH_ID(_p_hwfn) \
498 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
504 char name
[NAME_SIZE
];
507 bool first_on_engine
;
510 u8 num_funcs_on_engine
;
514 void OSAL_IOMEM
*regview
;
515 void OSAL_IOMEM
*doorbells
;
517 unsigned long db_size
;
520 struct ecore_ptt_pool
*p_ptt_pool
;
523 struct ecore_hw_info hw_info
;
525 /* rt_array (for init-tool) */
526 struct ecore_rt_data rt_data
;
529 struct ecore_spq
*p_spq
;
532 struct ecore_eq
*p_eq
;
535 struct ecore_consq
*p_consq
;
537 /* Slow-Path definitions */
539 bool b_sp_dpc_enabled
;
541 struct ecore_ptt
*p_main_ptt
;
542 struct ecore_ptt
*p_dpc_ptt
;
544 struct ecore_sb_sp_info
*p_sp_sb
;
545 struct ecore_sb_attn_info
*p_sb_attn
;
547 /* Protocol related */
549 struct ecore_ll2_info
*p_ll2_info
;
550 struct ecore_ooo_info
*p_ooo_info
;
551 struct ecore_iscsi_info
*p_iscsi_info
;
552 struct ecore_fcoe_info
*p_fcoe_info
;
553 struct ecore_rdma_info
*p_rdma_info
;
554 struct ecore_pf_params pf_params
;
556 bool b_rdma_enabled_in_prs
;
557 u32 rdma_prs_search_reg
;
559 /* Array of sb_info of all status blocks */
560 struct ecore_sb_info
*sbs_info
[MAX_SB_PER_PF_MIMD
];
563 struct ecore_cxt_mngr
*p_cxt_mngr
;
565 /* Flag indicating whether interrupts are enabled or not*/
567 bool b_int_requested
;
569 /* True if the driver requests for the link */
570 bool b_drv_link_init
;
572 struct ecore_vf_iov
*vf_iov_info
;
573 struct ecore_pf_iov
*pf_iov_info
;
574 struct ecore_mcp_info
*mcp_info
;
575 struct ecore_dcbx_info
*p_dcbx_info
;
577 struct ecore_dmae_info dmae_info
;
580 struct ecore_qm_info qm_info
;
582 #ifdef CONFIG_ECORE_ZIPPED_FW
583 /* Buffer for unzipping firmware data */
587 struct dbg_tools_data dbg_info
;
589 struct z_stream_s
*stream
;
591 /* PWM region specific data */
594 u32 dpi_start_offset
; /* this is used to
599 /* If one of the following is set then EDPM shouldn't be used */
604 struct ecore_l2_info
*p_l2_info
;
607 struct ecore_ptt
*p_arfs_ptt
;
610 #ifndef __EXTRACT__LINUX__
619 struct ecore_dbg_feature
{
625 enum qed_dbg_features
{
628 DBG_FEATURE_IDLE_CHK
,
629 DBG_FEATURE_MCP_TRACE
,
630 DBG_FEATURE_REG_FIFO
,
631 DBG_FEATURE_PROTECTION_OVERRIDE
,
638 char name
[NAME_SIZE
];
642 #define ECORE_DEV_TYPE_BB (0 << 0)
643 #define ECORE_DEV_TYPE_AH (1 << 0)
644 /* Translate type/revision combo into the proper conditions */
645 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
646 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
648 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
649 (CHIP_REV_IS_TEDIBEAR(dev)))
651 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
653 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
654 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
656 #define ECORE_DEV_ID_MASK 0xff00
657 #define ECORE_DEV_ID_MASK_BB 0x1600
658 #define ECORE_DEV_ID_MASK_AH 0x8000
664 #define CHIP_NUM_MASK 0xffff
665 #define CHIP_NUM_SHIFT 16
668 #define CHIP_REV_MASK 0xf
669 #define CHIP_REV_SHIFT 12
671 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
672 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
673 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
674 #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
675 CHIP_REV_IS_EMUL_B0(_p_dev))
676 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
677 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
678 #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
679 CHIP_REV_IS_FPGA_B0(_p_dev))
680 #define CHIP_REV_IS_SLOW(_p_dev) \
681 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
682 #define CHIP_REV_IS_A0(_p_dev) \
683 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
684 CHIP_REV_IS_FPGA_A0(_p_dev) || \
686 #define CHIP_REV_IS_B0(_p_dev) \
687 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
688 CHIP_REV_IS_FPGA_B0(_p_dev) || \
689 (_p_dev)->chip_rev == 1)
690 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
692 #define CHIP_REV_IS_A0(_p_dev) (!(_p_dev)->chip_rev)
693 #define CHIP_REV_IS_B0(_p_dev) ((_p_dev)->chip_rev == 1)
697 #define CHIP_METAL_MASK 0xff
698 #define CHIP_METAL_SHIFT 4
701 #define CHIP_BOND_ID_MASK 0xf
702 #define CHIP_BOND_ID_SHIFT 0
705 u8 num_ports_in_engines
;
706 u8 num_funcs_in_port
;
709 enum ecore_mf_mode mf_mode
;
710 #define IS_MF_DEFAULT(_p_hwfn) \
711 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
712 #define IS_MF_SI(_p_hwfn) \
713 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
714 #define IS_MF_SD(_p_hwfn) \
715 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
720 /* Add MF related configuration */
727 enum ecore_coalescing_mode int_coalescing_mode
;
728 u16 rx_coalesce_usecs
;
729 u16 tx_coalesce_usecs
;
731 /* Start Bar offset of first hwfn */
732 void OSAL_IOMEM
*regview
;
733 void OSAL_IOMEM
*doorbells
;
735 unsigned long db_size
;
741 const struct iro
*iro_arr
;
742 #define IRO (p_hwfn->p_dev->iro_arr)
746 struct ecore_hwfn hwfns
[MAX_HWFNS_PER_DEVICE
];
749 struct ecore_hw_sriov_info
*p_iov_info
;
750 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info)
751 struct ecore_tunnel_info tunnel
;
758 u32 rdma_max_srq_sge
;
760 struct ecore_eth_stats
*reset_stats
;
761 struct ecore_fw_data
*fw_data
;
768 /* Indicates whether should prevent attentions from being reasserted */
772 /* Indicates whether allowing the MFW to collect a crash dump */
775 /* Indicates if the reg_fifo is checked after any register access */
782 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
788 struct ecore_dbg_feature dbg_features
[DBG_FEATURE_NUM
];
792 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
794 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
795 : MAX_NUM_L2_QUEUES_K2)
796 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
798 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
799 : MAX_SB_PER_PATH_K2)
800 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
804 * @brief ecore_concrete_to_sw_fid - get the sw function id from
805 * the concrete value.
807 * @param concrete_fid
809 * @return OSAL_INLINE u8
811 static OSAL_INLINE u8
812 ecore_concrete_to_sw_fid(__rte_unused
struct ecore_dev
*p_dev
, u32 concrete_fid
)
814 u8 vfid
= GET_FIELD(concrete_fid
, PXP_CONCRETE_FID_VFID
);
815 u8 pfid
= GET_FIELD(concrete_fid
, PXP_CONCRETE_FID_PFID
);
816 u8 vf_valid
= GET_FIELD(concrete_fid
, PXP_CONCRETE_FID_VFVALID
);
820 sw_fid
= vfid
+ MAX_NUM_PFS
;
830 int ecore_configure_vport_wfq(struct ecore_dev
*p_dev
, u16 vp_id
, u32 rate
);
831 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev
*p_dev
,
834 int ecore_configure_pf_max_bandwidth(struct ecore_dev
*p_dev
, u8 max_bw
);
835 int ecore_configure_pf_min_bandwidth(struct ecore_dev
*p_dev
, u8 min_bw
);
836 void ecore_clean_wfq_db(struct ecore_hwfn
*p_hwfn
, struct ecore_ptt
*p_ptt
);
837 int ecore_device_num_engines(struct ecore_dev
*p_dev
);
838 int ecore_device_num_ports(struct ecore_dev
*p_dev
);
839 void ecore_set_fw_mac_addr(__le16
*fw_msb
, __le16
*fw_mid
, __le16
*fw_lsb
,
842 /* Flags for indication of required queues */
843 #define PQ_FLAGS_RLS (1 << 0)
844 #define PQ_FLAGS_MCOS (1 << 1)
845 #define PQ_FLAGS_LB (1 << 2)
846 #define PQ_FLAGS_OOO (1 << 3)
847 #define PQ_FLAGS_ACK (1 << 4)
848 #define PQ_FLAGS_OFLD (1 << 5)
849 #define PQ_FLAGS_VFS (1 << 6)
851 /* physical queue index for cm context intialization */
852 u16
ecore_get_cm_pq_idx(struct ecore_hwfn
*p_hwfn
, u32 pq_flags
);
853 u16
ecore_get_cm_pq_idx_mcos(struct ecore_hwfn
*p_hwfn
, u8 tc
);
854 u16
ecore_get_cm_pq_idx_vf(struct ecore_hwfn
*p_hwfn
, u16 vf
);
855 u16
ecore_get_cm_pq_idx_rl(struct ecore_hwfn
*p_hwfn
, u8 qpid
);
857 /* amount of resources used in qm init */
858 u8
ecore_init_qm_get_num_tcs(struct ecore_hwfn
*p_hwfn
);
859 u16
ecore_init_qm_get_num_vfs(struct ecore_hwfn
*p_hwfn
);
860 u16
ecore_init_qm_get_num_pf_rls(struct ecore_hwfn
*p_hwfn
);
861 u16
ecore_init_qm_get_num_vports(struct ecore_hwfn
*p_hwfn
);
862 u16
ecore_init_qm_get_num_pqs(struct ecore_hwfn
*p_hwfn
);
864 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
866 const char *ecore_hw_get_resc_name(enum ecore_resources res_id
);
868 #endif /* __ECORE_H */