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update sources to ceph Nautilus 14.2.1
[ceph.git] / ceph / src / seastar / dpdk / drivers / net / qede / base / ecore_dcbx.c
1 /*
2 * Copyright (c) 2016 QLogic Corporation.
3 * All rights reserved.
4 * www.qlogic.com
5 *
6 * See LICENSE.qede_pmd for copyright and licensing details.
7 */
8
9 #include "bcm_osal.h"
10 #include "ecore.h"
11 #include "ecore_sp_commands.h"
12 #include "ecore_dcbx.h"
13 #include "ecore_cxt.h"
14 #include "ecore_gtt_reg_addr.h"
15 #include "ecore_iro.h"
16 #include "ecore_iov_api.h"
17
18 #define ECORE_DCBX_MAX_MIB_READ_TRY (100)
19 #define ECORE_ETH_TYPE_DEFAULT (0)
20
21 #define ECORE_DCBX_INVALID_PRIORITY 0xFF
22
23 /* Get Traffic Class from priority traffic class table, 4 bits represent
24 * the traffic class corresponding to the priority.
25 */
26 #define ECORE_DCBX_PRIO2TC(prio_tc_tbl, prio) \
27 ((u32)(prio_tc_tbl >> ((7 - prio) * 4)) & 0x7)
28
29 static bool ecore_dcbx_app_ethtype(u32 app_info_bitmap)
30 {
31 return !!(ECORE_MFW_GET_FIELD(app_info_bitmap, DCBX_APP_SF) ==
32 DCBX_APP_SF_ETHTYPE);
33 }
34
35 static bool ecore_dcbx_ieee_app_ethtype(u32 app_info_bitmap)
36 {
37 u8 mfw_val = ECORE_MFW_GET_FIELD(app_info_bitmap, DCBX_APP_SF_IEEE);
38
39 /* Old MFW */
40 if (mfw_val == DCBX_APP_SF_IEEE_RESERVED)
41 return ecore_dcbx_app_ethtype(app_info_bitmap);
42
43 return !!(mfw_val == DCBX_APP_SF_IEEE_ETHTYPE);
44 }
45
46 static bool ecore_dcbx_app_port(u32 app_info_bitmap)
47 {
48 return !!(ECORE_MFW_GET_FIELD(app_info_bitmap, DCBX_APP_SF) ==
49 DCBX_APP_SF_PORT);
50 }
51
52 static bool ecore_dcbx_ieee_app_port(u32 app_info_bitmap, u8 type)
53 {
54 u8 mfw_val = ECORE_MFW_GET_FIELD(app_info_bitmap, DCBX_APP_SF_IEEE);
55
56 /* Old MFW */
57 if (mfw_val == DCBX_APP_SF_IEEE_RESERVED)
58 return ecore_dcbx_app_port(app_info_bitmap);
59
60 return !!(mfw_val == type || mfw_val == DCBX_APP_SF_IEEE_TCP_UDP_PORT);
61 }
62
63 static bool ecore_dcbx_default_tlv(u32 app_info_bitmap, u16 proto_id, bool ieee)
64 {
65 bool ethtype;
66
67 if (ieee)
68 ethtype = ecore_dcbx_ieee_app_ethtype(app_info_bitmap);
69 else
70 ethtype = ecore_dcbx_app_ethtype(app_info_bitmap);
71
72 return !!(ethtype && (proto_id == ECORE_ETH_TYPE_DEFAULT));
73 }
74
75 static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap,
76 u16 proto_id, bool ieee)
77 {
78 bool port;
79
80 if (!p_hwfn->p_dcbx_info->iwarp_port)
81 return false;
82
83 if (ieee)
84 port = ecore_dcbx_ieee_app_port(app_info_bitmap,
85 DCBX_APP_SF_IEEE_TCP_PORT);
86 else
87 port = ecore_dcbx_app_port(app_info_bitmap);
88
89 return !!(port && (proto_id == p_hwfn->p_dcbx_info->iwarp_port));
90 }
91
92 static void
93 ecore_dcbx_dp_protocol(struct ecore_hwfn *p_hwfn,
94 struct ecore_dcbx_results *p_data)
95 {
96 enum dcbx_protocol_type id;
97 int i;
98
99 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "DCBX negotiated: %d\n",
100 p_data->dcbx_enabled);
101
102 for (i = 0; i < OSAL_ARRAY_SIZE(ecore_dcbx_app_update); i++) {
103 id = ecore_dcbx_app_update[i].id;
104
105 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
106 "%s info: update %d, enable %d, prio %d, tc %d,"
107 " num_active_tc %d dscp_enable = %d dscp_val = %d\n",
108 ecore_dcbx_app_update[i].name,
109 p_data->arr[id].update,
110 p_data->arr[id].enable, p_data->arr[id].priority,
111 p_data->arr[id].tc, p_hwfn->hw_info.num_active_tc,
112 p_data->arr[id].dscp_enable,
113 p_data->arr[id].dscp_val);
114 }
115 }
116
117 static void
118 ecore_dcbx_set_params(struct ecore_dcbx_results *p_data,
119 struct ecore_hwfn *p_hwfn,
120 bool enable, u8 prio, u8 tc,
121 enum dcbx_protocol_type type,
122 enum ecore_pci_personality personality)
123 {
124 struct ecore_dcbx_dscp_params *dscp = &p_hwfn->p_dcbx_info->get.dscp;
125
126 /* PF update ramrod data */
127 p_data->arr[type].enable = enable;
128 p_data->arr[type].priority = prio;
129 p_data->arr[type].tc = tc;
130 p_data->arr[type].dscp_enable = dscp->enabled;
131 if (p_data->arr[type].dscp_enable) {
132 u8 i;
133
134 for (i = 0; i < ECORE_DCBX_DSCP_SIZE; i++)
135 if (prio == dscp->dscp_pri_map[i]) {
136 p_data->arr[type].dscp_val = i;
137 break;
138 }
139 }
140
141 if (enable && p_data->arr[type].dscp_enable)
142 p_data->arr[type].update = UPDATE_DCB_DSCP;
143 else if (enable)
144 p_data->arr[type].update = UPDATE_DCB;
145 else
146 p_data->arr[type].update = DONT_UPDATE_DCB_DSCP;
147
148 /* QM reconf data */
149 if (p_hwfn->hw_info.personality == personality)
150 p_hwfn->hw_info.offload_tc = tc;
151 }
152
153 /* Update app protocol data and hw_info fields with the TLV info */
154 static void
155 ecore_dcbx_update_app_info(struct ecore_dcbx_results *p_data,
156 struct ecore_hwfn *p_hwfn,
157 bool enable, u8 prio, u8 tc,
158 enum dcbx_protocol_type type)
159 {
160 enum ecore_pci_personality personality;
161 enum dcbx_protocol_type id;
162 const char *name; /* @DPDK */
163 int i;
164
165 for (i = 0; i < OSAL_ARRAY_SIZE(ecore_dcbx_app_update); i++) {
166 id = ecore_dcbx_app_update[i].id;
167
168 if (type != id)
169 continue;
170
171 personality = ecore_dcbx_app_update[i].personality;
172 name = ecore_dcbx_app_update[i].name;
173
174 ecore_dcbx_set_params(p_data, p_hwfn, enable,
175 prio, tc, type, personality);
176 }
177 }
178
179 static enum _ecore_status_t
180 ecore_dcbx_get_app_priority(u8 pri_bitmap, u8 *priority)
181 {
182 u32 pri_mask, pri = ECORE_MAX_PFC_PRIORITIES;
183 u32 index = ECORE_MAX_PFC_PRIORITIES - 1;
184 enum _ecore_status_t rc = ECORE_SUCCESS;
185
186 /* Bitmap 1 corresponds to priority 0, return priority 0 */
187 if (pri_bitmap == 1) {
188 *priority = 0;
189 return rc;
190 }
191
192 /* Choose the highest priority */
193 while ((pri == ECORE_MAX_PFC_PRIORITIES) && index) {
194 pri_mask = 1 << index;
195 if (pri_bitmap & pri_mask)
196 pri = index;
197 index--;
198 }
199
200 if (pri < ECORE_MAX_PFC_PRIORITIES)
201 *priority = (u8)pri;
202 else
203 rc = ECORE_INVAL;
204
205 return rc;
206 }
207
208 static bool
209 ecore_dcbx_get_app_protocol_type(struct ecore_hwfn *p_hwfn,
210 u32 app_prio_bitmap, u16 id,
211 enum dcbx_protocol_type *type, bool ieee)
212 {
213 if (ecore_dcbx_default_tlv(app_prio_bitmap, id, ieee)) {
214 *type = DCBX_PROTOCOL_ETH;
215 } else {
216 *type = DCBX_MAX_PROTOCOL_TYPE;
217 DP_ERR(p_hwfn,
218 "No action required, App TLV id = 0x%x"
219 " app_prio_bitmap = 0x%x\n",
220 id, app_prio_bitmap);
221 return false;
222 }
223
224 return true;
225 }
226
227 /* Parse app TLV's to update TC information in hw_info structure for
228 * reconfiguring QM. Get protocol specific data for PF update ramrod command.
229 */
230 static enum _ecore_status_t
231 ecore_dcbx_process_tlv(struct ecore_hwfn *p_hwfn,
232 struct ecore_dcbx_results *p_data,
233 struct dcbx_app_priority_entry *p_tbl, u32 pri_tc_tbl,
234 int count, u8 dcbx_version)
235 {
236 enum dcbx_protocol_type type;
237 u8 tc, priority_map;
238 bool enable, ieee;
239 u16 protocol_id;
240 u8 priority;
241 enum _ecore_status_t rc = ECORE_SUCCESS;
242 int i;
243
244 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
245 "Num APP entries = %d pri_tc_tbl = 0x%x dcbx_version = %u\n",
246 count, pri_tc_tbl, dcbx_version);
247
248 ieee = (dcbx_version == DCBX_CONFIG_VERSION_IEEE);
249 /* Parse APP TLV */
250 for (i = 0; i < count; i++) {
251 protocol_id = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
252 DCBX_APP_PROTOCOL_ID);
253 priority_map = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
254 DCBX_APP_PRI_MAP);
255 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "Id = 0x%x pri_map = %u\n",
256 protocol_id, priority_map);
257 rc = ecore_dcbx_get_app_priority(priority_map, &priority);
258 if (rc == ECORE_INVAL) {
259 DP_ERR(p_hwfn, "Invalid priority\n");
260 return ECORE_INVAL;
261 }
262
263 tc = ECORE_DCBX_PRIO2TC(pri_tc_tbl, priority);
264 if (ecore_dcbx_get_app_protocol_type(p_hwfn, p_tbl[i].entry,
265 protocol_id, &type,
266 ieee)) {
267 /* ETH always have the enable bit reset, as it gets
268 * vlan information per packet. For other protocols,
269 * should be set according to the dcbx_enabled
270 * indication, but we only got here if there was an
271 * app tlv for the protocol, so dcbx must be enabled.
272 */
273 enable = !(type == DCBX_PROTOCOL_ETH);
274
275 ecore_dcbx_update_app_info(p_data, p_hwfn, enable,
276 priority, tc, type);
277 }
278 }
279 /* Update ramrod protocol data and hw_info fields
280 * with default info when corresponding APP TLV's are not detected.
281 * The enabled field has a different logic for ethernet as only for
282 * ethernet dcb should disabled by default, as the information arrives
283 * from the OS (unless an explicit app tlv was present).
284 */
285 tc = p_data->arr[DCBX_PROTOCOL_ETH].tc;
286 priority = p_data->arr[DCBX_PROTOCOL_ETH].priority;
287 for (type = 0; type < DCBX_MAX_PROTOCOL_TYPE; type++) {
288 if (p_data->arr[type].update)
289 continue;
290
291 enable = (type == DCBX_PROTOCOL_ETH) ? false : !!dcbx_version;
292 ecore_dcbx_update_app_info(p_data, p_hwfn, enable,
293 priority, tc, type);
294 }
295
296 return ECORE_SUCCESS;
297 }
298
299 /* Parse app TLV's to update TC information in hw_info structure for
300 * reconfiguring QM. Get protocol specific data for PF update ramrod command.
301 */
302 static enum _ecore_status_t
303 ecore_dcbx_process_mib_info(struct ecore_hwfn *p_hwfn)
304 {
305 struct dcbx_app_priority_feature *p_app;
306 enum _ecore_status_t rc = ECORE_SUCCESS;
307 struct ecore_dcbx_results data = { 0 };
308 struct dcbx_app_priority_entry *p_tbl;
309 struct dcbx_ets_feature *p_ets;
310 struct ecore_hw_info *p_info;
311 u32 pri_tc_tbl, flags;
312 u8 dcbx_version;
313 int num_entries;
314
315 flags = p_hwfn->p_dcbx_info->operational.flags;
316 dcbx_version = ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION);
317
318 p_app = &p_hwfn->p_dcbx_info->operational.features.app;
319 p_tbl = p_app->app_pri_tbl;
320
321 p_ets = &p_hwfn->p_dcbx_info->operational.features.ets;
322 pri_tc_tbl = p_ets->pri_tc_tbl[0];
323
324 p_info = &p_hwfn->hw_info;
325 num_entries = ECORE_MFW_GET_FIELD(p_app->flags, DCBX_APP_NUM_ENTRIES);
326
327 rc = ecore_dcbx_process_tlv(p_hwfn, &data, p_tbl, pri_tc_tbl,
328 num_entries, dcbx_version);
329 if (rc != ECORE_SUCCESS)
330 return rc;
331
332 p_info->num_active_tc = ECORE_MFW_GET_FIELD(p_ets->flags,
333 DCBX_ETS_MAX_TCS);
334 p_hwfn->qm_info.ooo_tc = ECORE_MFW_GET_FIELD(p_ets->flags, DCBX_OOO_TC);
335 data.pf_id = p_hwfn->rel_pf_id;
336 data.dcbx_enabled = !!dcbx_version;
337
338 ecore_dcbx_dp_protocol(p_hwfn, &data);
339
340 OSAL_MEMCPY(&p_hwfn->p_dcbx_info->results, &data,
341 sizeof(struct ecore_dcbx_results));
342
343 return ECORE_SUCCESS;
344 }
345
346 static enum _ecore_status_t
347 ecore_dcbx_copy_mib(struct ecore_hwfn *p_hwfn,
348 struct ecore_ptt *p_ptt,
349 struct ecore_dcbx_mib_meta_data *p_data,
350 enum ecore_mib_read_type type)
351 {
352 enum _ecore_status_t rc = ECORE_SUCCESS;
353 u32 prefix_seq_num, suffix_seq_num;
354 int read_count = 0;
355
356 /* The data is considered to be valid only if both sequence numbers are
357 * the same.
358 */
359 do {
360 if (type == ECORE_DCBX_REMOTE_LLDP_MIB) {
361 ecore_memcpy_from(p_hwfn, p_ptt, p_data->lldp_remote,
362 p_data->addr, p_data->size);
363 prefix_seq_num = p_data->lldp_remote->prefix_seq_num;
364 suffix_seq_num = p_data->lldp_remote->suffix_seq_num;
365 } else {
366 ecore_memcpy_from(p_hwfn, p_ptt, p_data->mib,
367 p_data->addr, p_data->size);
368 prefix_seq_num = p_data->mib->prefix_seq_num;
369 suffix_seq_num = p_data->mib->suffix_seq_num;
370 }
371 read_count++;
372
373 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
374 "mib type = %d, try count = %d prefix seq num ="
375 " %d suffix seq num = %d\n",
376 type, read_count, prefix_seq_num, suffix_seq_num);
377 } while ((prefix_seq_num != suffix_seq_num) &&
378 (read_count < ECORE_DCBX_MAX_MIB_READ_TRY));
379
380 if (read_count >= ECORE_DCBX_MAX_MIB_READ_TRY) {
381 DP_ERR(p_hwfn,
382 "MIB read err, mib type = %d, try count ="
383 " %d prefix seq num = %d suffix seq num = %d\n",
384 type, read_count, prefix_seq_num, suffix_seq_num);
385 rc = ECORE_IO;
386 }
387
388 return rc;
389 }
390
391 static void
392 ecore_dcbx_get_priority_info(struct ecore_hwfn *p_hwfn,
393 struct ecore_dcbx_app_prio *p_prio,
394 struct ecore_dcbx_results *p_results)
395 {
396 u8 val;
397
398 if (p_results->arr[DCBX_PROTOCOL_ETH].update &&
399 p_results->arr[DCBX_PROTOCOL_ETH].enable)
400 p_prio->eth = p_results->arr[DCBX_PROTOCOL_ETH].priority;
401
402 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
403 "Priorities: eth %d\n",
404 p_prio->eth);
405 }
406
407 static void
408 ecore_dcbx_get_app_data(struct ecore_hwfn *p_hwfn,
409 struct dcbx_app_priority_feature *p_app,
410 struct dcbx_app_priority_entry *p_tbl,
411 struct ecore_dcbx_params *p_params, bool ieee)
412 {
413 struct ecore_app_entry *entry;
414 u8 pri_map;
415 int i;
416
417 p_params->app_willing = ECORE_MFW_GET_FIELD(p_app->flags,
418 DCBX_APP_WILLING);
419 p_params->app_valid = ECORE_MFW_GET_FIELD(p_app->flags,
420 DCBX_APP_ENABLED);
421 p_params->app_error = ECORE_MFW_GET_FIELD(p_app->flags, DCBX_APP_ERROR);
422 p_params->num_app_entries = ECORE_MFW_GET_FIELD(p_app->flags,
423 DCBX_APP_NUM_ENTRIES);
424 for (i = 0; i < DCBX_MAX_APP_PROTOCOL; i++) {
425 entry = &p_params->app_entry[i];
426 if (ieee) {
427 u8 sf_ieee;
428 u32 val;
429
430 sf_ieee = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
431 DCBX_APP_SF_IEEE);
432 switch (sf_ieee) {
433 case DCBX_APP_SF_IEEE_RESERVED:
434 /* Old MFW */
435 val = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
436 DCBX_APP_SF);
437 entry->sf_ieee = val ?
438 ECORE_DCBX_SF_IEEE_TCP_UDP_PORT :
439 ECORE_DCBX_SF_IEEE_ETHTYPE;
440 break;
441 case DCBX_APP_SF_IEEE_ETHTYPE:
442 entry->sf_ieee = ECORE_DCBX_SF_IEEE_ETHTYPE;
443 break;
444 case DCBX_APP_SF_IEEE_TCP_PORT:
445 entry->sf_ieee = ECORE_DCBX_SF_IEEE_TCP_PORT;
446 break;
447 case DCBX_APP_SF_IEEE_UDP_PORT:
448 entry->sf_ieee = ECORE_DCBX_SF_IEEE_UDP_PORT;
449 break;
450 case DCBX_APP_SF_IEEE_TCP_UDP_PORT:
451 entry->sf_ieee =
452 ECORE_DCBX_SF_IEEE_TCP_UDP_PORT;
453 break;
454 }
455 } else {
456 entry->ethtype = !(ECORE_MFW_GET_FIELD(p_tbl[i].entry,
457 DCBX_APP_SF));
458 }
459
460 pri_map = ECORE_MFW_GET_FIELD(p_tbl[i].entry, DCBX_APP_PRI_MAP);
461 ecore_dcbx_get_app_priority(pri_map, &entry->prio);
462 entry->proto_id = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
463 DCBX_APP_PROTOCOL_ID);
464 ecore_dcbx_get_app_protocol_type(p_hwfn, p_tbl[i].entry,
465 entry->proto_id,
466 &entry->proto_type, ieee);
467 }
468
469 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
470 "APP params: willing %d, valid %d error = %d\n",
471 p_params->app_willing, p_params->app_valid,
472 p_params->app_error);
473 }
474
475 static void
476 ecore_dcbx_get_pfc_data(struct ecore_hwfn *p_hwfn,
477 u32 pfc, struct ecore_dcbx_params *p_params)
478 {
479 u8 pfc_map;
480
481 p_params->pfc.willing = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_WILLING);
482 p_params->pfc.max_tc = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_CAPS);
483 p_params->pfc.enabled = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_ENABLED);
484 pfc_map = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_PRI_EN_BITMAP);
485 p_params->pfc.prio[0] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_0);
486 p_params->pfc.prio[1] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_1);
487 p_params->pfc.prio[2] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_2);
488 p_params->pfc.prio[3] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_3);
489 p_params->pfc.prio[4] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_4);
490 p_params->pfc.prio[5] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_5);
491 p_params->pfc.prio[6] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_6);
492 p_params->pfc.prio[7] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_7);
493
494 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
495 "PFC params: willing %d, pfc_bitmap %u max_tc = %u enabled = %d\n",
496 p_params->pfc.willing, pfc_map, p_params->pfc.max_tc,
497 p_params->pfc.enabled);
498 }
499
500 static void
501 ecore_dcbx_get_ets_data(struct ecore_hwfn *p_hwfn,
502 struct dcbx_ets_feature *p_ets,
503 struct ecore_dcbx_params *p_params)
504 {
505 u32 bw_map[2], tsa_map[2], pri_map;
506 int i;
507
508 p_params->ets_willing = ECORE_MFW_GET_FIELD(p_ets->flags,
509 DCBX_ETS_WILLING);
510 p_params->ets_enabled = ECORE_MFW_GET_FIELD(p_ets->flags,
511 DCBX_ETS_ENABLED);
512 p_params->ets_cbs = ECORE_MFW_GET_FIELD(p_ets->flags, DCBX_ETS_CBS);
513 p_params->max_ets_tc = ECORE_MFW_GET_FIELD(p_ets->flags,
514 DCBX_ETS_MAX_TCS);
515 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
516 "ETS params: willing %d, enabled = %d ets_cbs %d pri_tc_tbl_0 %x max_ets_tc %d\n",
517 p_params->ets_willing, p_params->ets_enabled,
518 p_params->ets_cbs, p_ets->pri_tc_tbl[0],
519 p_params->max_ets_tc);
520
521 /* 8 bit tsa and bw data corresponding to each of the 8 TC's are
522 * encoded in a type u32 array of size 2.
523 */
524 bw_map[0] = OSAL_BE32_TO_CPU(p_ets->tc_bw_tbl[0]);
525 bw_map[1] = OSAL_BE32_TO_CPU(p_ets->tc_bw_tbl[1]);
526 tsa_map[0] = OSAL_BE32_TO_CPU(p_ets->tc_tsa_tbl[0]);
527 tsa_map[1] = OSAL_BE32_TO_CPU(p_ets->tc_tsa_tbl[1]);
528 pri_map = p_ets->pri_tc_tbl[0];
529 for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++) {
530 p_params->ets_tc_bw_tbl[i] = ((u8 *)bw_map)[i];
531 p_params->ets_tc_tsa_tbl[i] = ((u8 *)tsa_map)[i];
532 p_params->ets_pri_tc_tbl[i] = ECORE_DCBX_PRIO2TC(pri_map, i);
533 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
534 "elem %d bw_tbl %x tsa_tbl %x\n",
535 i, p_params->ets_tc_bw_tbl[i],
536 p_params->ets_tc_tsa_tbl[i]);
537 }
538 }
539
540 static void
541 ecore_dcbx_get_common_params(struct ecore_hwfn *p_hwfn,
542 struct dcbx_app_priority_feature *p_app,
543 struct dcbx_app_priority_entry *p_tbl,
544 struct dcbx_ets_feature *p_ets,
545 u32 pfc, struct ecore_dcbx_params *p_params,
546 bool ieee)
547 {
548 ecore_dcbx_get_app_data(p_hwfn, p_app, p_tbl, p_params, ieee);
549 ecore_dcbx_get_ets_data(p_hwfn, p_ets, p_params);
550 ecore_dcbx_get_pfc_data(p_hwfn, pfc, p_params);
551 }
552
553 static void
554 ecore_dcbx_get_local_params(struct ecore_hwfn *p_hwfn,
555 struct ecore_ptt *p_ptt,
556 struct ecore_dcbx_get *params)
557 {
558 struct dcbx_features *p_feat;
559
560 p_feat = &p_hwfn->p_dcbx_info->local_admin.features;
561 ecore_dcbx_get_common_params(p_hwfn, &p_feat->app,
562 p_feat->app.app_pri_tbl, &p_feat->ets,
563 p_feat->pfc, &params->local.params, false);
564 params->local.valid = true;
565 }
566
567 static void
568 ecore_dcbx_get_remote_params(struct ecore_hwfn *p_hwfn,
569 struct ecore_ptt *p_ptt,
570 struct ecore_dcbx_get *params)
571 {
572 struct dcbx_features *p_feat;
573
574 p_feat = &p_hwfn->p_dcbx_info->remote.features;
575 ecore_dcbx_get_common_params(p_hwfn, &p_feat->app,
576 p_feat->app.app_pri_tbl, &p_feat->ets,
577 p_feat->pfc, &params->remote.params,
578 false);
579 params->remote.valid = true;
580 }
581
582 static enum _ecore_status_t
583 ecore_dcbx_get_operational_params(struct ecore_hwfn *p_hwfn,
584 struct ecore_ptt *p_ptt,
585 struct ecore_dcbx_get *params)
586 {
587 struct ecore_dcbx_operational_params *p_operational;
588 struct ecore_dcbx_results *p_results;
589 struct dcbx_features *p_feat;
590 bool enabled, err;
591 u32 flags;
592 bool val;
593
594 flags = p_hwfn->p_dcbx_info->operational.flags;
595
596 /* If DCBx version is non zero, then negotiation
597 * was successfuly performed
598 */
599 p_operational = &params->operational;
600 enabled = !!(ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) !=
601 DCBX_CONFIG_VERSION_DISABLED);
602 if (!enabled) {
603 p_operational->enabled = enabled;
604 p_operational->valid = false;
605 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "Dcbx is disabled\n");
606 return ECORE_INVAL;
607 }
608
609 p_feat = &p_hwfn->p_dcbx_info->operational.features;
610 p_results = &p_hwfn->p_dcbx_info->results;
611
612 val = !!(ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) ==
613 DCBX_CONFIG_VERSION_IEEE);
614 p_operational->ieee = val;
615
616 val = !!(ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) ==
617 DCBX_CONFIG_VERSION_CEE);
618 p_operational->cee = val;
619
620 val = !!(ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) ==
621 DCBX_CONFIG_VERSION_STATIC);
622 p_operational->local = val;
623
624 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
625 "Version support: ieee %d, cee %d, static %d\n",
626 p_operational->ieee, p_operational->cee,
627 p_operational->local);
628
629 ecore_dcbx_get_common_params(p_hwfn, &p_feat->app,
630 p_feat->app.app_pri_tbl, &p_feat->ets,
631 p_feat->pfc, &params->operational.params,
632 p_operational->ieee);
633 ecore_dcbx_get_priority_info(p_hwfn, &p_operational->app_prio,
634 p_results);
635 err = ECORE_MFW_GET_FIELD(p_feat->app.flags, DCBX_APP_ERROR);
636 p_operational->err = err;
637 p_operational->enabled = enabled;
638 p_operational->valid = true;
639
640 return ECORE_SUCCESS;
641 }
642
643 static void
644 ecore_dcbx_get_dscp_params(struct ecore_hwfn *p_hwfn,
645 struct ecore_ptt *p_ptt,
646 struct ecore_dcbx_get *params)
647 {
648 struct ecore_dcbx_dscp_params *p_dscp;
649 struct dcb_dscp_map *p_dscp_map;
650 int i, j, entry;
651 u32 pri_map;
652
653 p_dscp = &params->dscp;
654 p_dscp_map = &p_hwfn->p_dcbx_info->dscp_map;
655 p_dscp->enabled = ECORE_MFW_GET_FIELD(p_dscp_map->flags,
656 DCB_DSCP_ENABLE);
657 /* MFW encodes 64 dscp entries into 8 element array of u32 entries,
658 * where each entry holds the 4bit priority map for 8 dscp entries.
659 */
660 for (i = 0, entry = 0; i < ECORE_DCBX_DSCP_SIZE / 8; i++) {
661 pri_map = OSAL_BE32_TO_CPU(p_dscp_map->dscp_pri_map[i]);
662 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "elem %d pri_map 0x%x\n",
663 entry, pri_map);
664 for (j = 0; j < ECORE_DCBX_DSCP_SIZE / 8; j++, entry++)
665 p_dscp->dscp_pri_map[entry] = (u32)(pri_map >>
666 (j * 4)) & 0xf;
667 }
668 }
669
670 static void
671 ecore_dcbx_get_local_lldp_params(struct ecore_hwfn *p_hwfn,
672 struct ecore_ptt *p_ptt,
673 struct ecore_dcbx_get *params)
674 {
675 struct lldp_config_params_s *p_local;
676
677 p_local = &p_hwfn->p_dcbx_info->lldp_local[LLDP_NEAREST_BRIDGE];
678
679 OSAL_MEMCPY(params->lldp_local.local_chassis_id,
680 p_local->local_chassis_id,
681 OSAL_ARRAY_SIZE(p_local->local_chassis_id));
682 OSAL_MEMCPY(params->lldp_local.local_port_id, p_local->local_port_id,
683 OSAL_ARRAY_SIZE(p_local->local_port_id));
684 }
685
686 static void
687 ecore_dcbx_get_remote_lldp_params(struct ecore_hwfn *p_hwfn,
688 struct ecore_ptt *p_ptt,
689 struct ecore_dcbx_get *params)
690 {
691 struct lldp_status_params_s *p_remote;
692
693 p_remote = &p_hwfn->p_dcbx_info->lldp_remote[LLDP_NEAREST_BRIDGE];
694
695 OSAL_MEMCPY(params->lldp_remote.peer_chassis_id,
696 p_remote->peer_chassis_id,
697 OSAL_ARRAY_SIZE(p_remote->peer_chassis_id));
698 OSAL_MEMCPY(params->lldp_remote.peer_port_id, p_remote->peer_port_id,
699 OSAL_ARRAY_SIZE(p_remote->peer_port_id));
700 }
701
702 static enum _ecore_status_t
703 ecore_dcbx_get_params(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
704 struct ecore_dcbx_get *p_params,
705 enum ecore_mib_read_type type)
706 {
707 enum _ecore_status_t rc = ECORE_SUCCESS;
708
709 switch (type) {
710 case ECORE_DCBX_REMOTE_MIB:
711 ecore_dcbx_get_remote_params(p_hwfn, p_ptt, p_params);
712 break;
713 case ECORE_DCBX_LOCAL_MIB:
714 ecore_dcbx_get_local_params(p_hwfn, p_ptt, p_params);
715 break;
716 case ECORE_DCBX_OPERATIONAL_MIB:
717 ecore_dcbx_get_operational_params(p_hwfn, p_ptt, p_params);
718 break;
719 case ECORE_DCBX_REMOTE_LLDP_MIB:
720 ecore_dcbx_get_remote_lldp_params(p_hwfn, p_ptt, p_params);
721 break;
722 case ECORE_DCBX_LOCAL_LLDP_MIB:
723 ecore_dcbx_get_local_lldp_params(p_hwfn, p_ptt, p_params);
724 break;
725 default:
726 DP_ERR(p_hwfn, "MIB read err, unknown mib type %d\n", type);
727 return ECORE_INVAL;
728 }
729
730 return rc;
731 }
732
733 static enum _ecore_status_t
734 ecore_dcbx_read_local_lldp_mib(struct ecore_hwfn *p_hwfn,
735 struct ecore_ptt *p_ptt)
736 {
737 struct ecore_dcbx_mib_meta_data data;
738 enum _ecore_status_t rc = ECORE_SUCCESS;
739
740 OSAL_MEM_ZERO(&data, sizeof(data));
741 data.addr = p_hwfn->mcp_info->port_addr + offsetof(struct public_port,
742 lldp_config_params);
743 data.lldp_local = p_hwfn->p_dcbx_info->lldp_local;
744 data.size = sizeof(struct lldp_config_params_s);
745 ecore_memcpy_from(p_hwfn, p_ptt, data.lldp_local, data.addr, data.size);
746
747 return rc;
748 }
749
750 static enum _ecore_status_t
751 ecore_dcbx_read_remote_lldp_mib(struct ecore_hwfn *p_hwfn,
752 struct ecore_ptt *p_ptt,
753 enum ecore_mib_read_type type)
754 {
755 struct ecore_dcbx_mib_meta_data data;
756 enum _ecore_status_t rc = ECORE_SUCCESS;
757
758 OSAL_MEM_ZERO(&data, sizeof(data));
759 data.addr = p_hwfn->mcp_info->port_addr + offsetof(struct public_port,
760 lldp_status_params);
761 data.lldp_remote = p_hwfn->p_dcbx_info->lldp_remote;
762 data.size = sizeof(struct lldp_status_params_s);
763 rc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, type);
764
765 return rc;
766 }
767
768 static enum _ecore_status_t
769 ecore_dcbx_read_operational_mib(struct ecore_hwfn *p_hwfn,
770 struct ecore_ptt *p_ptt,
771 enum ecore_mib_read_type type)
772 {
773 struct ecore_dcbx_mib_meta_data data;
774 enum _ecore_status_t rc = ECORE_SUCCESS;
775
776 OSAL_MEM_ZERO(&data, sizeof(data));
777 data.addr = p_hwfn->mcp_info->port_addr +
778 offsetof(struct public_port, operational_dcbx_mib);
779 data.mib = &p_hwfn->p_dcbx_info->operational;
780 data.size = sizeof(struct dcbx_mib);
781 rc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, type);
782
783 return rc;
784 }
785
786 static enum _ecore_status_t
787 ecore_dcbx_read_remote_mib(struct ecore_hwfn *p_hwfn,
788 struct ecore_ptt *p_ptt,
789 enum ecore_mib_read_type type)
790 {
791 struct ecore_dcbx_mib_meta_data data;
792 enum _ecore_status_t rc = ECORE_SUCCESS;
793
794 OSAL_MEM_ZERO(&data, sizeof(data));
795 data.addr = p_hwfn->mcp_info->port_addr +
796 offsetof(struct public_port, remote_dcbx_mib);
797 data.mib = &p_hwfn->p_dcbx_info->remote;
798 data.size = sizeof(struct dcbx_mib);
799 rc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, type);
800
801 return rc;
802 }
803
804 static enum _ecore_status_t
805 ecore_dcbx_read_local_mib(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
806 {
807 struct ecore_dcbx_mib_meta_data data;
808 enum _ecore_status_t rc = ECORE_SUCCESS;
809
810 OSAL_MEM_ZERO(&data, sizeof(data));
811 data.addr = p_hwfn->mcp_info->port_addr +
812 offsetof(struct public_port, local_admin_dcbx_mib);
813 data.local_admin = &p_hwfn->p_dcbx_info->local_admin;
814 data.size = sizeof(struct dcbx_local_params);
815 ecore_memcpy_from(p_hwfn, p_ptt, data.local_admin,
816 data.addr, data.size);
817
818 return rc;
819 }
820
821 static void
822 ecore_dcbx_read_dscp_mib(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
823 {
824 struct ecore_dcbx_mib_meta_data data;
825
826 data.addr = p_hwfn->mcp_info->port_addr +
827 offsetof(struct public_port, dcb_dscp_map);
828 data.dscp_map = &p_hwfn->p_dcbx_info->dscp_map;
829 data.size = sizeof(struct dcb_dscp_map);
830 ecore_memcpy_from(p_hwfn, p_ptt, data.dscp_map, data.addr, data.size);
831 }
832
833 static enum _ecore_status_t ecore_dcbx_read_mib(struct ecore_hwfn *p_hwfn,
834 struct ecore_ptt *p_ptt,
835 enum ecore_mib_read_type type)
836 {
837 enum _ecore_status_t rc = ECORE_INVAL;
838
839 switch (type) {
840 case ECORE_DCBX_OPERATIONAL_MIB:
841 ecore_dcbx_read_dscp_mib(p_hwfn, p_ptt);
842 rc = ecore_dcbx_read_operational_mib(p_hwfn, p_ptt, type);
843 break;
844 case ECORE_DCBX_REMOTE_MIB:
845 rc = ecore_dcbx_read_remote_mib(p_hwfn, p_ptt, type);
846 break;
847 case ECORE_DCBX_LOCAL_MIB:
848 rc = ecore_dcbx_read_local_mib(p_hwfn, p_ptt);
849 break;
850 case ECORE_DCBX_REMOTE_LLDP_MIB:
851 rc = ecore_dcbx_read_remote_lldp_mib(p_hwfn, p_ptt, type);
852 break;
853 case ECORE_DCBX_LOCAL_LLDP_MIB:
854 rc = ecore_dcbx_read_local_lldp_mib(p_hwfn, p_ptt);
855 break;
856 default:
857 DP_ERR(p_hwfn, "MIB read err, unknown mib type %d\n", type);
858 }
859
860 return rc;
861 }
862
863 /*
864 * Read updated MIB.
865 * Reconfigure QM and invoke PF update ramrod command if operational MIB
866 * change is detected.
867 */
868 enum _ecore_status_t
869 ecore_dcbx_mib_update_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
870 enum ecore_mib_read_type type)
871 {
872 enum _ecore_status_t rc = ECORE_SUCCESS;
873
874 rc = ecore_dcbx_read_mib(p_hwfn, p_ptt, type);
875 if (rc)
876 return rc;
877
878 if (type == ECORE_DCBX_OPERATIONAL_MIB) {
879 ecore_dcbx_get_dscp_params(p_hwfn, p_ptt,
880 &p_hwfn->p_dcbx_info->get);
881
882 rc = ecore_dcbx_process_mib_info(p_hwfn);
883 if (!rc) {
884 bool enabled;
885
886 /* reconfigure tcs of QM queues according
887 * to negotiation results
888 */
889 ecore_qm_reconf(p_hwfn, p_ptt);
890
891 /* update storm FW with negotiation results */
892 ecore_sp_pf_update(p_hwfn);
893
894 /* set eagle enigne 1 flow control workaround
895 * according to negotiation results
896 */
897 enabled = p_hwfn->p_dcbx_info->results.dcbx_enabled;
898 }
899 }
900 ecore_dcbx_get_params(p_hwfn, p_ptt, &p_hwfn->p_dcbx_info->get, type);
901
902 /* Update the DSCP to TC mapping bit if required */
903 if ((type == ECORE_DCBX_OPERATIONAL_MIB) &&
904 p_hwfn->p_dcbx_info->dscp_nig_update) {
905 ecore_wr(p_hwfn, p_ptt, NIG_REG_DSCP_TO_TC_MAP_ENABLE, 0x1);
906 p_hwfn->p_dcbx_info->dscp_nig_update = false;
907 }
908
909 OSAL_DCBX_AEN(p_hwfn, type);
910
911 return rc;
912 }
913
914 enum _ecore_status_t ecore_dcbx_info_alloc(struct ecore_hwfn *p_hwfn)
915 {
916 p_hwfn->p_dcbx_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
917 sizeof(*p_hwfn->p_dcbx_info));
918 if (!p_hwfn->p_dcbx_info) {
919 DP_NOTICE(p_hwfn, true,
920 "Failed to allocate `struct ecore_dcbx_info'");
921 return ECORE_NOMEM;
922 }
923
924 p_hwfn->p_dcbx_info->iwarp_port =
925 p_hwfn->pf_params.rdma_pf_params.iwarp_port;
926
927 return ECORE_SUCCESS;
928 }
929
930 void ecore_dcbx_info_free(struct ecore_hwfn *p_hwfn,
931 struct ecore_dcbx_info *p_dcbx_info)
932 {
933 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_dcbx_info);
934 }
935
936 static void ecore_dcbx_update_protocol_data(struct protocol_dcb_data *p_data,
937 struct ecore_dcbx_results *p_src,
938 enum dcbx_protocol_type type)
939 {
940 p_data->dcb_enable_flag = p_src->arr[type].enable;
941 p_data->dcb_priority = p_src->arr[type].priority;
942 p_data->dcb_tc = p_src->arr[type].tc;
943 p_data->dscp_enable_flag = p_src->arr[type].dscp_enable;
944 p_data->dscp_val = p_src->arr[type].dscp_val;
945 }
946
947 /* Set pf update ramrod command params */
948 void ecore_dcbx_set_pf_update_params(struct ecore_dcbx_results *p_src,
949 struct pf_update_ramrod_data *p_dest)
950 {
951 struct protocol_dcb_data *p_dcb_data;
952 u8 update_flag;
953
954 p_dest->pf_id = p_src->pf_id;
955
956 update_flag = p_src->arr[DCBX_PROTOCOL_ETH].update;
957 p_dest->update_eth_dcb_data_mode = update_flag;
958 update_flag = p_src->arr[DCBX_PROTOCOL_IWARP].update;
959 p_dest->update_iwarp_dcb_data_mode = update_flag;
960
961 p_dcb_data = &p_dest->eth_dcb_data;
962 ecore_dcbx_update_protocol_data(p_dcb_data, p_src, DCBX_PROTOCOL_ETH);
963 p_dcb_data = &p_dest->iwarp_dcb_data;
964 ecore_dcbx_update_protocol_data(p_dcb_data, p_src, DCBX_PROTOCOL_IWARP);
965 }
966
967 enum _ecore_status_t ecore_dcbx_query_params(struct ecore_hwfn *p_hwfn,
968 struct ecore_dcbx_get *p_get,
969 enum ecore_mib_read_type type)
970 {
971 struct ecore_ptt *p_ptt;
972 enum _ecore_status_t rc;
973
974 if (IS_VF(p_hwfn->p_dev))
975 return ECORE_INVAL;
976
977 p_ptt = ecore_ptt_acquire(p_hwfn);
978 if (!p_ptt) {
979 rc = ECORE_TIMEOUT;
980 DP_ERR(p_hwfn, "rc = %d\n", rc);
981 return rc;
982 }
983
984 rc = ecore_dcbx_read_mib(p_hwfn, p_ptt, type);
985 if (rc != ECORE_SUCCESS)
986 goto out;
987
988 rc = ecore_dcbx_get_params(p_hwfn, p_ptt, p_get, type);
989
990 out:
991 ecore_ptt_release(p_hwfn, p_ptt);
992 return rc;
993 }
994
995 static void
996 ecore_dcbx_set_pfc_data(struct ecore_hwfn *p_hwfn,
997 u32 *pfc, struct ecore_dcbx_params *p_params)
998 {
999 u8 pfc_map = 0;
1000 int i;
1001
1002 if (p_params->pfc.willing)
1003 *pfc |= DCBX_PFC_WILLING_MASK;
1004 else
1005 *pfc &= ~DCBX_PFC_WILLING_MASK;
1006
1007 if (p_params->pfc.enabled)
1008 *pfc |= DCBX_PFC_ENABLED_MASK;
1009 else
1010 *pfc &= ~DCBX_PFC_ENABLED_MASK;
1011
1012 *pfc &= ~DCBX_PFC_CAPS_MASK;
1013 *pfc |= (u32)p_params->pfc.max_tc << DCBX_PFC_CAPS_SHIFT;
1014
1015 for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++)
1016 if (p_params->pfc.prio[i])
1017 pfc_map |= (1 << i);
1018 *pfc &= ~DCBX_PFC_PRI_EN_BITMAP_MASK;
1019 *pfc |= (pfc_map << DCBX_PFC_PRI_EN_BITMAP_SHIFT);
1020
1021 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "pfc = 0x%x\n", *pfc);
1022 }
1023
1024 static void
1025 ecore_dcbx_set_ets_data(struct ecore_hwfn *p_hwfn,
1026 struct dcbx_ets_feature *p_ets,
1027 struct ecore_dcbx_params *p_params)
1028 {
1029 u8 *bw_map, *tsa_map;
1030 u32 val;
1031 int i;
1032
1033 if (p_params->ets_willing)
1034 p_ets->flags |= DCBX_ETS_WILLING_MASK;
1035 else
1036 p_ets->flags &= ~DCBX_ETS_WILLING_MASK;
1037
1038 if (p_params->ets_cbs)
1039 p_ets->flags |= DCBX_ETS_CBS_MASK;
1040 else
1041 p_ets->flags &= ~DCBX_ETS_CBS_MASK;
1042
1043 if (p_params->ets_enabled)
1044 p_ets->flags |= DCBX_ETS_ENABLED_MASK;
1045 else
1046 p_ets->flags &= ~DCBX_ETS_ENABLED_MASK;
1047
1048 p_ets->flags &= ~DCBX_ETS_MAX_TCS_MASK;
1049 p_ets->flags |= (u32)p_params->max_ets_tc << DCBX_ETS_MAX_TCS_SHIFT;
1050
1051 bw_map = (u8 *)&p_ets->tc_bw_tbl[0];
1052 tsa_map = (u8 *)&p_ets->tc_tsa_tbl[0];
1053 p_ets->pri_tc_tbl[0] = 0;
1054 for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++) {
1055 bw_map[i] = p_params->ets_tc_bw_tbl[i];
1056 tsa_map[i] = p_params->ets_tc_tsa_tbl[i];
1057 /* Copy the priority value to the corresponding 4 bits in the
1058 * traffic class table.
1059 */
1060 val = (((u32)p_params->ets_pri_tc_tbl[i]) << ((7 - i) * 4));
1061 p_ets->pri_tc_tbl[0] |= val;
1062 }
1063 for (i = 0; i < 2; i++) {
1064 p_ets->tc_bw_tbl[i] = OSAL_CPU_TO_BE32(p_ets->tc_bw_tbl[i]);
1065 p_ets->tc_tsa_tbl[i] = OSAL_CPU_TO_BE32(p_ets->tc_tsa_tbl[i]);
1066 }
1067
1068 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1069 "flags = 0x%x pri_tc = 0x%x tc_bwl[] = {0x%x, 0x%x} tc_tsa = {0x%x, 0x%x}\n",
1070 p_ets->flags, p_ets->pri_tc_tbl[0], p_ets->tc_bw_tbl[0],
1071 p_ets->tc_bw_tbl[1], p_ets->tc_tsa_tbl[0],
1072 p_ets->tc_tsa_tbl[1]);
1073 }
1074
1075 static void
1076 ecore_dcbx_set_app_data(struct ecore_hwfn *p_hwfn,
1077 struct dcbx_app_priority_feature *p_app,
1078 struct ecore_dcbx_params *p_params, bool ieee)
1079 {
1080 u32 *entry;
1081 int i;
1082
1083 if (p_params->app_willing)
1084 p_app->flags |= DCBX_APP_WILLING_MASK;
1085 else
1086 p_app->flags &= ~DCBX_APP_WILLING_MASK;
1087
1088 if (p_params->app_valid)
1089 p_app->flags |= DCBX_APP_ENABLED_MASK;
1090 else
1091 p_app->flags &= ~DCBX_APP_ENABLED_MASK;
1092
1093 p_app->flags &= ~DCBX_APP_NUM_ENTRIES_MASK;
1094 p_app->flags |= (u32)p_params->num_app_entries <<
1095 DCBX_APP_NUM_ENTRIES_SHIFT;
1096
1097 for (i = 0; i < DCBX_MAX_APP_PROTOCOL; i++) {
1098 entry = &p_app->app_pri_tbl[i].entry;
1099 *entry = 0;
1100 if (ieee) {
1101 *entry &= ~(DCBX_APP_SF_IEEE_MASK | DCBX_APP_SF_MASK);
1102 switch (p_params->app_entry[i].sf_ieee) {
1103 case ECORE_DCBX_SF_IEEE_ETHTYPE:
1104 *entry |= ((u32)DCBX_APP_SF_IEEE_ETHTYPE <<
1105 DCBX_APP_SF_IEEE_SHIFT);
1106 *entry |= ((u32)DCBX_APP_SF_ETHTYPE <<
1107 DCBX_APP_SF_SHIFT);
1108 break;
1109 case ECORE_DCBX_SF_IEEE_TCP_PORT:
1110 *entry |= ((u32)DCBX_APP_SF_IEEE_TCP_PORT <<
1111 DCBX_APP_SF_IEEE_SHIFT);
1112 *entry |= ((u32)DCBX_APP_SF_PORT <<
1113 DCBX_APP_SF_SHIFT);
1114 break;
1115 case ECORE_DCBX_SF_IEEE_UDP_PORT:
1116 *entry |= ((u32)DCBX_APP_SF_IEEE_UDP_PORT <<
1117 DCBX_APP_SF_IEEE_SHIFT);
1118 *entry |= ((u32)DCBX_APP_SF_PORT <<
1119 DCBX_APP_SF_SHIFT);
1120 break;
1121 case ECORE_DCBX_SF_IEEE_TCP_UDP_PORT:
1122 *entry |= (u32)DCBX_APP_SF_IEEE_TCP_UDP_PORT <<
1123 DCBX_APP_SF_IEEE_SHIFT;
1124 *entry |= ((u32)DCBX_APP_SF_PORT <<
1125 DCBX_APP_SF_SHIFT);
1126 break;
1127 }
1128 } else {
1129 *entry &= ~DCBX_APP_SF_MASK;
1130 if (p_params->app_entry[i].ethtype)
1131 *entry |= ((u32)DCBX_APP_SF_ETHTYPE <<
1132 DCBX_APP_SF_SHIFT);
1133 else
1134 *entry |= ((u32)DCBX_APP_SF_PORT <<
1135 DCBX_APP_SF_SHIFT);
1136 }
1137 *entry &= ~DCBX_APP_PROTOCOL_ID_MASK;
1138 *entry |= ((u32)p_params->app_entry[i].proto_id <<
1139 DCBX_APP_PROTOCOL_ID_SHIFT);
1140 *entry &= ~DCBX_APP_PRI_MAP_MASK;
1141 *entry |= ((u32)(p_params->app_entry[i].prio) <<
1142 DCBX_APP_PRI_MAP_SHIFT);
1143 }
1144
1145 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "flags = 0x%x\n", p_app->flags);
1146 }
1147
1148 static enum _ecore_status_t
1149 ecore_dcbx_set_local_params(struct ecore_hwfn *p_hwfn,
1150 struct dcbx_local_params *local_admin,
1151 struct ecore_dcbx_set *params)
1152 {
1153 bool ieee = false;
1154
1155 local_admin->flags = 0;
1156 OSAL_MEMCPY(&local_admin->features,
1157 &p_hwfn->p_dcbx_info->operational.features,
1158 sizeof(local_admin->features));
1159
1160 if (params->enabled) {
1161 local_admin->config = params->ver_num;
1162 ieee = !!(params->ver_num & DCBX_CONFIG_VERSION_IEEE);
1163 } else {
1164 local_admin->config = DCBX_CONFIG_VERSION_DISABLED;
1165 }
1166
1167 if (params->override_flags & ECORE_DCBX_OVERRIDE_PFC_CFG)
1168 ecore_dcbx_set_pfc_data(p_hwfn, &local_admin->features.pfc,
1169 &params->config.params);
1170
1171 if (params->override_flags & ECORE_DCBX_OVERRIDE_ETS_CFG)
1172 ecore_dcbx_set_ets_data(p_hwfn, &local_admin->features.ets,
1173 &params->config.params);
1174
1175 if (params->override_flags & ECORE_DCBX_OVERRIDE_APP_CFG)
1176 ecore_dcbx_set_app_data(p_hwfn, &local_admin->features.app,
1177 &params->config.params, ieee);
1178
1179 return ECORE_SUCCESS;
1180 }
1181
1182 static enum _ecore_status_t
1183 ecore_dcbx_set_dscp_params(struct ecore_hwfn *p_hwfn,
1184 struct dcb_dscp_map *p_dscp_map,
1185 struct ecore_dcbx_set *p_params)
1186 {
1187 int entry, i, j;
1188 u32 val;
1189
1190 OSAL_MEMCPY(p_dscp_map, &p_hwfn->p_dcbx_info->dscp_map,
1191 sizeof(*p_dscp_map));
1192
1193 p_dscp_map->flags &= ~DCB_DSCP_ENABLE_MASK;
1194 if (p_params->dscp.enabled)
1195 p_dscp_map->flags |= DCB_DSCP_ENABLE_MASK;
1196
1197 for (i = 0, entry = 0; i < 8; i++) {
1198 val = 0;
1199 for (j = 0; j < 8; j++, entry++)
1200 val |= (((u32)p_params->dscp.dscp_pri_map[entry]) <<
1201 (j * 4));
1202
1203 p_dscp_map->dscp_pri_map[i] = OSAL_CPU_TO_BE32(val);
1204 }
1205
1206 p_hwfn->p_dcbx_info->dscp_nig_update = true;
1207
1208 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "flags = 0x%x\n", p_dscp_map->flags);
1209
1210 return ECORE_SUCCESS;
1211 }
1212
1213 enum _ecore_status_t ecore_dcbx_config_params(struct ecore_hwfn *p_hwfn,
1214 struct ecore_ptt *p_ptt,
1215 struct ecore_dcbx_set *params,
1216 bool hw_commit)
1217 {
1218 struct dcbx_local_params local_admin;
1219 struct ecore_dcbx_mib_meta_data data;
1220 struct dcb_dscp_map dscp_map;
1221 u32 resp = 0, param = 0;
1222 enum _ecore_status_t rc = ECORE_SUCCESS;
1223
1224 if (!hw_commit) {
1225 OSAL_MEMCPY(&p_hwfn->p_dcbx_info->set, params,
1226 sizeof(p_hwfn->p_dcbx_info->set));
1227 return ECORE_SUCCESS;
1228 }
1229
1230 /* clear set-parmas cache */
1231 OSAL_MEMSET(&p_hwfn->p_dcbx_info->set, 0,
1232 sizeof(struct ecore_dcbx_set));
1233
1234 OSAL_MEMSET(&local_admin, 0, sizeof(local_admin));
1235 ecore_dcbx_set_local_params(p_hwfn, &local_admin, params);
1236
1237 data.addr = p_hwfn->mcp_info->port_addr +
1238 offsetof(struct public_port, local_admin_dcbx_mib);
1239 data.local_admin = &local_admin;
1240 data.size = sizeof(struct dcbx_local_params);
1241 ecore_memcpy_to(p_hwfn, p_ptt, data.addr, data.local_admin, data.size);
1242
1243 if (params->override_flags & ECORE_DCBX_OVERRIDE_DSCP_CFG) {
1244 OSAL_MEMSET(&dscp_map, 0, sizeof(dscp_map));
1245 ecore_dcbx_set_dscp_params(p_hwfn, &dscp_map, params);
1246
1247 data.addr = p_hwfn->mcp_info->port_addr +
1248 offsetof(struct public_port, dcb_dscp_map);
1249 data.dscp_map = &dscp_map;
1250 data.size = sizeof(struct dcb_dscp_map);
1251 ecore_memcpy_to(p_hwfn, p_ptt, data.addr, data.dscp_map,
1252 data.size);
1253 }
1254
1255 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_DCBX,
1256 1 << DRV_MB_PARAM_LLDP_SEND_SHIFT, &resp, &param);
1257 if (rc != ECORE_SUCCESS) {
1258 DP_NOTICE(p_hwfn, false,
1259 "Failed to send DCBX update request\n");
1260 return rc;
1261 }
1262
1263 return rc;
1264 }
1265
1266 enum _ecore_status_t ecore_dcbx_get_config_params(struct ecore_hwfn *p_hwfn,
1267 struct ecore_dcbx_set *params)
1268 {
1269 struct ecore_dcbx_get *dcbx_info;
1270 int rc;
1271
1272 if (p_hwfn->p_dcbx_info->set.config.valid) {
1273 OSAL_MEMCPY(params, &p_hwfn->p_dcbx_info->set,
1274 sizeof(struct ecore_dcbx_set));
1275 return ECORE_SUCCESS;
1276 }
1277
1278 dcbx_info = OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,
1279 sizeof(*dcbx_info));
1280 if (!dcbx_info) {
1281 DP_ERR(p_hwfn, "Failed to allocate struct ecore_dcbx_info\n");
1282 return ECORE_NOMEM;
1283 }
1284
1285 OSAL_MEMSET(dcbx_info, 0, sizeof(*dcbx_info));
1286 rc = ecore_dcbx_query_params(p_hwfn, dcbx_info,
1287 ECORE_DCBX_OPERATIONAL_MIB);
1288 if (rc) {
1289 OSAL_FREE(p_hwfn->p_dev, dcbx_info);
1290 return rc;
1291 }
1292 p_hwfn->p_dcbx_info->set.override_flags = 0;
1293
1294 p_hwfn->p_dcbx_info->set.ver_num = DCBX_CONFIG_VERSION_DISABLED;
1295 if (dcbx_info->operational.cee)
1296 p_hwfn->p_dcbx_info->set.ver_num |= DCBX_CONFIG_VERSION_CEE;
1297 if (dcbx_info->operational.ieee)
1298 p_hwfn->p_dcbx_info->set.ver_num |= DCBX_CONFIG_VERSION_IEEE;
1299 if (dcbx_info->operational.local)
1300 p_hwfn->p_dcbx_info->set.ver_num |= DCBX_CONFIG_VERSION_STATIC;
1301
1302 p_hwfn->p_dcbx_info->set.enabled = dcbx_info->operational.enabled;
1303 OSAL_MEMCPY(&p_hwfn->p_dcbx_info->set.config.params,
1304 &dcbx_info->operational.params,
1305 sizeof(struct ecore_dcbx_admin_params));
1306 p_hwfn->p_dcbx_info->set.config.valid = true;
1307
1308 OSAL_MEMCPY(params, &p_hwfn->p_dcbx_info->set,
1309 sizeof(struct ecore_dcbx_set));
1310
1311 OSAL_FREE(p_hwfn->p_dev, dcbx_info);
1312
1313 return ECORE_SUCCESS;
1314 }
Ceph