ceph/src/seastar/dpdk/drivers/net/qede/base/ecore_int_api.h

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #ifndef __ECORE_INT_API_H__
  10 #define __ECORE_INT_API_H__
  11
  12 #ifndef __EXTRACT__LINUX__
  13 #define ECORE_SB_IDX            0x0002
  14
  15 #define RX_PI           0
  16 #define TX_PI(tc)       (RX_PI + 1 + tc)
  17
  18 #ifndef ECORE_INT_MODE
  19 #define ECORE_INT_MODE
  20 enum ecore_int_mode {
  21         ECORE_INT_MODE_INTA,
  22         ECORE_INT_MODE_MSIX,
  23         ECORE_INT_MODE_MSI,
  24         ECORE_INT_MODE_POLL,
  25 };
  26 #endif
  27
  28 struct ecore_sb_info {
  29         struct status_block *sb_virt;
  30         dma_addr_t sb_phys;
  31         u32 sb_ack;             /* Last given ack */
  32         u16 igu_sb_id;
  33         void OSAL_IOMEM *igu_addr;
  34         u8 flags;
  35 #define ECORE_SB_INFO_INIT      0x1
  36 #define ECORE_SB_INFO_SETUP     0x2
  37
  38 #ifdef ECORE_CONFIG_DIRECT_HWFN
  39         struct ecore_hwfn *p_hwfn;
  40 #endif
  41         struct ecore_dev *p_dev;
  42 };
  43
  44 struct ecore_sb_info_dbg {
  45         u32 igu_prod;
  46         u32 igu_cons;
  47         u16 pi[PIS_PER_SB];
  48 };
  49
  50 struct ecore_sb_cnt_info {
  51         int sb_cnt;
  52         int sb_iov_cnt;
  53         int sb_free_blk;
  54 };
  55
  56 static OSAL_INLINE u16 ecore_sb_update_sb_idx(struct ecore_sb_info *sb_info)
  57 {
  58         u32 prod = 0;
  59         u16 rc = 0;
  60
  61         /* barrier(); status block is written to by the chip */
  62         /* FIXME: need some sort of barrier. */
  63         prod = OSAL_LE32_TO_CPU(sb_info->sb_virt->prod_index) &
  64             STATUS_BLOCK_PROD_INDEX_MASK;
  65         if (sb_info->sb_ack != prod) {
  66                 sb_info->sb_ack = prod;
  67                 rc |= ECORE_SB_IDX;
  68         }
  69
  70         OSAL_MMIOWB(sb_info->p_dev);
  71         return rc;
  72 }
  73
  74 /**
  75  *
  76  * @brief This function creates an update command for interrupts that is
  77  *        written to the IGU.
  78  *
  79  * @param sb_info       - This is the structure allocated and
  80  *         initialized per status block. Assumption is
  81  *         that it was initialized using ecore_sb_init
  82  * @param int_cmd       - Enable/Disable/Nop
  83  * @param upd_flg       - whether igu consumer should be
  84  *         updated.
  85  *
  86  * @return OSAL_INLINE void
  87  */
  88 static OSAL_INLINE void ecore_sb_ack(struct ecore_sb_info *sb_info,
  89                                      enum igu_int_cmd int_cmd, u8 upd_flg)
  90 {
  91         struct igu_prod_cons_update igu_ack = { 0 };
  92
  93         igu_ack.sb_id_and_flags =
  94             ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
  95              (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
  96              (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
  97              (IGU_SEG_ACCESS_REG << IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
  98
  99 #ifdef ECORE_CONFIG_DIRECT_HWFN
 100         DIRECT_REG_WR(sb_info->p_hwfn, sb_info->igu_addr,
 101                       igu_ack.sb_id_and_flags);
 102 #else
 103         DIRECT_REG_WR(OSAL_NULL, sb_info->igu_addr, igu_ack.sb_id_and_flags);
 104 #endif
 105         /* Both segments (interrupts & acks) are written to same place address;
 106          * Need to guarantee all commands will be received (in-order) by HW.
 107          */
 108         OSAL_MMIOWB(sb_info->p_dev);
 109         OSAL_BARRIER(sb_info->p_dev);
 110 }
 111
 112 #ifdef ECORE_CONFIG_DIRECT_HWFN
 113 static OSAL_INLINE void __internal_ram_wr(struct ecore_hwfn *p_hwfn,
 114                                           void OSAL_IOMEM *addr,
 115                                           int size, u32 *data)
 116 #else
 117 static OSAL_INLINE void __internal_ram_wr(__rte_unused void *p_hwfn,
 118                                           void OSAL_IOMEM *addr,
 119                                           int size, u32 *data)
 120 #endif
 121 {
 122         unsigned int i;
 123
 124         for (i = 0; i < size / sizeof(*data); i++)
 125                 DIRECT_REG_WR(p_hwfn, &((u32 OSAL_IOMEM *)addr)[i], data[i]);
 126 }
 127
 128 #ifdef ECORE_CONFIG_DIRECT_HWFN
 129 static OSAL_INLINE void __internal_ram_wr_relaxed(struct ecore_hwfn *p_hwfn,
 130                                                   void OSAL_IOMEM * addr,
 131                                                   int size, u32 *data)
 132 #else
 133 static OSAL_INLINE void __internal_ram_wr_relaxed(__rte_unused void *p_hwfn,
 134                                                   void OSAL_IOMEM * addr,
 135                                                   int size, u32 *data)
 136 #endif
 137 {
 138         unsigned int i;
 139
 140         for (i = 0; i < size / sizeof(*data); i++)
 141                 DIRECT_REG_WR_RELAXED(p_hwfn, &((u32 OSAL_IOMEM *)addr)[i],
 142                                       data[i]);
 143 }
 144
 145 #ifdef ECORE_CONFIG_DIRECT_HWFN
 146 static OSAL_INLINE void internal_ram_wr(struct ecore_hwfn *p_hwfn,
 147                                                 void OSAL_IOMEM * addr,
 148                                                 int size, u32 *data)
 149 {
 150         __internal_ram_wr_relaxed(p_hwfn, addr, size, data);
 151 }
 152 #else
 153 static OSAL_INLINE void internal_ram_wr(void OSAL_IOMEM *addr,
 154                                                 int size, u32 *data)
 155 {
 156         __internal_ram_wr_relaxed(OSAL_NULL, addr, size, data);
 157 }
 158 #endif
 159
 160 #endif
 161
 162 struct ecore_hwfn;
 163 struct ecore_ptt;
 164
 165 enum ecore_coalescing_fsm {
 166         ECORE_COAL_RX_STATE_MACHINE,
 167         ECORE_COAL_TX_STATE_MACHINE
 168 };
 169
 170 /**
 171  * @brief ecore_int_cau_conf_pi - configure cau for a given
 172  *        status block
 173  *
 174  * @param p_hwfn
 175  * @param p_ptt
 176  * @param igu_sb_id
 177  * @param pi_index
 178  * @param state
 179  * @param timeset
 180  */
 181 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
 182                            struct ecore_ptt *p_ptt,
 183                            u16 igu_sb_id,
 184                            u32 pi_index,
 185                            enum ecore_coalescing_fsm coalescing_fsm,
 186                            u8 timeset);
 187
 188 /**
 189  *
 190  * @brief ecore_int_igu_enable_int - enable device interrupts
 191  *
 192  * @param p_hwfn
 193  * @param p_ptt
 194  * @param int_mode - interrupt mode to use
 195  */
 196 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
 197                               struct ecore_ptt *p_ptt,
 198                               enum ecore_int_mode int_mode);
 199
 200 /**
 201  *
 202  * @brief ecore_int_igu_disable_int - disable device interrupts
 203  *
 204  * @param p_hwfn
 205  * @param p_ptt
 206  */
 207 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
 208                                struct ecore_ptt *p_ptt);
 209
 210 /**
 211  *
 212  * @brief ecore_int_igu_read_sisr_reg - Reads the single isr multiple dpc
 213  *        register from igu.
 214  *
 215  * @param p_hwfn
 216  *
 217  * @return u64
 218  */
 219 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn);
 220
 221 #define ECORE_SP_SB_ID 0xffff
 222 /**
 223  * @brief ecore_int_sb_init - Initializes the sb_info structure.
 224  *
 225  * once the structure is initialized it can be passed to sb related functions.
 226  *
 227  * @param p_hwfn
 228  * @param p_ptt
 229  * @param sb_info       points to an uninitialized (but
 230  *                      allocated) sb_info structure
 231  * @param sb_virt_addr
 232  * @param sb_phy_addr
 233  * @param sb_id         the sb_id to be used (zero based in driver)
 234  *                      should use ECORE_SP_SB_ID for SP Status block
 235  *
 236  * @return enum _ecore_status_t
 237  */
 238 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
 239                                        struct ecore_ptt *p_ptt,
 240                                        struct ecore_sb_info *sb_info,
 241                                        void *sb_virt_addr,
 242                                        dma_addr_t sb_phy_addr, u16 sb_id);
 243 /**
 244  * @brief ecore_int_sb_setup - Setup the sb.
 245  *
 246  * @param p_hwfn
 247  * @param p_ptt
 248  * @param sb_info       initialized sb_info structure
 249  */
 250 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn,
 251                         struct ecore_ptt *p_ptt, struct ecore_sb_info *sb_info);
 252
 253 /**
 254  * @brief ecore_int_sb_release - releases the sb_info structure.
 255  *
 256  * once the structure is released, it's memory can be freed
 257  *
 258  * @param p_hwfn
 259  * @param sb_info       points to an allocated sb_info structure
 260  * @param sb_id         the sb_id to be used (zero based in driver)
 261  *                      should never be equal to ECORE_SP_SB_ID
 262  *                      (SP Status block)
 263  *
 264  * @return enum _ecore_status_t
 265  */
 266 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
 267                                           struct ecore_sb_info *sb_info,
 268                                           u16 sb_id);
 269
 270 /**
 271  * @brief ecore_int_sp_dpc - To be called when an interrupt is received on the
 272  *        default status block.
 273  *
 274  * @param p_hwfn - pointer to hwfn
 275  *
 276  */
 277 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie);
 278
 279 /**
 280  * @brief ecore_int_get_num_sbs - get the number of status
 281  *        blocks configured for this funciton in the igu.
 282  *
 283  * @param p_hwfn
 284  * @param p_sb_cnt_info
 285  *
 286  * @return
 287  */
 288 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
 289                            struct ecore_sb_cnt_info *p_sb_cnt_info);
 290
 291 /**
 292  * @brief ecore_int_disable_post_isr_release - performs the cleanup post ISR
 293  *        release. The API need to be called after releasing all slowpath IRQs
 294  *        of the device.
 295  *
 296  * @param p_dev
 297  *
 298  */
 299 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev);
 300
 301 /**
 302  * @brief ecore_int_attn_clr_enable - sets whether the general behavior is
 303  *        preventing attentions from being reasserted, or following the
 304  *        attributes of the specific attention.
 305  *
 306  * @param p_dev
 307  * @param clr_enable
 308  *
 309  */
 310 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable);
 311
 312 /**
 313  * @brief Read debug information regarding a given SB.
 314  *
 315  * @param p_hwfn
 316  * @param p_ptt
 317  * @param p_sb - point to Status block for which we want to get info.
 318  * @param p_info - pointer to struct to fill with information regarding SB.
 319  *
 320  * @return ECORE_SUCCESS if pointer is filled; failure otherwise.
 321  */
 322 enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
 323                                           struct ecore_ptt *p_ptt,
 324                                           struct ecore_sb_info *p_sb,
 325                                           struct ecore_sb_info_dbg *p_info);
 326
 327 #endif