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1 /*
2 * Copyright (c) 2016 QLogic Corporation.
3 * All rights reserved.
4 * www.qlogic.com
5 *
6 * See LICENSE.qede_pmd for copyright and licensing details.
7 */
8
9 #ifndef __ECORE_MCP_API_H__
10 #define __ECORE_MCP_API_H__
11
12 #include "ecore_status.h"
13
14 struct ecore_mcp_link_speed_params {
15 bool autoneg;
16 u32 advertised_speeds; /* bitmask of DRV_SPEED_CAPABILITY */
17 u32 forced_speed; /* In Mb/s */
18 };
19
20 struct ecore_mcp_link_pause_params {
21 bool autoneg;
22 bool forced_rx;
23 bool forced_tx;
24 };
25
26 struct ecore_mcp_link_params {
27 struct ecore_mcp_link_speed_params speed;
28 struct ecore_mcp_link_pause_params pause;
29 u32 loopback_mode; /* in PMM_LOOPBACK values */
30 };
31
32 struct ecore_mcp_link_capabilities {
33 u32 speed_capabilities;
34 bool default_speed_autoneg; /* In Mb/s */
35 u32 default_speed; /* In Mb/s */
36 };
37
38 struct ecore_mcp_link_state {
39 bool link_up;
40
41 u32 line_speed; /* In Mb/s */
42 u32 min_pf_rate; /* In Mb/s */
43 u32 speed; /* In Mb/s */
44 bool full_duplex;
45
46 bool an;
47 bool an_complete;
48 bool parallel_detection;
49 bool pfc_enabled;
50
51 #define ECORE_LINK_PARTNER_SPEED_1G_HD (1 << 0)
52 #define ECORE_LINK_PARTNER_SPEED_1G_FD (1 << 1)
53 #define ECORE_LINK_PARTNER_SPEED_10G (1 << 2)
54 #define ECORE_LINK_PARTNER_SPEED_20G (1 << 3)
55 #define ECORE_LINK_PARTNER_SPEED_25G (1 << 4)
56 #define ECORE_LINK_PARTNER_SPEED_40G (1 << 5)
57 #define ECORE_LINK_PARTNER_SPEED_50G (1 << 6)
58 #define ECORE_LINK_PARTNER_SPEED_100G (1 << 7)
59 u32 partner_adv_speed;
60
61 bool partner_tx_flow_ctrl_en;
62 bool partner_rx_flow_ctrl_en;
63
64 #define ECORE_LINK_PARTNER_SYMMETRIC_PAUSE (1)
65 #define ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE (2)
66 #define ECORE_LINK_PARTNER_BOTH_PAUSE (3)
67 u8 partner_adv_pause;
68
69 bool sfp_tx_fault;
70 };
71
72 struct ecore_mcp_function_info {
73 u8 pause_on_host;
74
75 enum ecore_pci_personality protocol;
76
77 u8 bandwidth_min;
78 u8 bandwidth_max;
79
80 u8 mac[ETH_ALEN];
81
82 u64 wwn_port;
83 u64 wwn_node;
84
85 #define ECORE_MCP_VLAN_UNSET (0xffff)
86 u16 ovlan;
87
88 u16 mtu;
89 };
90
91 struct ecore_mcp_nvm_common {
92 u32 offset;
93 u32 param;
94 u32 resp;
95 u32 cmd;
96 };
97
98 struct ecore_mcp_nvm_rd {
99 u32 *buf_size;
100 u32 *buf;
101 };
102
103 struct ecore_mcp_nvm_wr {
104 u32 buf_size;
105 u32 *buf;
106 };
107
108 struct ecore_mcp_nvm_params {
109 #define ECORE_MCP_CMD (1 << 0)
110 #define ECORE_MCP_NVM_RD (1 << 1)
111 #define ECORE_MCP_NVM_WR (1 << 2)
112 u8 type;
113
114 struct ecore_mcp_nvm_common nvm_common;
115
116 union {
117 struct ecore_mcp_nvm_rd nvm_rd;
118 struct ecore_mcp_nvm_wr nvm_wr;
119 };
120 };
121
122 #ifndef __EXTRACT__LINUX__
123 enum ecore_nvm_images {
124 ECORE_NVM_IMAGE_ISCSI_CFG,
125 ECORE_NVM_IMAGE_FCOE_CFG,
126 };
127 #endif
128
129 struct ecore_mcp_drv_version {
130 u32 version;
131 u8 name[MCP_DRV_VER_STR_SIZE - 4];
132 };
133
134 struct ecore_mcp_lan_stats {
135 u64 ucast_rx_pkts;
136 u64 ucast_tx_pkts;
137 u32 fcs_err;
138 };
139
140 #ifndef ECORE_PROTO_STATS
141 #define ECORE_PROTO_STATS
142 struct ecore_mcp_fcoe_stats {
143 u64 rx_pkts;
144 u64 tx_pkts;
145 u32 fcs_err;
146 u32 login_failure;
147 };
148
149 struct ecore_mcp_iscsi_stats {
150 u64 rx_pdus;
151 u64 tx_pdus;
152 u64 rx_bytes;
153 u64 tx_bytes;
154 };
155
156 struct ecore_mcp_rdma_stats {
157 u64 rx_pkts;
158 u64 tx_pkts;
159 u64 rx_bytes;
160 u64 tx_byts;
161 };
162
163 enum ecore_mcp_protocol_type {
164 ECORE_MCP_LAN_STATS,
165 ECORE_MCP_FCOE_STATS,
166 ECORE_MCP_ISCSI_STATS,
167 ECORE_MCP_RDMA_STATS
168 };
169
170 union ecore_mcp_protocol_stats {
171 struct ecore_mcp_lan_stats lan_stats;
172 struct ecore_mcp_fcoe_stats fcoe_stats;
173 struct ecore_mcp_iscsi_stats iscsi_stats;
174 struct ecore_mcp_rdma_stats rdma_stats;
175 };
176 #endif
177
178 enum ecore_ov_client {
179 ECORE_OV_CLIENT_DRV,
180 ECORE_OV_CLIENT_USER,
181 ECORE_OV_CLIENT_VENDOR_SPEC
182 };
183
184 enum ecore_ov_driver_state {
185 ECORE_OV_DRIVER_STATE_NOT_LOADED,
186 ECORE_OV_DRIVER_STATE_DISABLED,
187 ECORE_OV_DRIVER_STATE_ACTIVE
188 };
189
190 #define ECORE_MAX_NPIV_ENTRIES 128
191 #define ECORE_WWN_SIZE 8
192 struct ecore_fc_npiv_tbl {
193 u32 count;
194 u8 wwpn[ECORE_MAX_NPIV_ENTRIES][ECORE_WWN_SIZE];
195 u8 wwnn[ECORE_MAX_NPIV_ENTRIES][ECORE_WWN_SIZE];
196 };
197
198 #ifndef __EXTRACT__LINUX__
199 enum ecore_led_mode {
200 ECORE_LED_MODE_OFF,
201 ECORE_LED_MODE_ON,
202 ECORE_LED_MODE_RESTORE
203 };
204 #endif
205
206 struct ecore_temperature_sensor {
207 u8 sensor_location;
208 u8 threshold_high;
209 u8 critical;
210 u8 current_temp;
211 };
212
213 #define ECORE_MAX_NUM_OF_SENSORS 7
214 struct ecore_temperature_info {
215 u32 num_sensors;
216 struct ecore_temperature_sensor sensors[ECORE_MAX_NUM_OF_SENSORS];
217 };
218
219 enum ecore_mba_img_idx {
220 ECORE_MBA_LEGACY_IDX,
221 ECORE_MBA_PCI3CLP_IDX,
222 ECORE_MBA_PCI3_IDX,
223 ECORE_MBA_FCODE_IDX,
224 ECORE_EFI_X86_IDX,
225 ECORE_EFI_IPF_IDX,
226 ECORE_EFI_EBC_IDX,
227 ECORE_EFI_X64_IDX,
228 ECORE_MAX_NUM_OF_ROMIMG
229 };
230
231 struct ecore_mba_vers {
232 u32 mba_vers[ECORE_MAX_NUM_OF_ROMIMG];
233 };
234
235 enum ecore_mfw_tlv_type {
236 ECORE_MFW_TLV_GENERIC = 0x1, /* Core driver TLVs */
237 ECORE_MFW_TLV_ETH = 0x2, /* L2 driver TLVs */
238 ECORE_MFW_TLV_FCOE = 0x4, /* FCoE protocol TLVs */
239 ECORE_MFW_TLV_ISCSI = 0x8, /* SCSI protocol TLVs */
240 ECORE_MFW_TLV_MAX = 0x16,
241 };
242
243 struct ecore_mfw_tlv_generic {
244 u16 feat_flags;
245 bool feat_flags_set;
246 u64 local_mac;
247 bool local_mac_set;
248 u64 additional_mac1;
249 bool additional_mac1_set;
250 u64 additional_mac2;
251 bool additional_mac2_set;
252 u8 drv_state;
253 bool drv_state_set;
254 u8 pxe_progress;
255 bool pxe_progress_set;
256 u64 rx_frames;
257 bool rx_frames_set;
258 u64 rx_bytes;
259 bool rx_bytes_set;
260 u64 tx_frames;
261 bool tx_frames_set;
262 u64 tx_bytes;
263 bool tx_bytes_set;
264 };
265
266 struct ecore_mfw_tlv_eth {
267 u16 lso_maxoff_size;
268 bool lso_maxoff_size_set;
269 u16 lso_minseg_size;
270 bool lso_minseg_size_set;
271 u8 prom_mode;
272 bool prom_mode_set;
273 u16 tx_descr_size;
274 bool tx_descr_size_set;
275 u16 rx_descr_size;
276 bool rx_descr_size_set;
277 u16 netq_count;
278 bool netq_count_set;
279 u32 tcp4_offloads;
280 bool tcp4_offloads_set;
281 u32 tcp6_offloads;
282 bool tcp6_offloads_set;
283 u16 tx_descr_qdepth;
284 bool tx_descr_qdepth_set;
285 u16 rx_descr_qdepth;
286 bool rx_descr_qdepth_set;
287 u8 iov_offload;
288 bool iov_offload_set;
289 u8 txqs_empty;
290 bool txqs_empty_set;
291 u8 rxqs_empty;
292 bool rxqs_empty_set;
293 u8 num_txqs_full;
294 bool num_txqs_full_set;
295 u8 num_rxqs_full;
296 bool num_rxqs_full_set;
297 };
298
299 struct ecore_mfw_tlv_fcoe {
300 u8 scsi_timeout;
301 bool scsi_timeout_set;
302 u32 rt_tov;
303 bool rt_tov_set;
304 u32 ra_tov;
305 bool ra_tov_set;
306 u32 ed_tov;
307 bool ed_tov_set;
308 u32 cr_tov;
309 bool cr_tov_set;
310 u8 boot_type;
311 bool boot_type_set;
312 u8 npiv_state;
313 bool npiv_state_set;
314 u32 num_npiv_ids;
315 bool num_npiv_ids_set;
316 u8 switch_name[8];
317 bool switch_name_set;
318 u16 switch_portnum;
319 bool switch_portnum_set;
320 u8 switch_portid[3];
321 bool switch_portid_set;
322 u8 vendor_name[8];
323 bool vendor_name_set;
324 u8 switch_model[8];
325 bool switch_model_set;
326 u8 switch_fw_version[8];
327 bool switch_fw_version_set;
328 u8 qos_pri;
329 bool qos_pri_set;
330 u8 port_alias[3];
331 bool port_alias_set;
332 u8 port_state;
333 bool port_state_set;
334 u16 fip_tx_descr_size;
335 bool fip_tx_descr_size_set;
336 u16 fip_rx_descr_size;
337 bool fip_rx_descr_size_set;
338 u16 link_failures;
339 bool link_failures_set;
340 u8 fcoe_boot_progress;
341 bool fcoe_boot_progress_set;
342 u64 rx_bcast;
343 bool rx_bcast_set;
344 u64 tx_bcast;
345 bool tx_bcast_set;
346 u16 fcoe_txq_depth;
347 bool fcoe_txq_depth_set;
348 u16 fcoe_rxq_depth;
349 bool fcoe_rxq_depth_set;
350 u64 fcoe_rx_frames;
351 bool fcoe_rx_frames_set;
352 u64 fcoe_rx_bytes;
353 bool fcoe_rx_bytes_set;
354 u64 fcoe_tx_frames;
355 bool fcoe_tx_frames_set;
356 u64 fcoe_tx_bytes;
357 bool fcoe_tx_bytes_set;
358 u16 crc_count;
359 bool crc_count_set;
360 u32 crc_err_src_fcid[5];
361 bool crc_err_src_fcid_set[5];
362 u8 crc_err_tstamp[5][14];
363 bool crc_err_tstamp_set[5];
364 u16 losync_err;
365 bool losync_err_set;
366 u16 losig_err;
367 bool losig_err_set;
368 u16 primtive_err;
369 bool primtive_err_set;
370 u16 disparity_err;
371 bool disparity_err_set;
372 u16 code_violation_err;
373 bool code_violation_err_set;
374 u32 flogi_param[4];
375 bool flogi_param_set[4];
376 u8 flogi_tstamp[14];
377 bool flogi_tstamp_set;
378 u32 flogi_acc_param[4];
379 bool flogi_acc_param_set[4];
380 u8 flogi_acc_tstamp[14];
381 bool flogi_acc_tstamp_set;
382 u32 flogi_rjt;
383 bool flogi_rjt_set;
384 u8 flogi_rjt_tstamp[14];
385 bool flogi_rjt_tstamp_set;
386 u32 fdiscs;
387 bool fdiscs_set;
388 u8 fdisc_acc;
389 bool fdisc_acc_set;
390 u8 fdisc_rjt;
391 bool fdisc_rjt_set;
392 u8 plogi;
393 bool plogi_set;
394 u8 plogi_acc;
395 bool plogi_acc_set;
396 u8 plogi_rjt;
397 bool plogi_rjt_set;
398 u32 plogi_dst_fcid[5];
399 bool plogi_dst_fcid_set[5];
400 u8 plogi_tstamp[5][14];
401 bool plogi_tstamp_set[5];
402 u32 plogi_acc_src_fcid[5];
403 bool plogi_acc_src_fcid_set[5];
404 u8 plogi_acc_tstamp[5][14];
405 bool plogi_acc_tstamp_set[5];
406 u8 tx_plogos;
407 bool tx_plogos_set;
408 u8 plogo_acc;
409 bool plogo_acc_set;
410 u8 plogo_rjt;
411 bool plogo_rjt_set;
412 u32 plogo_src_fcid[5];
413 bool plogo_src_fcid_set[5];
414 u8 plogo_tstamp[5][14];
415 bool plogo_tstamp_set[5];
416 u8 rx_logos;
417 bool rx_logos_set;
418 u8 tx_accs;
419 bool tx_accs_set;
420 u8 tx_prlis;
421 bool tx_prlis_set;
422 u8 rx_accs;
423 bool rx_accs_set;
424 u8 tx_abts;
425 bool tx_abts_set;
426 u8 rx_abts_acc;
427 bool rx_abts_acc_set;
428 u8 rx_abts_rjt;
429 bool rx_abts_rjt_set;
430 u32 abts_dst_fcid[5];
431 bool abts_dst_fcid_set[5];
432 u8 abts_tstamp[5][14];
433 bool abts_tstamp_set[5];
434 u8 rx_rscn;
435 bool rx_rscn_set;
436 u32 rx_rscn_nport[4];
437 bool rx_rscn_nport_set[4];
438 u8 tx_lun_rst;
439 bool tx_lun_rst_set;
440 u8 abort_task_sets;
441 bool abort_task_sets_set;
442 u8 tx_tprlos;
443 bool tx_tprlos_set;
444 u8 tx_nos;
445 bool tx_nos_set;
446 u8 rx_nos;
447 bool rx_nos_set;
448 u8 ols;
449 bool ols_set;
450 u8 lr;
451 bool lr_set;
452 u8 lrr;
453 bool lrr_set;
454 u8 tx_lip;
455 bool tx_lip_set;
456 u8 rx_lip;
457 bool rx_lip_set;
458 u8 eofa;
459 bool eofa_set;
460 u8 eofni;
461 bool eofni_set;
462 u8 scsi_chks;
463 bool scsi_chks_set;
464 u8 scsi_cond_met;
465 bool scsi_cond_met_set;
466 u8 scsi_busy;
467 bool scsi_busy_set;
468 u8 scsi_inter;
469 bool scsi_inter_set;
470 u8 scsi_inter_cond_met;
471 bool scsi_inter_cond_met_set;
472 u8 scsi_rsv_conflicts;
473 bool scsi_rsv_conflicts_set;
474 u8 scsi_tsk_full;
475 bool scsi_tsk_full_set;
476 u8 scsi_aca_active;
477 bool scsi_aca_active_set;
478 u8 scsi_tsk_abort;
479 bool scsi_tsk_abort_set;
480 u32 scsi_rx_chk[5];
481 bool scsi_rx_chk_set[5];
482 u8 scsi_chk_tstamp[5][14];
483 bool scsi_chk_tstamp_set[5];
484 };
485
486 struct ecore_mfw_tlv_iscsi {
487 u8 target_llmnr;
488 bool target_llmnr_set;
489 u8 header_digest;
490 bool header_digest_set;
491 u8 data_digest;
492 bool data_digest_set;
493 u8 auth_method;
494 bool auth_method_set;
495 u16 boot_taget_portal;
496 bool boot_taget_portal_set;
497 u16 frame_size;
498 bool frame_size_set;
499 u16 tx_desc_size;
500 bool tx_desc_size_set;
501 u16 rx_desc_size;
502 bool rx_desc_size_set;
503 u8 boot_progress;
504 bool boot_progress_set;
505 u16 tx_desc_qdepth;
506 bool tx_desc_qdepth_set;
507 u16 rx_desc_qdepth;
508 bool rx_desc_qdepth_set;
509 u64 rx_frames;
510 bool rx_frames_set;
511 u64 rx_bytes;
512 bool rx_bytes_set;
513 u64 tx_frames;
514 bool tx_frames_set;
515 u64 tx_bytes;
516 bool tx_bytes_set;
517 };
518
519 union ecore_mfw_tlv_data {
520 struct ecore_mfw_tlv_generic generic;
521 struct ecore_mfw_tlv_eth eth;
522 struct ecore_mfw_tlv_fcoe fcoe;
523 struct ecore_mfw_tlv_iscsi iscsi;
524 };
525
526 /**
527 * @brief - returns the link params of the hw function
528 *
529 * @param p_hwfn
530 *
531 * @returns pointer to link params
532 */
533 struct ecore_mcp_link_params *ecore_mcp_get_link_params(struct ecore_hwfn *);
534
535 /**
536 * @brief - return the link state of the hw function
537 *
538 * @param p_hwfn
539 *
540 * @returns pointer to link state
541 */
542 struct ecore_mcp_link_state *ecore_mcp_get_link_state(struct ecore_hwfn *);
543
544 /**
545 * @brief - return the link capabilities of the hw function
546 *
547 * @param p_hwfn
548 *
549 * @returns pointer to link capabilities
550 */
551 struct ecore_mcp_link_capabilities
552 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn);
553
554 /**
555 * @brief Request the MFW to set the the link according to 'link_input'.
556 *
557 * @param p_hwfn
558 * @param p_ptt
559 * @param b_up - raise link if `true'. Reset link if `false'.
560 *
561 * @return enum _ecore_status_t
562 */
563 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
564 struct ecore_ptt *p_ptt,
565 bool b_up);
566
567 /**
568 * @brief Get the management firmware version value
569 *
570 * @param p_hwfn
571 * @param p_ptt
572 * @param p_mfw_ver - mfw version value
573 * @param p_running_bundle_id - image id in nvram; Optional.
574 *
575 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
576 */
577 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
578 struct ecore_ptt *p_ptt,
579 u32 *p_mfw_ver,
580 u32 *p_running_bundle_id);
581
582 /**
583 * @brief Get media type value of the port.
584 *
585 * @param p_dev - ecore dev pointer
586 * @param mfw_ver - media type value
587 *
588 * @return enum _ecore_status_t -
589 * ECORE_SUCCESS - Operation was successful.
590 * ECORE_BUSY - Operation failed
591 */
592 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev,
593 u32 *media_type);
594
595 /**
596 * @brief - Sends a command to the MCP mailbox.
597 *
598 * @param p_hwfn - hw function
599 * @param p_ptt - PTT required for register access
600 * @param cmd - command to be sent to the MCP
601 * @param param - optional param
602 * @param o_mcp_resp - the MCP response code (exclude sequence)
603 * @param o_mcp_param - optional parameter provided by the MCP response
604 *
605 * @return enum _ecore_status_t -
606 * ECORE_SUCCESS - operation was successful
607 * ECORE_BUSY - operation failed
608 */
609 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
610 struct ecore_ptt *p_ptt, u32 cmd, u32 param,
611 u32 *o_mcp_resp, u32 *o_mcp_param);
612
613 /**
614 * @brief - drains the nig, allowing completion to pass in case of pauses.
615 * (Should be called only from sleepable context)
616 *
617 * @param p_hwfn
618 * @param p_ptt
619 */
620 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
621 struct ecore_ptt *p_ptt);
622
623 #ifndef LINUX_REMOVE
624 /**
625 * @brief - return the mcp function info of the hw function
626 *
627 * @param p_hwfn
628 *
629 * @returns pointer to mcp function info
630 */
631 const struct ecore_mcp_function_info
632 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn);
633 #endif
634
635 /**
636 * @brief - Function for reading/manipulating the nvram. Following are supported
637 * functionalities.
638 * 1. Read: Read the specified nvram offset.
639 * input values:
640 * type - ECORE_MCP_NVM_RD
641 * cmd - command code (e.g. DRV_MSG_CODE_NVM_READ_NVRAM)
642 * offset - nvm offset
643 *
644 * output values:
645 * buf - buffer
646 * buf_size - buffer size
647 *
648 * 2. Write: Write the data at the specified nvram offset
649 * input values:
650 * type - ECORE_MCP_NVM_WR
651 * cmd - command code (e.g. DRV_MSG_CODE_NVM_WRITE_NVRAM)
652 * offset - nvm offset
653 * buf - buffer
654 * buf_size - buffer size
655 *
656 * 3. Command: Send the NVM command to MCP.
657 * input values:
658 * type - ECORE_MCP_CMD
659 * cmd - command code (e.g. DRV_MSG_CODE_NVM_DEL_FILE)
660 * offset - nvm offset
661 *
662 *
663 * @param p_hwfn
664 * @param p_ptt
665 * @param params
666 *
667 * @return ECORE_SUCCESS - operation was successful.
668 */
669 enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn,
670 struct ecore_ptt *p_ptt,
671 struct ecore_mcp_nvm_params *params);
672
673 #ifndef LINUX_REMOVE
674 /**
675 * @brief - count number of function with a matching personality on engine.
676 *
677 * @param p_hwfn
678 * @param p_ptt
679 * @param personalities - a bitmask of ecore_pci_personality values
680 *
681 * @returns the count of all devices on engine whose personality match one of
682 * the bitsmasks.
683 */
684 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
685 struct ecore_ptt *p_ptt,
686 u32 personalities);
687 #endif
688
689 /**
690 * @brief Get the flash size value
691 *
692 * @param p_hwfn
693 * @param p_ptt
694 * @param p_flash_size - flash size in bytes to be filled.
695 *
696 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
697 */
698 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
699 struct ecore_ptt *p_ptt,
700 u32 *p_flash_size);
701
702 /**
703 * @brief Send driver version to MFW
704 *
705 * @param p_hwfn
706 * @param p_ptt
707 * @param version - Version value
708 * @param name - Protocol driver name
709 *
710 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
711 */
712 enum _ecore_status_t
713 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
714 struct ecore_mcp_drv_version *p_ver);
715
716 /**
717 * @brief Read the MFW process kill counter
718 *
719 * @param p_hwfn
720 * @param p_ptt
721 *
722 * @return u32
723 */
724 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
725 struct ecore_ptt *p_ptt);
726
727 /**
728 * @brief Trigger a recovery process
729 *
730 * @param p_hwfn
731 * @param p_ptt
732 *
733 * @return enum _ecore_status_t
734 */
735 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
736 struct ecore_ptt *p_ptt);
737
738 /**
739 * @brief Notify MFW about the change in base device properties
740 *
741 * @param p_hwfn
742 * @param p_ptt
743 * @param client - ecore client type
744 *
745 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
746 */
747 enum _ecore_status_t
748 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
749 struct ecore_ptt *p_ptt,
750 enum ecore_ov_client client);
751
752 /**
753 * @brief Notify MFW about the driver state
754 *
755 * @param p_hwfn
756 * @param p_ptt
757 * @param drv_state - Driver state
758 *
759 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
760 */
761 enum _ecore_status_t
762 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
763 struct ecore_ptt *p_ptt,
764 enum ecore_ov_driver_state drv_state);
765
766 /**
767 * @brief Read NPIV settings form the MFW
768 *
769 * @param p_hwfn
770 * @param p_ptt
771 * @param p_table - Array to hold the FC NPIV data. Client need allocate the
772 * required buffer. The field 'count' specifies number of NPIV
773 * entries. A value of 0 means the table was not populated.
774 *
775 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
776 */
777 enum _ecore_status_t
778 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
779 struct ecore_fc_npiv_tbl *p_table);
780
781 /**
782 * @brief Send MTU size to MFW
783 *
784 * @param p_hwfn
785 * @param p_ptt
786 * @param mtu - MTU size
787 *
788 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
789 */
790 enum _ecore_status_t ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
791 struct ecore_ptt *p_ptt, u16 mtu);
792
793 /**
794 * @brief Set LED status
795 *
796 * @param p_hwfn
797 * @param p_ptt
798 * @param mode - LED mode
799 *
800 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
801 */
802 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
803 struct ecore_ptt *p_ptt,
804 enum ecore_led_mode mode);
805
806 /**
807 * @brief Set secure mode
808 *
809 * @param p_dev
810 * @param addr - nvm offset
811 *
812 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
813 */
814 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
815 u32 addr);
816
817 /**
818 * @brief Write to phy
819 *
820 * @param p_dev
821 * @param addr - nvm offset
822 * @param cmd - nvm command
823 * @param p_buf - nvm write buffer
824 * @param len - buffer len
825 *
826 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
827 */
828 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
829 u32 addr, u8 *p_buf, u32 len);
830
831 /**
832 * @brief Write to nvm
833 *
834 * @param p_dev
835 * @param addr - nvm offset
836 * @param cmd - nvm command
837 * @param p_buf - nvm write buffer
838 * @param len - buffer len
839 *
840 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
841 */
842 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
843 u32 addr, u8 *p_buf, u32 len);
844
845 /**
846 * @brief Put file begin
847 *
848 * @param p_dev
849 * @param addr - nvm offset
850 *
851 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
852 */
853 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
854 u32 addr);
855
856 /**
857 * @brief Delete file
858 *
859 * @param p_dev
860 * @param addr - nvm offset
861 *
862 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
863 */
864 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev,
865 u32 addr);
866
867 /**
868 * @brief Check latest response
869 *
870 * @param p_dev
871 * @param p_buf - nvm write buffer
872 *
873 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
874 */
875 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf);
876
877 /**
878 * @brief Read from phy
879 *
880 * @param p_dev
881 * @param addr - nvm offset
882 * @param cmd - nvm command
883 * @param p_buf - nvm write buffer
884 * @param len - buffer len
885 *
886 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
887 */
888 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
889 u32 addr, u8 *p_buf, u32 len);
890
891 /**
892 * @brief Read from nvm
893 *
894 * @param p_dev
895 * @param addr - nvm offset
896 * @param p_buf - nvm write buffer
897 * @param len - buffer len
898 *
899 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
900 */
901 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
902 u8 *p_buf, u32 len);
903
904 /**
905 * @brief Read from sfp
906 *
907 * @param p_hwfn - hw function
908 * @param p_ptt - PTT required for register access
909 * @param port - transceiver port
910 * @param addr - I2C address
911 * @param offset - offset in sfp
912 * @param len - buffer length
913 * @param p_buf - buffer to read into
914 *
915 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
916 */
917 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
918 struct ecore_ptt *p_ptt,
919 u32 port, u32 addr, u32 offset,
920 u32 len, u8 *p_buf);
921
922 /**
923 * @brief Write to sfp
924 *
925 * @param p_hwfn - hw function
926 * @param p_ptt - PTT required for register access
927 * @param port - transceiver port
928 * @param addr - I2C address
929 * @param offset - offset in sfp
930 * @param len - buffer length
931 * @param p_buf - buffer to write from
932 *
933 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
934 */
935 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
936 struct ecore_ptt *p_ptt,
937 u32 port, u32 addr, u32 offset,
938 u32 len, u8 *p_buf);
939
940 /**
941 * @brief Gpio read
942 *
943 * @param p_hwfn - hw function
944 * @param p_ptt - PTT required for register access
945 * @param gpio - gpio number
946 * @param gpio_val - value read from gpio
947 *
948 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
949 */
950 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
951 struct ecore_ptt *p_ptt,
952 u16 gpio, u32 *gpio_val);
953
954 /**
955 * @brief Gpio write
956 *
957 * @param p_hwfn - hw function
958 * @param p_ptt - PTT required for register access
959 * @param gpio - gpio number
960 * @param gpio_val - value to write to gpio
961 *
962 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
963 */
964 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
965 struct ecore_ptt *p_ptt,
966 u16 gpio, u16 gpio_val);
967
968 /**
969 * @brief Gpio get information
970 *
971 * @param p_hwfn - hw function
972 * @param p_ptt - PTT required for register access
973 * @param gpio - gpio number
974 * @param gpio_direction - gpio is output (0) or input (1)
975 * @param gpio_ctrl - gpio control is uninitialized (0),
976 * path 0 (1), path 1 (2) or shared(3)
977 *
978 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
979 */
980 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
981 struct ecore_ptt *p_ptt,
982 u16 gpio, u32 *gpio_direction,
983 u32 *gpio_ctrl);
984
985 /**
986 * @brief Bist register test
987 *
988 * @param p_hwfn - hw function
989 * @param p_ptt - PTT required for register access
990 *
991 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
992 */
993 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
994 struct ecore_ptt *p_ptt);
995
996 /**
997 * @brief Bist clock test
998 *
999 * @param p_hwfn - hw function
1000 * @param p_ptt - PTT required for register access
1001 *
1002 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1003 */
1004 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
1005 struct ecore_ptt *p_ptt);
1006
1007 /**
1008 * @brief Bist nvm test - get number of images
1009 *
1010 * @param p_hwfn - hw function
1011 * @param p_ptt - PTT required for register access
1012 * @param num_images - number of images if operation was
1013 * successful. 0 if not.
1014 *
1015 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1016 */
1017 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
1018 struct ecore_hwfn *p_hwfn,
1019 struct ecore_ptt *p_ptt,
1020 u32 *num_images);
1021
1022 /**
1023 * @brief Bist nvm test - get image attributes by index
1024 *
1025 * @param p_hwfn - hw function
1026 * @param p_ptt - PTT required for register access
1027 * @param p_image_att - Attributes of image
1028 * @param image_index - Index of image to get information for
1029 *
1030 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1031 */
1032 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
1033 struct ecore_hwfn *p_hwfn,
1034 struct ecore_ptt *p_ptt,
1035 struct bist_nvm_image_att *p_image_att,
1036 u32 image_index);
1037
1038 /**
1039 * @brief ecore_mcp_get_temperature_info - get the status of the temperature
1040 * sensors
1041 *
1042 * @param p_hwfn - hw function
1043 * @param p_ptt - PTT required for register access
1044 * @param p_temp_status - A pointer to an ecore_temperature_info structure to
1045 * be filled with the temperature data
1046 *
1047 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1048 */
1049 enum _ecore_status_t
1050 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
1051 struct ecore_ptt *p_ptt,
1052 struct ecore_temperature_info *p_temp_info);
1053
1054 /**
1055 * @brief Get MBA versions - get MBA sub images versions
1056 *
1057 * @param p_hwfn - hw function
1058 * @param p_ptt - PTT required for register access
1059 * @param p_mba_vers - MBA versions array to fill
1060 *
1061 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1062 */
1063 enum _ecore_status_t ecore_mcp_get_mba_versions(
1064 struct ecore_hwfn *p_hwfn,
1065 struct ecore_ptt *p_ptt,
1066 struct ecore_mba_vers *p_mba_vers);
1067
1068 /**
1069 * @brief Count memory ecc events
1070 *
1071 * @param p_hwfn - hw function
1072 * @param p_ptt - PTT required for register access
1073 * @param num_events - number of memory ecc events
1074 *
1075 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
1076 */
1077 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
1078 struct ecore_ptt *p_ptt,
1079 u64 *num_events);
1080
1081 struct ecore_mdump_info {
1082 u32 reason;
1083 u32 version;
1084 u32 config;
1085 u32 epoch;
1086 u32 num_of_logs;
1087 u32 valid_logs;
1088 };
1089
1090 /**
1091 * @brief - Gets the MFW crash dump configuration and logs info.
1092 *
1093 * @param p_hwfn
1094 * @param p_ptt
1095 * @param p_mdump_info
1096 *
1097 * @param return ECORE_SUCCESS upon success.
1098 */
1099 enum _ecore_status_t
1100 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1101 struct ecore_mdump_info *p_mdump_info);
1102
1103 /**
1104 * @brief - Clears the MFW crash dump logs.
1105 *
1106 * @param p_hwfn
1107 * @param p_ptt
1108 *
1109 * @param return ECORE_SUCCESS upon success.
1110 */
1111 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1112 struct ecore_ptt *p_ptt);
1113
1114 /**
1115 * @brief - Processes the TLV request from MFW i.e., get the required TLV info
1116 * from the ecore client and send it to the MFW.
1117 *
1118 * @param p_hwfn
1119 * @param p_ptt
1120 *
1121 * @param return ECORE_SUCCESS upon success.
1122 */
1123 enum _ecore_status_t ecore_mfw_process_tlv_req(struct ecore_hwfn *p_hwfn,
1124 struct ecore_ptt *p_ptt);
1125
1126 #endif