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[ceph.git] / ceph / src / seastar / dpdk / drivers / net / qede / base / ecore_vf.c
1 /*
2 * Copyright (c) 2016 QLogic Corporation.
3 * All rights reserved.
4 * www.qlogic.com
5 *
6 * See LICENSE.qede_pmd for copyright and licensing details.
7 */
8
9 #include "bcm_osal.h"
10 #include "ecore.h"
11 #include "ecore_hsi_eth.h"
12 #include "ecore_sriov.h"
13 #include "ecore_l2_api.h"
14 #include "ecore_vf.h"
15 #include "ecore_vfpf_if.h"
16 #include "ecore_status.h"
17 #include "reg_addr.h"
18 #include "ecore_int.h"
19 #include "ecore_l2.h"
20 #include "ecore_mcp_api.h"
21 #include "ecore_vf_api.h"
22
23 static void *ecore_vf_pf_prep(struct ecore_hwfn *p_hwfn, u16 type, u16 length)
24 {
25 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
26 void *p_tlv;
27
28 /* This lock is released when we receive PF's response
29 * in ecore_send_msg2pf().
30 * So, ecore_vf_pf_prep() and ecore_send_msg2pf()
31 * must come in sequence.
32 */
33 OSAL_MUTEX_ACQUIRE(&p_iov->mutex);
34
35 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
36 "preparing to send %s tlv over vf pf channel\n",
37 ecore_channel_tlvs_string[type]);
38
39 /* Reset Request offset */
40 p_iov->offset = (u8 *)(p_iov->vf2pf_request);
41
42 /* Clear mailbox - both request and reply */
43 OSAL_MEMSET(p_iov->vf2pf_request, 0, sizeof(union vfpf_tlvs));
44 OSAL_MEMSET(p_iov->pf2vf_reply, 0, sizeof(union pfvf_tlvs));
45
46 /* Init type and length */
47 p_tlv = ecore_add_tlv(p_hwfn, &p_iov->offset, type, length);
48
49 /* Init first tlv header */
50 ((struct vfpf_first_tlv *)p_tlv)->reply_address =
51 (u64)p_iov->pf2vf_reply_phys;
52
53 return p_tlv;
54 }
55
56 static void ecore_vf_pf_req_end(struct ecore_hwfn *p_hwfn,
57 enum _ecore_status_t req_status)
58 {
59 union pfvf_tlvs *resp = p_hwfn->vf_iov_info->pf2vf_reply;
60
61 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
62 "VF request status = 0x%x, PF reply status = 0x%x\n",
63 req_status, resp->default_resp.hdr.status);
64
65 OSAL_MUTEX_RELEASE(&p_hwfn->vf_iov_info->mutex);
66 }
67
68 static enum _ecore_status_t
69 ecore_send_msg2pf(struct ecore_hwfn *p_hwfn,
70 u8 *done, u32 resp_size)
71 {
72 union vfpf_tlvs *p_req = p_hwfn->vf_iov_info->vf2pf_request;
73 struct ustorm_trigger_vf_zone trigger;
74 struct ustorm_vf_zone *zone_data;
75 enum _ecore_status_t rc = ECORE_SUCCESS;
76 int time = 100;
77
78 zone_data = (struct ustorm_vf_zone *)PXP_VF_BAR0_START_USDM_ZONE_B;
79
80 /* output tlvs list */
81 ecore_dp_tlv_list(p_hwfn, p_req);
82
83 /* need to add the END TLV to the message size */
84 resp_size += sizeof(struct channel_list_end_tlv);
85
86 /* Send TLVs over HW channel */
87 OSAL_MEMSET(&trigger, 0, sizeof(struct ustorm_trigger_vf_zone));
88 trigger.vf_pf_msg_valid = 1;
89
90 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
91 "VF -> PF [%02x] message: [%08x, %08x] --> %p,"
92 " %08x --> %p\n",
93 GET_FIELD(p_hwfn->hw_info.concrete_fid,
94 PXP_CONCRETE_FID_PFID),
95 U64_HI(p_hwfn->vf_iov_info->vf2pf_request_phys),
96 U64_LO(p_hwfn->vf_iov_info->vf2pf_request_phys),
97 &zone_data->non_trigger.vf_pf_msg_addr,
98 *((u32 *)&trigger), &zone_data->trigger);
99
100 REG_WR(p_hwfn,
101 (osal_uintptr_t)&zone_data->non_trigger.vf_pf_msg_addr.lo,
102 U64_LO(p_hwfn->vf_iov_info->vf2pf_request_phys));
103
104 REG_WR(p_hwfn,
105 (osal_uintptr_t)&zone_data->non_trigger.vf_pf_msg_addr.hi,
106 U64_HI(p_hwfn->vf_iov_info->vf2pf_request_phys));
107
108 /* The message data must be written first, to prevent trigger before
109 * data is written.
110 */
111 OSAL_WMB(p_hwfn->p_dev);
112
113 REG_WR(p_hwfn, (osal_uintptr_t)&zone_data->trigger,
114 *((u32 *)&trigger));
115
116 /* When PF would be done with the response, it would write back to the
117 * `done' address. Poll until then.
118 */
119 while ((!*done) && time) {
120 OSAL_MSLEEP(25);
121 time--;
122 }
123
124 if (!*done) {
125 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
126 "VF <-- PF Timeout [Type %d]\n",
127 p_req->first_tlv.tl.type);
128 rc = ECORE_TIMEOUT;
129 } else {
130 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
131 "PF response: %d [Type %d]\n",
132 *done, p_req->first_tlv.tl.type);
133 }
134
135 return rc;
136 }
137
138 #define VF_ACQUIRE_THRESH 3
139 static void ecore_vf_pf_acquire_reduce_resc(struct ecore_hwfn *p_hwfn,
140 struct vf_pf_resc_request *p_req,
141 struct pf_vf_resc *p_resp)
142 {
143 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
144 "PF unwilling to fullill resource request: rxq [%02x/%02x]"
145 " txq [%02x/%02x] sbs [%02x/%02x] mac [%02x/%02x]"
146 " vlan [%02x/%02x] mc [%02x/%02x]."
147 " Try PF recommended amount\n",
148 p_req->num_rxqs, p_resp->num_rxqs,
149 p_req->num_rxqs, p_resp->num_txqs,
150 p_req->num_sbs, p_resp->num_sbs,
151 p_req->num_mac_filters, p_resp->num_mac_filters,
152 p_req->num_vlan_filters, p_resp->num_vlan_filters,
153 p_req->num_mc_filters, p_resp->num_mc_filters);
154
155 /* humble our request */
156 p_req->num_txqs = p_resp->num_txqs;
157 p_req->num_rxqs = p_resp->num_rxqs;
158 p_req->num_sbs = p_resp->num_sbs;
159 p_req->num_mac_filters = p_resp->num_mac_filters;
160 p_req->num_vlan_filters = p_resp->num_vlan_filters;
161 p_req->num_mc_filters = p_resp->num_mc_filters;
162 }
163
164 static enum _ecore_status_t ecore_vf_pf_acquire(struct ecore_hwfn *p_hwfn)
165 {
166 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
167 struct pfvf_acquire_resp_tlv *resp = &p_iov->pf2vf_reply->acquire_resp;
168 struct pf_vf_pfdev_info *pfdev_info = &resp->pfdev_info;
169 struct ecore_vf_acquire_sw_info vf_sw_info;
170 struct vf_pf_resc_request *p_resc;
171 bool resources_acquired = false;
172 struct vfpf_acquire_tlv *req;
173 int attempts = 0;
174 enum _ecore_status_t rc = ECORE_SUCCESS;
175
176 /* clear mailbox and prep first tlv */
177 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_ACQUIRE, sizeof(*req));
178 p_resc = &req->resc_request;
179
180 /* @@@ TBD: PF may not be ready bnx2x_get_vf_id... */
181 req->vfdev_info.opaque_fid = p_hwfn->hw_info.opaque_fid;
182
183 p_resc->num_rxqs = ECORE_MAX_VF_CHAINS_PER_PF;
184 p_resc->num_txqs = ECORE_MAX_VF_CHAINS_PER_PF;
185 p_resc->num_sbs = ECORE_MAX_VF_CHAINS_PER_PF;
186 p_resc->num_mac_filters = ECORE_ETH_VF_NUM_MAC_FILTERS;
187 p_resc->num_vlan_filters = ECORE_ETH_VF_NUM_VLAN_FILTERS;
188
189 OSAL_MEMSET(&vf_sw_info, 0, sizeof(vf_sw_info));
190 OSAL_VF_FILL_ACQUIRE_RESC_REQ(p_hwfn, &req->resc_request, &vf_sw_info);
191
192 req->vfdev_info.os_type = vf_sw_info.os_type;
193 req->vfdev_info.driver_version = vf_sw_info.driver_version;
194 req->vfdev_info.fw_major = FW_MAJOR_VERSION;
195 req->vfdev_info.fw_minor = FW_MINOR_VERSION;
196 req->vfdev_info.fw_revision = FW_REVISION_VERSION;
197 req->vfdev_info.fw_engineering = FW_ENGINEERING_VERSION;
198 req->vfdev_info.eth_fp_hsi_major = ETH_HSI_VER_MAJOR;
199 req->vfdev_info.eth_fp_hsi_minor = ETH_HSI_VER_MINOR;
200
201 /* Fill capability field with any non-deprecated config we support */
202 req->vfdev_info.capabilities |= VFPF_ACQUIRE_CAP_100G;
203
204 /* pf 2 vf bulletin board address */
205 req->bulletin_addr = p_iov->bulletin.phys;
206 req->bulletin_size = p_iov->bulletin.size;
207
208 /* add list termination tlv */
209 ecore_add_tlv(p_hwfn, &p_iov->offset,
210 CHANNEL_TLV_LIST_END,
211 sizeof(struct channel_list_end_tlv));
212
213 while (!resources_acquired) {
214 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
215 "attempting to acquire resources\n");
216
217 /* Clear response buffer, as this might be a re-send */
218 OSAL_MEMSET(p_iov->pf2vf_reply, 0,
219 sizeof(union pfvf_tlvs));
220
221 /* send acquire request */
222 rc = ecore_send_msg2pf(p_hwfn,
223 &resp->hdr.status, sizeof(*resp));
224
225 /* PF timeout */
226 if (rc)
227 return rc;
228
229 /* copy acquire response from buffer to p_hwfn */
230 OSAL_MEMCPY(&p_iov->acquire_resp,
231 resp, sizeof(p_iov->acquire_resp));
232
233 attempts++;
234
235 if (resp->hdr.status == PFVF_STATUS_SUCCESS) {
236 /* PF agrees to allocate our resources */
237 if (!(resp->pfdev_info.capabilities &
238 PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE)) {
239 /* It's possible legacy PF mistakenly accepted;
240 * but we don't care - simply mark it as
241 * legacy and continue.
242 */
243 req->vfdev_info.capabilities |=
244 VFPF_ACQUIRE_CAP_PRE_FP_HSI;
245 }
246 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
247 "resources acquired\n");
248 resources_acquired = true;
249 } /* PF refuses to allocate our resources */
250 else if (resp->hdr.status == PFVF_STATUS_NO_RESOURCE &&
251 attempts < VF_ACQUIRE_THRESH) {
252 ecore_vf_pf_acquire_reduce_resc(p_hwfn, p_resc,
253 &resp->resc);
254
255 } else if (resp->hdr.status == PFVF_STATUS_NOT_SUPPORTED) {
256 if (pfdev_info->major_fp_hsi &&
257 (pfdev_info->major_fp_hsi != ETH_HSI_VER_MAJOR)) {
258 DP_NOTICE(p_hwfn, false,
259 "PF uses an incompatible fastpath HSI"
260 " %02x.%02x [VF requires %02x.%02x]."
261 " Please change to a VF driver using"
262 " %02x.xx.\n",
263 pfdev_info->major_fp_hsi,
264 pfdev_info->minor_fp_hsi,
265 ETH_HSI_VER_MAJOR, ETH_HSI_VER_MINOR,
266 pfdev_info->major_fp_hsi);
267 rc = ECORE_INVAL;
268 goto exit;
269 }
270
271 if (!pfdev_info->major_fp_hsi) {
272 if (req->vfdev_info.capabilities &
273 VFPF_ACQUIRE_CAP_PRE_FP_HSI) {
274 DP_NOTICE(p_hwfn, false,
275 "PF uses very old drivers."
276 " Please change to a VF"
277 " driver using no later than"
278 " 8.8.x.x.\n");
279 rc = ECORE_INVAL;
280 goto exit;
281 } else {
282 DP_INFO(p_hwfn,
283 "PF is old - try re-acquire to"
284 " see if it supports FW-version"
285 " override\n");
286 req->vfdev_info.capabilities |=
287 VFPF_ACQUIRE_CAP_PRE_FP_HSI;
288 continue;
289 }
290 }
291
292 /* If PF/VF are using same Major, PF must have had
293 * it's reasons. Simply fail.
294 */
295 DP_NOTICE(p_hwfn, false,
296 "PF rejected acquisition by VF\n");
297 rc = ECORE_INVAL;
298 goto exit;
299 } else {
300 DP_ERR(p_hwfn,
301 "PF returned err %d to VF acquisition request\n",
302 resp->hdr.status);
303 rc = ECORE_AGAIN;
304 goto exit;
305 }
306 }
307
308 /* Mark the PF as legacy, if needed */
309 if (req->vfdev_info.capabilities &
310 VFPF_ACQUIRE_CAP_PRE_FP_HSI)
311 p_iov->b_pre_fp_hsi = true;
312
313 rc = OSAL_VF_UPDATE_ACQUIRE_RESC_RESP(p_hwfn, &resp->resc);
314 if (rc) {
315 DP_NOTICE(p_hwfn, true,
316 "VF_UPDATE_ACQUIRE_RESC_RESP Failed:"
317 " status = 0x%x.\n",
318 rc);
319 rc = ECORE_AGAIN;
320 goto exit;
321 }
322
323 /* Update bulletin board size with response from PF */
324 p_iov->bulletin.size = resp->bulletin_size;
325
326 /* get HW info */
327 p_hwfn->p_dev->type = resp->pfdev_info.dev_type;
328 p_hwfn->p_dev->chip_rev = resp->pfdev_info.chip_rev;
329
330 DP_INFO(p_hwfn, "Chip details - %s%d\n",
331 ECORE_IS_BB(p_hwfn->p_dev) ? "BB" : "AH",
332 CHIP_REV_IS_A0(p_hwfn->p_dev) ? 0 : 1);
333
334 p_hwfn->p_dev->chip_num = pfdev_info->chip_num & 0xffff;
335
336 /* Learn of the possibility of CMT */
337 if (IS_LEAD_HWFN(p_hwfn)) {
338 if (resp->pfdev_info.capabilities & PFVF_ACQUIRE_CAP_100G) {
339 DP_INFO(p_hwfn, "100g VF\n");
340 p_hwfn->p_dev->num_hwfns = 2;
341 }
342 }
343
344 /* @DPDK */
345 if ((~p_iov->b_pre_fp_hsi &
346 ETH_HSI_VER_MINOR) &&
347 (resp->pfdev_info.minor_fp_hsi < ETH_HSI_VER_MINOR))
348 DP_INFO(p_hwfn,
349 "PF is using older fastpath HSI;"
350 " %02x.%02x is configured\n",
351 ETH_HSI_VER_MAJOR,
352 resp->pfdev_info.minor_fp_hsi);
353
354 exit:
355 ecore_vf_pf_req_end(p_hwfn, rc);
356
357 return rc;
358 }
359
360 enum _ecore_status_t ecore_vf_hw_prepare(struct ecore_hwfn *p_hwfn)
361 {
362 struct ecore_vf_iov *p_iov;
363 u32 reg;
364
365 /* Set number of hwfns - might be overridden once leading hwfn learns
366 * actual configuration from PF.
367 */
368 if (IS_LEAD_HWFN(p_hwfn))
369 p_hwfn->p_dev->num_hwfns = 1;
370
371 /* Set the doorbell bar. Assumption: regview is set */
372 p_hwfn->doorbells = (u8 OSAL_IOMEM *)p_hwfn->regview +
373 PXP_VF_BAR0_START_DQ;
374
375 reg = PXP_VF_BAR0_ME_OPAQUE_ADDRESS;
376 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, reg);
377
378 reg = PXP_VF_BAR0_ME_CONCRETE_ADDRESS;
379 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, reg);
380
381 /* Allocate vf sriov info */
382 p_iov = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_iov));
383 if (!p_iov) {
384 DP_NOTICE(p_hwfn, true,
385 "Failed to allocate `struct ecore_sriov'\n");
386 return ECORE_NOMEM;
387 }
388
389 /* Allocate vf2pf msg */
390 p_iov->vf2pf_request = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
391 &p_iov->
392 vf2pf_request_phys,
393 sizeof(union
394 vfpf_tlvs));
395 if (!p_iov->vf2pf_request) {
396 DP_NOTICE(p_hwfn, true,
397 "Failed to allocate `vf2pf_request' DMA memory\n");
398 goto free_p_iov;
399 }
400
401 p_iov->pf2vf_reply = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
402 &p_iov->
403 pf2vf_reply_phys,
404 sizeof(union pfvf_tlvs));
405 if (!p_iov->pf2vf_reply) {
406 DP_NOTICE(p_hwfn, true,
407 "Failed to allocate `pf2vf_reply' DMA memory\n");
408 goto free_vf2pf_request;
409 }
410
411 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
412 "VF's Request mailbox [%p virt 0x%lx phys], "
413 "Response mailbox [%p virt 0x%lx phys]\n",
414 p_iov->vf2pf_request,
415 (unsigned long)p_iov->vf2pf_request_phys,
416 p_iov->pf2vf_reply,
417 (unsigned long)p_iov->pf2vf_reply_phys);
418
419 /* Allocate Bulletin board */
420 p_iov->bulletin.size = sizeof(struct ecore_bulletin_content);
421 p_iov->bulletin.p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
422 &p_iov->bulletin.
423 phys,
424 p_iov->bulletin.
425 size);
426 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
427 "VF's bulletin Board [%p virt 0x%lx phys 0x%08x bytes]\n",
428 p_iov->bulletin.p_virt, (unsigned long)p_iov->bulletin.phys,
429 p_iov->bulletin.size);
430
431 OSAL_MUTEX_ALLOC(p_hwfn, &p_iov->mutex);
432 OSAL_MUTEX_INIT(&p_iov->mutex);
433
434 p_hwfn->vf_iov_info = p_iov;
435
436 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
437
438 return ecore_vf_pf_acquire(p_hwfn);
439
440 free_vf2pf_request:
441 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_iov->vf2pf_request,
442 p_iov->vf2pf_request_phys,
443 sizeof(union vfpf_tlvs));
444 free_p_iov:
445 OSAL_FREE(p_hwfn->p_dev, p_iov);
446
447 return ECORE_NOMEM;
448 }
449
450 #define TSTORM_QZONE_START PXP_VF_BAR0_START_SDM_ZONE_A
451 #define MSTORM_QZONE_START(dev) (TSTORM_QZONE_START + \
452 (TSTORM_QZONE_SIZE * NUM_OF_L2_QUEUES(dev)))
453
454 /* @DPDK - changed enum ecore_tunn_clss to enum ecore_tunn_mode */
455 static void
456 __ecore_vf_prep_tunn_req_tlv(struct vfpf_update_tunn_param_tlv *p_req,
457 struct ecore_tunn_update_type *p_src,
458 enum ecore_tunn_mode mask, u8 *p_cls)
459 {
460 if (p_src->b_update_mode) {
461 p_req->tun_mode_update_mask |= (1 << mask);
462
463 if (p_src->b_mode_enabled)
464 p_req->tunn_mode |= (1 << mask);
465 }
466
467 *p_cls = p_src->tun_cls;
468 }
469
470 /* @DPDK - changed enum ecore_tunn_clss to enum ecore_tunn_mode */
471 static void
472 ecore_vf_prep_tunn_req_tlv(struct vfpf_update_tunn_param_tlv *p_req,
473 struct ecore_tunn_update_type *p_src,
474 enum ecore_tunn_mode mask, u8 *p_cls,
475 struct ecore_tunn_update_udp_port *p_port,
476 u8 *p_update_port, u16 *p_udp_port)
477 {
478 if (p_port->b_update_port) {
479 *p_update_port = 1;
480 *p_udp_port = p_port->port;
481 }
482
483 __ecore_vf_prep_tunn_req_tlv(p_req, p_src, mask, p_cls);
484 }
485
486 void ecore_vf_set_vf_start_tunn_update_param(struct ecore_tunnel_info *p_tun)
487 {
488 if (p_tun->vxlan.b_mode_enabled)
489 p_tun->vxlan.b_update_mode = true;
490 if (p_tun->l2_geneve.b_mode_enabled)
491 p_tun->l2_geneve.b_update_mode = true;
492 if (p_tun->ip_geneve.b_mode_enabled)
493 p_tun->ip_geneve.b_update_mode = true;
494 if (p_tun->l2_gre.b_mode_enabled)
495 p_tun->l2_gre.b_update_mode = true;
496 if (p_tun->ip_gre.b_mode_enabled)
497 p_tun->ip_gre.b_update_mode = true;
498
499 p_tun->b_update_rx_cls = true;
500 p_tun->b_update_tx_cls = true;
501 }
502
503 static void
504 __ecore_vf_update_tunn_param(struct ecore_tunn_update_type *p_tun,
505 u16 feature_mask, u8 tunn_mode, u8 tunn_cls,
506 enum ecore_tunn_mode val)
507 {
508 if (feature_mask & (1 << val)) {
509 p_tun->b_mode_enabled = tunn_mode;
510 p_tun->tun_cls = tunn_cls;
511 } else {
512 p_tun->b_mode_enabled = false;
513 }
514 }
515
516 static void
517 ecore_vf_update_tunn_param(struct ecore_hwfn *p_hwfn,
518 struct ecore_tunnel_info *p_tun,
519 struct pfvf_update_tunn_param_tlv *p_resp)
520 {
521 /* Update mode and classes provided by PF */
522 u16 feat_mask = p_resp->tunn_feature_mask;
523
524 __ecore_vf_update_tunn_param(&p_tun->vxlan, feat_mask,
525 p_resp->vxlan_mode, p_resp->vxlan_clss,
526 ECORE_MODE_VXLAN_TUNN);
527 __ecore_vf_update_tunn_param(&p_tun->l2_geneve, feat_mask,
528 p_resp->l2geneve_mode,
529 p_resp->l2geneve_clss,
530 ECORE_MODE_L2GENEVE_TUNN);
531 __ecore_vf_update_tunn_param(&p_tun->ip_geneve, feat_mask,
532 p_resp->ipgeneve_mode,
533 p_resp->ipgeneve_clss,
534 ECORE_MODE_IPGENEVE_TUNN);
535 __ecore_vf_update_tunn_param(&p_tun->l2_gre, feat_mask,
536 p_resp->l2gre_mode, p_resp->l2gre_clss,
537 ECORE_MODE_L2GRE_TUNN);
538 __ecore_vf_update_tunn_param(&p_tun->ip_gre, feat_mask,
539 p_resp->ipgre_mode, p_resp->ipgre_clss,
540 ECORE_MODE_IPGRE_TUNN);
541 p_tun->geneve_port.port = p_resp->geneve_udp_port;
542 p_tun->vxlan_port.port = p_resp->vxlan_udp_port;
543
544 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
545 "tunn mode: vxlan=0x%x, l2geneve=0x%x, ipgeneve=0x%x, l2gre=0x%x, ipgre=0x%x",
546 p_tun->vxlan.b_mode_enabled, p_tun->l2_geneve.b_mode_enabled,
547 p_tun->ip_geneve.b_mode_enabled,
548 p_tun->l2_gre.b_mode_enabled,
549 p_tun->ip_gre.b_mode_enabled);
550 }
551
552 enum _ecore_status_t
553 ecore_vf_pf_tunnel_param_update(struct ecore_hwfn *p_hwfn,
554 struct ecore_tunnel_info *p_src)
555 {
556 struct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;
557 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
558 struct pfvf_update_tunn_param_tlv *p_resp;
559 struct vfpf_update_tunn_param_tlv *p_req;
560 enum _ecore_status_t rc;
561
562 p_req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_UPDATE_TUNN_PARAM,
563 sizeof(*p_req));
564
565 if (p_src->b_update_rx_cls && p_src->b_update_tx_cls)
566 p_req->update_tun_cls = 1;
567
568 ecore_vf_prep_tunn_req_tlv(p_req, &p_src->vxlan, ECORE_MODE_VXLAN_TUNN,
569 &p_req->vxlan_clss, &p_src->vxlan_port,
570 &p_req->update_vxlan_port,
571 &p_req->vxlan_port);
572 ecore_vf_prep_tunn_req_tlv(p_req, &p_src->l2_geneve,
573 ECORE_MODE_L2GENEVE_TUNN,
574 &p_req->l2geneve_clss, &p_src->geneve_port,
575 &p_req->update_geneve_port,
576 &p_req->geneve_port);
577 __ecore_vf_prep_tunn_req_tlv(p_req, &p_src->ip_geneve,
578 ECORE_MODE_IPGENEVE_TUNN,
579 &p_req->ipgeneve_clss);
580 __ecore_vf_prep_tunn_req_tlv(p_req, &p_src->l2_gre,
581 ECORE_MODE_L2GRE_TUNN, &p_req->l2gre_clss);
582 __ecore_vf_prep_tunn_req_tlv(p_req, &p_src->ip_gre,
583 ECORE_MODE_IPGRE_TUNN, &p_req->ipgre_clss);
584
585 /* add list termination tlv */
586 ecore_add_tlv(p_hwfn, &p_iov->offset,
587 CHANNEL_TLV_LIST_END,
588 sizeof(struct channel_list_end_tlv));
589
590 p_resp = &p_iov->pf2vf_reply->tunn_param_resp;
591 rc = ecore_send_msg2pf(p_hwfn, &p_resp->hdr.status, sizeof(*p_resp));
592
593 if (rc)
594 goto exit;
595
596 if (p_resp->hdr.status != PFVF_STATUS_SUCCESS) {
597 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
598 "Failed to update tunnel parameters\n");
599 rc = ECORE_INVAL;
600 }
601
602 ecore_vf_update_tunn_param(p_hwfn, p_tun, p_resp);
603 exit:
604 ecore_vf_pf_req_end(p_hwfn, rc);
605 return rc;
606 }
607
608 enum _ecore_status_t
609 ecore_vf_pf_rxq_start(struct ecore_hwfn *p_hwfn,
610 struct ecore_queue_cid *p_cid,
611 u16 bd_max_bytes,
612 dma_addr_t bd_chain_phys_addr,
613 dma_addr_t cqe_pbl_addr,
614 u16 cqe_pbl_size,
615 void OSAL_IOMEM **pp_prod)
616 {
617 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
618 struct pfvf_start_queue_resp_tlv *resp;
619 struct vfpf_start_rxq_tlv *req;
620 u16 rx_qid = p_cid->rel.queue_id;
621 enum _ecore_status_t rc;
622
623 /* clear mailbox and prep first tlv */
624 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_START_RXQ, sizeof(*req));
625
626 req->rx_qid = rx_qid;
627 req->cqe_pbl_addr = cqe_pbl_addr;
628 req->cqe_pbl_size = cqe_pbl_size;
629 req->rxq_addr = bd_chain_phys_addr;
630 req->hw_sb = p_cid->rel.sb;
631 req->sb_index = p_cid->rel.sb_idx;
632 req->bd_max_bytes = bd_max_bytes;
633 req->stat_id = -1; /* Keep initialized, for future compatibility */
634
635 /* If PF is legacy, we'll need to calculate producers ourselves
636 * as well as clean them.
637 */
638 if (p_iov->b_pre_fp_hsi) {
639 u8 hw_qid = p_iov->acquire_resp.resc.hw_qid[rx_qid];
640 u32 init_prod_val = 0;
641
642 *pp_prod = (u8 OSAL_IOMEM *)
643 p_hwfn->regview +
644 MSTORM_QZONE_START(p_hwfn->p_dev) +
645 (hw_qid) * MSTORM_QZONE_SIZE;
646
647 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
648 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
649 (u32 *)(&init_prod_val));
650 }
651
652 /* add list termination tlv */
653 ecore_add_tlv(p_hwfn, &p_iov->offset,
654 CHANNEL_TLV_LIST_END,
655 sizeof(struct channel_list_end_tlv));
656
657 resp = &p_iov->pf2vf_reply->queue_start;
658 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
659 if (rc)
660 goto exit;
661
662 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
663 rc = ECORE_INVAL;
664 goto exit;
665 }
666
667 /* Learn the address of the producer from the response */
668 if (!p_iov->b_pre_fp_hsi) {
669 u32 init_prod_val = 0;
670
671 *pp_prod = (u8 OSAL_IOMEM *)p_hwfn->regview + resp->offset;
672 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
673 "Rxq[0x%02x]: producer at %p [offset 0x%08x]\n",
674 rx_qid, *pp_prod, resp->offset);
675
676 /* Init the rcq, rx bd and rx sge (if valid) producers to 0.
677 * It was actually the PF's responsibility, but since some
678 * old PFs might fail to do so, we do this as well.
679 */
680 OSAL_BUILD_BUG_ON(ETH_HSI_VER_MAJOR != 3);
681 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
682 (u32 *)&init_prod_val);
683 }
684
685 exit:
686 ecore_vf_pf_req_end(p_hwfn, rc);
687
688 return rc;
689 }
690
691 enum _ecore_status_t ecore_vf_pf_rxq_stop(struct ecore_hwfn *p_hwfn,
692 struct ecore_queue_cid *p_cid,
693 bool cqe_completion)
694 {
695 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
696 struct vfpf_stop_rxqs_tlv *req;
697 struct pfvf_def_resp_tlv *resp;
698 enum _ecore_status_t rc;
699
700 /* clear mailbox and prep first tlv */
701 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_STOP_RXQS, sizeof(*req));
702
703 req->rx_qid = p_cid->rel.queue_id;
704 req->num_rxqs = 1;
705 req->cqe_completion = cqe_completion;
706
707 /* add list termination tlv */
708 ecore_add_tlv(p_hwfn, &p_iov->offset,
709 CHANNEL_TLV_LIST_END,
710 sizeof(struct channel_list_end_tlv));
711
712 resp = &p_iov->pf2vf_reply->default_resp;
713 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
714 if (rc)
715 goto exit;
716
717 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
718 rc = ECORE_INVAL;
719 goto exit;
720 }
721
722 exit:
723 ecore_vf_pf_req_end(p_hwfn, rc);
724
725 return rc;
726 }
727
728 enum _ecore_status_t
729 ecore_vf_pf_txq_start(struct ecore_hwfn *p_hwfn,
730 struct ecore_queue_cid *p_cid,
731 dma_addr_t pbl_addr, u16 pbl_size,
732 void OSAL_IOMEM **pp_doorbell)
733 {
734 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
735 struct pfvf_start_queue_resp_tlv *resp;
736 struct vfpf_start_txq_tlv *req;
737 u16 qid = p_cid->rel.queue_id;
738 enum _ecore_status_t rc;
739
740 /* clear mailbox and prep first tlv */
741 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_START_TXQ, sizeof(*req));
742
743 req->tx_qid = qid;
744
745 /* Tx */
746 req->pbl_addr = pbl_addr;
747 req->pbl_size = pbl_size;
748 req->hw_sb = p_cid->rel.sb;
749 req->sb_index = p_cid->rel.sb_idx;
750
751 /* add list termination tlv */
752 ecore_add_tlv(p_hwfn, &p_iov->offset,
753 CHANNEL_TLV_LIST_END,
754 sizeof(struct channel_list_end_tlv));
755
756 resp = &p_iov->pf2vf_reply->queue_start;
757 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
758 if (rc)
759 goto exit;
760
761 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
762 rc = ECORE_INVAL;
763 goto exit;
764 }
765
766 /* Modern PFs provide the actual offsets, while legacy
767 * provided only the queue id.
768 */
769 if (!p_iov->b_pre_fp_hsi) {
770 *pp_doorbell = (u8 OSAL_IOMEM *)p_hwfn->doorbells +
771 resp->offset;
772 } else {
773 u8 cid = p_iov->acquire_resp.resc.cid[qid];
774
775 *pp_doorbell = (u8 OSAL_IOMEM *)p_hwfn->doorbells +
776 DB_ADDR_VF(cid, DQ_DEMS_LEGACY);
777 }
778
779 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
780 "Txq[0x%02x]: doorbell at %p [offset 0x%08x]\n",
781 qid, *pp_doorbell, resp->offset);
782 exit:
783 ecore_vf_pf_req_end(p_hwfn, rc);
784
785 return rc;
786 }
787
788 enum _ecore_status_t ecore_vf_pf_txq_stop(struct ecore_hwfn *p_hwfn,
789 struct ecore_queue_cid *p_cid)
790 {
791 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
792 struct vfpf_stop_txqs_tlv *req;
793 struct pfvf_def_resp_tlv *resp;
794 enum _ecore_status_t rc;
795
796 /* clear mailbox and prep first tlv */
797 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_STOP_TXQS, sizeof(*req));
798
799 req->tx_qid = p_cid->rel.queue_id;
800 req->num_txqs = 1;
801
802 /* add list termination tlv */
803 ecore_add_tlv(p_hwfn, &p_iov->offset,
804 CHANNEL_TLV_LIST_END,
805 sizeof(struct channel_list_end_tlv));
806
807 resp = &p_iov->pf2vf_reply->default_resp;
808 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
809 if (rc)
810 goto exit;
811
812 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
813 rc = ECORE_INVAL;
814 goto exit;
815 }
816
817 exit:
818 ecore_vf_pf_req_end(p_hwfn, rc);
819
820 return rc;
821 }
822
823 enum _ecore_status_t ecore_vf_pf_rxqs_update(struct ecore_hwfn *p_hwfn,
824 struct ecore_queue_cid **pp_cid,
825 u8 num_rxqs,
826 u8 comp_cqe_flg,
827 u8 comp_event_flg)
828 {
829 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
830 struct pfvf_def_resp_tlv *resp = &p_iov->pf2vf_reply->default_resp;
831 struct vfpf_update_rxq_tlv *req;
832 enum _ecore_status_t rc;
833
834 /* TODO - API is limited to assuming continuous regions of queues,
835 * but VF queues might not fullfil this requirement.
836 * Need to consider whether we need new TLVs for this, or whether
837 * simply doing it iteratively is good enough.
838 */
839 if (!num_rxqs)
840 return ECORE_INVAL;
841
842 again:
843 /* clear mailbox and prep first tlv */
844 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_UPDATE_RXQ, sizeof(*req));
845
846 /* Find the length of the current contagious range of queues beginning
847 * at first queue's index.
848 */
849 req->rx_qid = (*pp_cid)->rel.queue_id;
850 for (req->num_rxqs = 1; req->num_rxqs < num_rxqs; req->num_rxqs++)
851 if (pp_cid[req->num_rxqs]->rel.queue_id !=
852 req->rx_qid + req->num_rxqs)
853 break;
854
855 if (comp_cqe_flg)
856 req->flags |= VFPF_RXQ_UPD_COMPLETE_CQE_FLAG;
857 if (comp_event_flg)
858 req->flags |= VFPF_RXQ_UPD_COMPLETE_EVENT_FLAG;
859
860 /* add list termination tlv */
861 ecore_add_tlv(p_hwfn, &p_iov->offset,
862 CHANNEL_TLV_LIST_END,
863 sizeof(struct channel_list_end_tlv));
864
865 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
866 if (rc)
867 goto exit;
868
869 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
870 rc = ECORE_INVAL;
871 goto exit;
872 }
873
874 /* Make sure we're done with all the queues */
875 if (req->num_rxqs < num_rxqs) {
876 num_rxqs -= req->num_rxqs;
877 pp_cid += req->num_rxqs;
878 /* TODO - should we give a non-locked variant instead? */
879 ecore_vf_pf_req_end(p_hwfn, rc);
880 goto again;
881 }
882
883 exit:
884 ecore_vf_pf_req_end(p_hwfn, rc);
885 return rc;
886 }
887
888 enum _ecore_status_t
889 ecore_vf_pf_vport_start(struct ecore_hwfn *p_hwfn, u8 vport_id,
890 u16 mtu, u8 inner_vlan_removal,
891 enum ecore_tpa_mode tpa_mode, u8 max_buffers_per_cqe,
892 u8 only_untagged)
893 {
894 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
895 struct vfpf_vport_start_tlv *req;
896 struct pfvf_def_resp_tlv *resp;
897 enum _ecore_status_t rc;
898 int i;
899
900 /* clear mailbox and prep first tlv */
901 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_VPORT_START, sizeof(*req));
902
903 req->mtu = mtu;
904 req->vport_id = vport_id;
905 req->inner_vlan_removal = inner_vlan_removal;
906 req->tpa_mode = tpa_mode;
907 req->max_buffers_per_cqe = max_buffers_per_cqe;
908 req->only_untagged = only_untagged;
909
910 /* status blocks */
911 for (i = 0; i < p_hwfn->vf_iov_info->acquire_resp.resc.num_sbs; i++)
912 if (p_hwfn->sbs_info[i])
913 req->sb_addr[i] = p_hwfn->sbs_info[i]->sb_phys;
914
915 /* add list termination tlv */
916 ecore_add_tlv(p_hwfn, &p_iov->offset,
917 CHANNEL_TLV_LIST_END,
918 sizeof(struct channel_list_end_tlv));
919
920 resp = &p_iov->pf2vf_reply->default_resp;
921 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
922 if (rc)
923 goto exit;
924
925 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
926 rc = ECORE_INVAL;
927 goto exit;
928 }
929
930 exit:
931 ecore_vf_pf_req_end(p_hwfn, rc);
932
933 return rc;
934 }
935
936 enum _ecore_status_t ecore_vf_pf_vport_stop(struct ecore_hwfn *p_hwfn)
937 {
938 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
939 struct pfvf_def_resp_tlv *resp = &p_iov->pf2vf_reply->default_resp;
940 enum _ecore_status_t rc;
941
942 /* clear mailbox and prep first tlv */
943 ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_VPORT_TEARDOWN,
944 sizeof(struct vfpf_first_tlv));
945
946 /* add list termination tlv */
947 ecore_add_tlv(p_hwfn, &p_iov->offset,
948 CHANNEL_TLV_LIST_END,
949 sizeof(struct channel_list_end_tlv));
950
951 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
952 if (rc)
953 goto exit;
954
955 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
956 rc = ECORE_INVAL;
957 goto exit;
958 }
959
960 exit:
961 ecore_vf_pf_req_end(p_hwfn, rc);
962
963 return rc;
964 }
965
966 static bool
967 ecore_vf_handle_vp_update_is_needed(struct ecore_hwfn *p_hwfn,
968 struct ecore_sp_vport_update_params *p_data,
969 u16 tlv)
970 {
971 switch (tlv) {
972 case CHANNEL_TLV_VPORT_UPDATE_ACTIVATE:
973 return !!(p_data->update_vport_active_rx_flg ||
974 p_data->update_vport_active_tx_flg);
975 case CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH:
976 #ifndef ASIC_ONLY
977 /* FPGA doesn't have PVFC and so can't support tx-switching */
978 return !!(p_data->update_tx_switching_flg &&
979 !CHIP_REV_IS_FPGA(p_hwfn->p_dev));
980 #else
981 return !!p_data->update_tx_switching_flg;
982 #endif
983 case CHANNEL_TLV_VPORT_UPDATE_VLAN_STRIP:
984 return !!p_data->update_inner_vlan_removal_flg;
985 case CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN:
986 return !!p_data->update_accept_any_vlan_flg;
987 case CHANNEL_TLV_VPORT_UPDATE_MCAST:
988 return !!p_data->update_approx_mcast_flg;
989 case CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM:
990 return !!(p_data->accept_flags.update_rx_mode_config ||
991 p_data->accept_flags.update_tx_mode_config);
992 case CHANNEL_TLV_VPORT_UPDATE_RSS:
993 return !!p_data->rss_params;
994 case CHANNEL_TLV_VPORT_UPDATE_SGE_TPA:
995 return !!p_data->sge_tpa_params;
996 default:
997 DP_INFO(p_hwfn, "Unexpected vport-update TLV[%d] %s\n",
998 tlv, ecore_channel_tlvs_string[tlv]);
999 return false;
1000 }
1001 }
1002
1003 static void
1004 ecore_vf_handle_vp_update_tlvs_resp(struct ecore_hwfn *p_hwfn,
1005 struct ecore_sp_vport_update_params *p_data)
1006 {
1007 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1008 struct pfvf_def_resp_tlv *p_resp;
1009 u16 tlv;
1010
1011 for (tlv = CHANNEL_TLV_VPORT_UPDATE_ACTIVATE;
1012 tlv < CHANNEL_TLV_VPORT_UPDATE_MAX;
1013 tlv++) {
1014 if (!ecore_vf_handle_vp_update_is_needed(p_hwfn, p_data, tlv))
1015 continue;
1016
1017 p_resp = (struct pfvf_def_resp_tlv *)
1018 ecore_iov_search_list_tlvs(p_hwfn, p_iov->pf2vf_reply, tlv);
1019 if (p_resp && p_resp->hdr.status)
1020 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1021 "TLV[%d] type %s Configuration %s\n",
1022 tlv, ecore_channel_tlvs_string[tlv],
1023 (p_resp && p_resp->hdr.status) ? "succeeded"
1024 : "failed");
1025 }
1026 }
1027
1028 enum _ecore_status_t
1029 ecore_vf_pf_vport_update(struct ecore_hwfn *p_hwfn,
1030 struct ecore_sp_vport_update_params *p_params)
1031 {
1032 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1033 struct vfpf_vport_update_tlv *req;
1034 struct pfvf_def_resp_tlv *resp;
1035 u8 update_rx, update_tx;
1036 u32 resp_size = 0;
1037 u16 size, tlv;
1038 enum _ecore_status_t rc;
1039
1040 resp = &p_iov->pf2vf_reply->default_resp;
1041 resp_size = sizeof(*resp);
1042
1043 update_rx = p_params->update_vport_active_rx_flg;
1044 update_tx = p_params->update_vport_active_tx_flg;
1045
1046 /* clear mailbox and prep header tlv */
1047 ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_VPORT_UPDATE, sizeof(*req));
1048
1049 /* Prepare extended tlvs */
1050 if (update_rx || update_tx) {
1051 struct vfpf_vport_update_activate_tlv *p_act_tlv;
1052
1053 size = sizeof(struct vfpf_vport_update_activate_tlv);
1054 p_act_tlv = ecore_add_tlv(p_hwfn, &p_iov->offset,
1055 CHANNEL_TLV_VPORT_UPDATE_ACTIVATE,
1056 size);
1057 resp_size += sizeof(struct pfvf_def_resp_tlv);
1058
1059 if (update_rx) {
1060 p_act_tlv->update_rx = update_rx;
1061 p_act_tlv->active_rx = p_params->vport_active_rx_flg;
1062 }
1063
1064 if (update_tx) {
1065 p_act_tlv->update_tx = update_tx;
1066 p_act_tlv->active_tx = p_params->vport_active_tx_flg;
1067 }
1068 }
1069
1070 if (p_params->update_inner_vlan_removal_flg) {
1071 struct vfpf_vport_update_vlan_strip_tlv *p_vlan_tlv;
1072
1073 size = sizeof(struct vfpf_vport_update_vlan_strip_tlv);
1074 p_vlan_tlv = ecore_add_tlv(p_hwfn, &p_iov->offset,
1075 CHANNEL_TLV_VPORT_UPDATE_VLAN_STRIP,
1076 size);
1077 resp_size += sizeof(struct pfvf_def_resp_tlv);
1078
1079 p_vlan_tlv->remove_vlan = p_params->inner_vlan_removal_flg;
1080 }
1081
1082 if (p_params->update_tx_switching_flg) {
1083 struct vfpf_vport_update_tx_switch_tlv *p_tx_switch_tlv;
1084
1085 size = sizeof(struct vfpf_vport_update_tx_switch_tlv);
1086 tlv = CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH;
1087 p_tx_switch_tlv = ecore_add_tlv(p_hwfn, &p_iov->offset,
1088 tlv, size);
1089 resp_size += sizeof(struct pfvf_def_resp_tlv);
1090
1091 p_tx_switch_tlv->tx_switching = p_params->tx_switching_flg;
1092 }
1093
1094 if (p_params->update_approx_mcast_flg) {
1095 struct vfpf_vport_update_mcast_bin_tlv *p_mcast_tlv;
1096
1097 size = sizeof(struct vfpf_vport_update_mcast_bin_tlv);
1098 p_mcast_tlv = ecore_add_tlv(p_hwfn, &p_iov->offset,
1099 CHANNEL_TLV_VPORT_UPDATE_MCAST,
1100 size);
1101 resp_size += sizeof(struct pfvf_def_resp_tlv);
1102
1103 OSAL_MEMCPY(p_mcast_tlv->bins, p_params->bins,
1104 sizeof(unsigned long) *
1105 ETH_MULTICAST_MAC_BINS_IN_REGS);
1106 }
1107
1108 update_rx = p_params->accept_flags.update_rx_mode_config;
1109 update_tx = p_params->accept_flags.update_tx_mode_config;
1110
1111 if (update_rx || update_tx) {
1112 struct vfpf_vport_update_accept_param_tlv *p_accept_tlv;
1113
1114 tlv = CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM;
1115 size = sizeof(struct vfpf_vport_update_accept_param_tlv);
1116 p_accept_tlv = ecore_add_tlv(p_hwfn, &p_iov->offset, tlv, size);
1117 resp_size += sizeof(struct pfvf_def_resp_tlv);
1118
1119 if (update_rx) {
1120 p_accept_tlv->update_rx_mode = update_rx;
1121 p_accept_tlv->rx_accept_filter =
1122 p_params->accept_flags.rx_accept_filter;
1123 }
1124
1125 if (update_tx) {
1126 p_accept_tlv->update_tx_mode = update_tx;
1127 p_accept_tlv->tx_accept_filter =
1128 p_params->accept_flags.tx_accept_filter;
1129 }
1130 }
1131
1132 if (p_params->rss_params) {
1133 struct ecore_rss_params *rss_params = p_params->rss_params;
1134 struct vfpf_vport_update_rss_tlv *p_rss_tlv;
1135 int i, table_size;
1136
1137 size = sizeof(struct vfpf_vport_update_rss_tlv);
1138 p_rss_tlv = ecore_add_tlv(p_hwfn, &p_iov->offset,
1139 CHANNEL_TLV_VPORT_UPDATE_RSS, size);
1140 resp_size += sizeof(struct pfvf_def_resp_tlv);
1141
1142 if (rss_params->update_rss_config)
1143 p_rss_tlv->update_rss_flags |=
1144 VFPF_UPDATE_RSS_CONFIG_FLAG;
1145 if (rss_params->update_rss_capabilities)
1146 p_rss_tlv->update_rss_flags |=
1147 VFPF_UPDATE_RSS_CAPS_FLAG;
1148 if (rss_params->update_rss_ind_table)
1149 p_rss_tlv->update_rss_flags |=
1150 VFPF_UPDATE_RSS_IND_TABLE_FLAG;
1151 if (rss_params->update_rss_key)
1152 p_rss_tlv->update_rss_flags |= VFPF_UPDATE_RSS_KEY_FLAG;
1153
1154 p_rss_tlv->rss_enable = rss_params->rss_enable;
1155 p_rss_tlv->rss_caps = rss_params->rss_caps;
1156 p_rss_tlv->rss_table_size_log = rss_params->rss_table_size_log;
1157
1158 table_size = OSAL_MIN_T(int, T_ETH_INDIRECTION_TABLE_SIZE,
1159 1 << p_rss_tlv->rss_table_size_log);
1160 for (i = 0; i < table_size; i++) {
1161 struct ecore_queue_cid *p_queue;
1162
1163 p_queue = rss_params->rss_ind_table[i];
1164 p_rss_tlv->rss_ind_table[i] = p_queue->rel.queue_id;
1165 }
1166
1167 OSAL_MEMCPY(p_rss_tlv->rss_key, rss_params->rss_key,
1168 sizeof(rss_params->rss_key));
1169 }
1170
1171 if (p_params->update_accept_any_vlan_flg) {
1172 struct vfpf_vport_update_accept_any_vlan_tlv *p_any_vlan_tlv;
1173
1174 size = sizeof(struct vfpf_vport_update_accept_any_vlan_tlv);
1175 tlv = CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN;
1176 p_any_vlan_tlv = ecore_add_tlv(p_hwfn, &p_iov->offset,
1177 tlv, size);
1178
1179 resp_size += sizeof(struct pfvf_def_resp_tlv);
1180 p_any_vlan_tlv->accept_any_vlan = p_params->accept_any_vlan;
1181 p_any_vlan_tlv->update_accept_any_vlan_flg =
1182 p_params->update_accept_any_vlan_flg;
1183 }
1184
1185 if (p_params->sge_tpa_params) {
1186 struct ecore_sge_tpa_params *sge_tpa_params;
1187 struct vfpf_vport_update_sge_tpa_tlv *p_sge_tpa_tlv;
1188
1189 sge_tpa_params = p_params->sge_tpa_params;
1190 size = sizeof(struct vfpf_vport_update_sge_tpa_tlv);
1191 p_sge_tpa_tlv = ecore_add_tlv(p_hwfn, &p_iov->offset,
1192 CHANNEL_TLV_VPORT_UPDATE_SGE_TPA,
1193 size);
1194 resp_size += sizeof(struct pfvf_def_resp_tlv);
1195
1196 if (sge_tpa_params->update_tpa_en_flg)
1197 p_sge_tpa_tlv->update_sge_tpa_flags |=
1198 VFPF_UPDATE_TPA_EN_FLAG;
1199 if (sge_tpa_params->update_tpa_param_flg)
1200 p_sge_tpa_tlv->update_sge_tpa_flags |=
1201 VFPF_UPDATE_TPA_PARAM_FLAG;
1202
1203 if (sge_tpa_params->tpa_ipv4_en_flg)
1204 p_sge_tpa_tlv->sge_tpa_flags |= VFPF_TPA_IPV4_EN_FLAG;
1205 if (sge_tpa_params->tpa_ipv6_en_flg)
1206 p_sge_tpa_tlv->sge_tpa_flags |= VFPF_TPA_IPV6_EN_FLAG;
1207 if (sge_tpa_params->tpa_pkt_split_flg)
1208 p_sge_tpa_tlv->sge_tpa_flags |= VFPF_TPA_PKT_SPLIT_FLAG;
1209 if (sge_tpa_params->tpa_hdr_data_split_flg)
1210 p_sge_tpa_tlv->sge_tpa_flags |=
1211 VFPF_TPA_HDR_DATA_SPLIT_FLAG;
1212 if (sge_tpa_params->tpa_gro_consistent_flg)
1213 p_sge_tpa_tlv->sge_tpa_flags |=
1214 VFPF_TPA_GRO_CONSIST_FLAG;
1215
1216 p_sge_tpa_tlv->tpa_max_aggs_num =
1217 sge_tpa_params->tpa_max_aggs_num;
1218 p_sge_tpa_tlv->tpa_max_size = sge_tpa_params->tpa_max_size;
1219 p_sge_tpa_tlv->tpa_min_size_to_start =
1220 sge_tpa_params->tpa_min_size_to_start;
1221 p_sge_tpa_tlv->tpa_min_size_to_cont =
1222 sge_tpa_params->tpa_min_size_to_cont;
1223
1224 p_sge_tpa_tlv->max_buffers_per_cqe =
1225 sge_tpa_params->max_buffers_per_cqe;
1226 }
1227
1228 /* add list termination tlv */
1229 ecore_add_tlv(p_hwfn, &p_iov->offset,
1230 CHANNEL_TLV_LIST_END,
1231 sizeof(struct channel_list_end_tlv));
1232
1233 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, resp_size);
1234 if (rc)
1235 goto exit;
1236
1237 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1238 rc = ECORE_INVAL;
1239 goto exit;
1240 }
1241
1242 ecore_vf_handle_vp_update_tlvs_resp(p_hwfn, p_params);
1243
1244 exit:
1245 ecore_vf_pf_req_end(p_hwfn, rc);
1246
1247 return rc;
1248 }
1249
1250 enum _ecore_status_t ecore_vf_pf_reset(struct ecore_hwfn *p_hwfn)
1251 {
1252 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1253 struct pfvf_def_resp_tlv *resp;
1254 struct vfpf_first_tlv *req;
1255 enum _ecore_status_t rc;
1256
1257 /* clear mailbox and prep first tlv */
1258 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_CLOSE, sizeof(*req));
1259
1260 /* add list termination tlv */
1261 ecore_add_tlv(p_hwfn, &p_iov->offset,
1262 CHANNEL_TLV_LIST_END,
1263 sizeof(struct channel_list_end_tlv));
1264
1265 resp = &p_iov->pf2vf_reply->default_resp;
1266 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1267 if (rc)
1268 goto exit;
1269
1270 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1271 rc = ECORE_AGAIN;
1272 goto exit;
1273 }
1274
1275 p_hwfn->b_int_enabled = 0;
1276
1277 exit:
1278 ecore_vf_pf_req_end(p_hwfn, rc);
1279
1280 return rc;
1281 }
1282
1283 enum _ecore_status_t ecore_vf_pf_release(struct ecore_hwfn *p_hwfn)
1284 {
1285 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1286 struct pfvf_def_resp_tlv *resp;
1287 struct vfpf_first_tlv *req;
1288 u32 size;
1289 enum _ecore_status_t rc;
1290
1291 /* clear mailbox and prep first tlv */
1292 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_RELEASE, sizeof(*req));
1293
1294 /* add list termination tlv */
1295 ecore_add_tlv(p_hwfn, &p_iov->offset,
1296 CHANNEL_TLV_LIST_END,
1297 sizeof(struct channel_list_end_tlv));
1298
1299 resp = &p_iov->pf2vf_reply->default_resp;
1300 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1301
1302 if (rc == ECORE_SUCCESS && resp->hdr.status != PFVF_STATUS_SUCCESS)
1303 rc = ECORE_AGAIN;
1304
1305 ecore_vf_pf_req_end(p_hwfn, rc);
1306
1307 p_hwfn->b_int_enabled = 0;
1308
1309 if (p_iov->vf2pf_request)
1310 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1311 p_iov->vf2pf_request,
1312 p_iov->vf2pf_request_phys,
1313 sizeof(union vfpf_tlvs));
1314 if (p_iov->pf2vf_reply)
1315 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1316 p_iov->pf2vf_reply,
1317 p_iov->pf2vf_reply_phys,
1318 sizeof(union pfvf_tlvs));
1319
1320 if (p_iov->bulletin.p_virt) {
1321 size = sizeof(struct ecore_bulletin_content);
1322 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1323 p_iov->bulletin.p_virt,
1324 p_iov->bulletin.phys, size);
1325 }
1326
1327 OSAL_FREE(p_hwfn->p_dev, p_hwfn->vf_iov_info);
1328
1329 return rc;
1330 }
1331
1332 void ecore_vf_pf_filter_mcast(struct ecore_hwfn *p_hwfn,
1333 struct ecore_filter_mcast *p_filter_cmd)
1334 {
1335 struct ecore_sp_vport_update_params sp_params;
1336 int i;
1337
1338 OSAL_MEMSET(&sp_params, 0, sizeof(sp_params));
1339 sp_params.update_approx_mcast_flg = 1;
1340
1341 if (p_filter_cmd->opcode == ECORE_FILTER_ADD) {
1342 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1343 u32 bit;
1344
1345 bit = ecore_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1346 OSAL_SET_BIT(bit, sp_params.bins);
1347 }
1348 }
1349
1350 ecore_vf_pf_vport_update(p_hwfn, &sp_params);
1351 }
1352
1353 enum _ecore_status_t ecore_vf_pf_filter_ucast(struct ecore_hwfn *p_hwfn,
1354 struct ecore_filter_ucast
1355 *p_ucast)
1356 {
1357 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1358 struct vfpf_ucast_filter_tlv *req;
1359 struct pfvf_def_resp_tlv *resp;
1360 enum _ecore_status_t rc;
1361
1362 /* Sanitize */
1363 if (p_ucast->opcode == ECORE_FILTER_MOVE) {
1364 DP_NOTICE(p_hwfn, true,
1365 "VFs don't support Moving of filters\n");
1366 return ECORE_INVAL;
1367 }
1368
1369 /* clear mailbox and prep first tlv */
1370 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_UCAST_FILTER, sizeof(*req));
1371 req->opcode = (u8)p_ucast->opcode;
1372 req->type = (u8)p_ucast->type;
1373 OSAL_MEMCPY(req->mac, p_ucast->mac, ETH_ALEN);
1374 req->vlan = p_ucast->vlan;
1375
1376 /* add list termination tlv */
1377 ecore_add_tlv(p_hwfn, &p_iov->offset,
1378 CHANNEL_TLV_LIST_END,
1379 sizeof(struct channel_list_end_tlv));
1380
1381 resp = &p_iov->pf2vf_reply->default_resp;
1382 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1383 if (rc)
1384 goto exit;
1385
1386 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1387 rc = ECORE_AGAIN;
1388 goto exit;
1389 }
1390
1391 exit:
1392 ecore_vf_pf_req_end(p_hwfn, rc);
1393
1394 return rc;
1395 }
1396
1397 enum _ecore_status_t ecore_vf_pf_int_cleanup(struct ecore_hwfn *p_hwfn)
1398 {
1399 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1400 struct pfvf_def_resp_tlv *resp = &p_iov->pf2vf_reply->default_resp;
1401 enum _ecore_status_t rc;
1402
1403 /* clear mailbox and prep first tlv */
1404 ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_INT_CLEANUP,
1405 sizeof(struct vfpf_first_tlv));
1406
1407 /* add list termination tlv */
1408 ecore_add_tlv(p_hwfn, &p_iov->offset,
1409 CHANNEL_TLV_LIST_END,
1410 sizeof(struct channel_list_end_tlv));
1411
1412 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1413 if (rc)
1414 goto exit;
1415
1416 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1417 rc = ECORE_INVAL;
1418 goto exit;
1419 }
1420
1421 exit:
1422 ecore_vf_pf_req_end(p_hwfn, rc);
1423
1424 return rc;
1425 }
1426
1427 enum _ecore_status_t
1428 ecore_vf_pf_set_coalesce(struct ecore_hwfn *p_hwfn, u16 rx_coal, u16 tx_coal,
1429 struct ecore_queue_cid *p_cid)
1430 {
1431 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1432 struct vfpf_update_coalesce *req;
1433 struct pfvf_def_resp_tlv *resp;
1434 enum _ecore_status_t rc;
1435
1436 /* clear mailbox and prep header tlv */
1437 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_COALESCE_UPDATE,
1438 sizeof(*req));
1439
1440 req->rx_coal = rx_coal;
1441 req->tx_coal = tx_coal;
1442 req->qid = p_cid->rel.queue_id;
1443
1444 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1445 "Setting coalesce rx_coal = %d, tx_coal = %d at queue = %d\n",
1446 rx_coal, tx_coal, req->qid);
1447
1448 /* add list termination tlv */
1449 ecore_add_tlv(p_hwfn, &p_iov->offset, CHANNEL_TLV_LIST_END,
1450 sizeof(struct channel_list_end_tlv));
1451
1452 resp = &p_iov->pf2vf_reply->default_resp;
1453 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1454
1455 if (rc != ECORE_SUCCESS)
1456 goto exit;
1457
1458 if (resp->hdr.status != PFVF_STATUS_SUCCESS)
1459 goto exit;
1460
1461 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
1462 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
1463
1464 exit:
1465 ecore_vf_pf_req_end(p_hwfn, rc);
1466 return rc;
1467 }
1468
1469 u16 ecore_vf_get_igu_sb_id(struct ecore_hwfn *p_hwfn,
1470 u16 sb_id)
1471 {
1472 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1473
1474 if (!p_iov) {
1475 DP_NOTICE(p_hwfn, true, "vf_sriov_info isn't initialized\n");
1476 return 0;
1477 }
1478
1479 return p_iov->acquire_resp.resc.hw_sbs[sb_id].hw_sb_id;
1480 }
1481
1482 enum _ecore_status_t ecore_vf_read_bulletin(struct ecore_hwfn *p_hwfn,
1483 u8 *p_change)
1484 {
1485 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1486 struct ecore_bulletin_content shadow;
1487 u32 crc, crc_size;
1488
1489 crc_size = sizeof(p_iov->bulletin.p_virt->crc);
1490 *p_change = 0;
1491
1492 /* Need to guarantee PF is not in the middle of writing it */
1493 OSAL_MEMCPY(&shadow, p_iov->bulletin.p_virt, p_iov->bulletin.size);
1494
1495 /* If version did not update, no need to do anything */
1496 if (shadow.version == p_iov->bulletin_shadow.version)
1497 return ECORE_SUCCESS;
1498
1499 /* Verify the bulletin we see is valid */
1500 crc = ecore_crc32(0, (u8 *)&shadow + crc_size,
1501 p_iov->bulletin.size - crc_size);
1502 if (crc != shadow.crc)
1503 return ECORE_AGAIN;
1504
1505 /* Set the shadow bulletin and process it */
1506 OSAL_MEMCPY(&p_iov->bulletin_shadow, &shadow, p_iov->bulletin.size);
1507
1508 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1509 "Read a bulletin update %08x\n", shadow.version);
1510
1511 *p_change = 1;
1512
1513 return ECORE_SUCCESS;
1514 }
1515
1516 void __ecore_vf_get_link_params(struct ecore_hwfn *p_hwfn,
1517 struct ecore_mcp_link_params *p_params,
1518 struct ecore_bulletin_content *p_bulletin)
1519 {
1520 OSAL_MEMSET(p_params, 0, sizeof(*p_params));
1521
1522 p_params->speed.autoneg = p_bulletin->req_autoneg;
1523 p_params->speed.advertised_speeds = p_bulletin->req_adv_speed;
1524 p_params->speed.forced_speed = p_bulletin->req_forced_speed;
1525 p_params->pause.autoneg = p_bulletin->req_autoneg_pause;
1526 p_params->pause.forced_rx = p_bulletin->req_forced_rx;
1527 p_params->pause.forced_tx = p_bulletin->req_forced_tx;
1528 p_params->loopback_mode = p_bulletin->req_loopback;
1529 }
1530
1531 void ecore_vf_get_link_params(struct ecore_hwfn *p_hwfn,
1532 struct ecore_mcp_link_params *params)
1533 {
1534 __ecore_vf_get_link_params(p_hwfn, params,
1535 &p_hwfn->vf_iov_info->bulletin_shadow);
1536 }
1537
1538 void __ecore_vf_get_link_state(struct ecore_hwfn *p_hwfn,
1539 struct ecore_mcp_link_state *p_link,
1540 struct ecore_bulletin_content *p_bulletin)
1541 {
1542 OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1543
1544 p_link->link_up = p_bulletin->link_up;
1545 p_link->speed = p_bulletin->speed;
1546 p_link->full_duplex = p_bulletin->full_duplex;
1547 p_link->an = p_bulletin->autoneg;
1548 p_link->an_complete = p_bulletin->autoneg_complete;
1549 p_link->parallel_detection = p_bulletin->parallel_detection;
1550 p_link->pfc_enabled = p_bulletin->pfc_enabled;
1551 p_link->partner_adv_speed = p_bulletin->partner_adv_speed;
1552 p_link->partner_tx_flow_ctrl_en = p_bulletin->partner_tx_flow_ctrl_en;
1553 p_link->partner_rx_flow_ctrl_en = p_bulletin->partner_rx_flow_ctrl_en;
1554 p_link->partner_adv_pause = p_bulletin->partner_adv_pause;
1555 p_link->sfp_tx_fault = p_bulletin->sfp_tx_fault;
1556 }
1557
1558 void ecore_vf_get_link_state(struct ecore_hwfn *p_hwfn,
1559 struct ecore_mcp_link_state *link)
1560 {
1561 __ecore_vf_get_link_state(p_hwfn, link,
1562 &p_hwfn->vf_iov_info->bulletin_shadow);
1563 }
1564
1565 void __ecore_vf_get_link_caps(struct ecore_hwfn *p_hwfn,
1566 struct ecore_mcp_link_capabilities *p_link_caps,
1567 struct ecore_bulletin_content *p_bulletin)
1568 {
1569 OSAL_MEMSET(p_link_caps, 0, sizeof(*p_link_caps));
1570 p_link_caps->speed_capabilities = p_bulletin->capability_speed;
1571 }
1572
1573 void ecore_vf_get_link_caps(struct ecore_hwfn *p_hwfn,
1574 struct ecore_mcp_link_capabilities *p_link_caps)
1575 {
1576 __ecore_vf_get_link_caps(p_hwfn, p_link_caps,
1577 &p_hwfn->vf_iov_info->bulletin_shadow);
1578 }
1579
1580 void ecore_vf_get_num_rxqs(struct ecore_hwfn *p_hwfn, u8 *num_rxqs)
1581 {
1582 *num_rxqs = p_hwfn->vf_iov_info->acquire_resp.resc.num_rxqs;
1583 }
1584
1585 void ecore_vf_get_num_txqs(struct ecore_hwfn *p_hwfn,
1586 u8 *num_txqs)
1587 {
1588 *num_txqs = p_hwfn->vf_iov_info->acquire_resp.resc.num_txqs;
1589 }
1590
1591 void ecore_vf_get_port_mac(struct ecore_hwfn *p_hwfn, u8 *port_mac)
1592 {
1593 OSAL_MEMCPY(port_mac,
1594 p_hwfn->vf_iov_info->acquire_resp.pfdev_info.port_mac,
1595 ETH_ALEN);
1596 }
1597
1598 void ecore_vf_get_num_vlan_filters(struct ecore_hwfn *p_hwfn,
1599 u8 *num_vlan_filters)
1600 {
1601 struct ecore_vf_iov *p_vf;
1602
1603 p_vf = p_hwfn->vf_iov_info;
1604 *num_vlan_filters = p_vf->acquire_resp.resc.num_vlan_filters;
1605 }
1606
1607 void ecore_vf_get_num_sbs(struct ecore_hwfn *p_hwfn,
1608 u32 *num_sbs)
1609 {
1610 struct ecore_vf_iov *p_vf;
1611
1612 p_vf = p_hwfn->vf_iov_info;
1613 *num_sbs = (u32)p_vf->acquire_resp.resc.num_sbs;
1614 }
1615
1616 void ecore_vf_get_num_mac_filters(struct ecore_hwfn *p_hwfn,
1617 u32 *num_mac_filters)
1618 {
1619 struct ecore_vf_iov *p_vf = p_hwfn->vf_iov_info;
1620
1621 *num_mac_filters = p_vf->acquire_resp.resc.num_mac_filters;
1622 }
1623
1624 bool ecore_vf_check_mac(struct ecore_hwfn *p_hwfn, u8 *mac)
1625 {
1626 struct ecore_bulletin_content *bulletin;
1627
1628 bulletin = &p_hwfn->vf_iov_info->bulletin_shadow;
1629 if (!(bulletin->valid_bitmap & (1 << MAC_ADDR_FORCED)))
1630 return true;
1631
1632 /* Forbid VF from changing a MAC enforced by PF */
1633 if (OSAL_MEMCMP(bulletin->mac, mac, ETH_ALEN))
1634 return false;
1635
1636 return false;
1637 }
1638
1639 bool ecore_vf_bulletin_get_forced_mac(struct ecore_hwfn *hwfn, u8 *dst_mac,
1640 u8 *p_is_forced)
1641 {
1642 struct ecore_bulletin_content *bulletin;
1643
1644 bulletin = &hwfn->vf_iov_info->bulletin_shadow;
1645
1646 if (bulletin->valid_bitmap & (1 << MAC_ADDR_FORCED)) {
1647 if (p_is_forced)
1648 *p_is_forced = 1;
1649 } else if (bulletin->valid_bitmap & (1 << VFPF_BULLETIN_MAC_ADDR)) {
1650 if (p_is_forced)
1651 *p_is_forced = 0;
1652 } else {
1653 return false;
1654 }
1655
1656 OSAL_MEMCPY(dst_mac, bulletin->mac, ETH_ALEN);
1657
1658 return true;
1659 }
1660
1661 void ecore_vf_bulletin_get_udp_ports(struct ecore_hwfn *p_hwfn,
1662 u16 *p_vxlan_port,
1663 u16 *p_geneve_port)
1664 {
1665 struct ecore_bulletin_content *p_bulletin;
1666
1667 p_bulletin = &p_hwfn->vf_iov_info->bulletin_shadow;
1668
1669 *p_vxlan_port = p_bulletin->vxlan_udp_port;
1670 *p_geneve_port = p_bulletin->geneve_udp_port;
1671 }
1672
1673 bool ecore_vf_bulletin_get_forced_vlan(struct ecore_hwfn *hwfn, u16 *dst_pvid)
1674 {
1675 struct ecore_bulletin_content *bulletin;
1676
1677 bulletin = &hwfn->vf_iov_info->bulletin_shadow;
1678
1679 if (!(bulletin->valid_bitmap & (1 << VLAN_ADDR_FORCED)))
1680 return false;
1681
1682 if (dst_pvid)
1683 *dst_pvid = bulletin->pvid;
1684
1685 return true;
1686 }
1687
1688 bool ecore_vf_get_pre_fp_hsi(struct ecore_hwfn *p_hwfn)
1689 {
1690 return p_hwfn->vf_iov_info->b_pre_fp_hsi;
1691 }
1692
1693 void ecore_vf_get_fw_version(struct ecore_hwfn *p_hwfn,
1694 u16 *fw_major, u16 *fw_minor, u16 *fw_rev,
1695 u16 *fw_eng)
1696 {
1697 struct pf_vf_pfdev_info *info;
1698
1699 info = &p_hwfn->vf_iov_info->acquire_resp.pfdev_info;
1700
1701 *fw_major = info->fw_major;
1702 *fw_minor = info->fw_minor;
1703 *fw_rev = info->fw_rev;
1704 *fw_eng = info->fw_eng;
1705 }
Ceph